[llvm] [AArch64][SVE] Enable known bits for predicated shifts (PR #200347)

[Harry Ramsey via llvm-commits]

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@@ -335,6 +335,110 @@ define <vscale x 2 x i64> @ssra_disjoint_or2xi64(<vscale x 2 x i64> %a, <vscale
   ret <vscale x 2 x i64> %add
 }
 
+define <vscale x 16 x i8> @usra_disjoint_shift_or16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
+; CHECK-LABEL: usra_disjoint_shift_or16xi8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.b, z0.b, #7
+; CHECK-NEXT:    usra z0.b, z1.b, #1
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Harry-Ramsey wrote:

I believe this is the GitHub UI as the patch is separated into two commits with the first commit containing the tests. 

https://github.com/llvm/llvm-project/pull/200347