[llvm] [SelectionDAG] Remove the remaining `NoSignedZerosFPMath` use (PR #201535)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 5 04:17:38 PDT 2026
https://github.com/paperchalice updated https://github.com/llvm/llvm-project/pull/201535
>From 9c47b14e511a24b469748d523ee822e43d7ef52c Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Jun 2026 17:01:56 +0800
Subject: [PATCH 1/5] [SelectionDAG] Propagate fast-math flags from {u,s}itofp
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index eca5bb1598ae0..19472f3dd2cb9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4054,6 +4054,8 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) {
SDNodeFlags Flags;
if (auto *PNI = dyn_cast<PossiblyNonNegInst>(&I))
Flags.setNonNeg(PNI->hasNonNeg());
+ if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
+ Flags.copyFMF(*FPOp);
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
@@ -4063,7 +4065,11 @@ void SelectionDAGBuilder::visitSIToFP(const User &I) {
SDValue N = getValue(I.getOperand(0));
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
I.getType());
- setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
+ SDNodeFlags Flags;
+ if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
+ Flags.copyFMF(*FPOp);
+
+ setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
void SelectionDAGBuilder::visitPtrToAddr(const User &I) {
>From c718940cc775278aaeadeacf70f01525a1c0e2f6 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Jun 2026 17:02:58 +0800
Subject: [PATCH 2/5] [SelectionDAG] Remove NoSignedZerosFPMath uses
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6cb9ae5fa7803..7b2a35b10c318 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19962,8 +19962,7 @@ static SDValue foldFPToIntToFP(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
TLI.isOperationLegal(IntToFPOp, VT))
return SDValue();
- bool IsSignedZeroSafe = DAG.getTarget().Options.NoSignedZerosFPMath ||
- DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
+ bool IsSignedZeroSafe = DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
// For signed conversions: The optimization changes signed zero behavior.
if (IsSigned && !IsSignedZeroSafe)
return SDValue();
>From ca9e6194eae4378bb8daf6576e424e323ee04a71 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Jun 2026 18:05:28 +0800
Subject: [PATCH 3/5] fix tests
---
llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll | 359 +++++++++++-------
llvm/test/CodeGen/AArch64/ftrunc.ll | 18 +-
.../AArch64/sve-fixed-length-frintz.ll | 8 +-
llvm/test/CodeGen/AArch64/sve-frintz.ll | 147 ++++---
llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll | 61 +--
.../CodeGen/PowerPC/fp-int128-fp-combine.ll | 6 +-
llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll | 13 +-
llvm/test/CodeGen/PowerPC/ftrunc-vec.ll | 18 +-
.../CodeGen/PowerPC/no-extra-fp-conv-ldst.ll | 26 +-
llvm/test/CodeGen/X86/ftrunc.ll | 36 +-
10 files changed, 395 insertions(+), 297 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll b/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
index a50716e4ab183..ab219e8e30641 100644
--- a/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,SIGNED-ZEROS
-; RUN: llc -mtriple=aarch64 --enable-no-signed-zeros-fp-math < %s | FileCheck %s --check-prefixes=CHECK,NO-SIGNED-ZEROS
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
; Test folding of float->int->float roundtrips into float-only operations.
; The optimization could converts patterns like:
@@ -9,62 +8,63 @@
; This is relevant for AArch64 as it avoids GPR bouncing and keeps computation in SIMD/FP registers.
define float @test_signed_basic(float %x) {
-; SIGNED-ZEROS-LABEL: test_signed_basic:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs s0, s0
-; SIGNED-ZEROS-NEXT: scvtf s0, s0
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_basic:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_basic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs s0, s0
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: ret
entry:
%i = fptosi float %x to i32
%f = sitofp i32 %i to float
ret float %f
}
+define float @test_signed_basic_nsz(float %x) {
+; CHECK-LABEL: test_signed_basic_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi float %x to i32
+ %f = sitofp nsz i32 %i to float
+ ret float %f
+}
+
define float @test_unsigned_basic(float %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_basic:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu s0, s0
-; SIGNED-ZEROS-NEXT: ucvtf s0, s0
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_basic:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_basic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu s0, s0
+; CHECK-NEXT: ucvtf s0, s0
+; CHECK-NEXT: ret
entry:
%i = fptoui float %x to i32
%f = uitofp i32 %i to float
ret float %f
}
+define float @test_unsigned_basic_nsz(float %x) {
+; CHECK-LABEL: test_unsigned_basic_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui float %x to i32
+ %f = uitofp nsz i32 %i to float
+ ret float %f
+}
+
define float @test_signed_min_max(float %x) {
-; SIGNED-ZEROS-LABEL: test_signed_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs w9, s0
-; SIGNED-ZEROS-NEXT: mov w8, #-512 // =0xfffffe00
-; SIGNED-ZEROS-NEXT: cmn w9, #512
-; SIGNED-ZEROS-NEXT: csel w8, w9, w8, gt
-; SIGNED-ZEROS-NEXT: mov w9, #1023 // =0x3ff
-; SIGNED-ZEROS-NEXT: cmp w8, #1023
-; SIGNED-ZEROS-NEXT: csel w8, w8, w9, lt
-; SIGNED-ZEROS-NEXT: scvtf s0, w8
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.2s, #196, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: fmov s1, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: mov w8, #-512 // =0xfffffe00
+; CHECK-NEXT: cmn w9, #512
+; CHECK-NEXT: csel w8, w9, w8, gt
+; CHECK-NEXT: mov w9, #1023 // =0x3ff
+; CHECK-NEXT: cmp w8, #1023
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: ret
entry:
%i = fptosi float %x to i32
%lower = call i32 @llvm.smax.i32(i32 %i, i32 -512)
@@ -73,29 +73,37 @@ entry:
ret float %f
}
+define float @test_signed_min_max_nsz(float %x) {
+; CHECK-LABEL: test_signed_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2s, #196, lsl #24
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm s0, s0, s1
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi float %x to i32
+ %lower = call i32 @llvm.smax.i32(i32 %i, i32 -512)
+ %clamped = call i32 @llvm.smin.i32(i32 %lower, i32 1023)
+ %f = sitofp nsz i32 %clamped to float
+ ret float %f
+}
+
define float @test_unsigned_min_max(float %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu w9, s0
-; SIGNED-ZEROS-NEXT: mov w8, #512 // =0x200
-; SIGNED-ZEROS-NEXT: cmp w9, #512
-; SIGNED-ZEROS-NEXT: csel w8, w9, w8, hi
-; SIGNED-ZEROS-NEXT: mov w9, #1023 // =0x3ff
-; SIGNED-ZEROS-NEXT: cmp w8, #1023
-; SIGNED-ZEROS-NEXT: csel w8, w8, w9, lo
-; SIGNED-ZEROS-NEXT: ucvtf s0, w8
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.2s, #68, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: fmov s1, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm s0, s0, s1
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu w9, s0
+; CHECK-NEXT: mov w8, #512 // =0x200
+; CHECK-NEXT: cmp w9, #512
+; CHECK-NEXT: csel w8, w9, w8, hi
+; CHECK-NEXT: mov w9, #1023 // =0x3ff
+; CHECK-NEXT: cmp w8, #1023
+; CHECK-NEXT: csel w8, w8, w9, lo
+; CHECK-NEXT: ucvtf s0, w8
+; CHECK-NEXT: ret
entry:
%i = fptoui float %x to i32
%lower = call i32 @llvm.umax.i32(i32 %i, i32 512)
@@ -104,6 +112,25 @@ entry:
ret float %f
}
+define float @test_unsigned_min_max_nsz(float %x) {
+; CHECK-LABEL: test_unsigned_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2s, #68, lsl #24
+; CHECK-NEXT: frintz s0, s0
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm s0, s0, s1
+; CHECK-NEXT: fmov s1, w8
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui float %x to i32
+ %lower = call i32 @llvm.umax.i32(i32 %i, i32 512)
+ %clamped = call i32 @llvm.umin.i32(i32 %lower, i32 1023)
+ %f = uitofp nsz i32 %clamped to float
+ ret float %f
+}
+
; 16777217 is NOT exactly representable in f32.
define float @test_inexact_16777217(float %x) {
; CHECK-LABEL: test_inexact_16777217:
@@ -124,94 +151,107 @@ entry:
}
define <4 x float> @test_signed_v4f32(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v4f32:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: scvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v4f32:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptosi <4 x float> %x to <4 x i32>
%f = sitofp <4 x i32> %i to <4 x float>
ret <4 x float> %f
}
+define <4 x float> @test_signed_v4f32_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_signed_v4f32_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <4 x float> %x to <4 x i32>
+ %f = sitofp nsz <4 x i32> %i to <4 x float>
+ ret <4 x float> %f
+}
+
define <4 x float> @test_unsigned_v4f32(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v4f32:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ucvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v4f32:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptoui <4 x float> %x to <4 x i32>
%f = uitofp <4 x i32> %i to <4 x float>
ret <4 x float> %f
}
+define <4 x float> @test_unsigned_v4f32_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_unsigned_v4f32_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <4 x float> %x to <4 x i32>
+ %f = uitofp nsz <4 x i32> %i to <4 x float>
+ ret <4 x float> %f
+}
+
define <2 x double> @test_signed_v2f64(<2 x double> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v2f64:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: scvtf v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v2f64:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.2d, v0.2d
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: scvtf v0.2d, v0.2d
+; CHECK-NEXT: ret
entry:
%i = fptosi <2 x double> %x to <2 x i64>
%f = sitofp <2 x i64> %i to <2 x double>
ret <2 x double> %f
}
+define <2 x double> @test_signed_v2f64_nsz(<2 x double> %x) {
+; CHECK-LABEL: test_signed_v2f64_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <2 x double> %x to <2 x i64>
+ %f = sitofp nsz <2 x i64> %i to <2 x double>
+ ret <2 x double> %f
+}
+
define <2 x double> @test_unsigned_v2f64(<2 x double> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v2f64:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzu v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ucvtf v0.2d, v0.2d
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v2f64:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: frintz v0.2d, v0.2d
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: ucvtf v0.2d, v0.2d
+; CHECK-NEXT: ret
entry:
%i = fptoui <2 x double> %x to <2 x i64>
%f = uitofp <2 x i64> %i to <2 x double>
ret <2 x double> %f
}
+define <2 x double> @test_unsigned_v2f64_nsz(<2 x double> %x) {
+; CHECK-LABEL: test_unsigned_v2f64_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintz v0.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <2 x double> %x to <2 x i64>
+ %f = uitofp nsz <2 x i64> %i to <2 x double>
+ ret <2 x double> %f
+}
+
define <4 x float> @test_signed_v4f32_min_max(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_signed_v4f32_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: fcvtzs v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: mvni v1.4s, #1, msl #8
-; SIGNED-ZEROS-NEXT: movi v2.4s, #3, msl #8
-; SIGNED-ZEROS-NEXT: smax v0.4s, v0.4s, v1.4s
-; SIGNED-ZEROS-NEXT: smin v0.4s, v0.4s, v2.4s
-; SIGNED-ZEROS-NEXT: scvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_v4f32_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.4s, #196, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: dup v1.4s, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_signed_v4f32_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mvni v1.4s, #1, msl #8
+; CHECK-NEXT: movi v2.4s, #3, msl #8
+; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: smin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptosi <4 x float> %x to <4 x i32>
%lower = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 -512))
@@ -220,27 +260,35 @@ entry:
ret <4 x float> %f
}
+define <4 x float> @test_signed_v4f32_min_max_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_signed_v4f32_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #196, lsl #24
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptosi <4 x float> %x to <4 x i32>
+ %lower = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 -512))
+ %clamped = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %lower, <4 x i32> splat (i32 1023))
+ %f = sitofp nsz <4 x i32> %clamped to <4 x float>
+ ret <4 x float> %f
+}
+
define <4 x float> @test_unsigned_v4f32_min_max(<4 x float> %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_v4f32_min_max:
-; SIGNED-ZEROS: // %bb.0: // %entry
-; SIGNED-ZEROS-NEXT: movi v1.4s, #2, lsl #8
-; SIGNED-ZEROS-NEXT: fcvtzu v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: movi v2.4s, #3, msl #8
-; SIGNED-ZEROS-NEXT: umax v0.4s, v0.4s, v1.4s
-; SIGNED-ZEROS-NEXT: umin v0.4s, v0.4s, v2.4s
-; SIGNED-ZEROS-NEXT: ucvtf v0.4s, v0.4s
-; SIGNED-ZEROS-NEXT: ret
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_v4f32_min_max:
-; NO-SIGNED-ZEROS: // %bb.0: // %entry
-; NO-SIGNED-ZEROS-NEXT: movi v1.4s, #68, lsl #24
-; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
-; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
-; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
-; NO-SIGNED-ZEROS-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: dup v1.4s, w8
-; NO-SIGNED-ZEROS-NEXT: fminnm v0.4s, v0.4s, v1.4s
-; NO-SIGNED-ZEROS-NEXT: ret
+; CHECK-LABEL: test_unsigned_v4f32_min_max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #2, lsl #8
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: movi v2.4s, #3, msl #8
+; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: ret
entry:
%i = fptoui <4 x float> %x to <4 x i32>
%lower = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 512))
@@ -249,6 +297,25 @@ entry:
ret <4 x float> %f
}
+define <4 x float> @test_unsigned_v4f32_min_max_nsz(<4 x float> %x) {
+; CHECK-LABEL: test_unsigned_v4f32_min_max_nsz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #68, lsl #24
+; CHECK-NEXT: frintz v0.4s, v0.4s
+; CHECK-NEXT: mov w8, #49152 // =0xc000
+; CHECK-NEXT: movk w8, #17535, lsl #16
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %i = fptoui <4 x float> %x to <4 x i32>
+ %lower = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 512))
+ %clamped = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %lower, <4 x i32> splat (i32 1023))
+ %f = uitofp nsz <4 x i32> %clamped to <4 x float>
+ ret <4 x float> %f
+}
+
define i1 @test_fcmp(float %x) {
; CHECK-LABEL: test_fcmp:
diff --git a/llvm/test/CodeGen/AArch64/ftrunc.ll b/llvm/test/CodeGen/AArch64/ftrunc.ll
index c7bf514e902be..093262160af97 100644
--- a/llvm/test/CodeGen/AArch64/ftrunc.ll
+++ b/llvm/test/CodeGen/AArch64/ftrunc.ll
@@ -1,45 +1,43 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
-define float @trunc_unsigned_f32(float %x) #0 {
+define float @trunc_unsigned_f32(float %x) {
; CHECK-LABEL: trunc_unsigned_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz s0, s0
; CHECK-NEXT: ret
%i = fptoui float %x to i32
- %r = uitofp i32 %i to float
+ %r = uitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_unsigned_f64(double %x) #0 {
+define double @trunc_unsigned_f64(double %x) {
; CHECK-LABEL: trunc_unsigned_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz d0, d0
; CHECK-NEXT: ret
%i = fptoui double %x to i64
- %r = uitofp i64 %i to double
+ %r = uitofp nsz i64 %i to double
ret double %r
}
-define float @trunc_signed_f32(float %x) #0 {
+define float @trunc_signed_f32(float %x) {
; CHECK-LABEL: trunc_signed_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz s0, s0
; CHECK-NEXT: ret
%i = fptosi float %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_signed_f64(double %x) #0 {
+define double @trunc_signed_f64(double %x) {
; CHECK-LABEL: trunc_signed_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz d0, d0
; CHECK-NEXT: ret
%i = fptosi double %x to i64
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
-attributes #0 = { "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
index 26cab6d542c65..74ba9c5eaf4da 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
@@ -22,7 +22,7 @@ define <8 x float> @frintz_f32_i32_f32(<8 x float> %in) {
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%res = fptosi <8 x float> %in to <8 x i32>
- %res2 = sitofp <8 x i32> %res to <8 x float>
+ %res2 = sitofp nsz <8 x i32> %res to <8 x float>
ret <8 x float> %res2
}
@@ -41,7 +41,7 @@ define <4 x double> @frintz_f64_i32_f64(<4 x double> %in) {
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%res = fptosi <4 x double> %in to <4 x i32>
- %res2 = sitofp <4 x i32> %res to <4 x double>
+ %res2 = sitofp nsz <4 x i32> %res to <4 x double>
ret <4 x double> %res2
}
@@ -60,7 +60,7 @@ define <4 x double> @frintz_f64_i64_f64(<4 x double> %in) {
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%res = fptosi <4 x double> %in to <4 x i64>
- %res2 = sitofp <4 x i64> %res to <4 x double>
+ %res2 = sitofp nsz <4 x i64> %res to <4 x double>
ret <4 x double> %res2
}
@@ -79,6 +79,6 @@ define <8 x float> @frintz_f32_i64_f32(<8 x float> %in) {
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%res = fptosi <8 x float> %in to <8 x i64>
- %res2 = sitofp <8 x i64> %res to <8 x float>
+ %res2 = sitofp nsz <8 x i64> %res to <8 x float>
ret <8 x float> %res2
}
diff --git a/llvm/test/CodeGen/AArch64/sve-frintz.ll b/llvm/test/CodeGen/AArch64/sve-frintz.ll
index f72ee35b0b58a..f1d9ffa9dd06d 100644
--- a/llvm/test/CodeGen/AArch64/sve-frintz.ll
+++ b/llvm/test/CodeGen/AArch64/sve-frintz.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc --enable-no-signed-zeros-fp-math -mattr=+sve < %s | FileCheck %s
-; RUN: llc -mattr=+sve < %s | FileCheck %s --check-prefix=SIGNED-ZEROS
+; RUN: llc -mattr=+sve < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu"
@@ -12,56 +11,71 @@ define <vscale x 4 x float> @frintz_f32_i32_f32(<vscale x 4 x float> %in) {
; CHECK-LABEL: frintz_f32_i32_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: frintz z0.s, p0/m, z0.s
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: scvtf z0.s, p0/m, z0.s
; CHECK-NEXT: ret
-;
-; SIGNED-ZEROS-LABEL: frintz_f32_i32_f32:
-; SIGNED-ZEROS: // %bb.0:
-; SIGNED-ZEROS-NEXT: ptrue p0.s
-; SIGNED-ZEROS-NEXT: fcvtzs z0.s, p0/m, z0.s
-; SIGNED-ZEROS-NEXT: scvtf z0.s, p0/m, z0.s
-; SIGNED-ZEROS-NEXT: ret
%res = fptosi <vscale x 4 x float> %in to <vscale x 4 x i32>
%res2 = sitofp <vscale x 4 x i32> %res to <vscale x 4 x float>
ret <vscale x 4 x float> %res2
}
+define <vscale x 4 x float> @frintz_f32_i32_f32_nsz(<vscale x 4 x float> %in) {
+; CHECK-LABEL: frintz_f32_i32_f32_nsz:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: frintz z0.s, p0/m, z0.s
+; CHECK-NEXT: ret
+ %res = fptosi <vscale x 4 x float> %in to <vscale x 4 x i32>
+ %res2 = sitofp nsz <vscale x 4 x i32> %res to <vscale x 4 x float>
+ ret <vscale x 4 x float> %res2
+}
+
define <vscale x 2 x double> @frintz_f64_i32_f64(<vscale x 2 x double> %in) {
; CHECK-LABEL: frintz_f64_i32_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: frintz z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
; CHECK-NEXT: ret
-;
-; SIGNED-ZEROS-LABEL: frintz_f64_i32_f64:
-; SIGNED-ZEROS: // %bb.0:
-; SIGNED-ZEROS-NEXT: ptrue p0.d
-; SIGNED-ZEROS-NEXT: fcvtzs z0.d, p0/m, z0.d
-; SIGNED-ZEROS-NEXT: scvtf z0.d, p0/m, z0.d
-; SIGNED-ZEROS-NEXT: ret
%res = fptosi <vscale x 2 x double> %in to <vscale x 2 x i32>
%res2 = sitofp <vscale x 2 x i32> %res to <vscale x 2 x double>
ret <vscale x 2 x double> %res2
}
+define <vscale x 2 x double> @frintz_f64_i32_f64_nsz(<vscale x 2 x double> %in) {
+; CHECK-LABEL: frintz_f64_i32_f64_nsz:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: frintz z0.d, p0/m, z0.d
+; CHECK-NEXT: ret
+ %res = fptosi <vscale x 2 x double> %in to <vscale x 2 x i32>
+ %res2 = sitofp nsz <vscale x 2 x i32> %res to <vscale x 2 x double>
+ ret <vscale x 2 x double> %res2
+}
+
define <vscale x 8 x float> @frintz_f32_i32_f32_nxv8i32(<vscale x 8 x float> %in) {
; CHECK-LABEL: frintz_f32_i32_f32_nxv8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: scvtf z0.s, p0/m, z0.s
+; CHECK-NEXT: scvtf z1.s, p0/m, z1.s
+; CHECK-NEXT: ret
+ %res = fptosi <vscale x 8 x float> %in to <vscale x 8 x i32>
+ %res2 = sitofp <vscale x 8 x i32> %res to <vscale x 8 x float>
+ ret <vscale x 8 x float> %res2
+}
+
+define <vscale x 8 x float> @frintz_f32_i32_f32_nxv8i32_nsz(<vscale x 8 x float> %in) {
+; CHECK-LABEL: frintz_f32_i32_f32_nxv8i32_nsz:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: frintz z0.s, p0/m, z0.s
; CHECK-NEXT: frintz z1.s, p0/m, z1.s
; CHECK-NEXT: ret
-;
-; SIGNED-ZEROS-LABEL: frintz_f32_i32_f32_nxv8i32:
-; SIGNED-ZEROS: // %bb.0:
-; SIGNED-ZEROS-NEXT: ptrue p0.s
-; SIGNED-ZEROS-NEXT: fcvtzs z1.s, p0/m, z1.s
-; SIGNED-ZEROS-NEXT: fcvtzs z0.s, p0/m, z0.s
-; SIGNED-ZEROS-NEXT: scvtf z0.s, p0/m, z0.s
-; SIGNED-ZEROS-NEXT: scvtf z1.s, p0/m, z1.s
-; SIGNED-ZEROS-NEXT: ret
%res = fptosi <vscale x 8 x float> %in to <vscale x 8 x i32>
- %res2 = sitofp <vscale x 8 x i32> %res to <vscale x 8 x float>
+ %res2 = sitofp nsz <vscale x 8 x i32> %res to <vscale x 8 x float>
ret <vscale x 8 x float> %res2
}
@@ -69,40 +83,50 @@ define <vscale x 2 x double> @frintz_f64_i64_f64(<vscale x 2 x double> %in) {
; CHECK-LABEL: frintz_f64_i64_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: frintz z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
; CHECK-NEXT: ret
-;
-; SIGNED-ZEROS-LABEL: frintz_f64_i64_f64:
-; SIGNED-ZEROS: // %bb.0:
-; SIGNED-ZEROS-NEXT: ptrue p0.d
-; SIGNED-ZEROS-NEXT: fcvtzs z0.d, p0/m, z0.d
-; SIGNED-ZEROS-NEXT: scvtf z0.d, p0/m, z0.d
-; SIGNED-ZEROS-NEXT: ret
%res = fptosi <vscale x 2 x double> %in to <vscale x 2 x i64>
%res2 = sitofp <vscale x 2 x i64> %res to <vscale x 2 x double>
ret <vscale x 2 x double> %res2
}
+define <vscale x 2 x double> @frintz_f64_i64_f64_nsz(<vscale x 2 x double> %in) {
+; CHECK-LABEL: frintz_f64_i64_f64_nsz:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: frintz z0.d, p0/m, z0.d
+; CHECK-NEXT: ret
+ %res = fptosi <vscale x 2 x double> %in to <vscale x 2 x i64>
+ %res2 = sitofp nsz <vscale x 2 x i64> %res to <vscale x 2 x double>
+ ret <vscale x 2 x double> %res2
+}
+
define <vscale x 4 x float> @frintz_f32_i64_f32(<vscale x 4 x float> %in) {
; CHECK-LABEL: frintz_f32_i64_f32:
; CHECK: // %bb.0:
+; CHECK-NEXT: uunpklo z1.d, z0.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: scvtf z0.s, p0/m, z0.d
+; CHECK-NEXT: scvtf z1.s, p0/m, z1.d
+; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
+; CHECK-NEXT: ret
+ %res = fptosi <vscale x 4 x float> %in to <vscale x 4 x i64>
+ %res2 = sitofp <vscale x 4 x i64> %res to <vscale x 4 x float>
+ ret <vscale x 4 x float> %res2
+}
+
+define <vscale x 4 x float> @frintz_f32_i64_f32_nsz(<vscale x 4 x float> %in) {
+; CHECK-LABEL: frintz_f32_i64_f32_nsz:
+; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: frintz z0.s, p0/m, z0.s
; CHECK-NEXT: ret
-;
-; SIGNED-ZEROS-LABEL: frintz_f32_i64_f32:
-; SIGNED-ZEROS: // %bb.0:
-; SIGNED-ZEROS-NEXT: uunpklo z1.d, z0.s
-; SIGNED-ZEROS-NEXT: uunpkhi z0.d, z0.s
-; SIGNED-ZEROS-NEXT: ptrue p0.d
-; SIGNED-ZEROS-NEXT: fcvtzs z1.d, p0/m, z1.s
-; SIGNED-ZEROS-NEXT: fcvtzs z0.d, p0/m, z0.s
-; SIGNED-ZEROS-NEXT: scvtf z0.s, p0/m, z0.d
-; SIGNED-ZEROS-NEXT: scvtf z1.s, p0/m, z1.d
-; SIGNED-ZEROS-NEXT: uzp1 z0.s, z1.s, z0.s
-; SIGNED-ZEROS-NEXT: ret
%res = fptosi <vscale x 4 x float> %in to <vscale x 4 x i64>
- %res2 = sitofp <vscale x 4 x i64> %res to <vscale x 4 x float>
+ %res2 = sitofp nsz <vscale x 4 x i64> %res to <vscale x 4 x float>
ret <vscale x 4 x float> %res2
}
@@ -110,19 +134,24 @@ define <vscale x 4 x double> @frintz_f64_i64_f64_nxv4i64(<vscale x 4 x double> %
; CHECK-LABEL: frintz_f64_i64_f64_nxv4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
+; CHECK-NEXT: scvtf z1.d, p0/m, z1.d
+; CHECK-NEXT: ret
+ %res = fptosi <vscale x 4 x double> %in to <vscale x 4 x i64>
+ %res2 = sitofp <vscale x 4 x i64> %res to <vscale x 4 x double>
+ ret <vscale x 4 x double> %res2
+}
+
+define <vscale x 4 x double> @frintz_f64_i64_f64_nxv4i64_nsz(<vscale x 4 x double> %in) {
+; CHECK-LABEL: frintz_f64_i64_f64_nxv4i64_nsz:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: frintz z0.d, p0/m, z0.d
; CHECK-NEXT: frintz z1.d, p0/m, z1.d
; CHECK-NEXT: ret
-;
-; SIGNED-ZEROS-LABEL: frintz_f64_i64_f64_nxv4i64:
-; SIGNED-ZEROS: // %bb.0:
-; SIGNED-ZEROS-NEXT: ptrue p0.d
-; SIGNED-ZEROS-NEXT: fcvtzs z1.d, p0/m, z1.d
-; SIGNED-ZEROS-NEXT: fcvtzs z0.d, p0/m, z0.d
-; SIGNED-ZEROS-NEXT: scvtf z0.d, p0/m, z0.d
-; SIGNED-ZEROS-NEXT: scvtf z1.d, p0/m, z1.d
-; SIGNED-ZEROS-NEXT: ret
%res = fptosi <vscale x 4 x double> %in to <vscale x 4 x i64>
- %res2 = sitofp <vscale x 4 x i64> %res to <vscale x 4 x double>
+ %res2 = sitofp nsz <vscale x 4 x i64> %res to <vscale x 4 x double>
ret <vscale x 4 x double> %res2
}
diff --git a/llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll b/llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
index 2416d6a852eb9..85df90c096a5a 100644
--- a/llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
@@ -1,48 +1,59 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn < %s | FileCheck %s --check-prefixes=CHECK,SIGNED-ZEROS
-; RUN: llc -mtriple=amdgcn --enable-no-signed-zeros-fp-math < %s | FileCheck %s --check-prefixes=CHECK,NO-SIGNED-ZEROS
+; RUN: llc -mtriple=amdgcn < %s | FileCheck %s
; Test folding of float->int->float roundtrips into float-only operations.
define float @test_signed_basic(float %x) {
-; SIGNED-ZEROS-LABEL: test_signed_basic:
-; SIGNED-ZEROS: ; %bb.0: ; %entry
-; SIGNED-ZEROS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SIGNED-ZEROS-NEXT: v_cvt_i32_f32_e32 v0, v0
-; SIGNED-ZEROS-NEXT: v_cvt_f32_i32_e32 v0, v0
-; SIGNED-ZEROS-NEXT: s_setpc_b64 s[30:31]
-;
-; NO-SIGNED-ZEROS-LABEL: test_signed_basic:
-; NO-SIGNED-ZEROS: ; %bb.0: ; %entry
-; NO-SIGNED-ZEROS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; NO-SIGNED-ZEROS-NEXT: v_trunc_f32_e32 v0, v0
-; NO-SIGNED-ZEROS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test_signed_basic:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cvt_i32_f32_e32 v0, v0
+; CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
%i = fptosi float %x to i32
%f = sitofp i32 %i to float
ret float %f
}
+define float @test_signed_basic_nsz(float %x) {
+; CHECK-LABEL: test_signed_basic_nsz:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_trunc_f32_e32 v0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %i = fptosi float %x to i32
+ %f = sitofp nsz i32 %i to float
+ ret float %f
+}
+
; For unsigned conversions, even when signed zeros are possible, we can still
; use truncate because fabs is free.
define float @test_unsigned_basic(float %x) {
-; SIGNED-ZEROS-LABEL: test_unsigned_basic:
-; SIGNED-ZEROS: ; %bb.0: ; %entry
-; SIGNED-ZEROS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SIGNED-ZEROS-NEXT: v_trunc_f32_e64 v0, |v0|
-; SIGNED-ZEROS-NEXT: s_setpc_b64 s[30:31]
-;
-; NO-SIGNED-ZEROS-LABEL: test_unsigned_basic:
-; NO-SIGNED-ZEROS: ; %bb.0: ; %entry
-; NO-SIGNED-ZEROS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; NO-SIGNED-ZEROS-NEXT: v_trunc_f32_e32 v0, v0
-; NO-SIGNED-ZEROS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test_unsigned_basic:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_trunc_f32_e64 v0, |v0|
+; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
%i = fptoui float %x to i32
%f = uitofp i32 %i to float
ret float %f
}
+define float @test_unsigned_basic_nsz(float %x) {
+; CHECK-LABEL: test_unsigned_basic_nsz:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_trunc_f32_e32 v0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %i = fptoui float %x to i32
+ %f = uitofp nsz i32 %i to float
+ ret float %f
+}
+
; 16777217 is NOT exactly representable in f32.
define float @test_inexact_16777217(float %x) {
; CHECK-LABEL: test_inexact_16777217:
diff --git a/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll b/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
index 8ebf54a3dc489..9af6443d85230 100644
--- a/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
@@ -26,16 +26,14 @@ entry:
; NSZ, so it's safe to friz.
-define float @f_i128_fi_nsz(float %v) #0 {
+define float @f_i128_fi_nsz(float %v) {
; CHECK-LABEL: f_i128_fi_nsz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsrdpiz 1, 1
; CHECK-NEXT: blr
entry:
%a = fptosi float %v to i128
- %b = sitofp i128 %a to float
+ %b = sitofp nsz i128 %a to float
ret float %b
}
-attributes #0 = { "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
index 11460349c90fb..de6b381275b4b 100644
--- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
@@ -25,7 +25,7 @@ define float @fool(float %X) #0 {
; PWR9-NEXT: blr
entry:
%conv = fptosi float %X to i64
- %conv1 = sitofp i64 %conv to float
+ %conv1 = sitofp nsz i64 %conv to float
ret float %conv1
@@ -50,7 +50,7 @@ define double @foodl(double %X) #0 {
; PWR9-NEXT: blr
entry:
%conv = fptosi double %X to i64
- %conv1 = sitofp i64 %conv to double
+ %conv1 = sitofp nsz i64 %conv to double
ret double %conv1
@@ -132,7 +132,7 @@ define float @fooul(float %X) #0 {
; PWR9-NEXT: blr
entry:
%conv = fptoui float %X to i64
- %conv1 = uitofp i64 %conv to float
+ %conv1 = uitofp nsz i64 %conv to float
ret float %conv1
}
@@ -188,7 +188,7 @@ define double @fooudl(double %X) #0 {
; PWR9-NEXT: blr
entry:
%conv = fptoui double %X to i64
- %conv1 = uitofp i64 %conv to double
+ %conv1 = uitofp nsz i64 %conv to double
ret double %conv1
}
@@ -288,7 +288,7 @@ define double @si1_to_f64(i1 %X) #0 {
; PWR9-NEXT: xscvsxddp 1, 0
; PWR9-NEXT: blr
entry:
- %conv = sitofp i1 %X to double
+ %conv = sitofp nsz i1 %X to double
ret double %conv
}
@@ -319,9 +319,8 @@ define double @ui1_to_f64(i1 %X) #0 {
; PWR9-NEXT: xscvsxddp 1, 0
; PWR9-NEXT: blr
entry:
- %conv = uitofp i1 %X to double
+ %conv = uitofp nsz i1 %X to double
ret double %conv
}
-attributes #0 = { nounwind readnone "no-signed-zeros-fp-math"="true" }
diff --git a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
index ecad35d22e859..b0faf1430b8fa 100644
--- a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
+++ b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
@@ -2,45 +2,43 @@
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -verify-machineinstrs < %s | FileCheck %s
-define <4 x float> @truncf32(<4 x float> %a) #0 {
+define <4 x float> @truncf32(<4 x float> %a) {
; CHECK-LABEL: truncf32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrspiz 34, 34
; CHECK-NEXT: blr
%t0 = fptosi <4 x float> %a to <4 x i32>
- %t1 = sitofp <4 x i32> %t0 to <4 x float>
+ %t1 = sitofp nsz <4 x i32> %t0 to <4 x float>
ret <4 x float> %t1
}
-define <2 x double> @truncf64(<2 x double> %a) #0 {
+define <2 x double> @truncf64(<2 x double> %a) {
; CHECK-LABEL: truncf64:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrdpiz 34, 34
; CHECK-NEXT: blr
%t0 = fptosi <2 x double> %a to <2 x i64>
- %t1 = sitofp <2 x i64> %t0 to <2 x double>
+ %t1 = sitofp nsz <2 x i64> %t0 to <2 x double>
ret <2 x double> %t1
}
-define <4 x float> @truncf32u(<4 x float> %a) #0 {
+define <4 x float> @truncf32u(<4 x float> %a) {
; CHECK-LABEL: truncf32u:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrspiz 34, 34
; CHECK-NEXT: blr
%t0 = fptoui <4 x float> %a to <4 x i32>
- %t1 = uitofp <4 x i32> %t0 to <4 x float>
+ %t1 = uitofp nsz <4 x i32> %t0 to <4 x float>
ret <4 x float> %t1
}
-define <2 x double> @truncf64u(<2 x double> %a) #0 {
+define <2 x double> @truncf64u(<2 x double> %a) {
; CHECK-LABEL: truncf64u:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrdpiz 34, 34
; CHECK-NEXT: blr
%t0 = fptoui <2 x double> %a to <2 x i64>
- %t1 = uitofp <2 x i64> %t0 to <2 x double>
+ %t1 = uitofp nsz <2 x i64> %t0 to <2 x double>
ret <2 x double> %t1
}
-attributes #0 = { "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll b/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
index 3ce14d35c4aea..eead1e932eeb6 100644
--- a/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
@@ -3,10 +3,10 @@ target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readonly
-define double @test1(ptr nocapture readonly %x) #0 {
+define double @test1(ptr nocapture readonly %x) {
entry:
%0 = load i64, ptr %x, align 8
- %conv = sitofp i64 %0 to double
+ %conv = sitofp nsz i64 %0 to double
ret double %conv
; CHECK-LABEL: @test1
@@ -16,10 +16,10 @@ entry:
}
; Function Attrs: nounwind readonly
-define double @test2(ptr nocapture readonly %x) #0 {
+define double @test2(ptr nocapture readonly %x) {
entry:
%0 = load i32, ptr %x, align 4
- %conv = sitofp i32 %0 to double
+ %conv = sitofp nsz i32 %0 to double
ret double %conv
; CHECK-LABEL: @test2
@@ -29,10 +29,10 @@ entry:
}
; Function Attrs: nounwind readnone
-define float @foo(float %X) #0 {
+define float @foo(float %X) {
entry:
%conv = fptosi float %X to i32
- %conv1 = sitofp i32 %conv to float
+ %conv1 = sitofp nsz i32 %conv to float
ret float %conv1
; CHECK-LABEL: @foo
@@ -41,10 +41,10 @@ entry:
}
; Function Attrs: nounwind readnone
-define double @food(double %X) #0 {
+define double @food(double %X) {
entry:
%conv = fptosi double %X to i32
- %conv1 = sitofp i32 %conv to double
+ %conv1 = sitofp nsz i32 %conv to double
ret double %conv1
; CHECK-LABEL: @food
@@ -53,10 +53,10 @@ entry:
}
; Function Attrs: nounwind readnone
-define float @foou(float %X) #0 {
+define float @foou(float %X) {
entry:
%conv = fptoui float %X to i32
- %conv1 = uitofp i32 %conv to float
+ %conv1 = uitofp nsz i32 %conv to float
ret float %conv1
; CHECK-LABEL: @foou
@@ -65,10 +65,10 @@ entry:
}
; Function Attrs: nounwind readnone
-define double @fooud(double %X) #0 {
+define double @fooud(double %X) {
entry:
%conv = fptoui double %X to i32
- %conv1 = uitofp i32 %conv to double
+ %conv1 = uitofp nsz i32 %conv to double
ret double %conv1
; CHECK-LABEL: @fooud
@@ -76,5 +76,3 @@ entry:
; CHECK: blr
}
-attributes #0 = { nounwind readonly "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/X86/ftrunc.ll b/llvm/test/CodeGen/X86/ftrunc.ll
index 9095fb1550e70..1ab9040a2810f 100644
--- a/llvm/test/CodeGen/X86/ftrunc.ll
+++ b/llvm/test/CodeGen/X86/ftrunc.ll
@@ -36,7 +36,7 @@ define float @trunc_unsigned_f32(float %x) #0 {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptoui float %x to i32
- %r = uitofp i32 %i to float
+ %r = uitofp nsz i32 %i to float
ret float %r
}
@@ -82,7 +82,7 @@ define double @trunc_unsigned_f64(double %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptoui double %x to i64
- %r = uitofp i64 %i to double
+ %r = uitofp nsz i64 %i to double
ret double %r
}
@@ -115,7 +115,7 @@ define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) #0 {
; AVX-NEXT: vroundps $11, %xmm0, %xmm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptoui <4 x float> %x to <4 x i32>
- %r = uitofp <4 x i32> %i to <4 x float>
+ %r = uitofp nsz <4 x i32> %i to <4 x float>
ret <4 x float> %r
}
@@ -162,7 +162,7 @@ define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 {
; AVX-NEXT: vroundpd $11, %xmm0, %xmm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptoui <2 x double> %x to <2 x i64>
- %r = uitofp <2 x i64> %i to <2 x double>
+ %r = uitofp nsz <2 x i64> %i to <2 x double>
ret <2 x double> %r
}
@@ -239,7 +239,7 @@ define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 {
; AVX-NEXT: vroundpd $11, %ymm0, %ymm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptoui <4 x double> %x to <4 x i64>
- %r = uitofp <4 x i64> %i to <4 x double>
+ %r = uitofp nsz <4 x i64> %i to <4 x double>
ret <4 x double> %r
}
@@ -300,7 +300,7 @@ define float @trunc_signed_f32_nsz(float %x) #0 {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptosi float %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
@@ -367,7 +367,7 @@ define double @trunc_signed32_f64_nsz(double %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i32
- %r = sitofp i32 %i to double
+ %r = sitofp nsz i32 %i to double
ret double %r
}
@@ -399,7 +399,7 @@ define double @trunc_f32_signed32_f64_no_fast_math(float %x) nounwind {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi float %x to i32
- %r = sitofp i32 %i to double
+ %r = sitofp nsz i32 %i to double
ret double %r
}
@@ -431,7 +431,7 @@ define double @trunc_f32_signed32_f64_nsz(float %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi float %x to i32
- %r = sitofp i32 %i to double
+ %r = sitofp nsz i32 %i to double
ret double %r
}
@@ -459,7 +459,7 @@ define float @trunc_f64_signed32_f32_no_fast_math(double %x) nounwind {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
@@ -487,7 +487,7 @@ define float @trunc_f64_signed32_f32_nsz(double %x) #0 {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
@@ -560,7 +560,7 @@ define double @trunc_signed_f64_nsz(double %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i64
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
@@ -581,7 +581,7 @@ define <4 x float> @trunc_signed_v4f32_nsz(<4 x float> %x) #0 {
; AVX-NEXT: vroundps $11, %xmm0, %xmm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptosi <4 x float> %x to <4 x i32>
- %r = sitofp <4 x i32> %i to <4 x float>
+ %r = sitofp nsz <4 x i32> %i to <4 x float>
ret <4 x float> %r
}
@@ -607,7 +607,7 @@ define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 {
; AVX-NEXT: vroundpd $11, %xmm0, %xmm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptosi <2 x double> %x to <2 x i64>
- %r = sitofp <2 x i64> %i to <2 x double>
+ %r = sitofp nsz <2 x i64> %i to <2 x double>
ret <2 x double> %r
}
@@ -642,7 +642,7 @@ define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 {
; AVX-NEXT: vroundpd $11, %ymm0, %ymm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptosi <4 x double> %x to <4 x i64>
- %r = sitofp <4 x i64> %i to <4 x double>
+ %r = sitofp nsz <4 x i64> %i to <4 x double>
ret <4 x double> %r
}
@@ -709,7 +709,7 @@ define float @trunc_unsigned_f32_disable_via_intrinsic(float %x) #0 {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = call i32 @llvm.fptoui.sat.i32.f32(float %x)
- %r = uitofp i32 %i to float
+ %r = uitofp nsz i32 %i to float
ret float %r
}
@@ -778,8 +778,8 @@ define double @trunc_signed_f64_disable_via_intrinsic(double %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = call i64 @llvm.fptosi.sat.i64.f64(double %x)
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
-attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" }
+attributes #0 = { nounwind }
>From cb87bcadcbaf321e738697e1a6f0b4af2af02d9c Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Fri, 5 Jun 2026 15:53:15 +0800
Subject: [PATCH 4/5] use `cast` directly
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 19472f3dd2cb9..0608a95e09278 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4052,10 +4052,8 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) {
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
I.getType());
SDNodeFlags Flags;
- if (auto *PNI = dyn_cast<PossiblyNonNegInst>(&I))
- Flags.setNonNeg(PNI->hasNonNeg());
- if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
- Flags.copyFMF(*FPOp);
+ Flags.setNonNeg(cast<PossiblyNonNegInst>(&I)->hasNonNeg());
+ Flags.copyFMF(*cast<FPMathOperator>(&I));
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
@@ -4066,8 +4064,7 @@ void SelectionDAGBuilder::visitSIToFP(const User &I) {
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
I.getType());
SDNodeFlags Flags;
- if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
- Flags.copyFMF(*FPOp);
+ Flags.copyFMF(*cast<FPMathOperator>(&I));
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
>From 416a27badc0287f16d57a5233e5adb6443c0f42a Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Fri, 5 Jun 2026 18:06:41 +0800
Subject: [PATCH 5/5] remove redundant --enable-no-signed-zeros-fp-math
---
llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
index 74ba9c5eaf4da..7334381a289af 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc --enable-no-signed-zeros-fp-math -mattr=+sve -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
+; RUN: llc -mattr=+sve -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
; Check that fp -> int -> fp conversions can be
; lowered to the SVE FRINTZ instructions for
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