[llvm] [AArch64] Align ZCM/ZCZ test strictness(NFC) (PR #200645)
Tomer Shafir via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 5 02:30:03 PDT 2026
https://github.com/tomershafir updated https://github.com/llvm/llvm-project/pull/200645
>From c2ac03167c64635853c8f851a74370b975fd1a69 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Sun, 31 May 2026 11:39:05 +0300
Subject: [PATCH 1/2] [AArch64] Align ZCM/ZCZ test strictness(NFC)
---
.../AArch64/arm64-zero-cycle-regmove-fpr.ll | 10 ++---
.../AArch64/arm64-zero-cycle-regmove-fpr8.mir | 10 ++---
.../AArch64/arm64-zero-cycle-regmove-gpr.ll | 10 ++---
.../AArch64/arm64-zero-cycle-zeroing-gpr.ll | 42 +++++++++----------
4 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
index 8980457b8c9e7..ef5ad5029c1b6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-CPU --match-full-lines
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-CPU --match-full-lines
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=CHECK,ZCM-FPR128-CPU --match-full-lines
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-ATTR --match-full-lines
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 | FileCheck %s -check-prefixes=CHECK,ZCM-FPR128-ATTR --match-full-lines
+; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-CPU
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-CPU
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=CHECK,ZCM-FPR128-CPU
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-ATTR
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 | FileCheck %s --match-full-lines -check-prefixes=CHECK,ZCM-FPR128-ATTR
define void @zero_cycle_regmove_FPR64(double %a, double %b, double %c, double %d) {
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir
index f8ebc26f5e0ae..22917a89d928a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir
@@ -1,8 +1,8 @@
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-linux-gnu %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-CPU --match-full-lines
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=generic %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-CPU --match-full-lines
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 %s | FileCheck %s -check-prefixes=ALL,ZCM-FPR128-CPU --match-full-lines
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-ATTR --match-full-lines
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 %s | FileCheck %s -check-prefixes=ALL,ZCM-FPR128-ATTR --match-full-lines
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-linux-gnu %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-CPU
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=generic %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-CPU
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCM-FPR128-CPU
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-ATTR
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCM-FPR128-ATTR
---
name: zero_cycle_regmove_FPR8
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
index f3a99cb7e83b3..354a89c16b124 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOTCPU-LINUX
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOTCPU-APPLE
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,CPU
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-gpr64 | FileCheck %s -check-prefixes=ALL,NOTATTR
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-gpr64 | FileCheck %s -check-prefixes=ALL,ATTR
+; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTCPU-LINUX
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTCPU-APPLE
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=ALL,CPU
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTATTR
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,ATTR
define void @zero_cycle_regmove_GPR32(i32 %a, i32 %b, i32 %c, i32 %d) {
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
index 0f284aa9ad282..abfd79e092395 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
@@ -1,44 +1,44 @@
-; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr32 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-ZCZ-GPR64
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
-; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr32 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-ZCZ-GPR64
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
+; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
define i8 @ti8() {
entry:
-; ALL-LABEL: ti8:
+; ALL-LABEL: {{_?}}ti8:{{ *}}{{(;|//)}}{{ *}}@ti8
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
+; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
ret i8 0
}
define i16 @ti16() {
entry:
-; ALL-LABEL: ti16:
+; ALL-LABEL: {{_?}}ti16:{{ *}}{{(;|//)}}{{ *}}@ti16
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
+; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
ret i16 0
}
define i32 @ti32() {
entry:
-; ALL-LABEL: ti32:
+; ALL-LABEL: {{_?}}ti32:{{ *}}{{(;|//)}}{{ *}}@ti32
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
+; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
ret i32 0
}
define i64 @ti64() {
entry:
-; ALL-LABEL: ti64:
-; NOZCZ-GPR32-NOZCZ-GPR64 mov x0, xzr
-; ZCZ-GPR64: mov x0, #0
+; ALL-LABEL: {{_?}}ti64:{{ *}}{{(;|//)}}{{ *}}@ti64
+; NOZCZ-GPR32-NOZCZ-GPR64: mov x0, xzr
+; ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
ret i64 0
}
>From d265c74a3d88bf3f0c0ec0cc9682a143de50755b Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Fri, 5 Jun 2026 11:20:29 +0300
Subject: [PATCH 2/2] simplify middle-end regex
---
.../AArch64/arm64-zero-cycle-regmove-fpr.ll | 6 ++--
.../AArch64/arm64-zero-cycle-regmove-gpr.ll | 2 +-
.../AArch64/arm64-zero-cycle-zeroing-fpr.ll | 28 +++++++++----------
.../AArch64/arm64-zero-cycle-zeroing-gpr.ll | 22 +++++++--------
4 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
index ef5ad5029c1b6..5034d999f2e29 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
@@ -6,7 +6,7 @@
define void @zero_cycle_regmove_FPR64(double %a, double %b, double %c, double %d) {
entry:
-; CHECK-LABEL: {{_?zero_cycle_regmove_FPR64}}:{{ *}}{{(;|//)}}{{ *}}@zero_cycle_regmove_FPR64
+; CHECK-LABEL: {{_?zero_cycle_regmove_FPR64}}:{{ *(;|//) *}}@zero_cycle_regmove_FPR64
; NOZCM-FPR128-CPU: fmov d0, d2
; NOZCM-FPR128-CPU: fmov d1, d3
@@ -48,7 +48,7 @@ declare float @foo_double(double, double)
define void @zero_cycle_regmove_FPR32(float %a, float %b, float %c, float %d) {
entry:
-; CHECK-LABEL: {{_?zero_cycle_regmove_FPR32}}:{{ *}}{{(;|//)}}{{ *}}@zero_cycle_regmove_FPR32
+; CHECK-LABEL: {{_?zero_cycle_regmove_FPR32}}:{{ *(;|//) *}}@zero_cycle_regmove_FPR32
; NOZCM-FPR128-CPU: fmov s0, s2
; NOZCM-FPR128-CPU: fmov s1, s3
@@ -90,7 +90,7 @@ declare float @foo_float(float, float)
define void @zero_cycle_regmove_FPR16(half %a, half %b, half %c, half %d) {
entry:
-; CHECK-LABEL: {{_?zero_cycle_regmove_FPR16}}:{{ *}}{{(;|//)}}{{ *}}@zero_cycle_regmove_FPR16
+; CHECK-LABEL: {{_?zero_cycle_regmove_FPR16}}:{{ *(;|//) *}}@zero_cycle_regmove_FPR16
; NOZCM-FPR128-CPU: fmov s0, s2
; NOZCM-FPR128-CPU: fmov s1, s3
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
index 354a89c16b124..c7fa5d637c426 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
@@ -6,7 +6,7 @@
define void @zero_cycle_regmove_GPR32(i32 %a, i32 %b, i32 %c, i32 %d) {
entry:
-; ALL-LABEL: {{_?zero_cycle_regmove_GPR32}}:{{ *}}{{(;|//)}}{{ *}}@zero_cycle_regmove_GPR32
+; ALL-LABEL: {{_?zero_cycle_regmove_GPR32}}:{{ *(;|//) *}}@zero_cycle_regmove_GPR32
; NOTCPU-LINUX: mov w0, w2
; NOTCPU-LINUX: mov w1, w3
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
index 293faf2405fdd..643e4ae9092df 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
@@ -11,7 +11,7 @@
define half @tf16() {
entry:
-; ALL-LABEL: {{_?}}tf16:{{ *}}{{(;|//)}}{{ *}}@tf16
+; ALL-LABEL: {{_?}}tf16:{{ *(;|//) *}}@tf16
; FP-WORKAROUND: fmov s0, wzr
; NOZCZ-FPR64-NOZCZ-FPR128: fmov s0, wzr
; NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16: fmov h0, wzr
@@ -22,7 +22,7 @@ entry:
define float @tf32() {
entry:
-; ALL-LABEL: {{_?}}tf32:{{ *}}{{(;|//)}}{{ *}}@tf32
+; ALL-LABEL: {{_?}}tf32:{{ *(;|//) *}}@tf32
; FP-WORKAROUND: fmov s0, wzr
; NOZCZ-FPR64-NOZCZ-FPR128: fmov s0, wzr
; ZCZ-FPR64: movi d0, #0000000000000000
@@ -32,7 +32,7 @@ entry:
define double @td64() {
entry:
-; ALL-LABEL: {{_?}}td64:{{ *}}{{(;|//)}}{{ *}}@td64
+; ALL-LABEL: {{_?}}td64:{{ *(;|//) *}}@td64
; FP-WORKAROUND: fmov d0, xzr
; NOZCZ-FPR64-NOZCZ-FPR128: fmov d0, xzr
; ZCZ-FPR64: movi d0, #0000000000000000
@@ -42,7 +42,7 @@ entry:
define <8 x i8> @tv8i8() {
entry:
-; ALL-LABEL: {{_?}}tv8i8:{{ *}}{{(;|//)}}{{ *}}@tv8i8
+; ALL-LABEL: {{_?}}tv8i8:{{ *(;|//) *}}@tv8i8
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -52,7 +52,7 @@ entry:
define <4 x i16> @tv4i16() {
entry:
-; ALL-LABEL: {{_?}}tv4i16:{{ *}}{{(;|//)}}{{ *}}@tv4i16
+; ALL-LABEL: {{_?}}tv4i16:{{ *(;|//) *}}@tv4i16
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -62,7 +62,7 @@ entry:
define <2 x i32> @tv2i32() {
entry:
-; ALL-LABEL: {{_?}}tv2i32:{{ *}}{{(;|//)}}{{ *}}@tv2i32
+; ALL-LABEL: {{_?}}tv2i32:{{ *(;|//) *}}@tv2i32
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -72,7 +72,7 @@ entry:
define <2 x float> @tv2f32() {
entry:
-; ALL-LABEL: {{_?}}tv2f32:{{ *}}{{(;|//)}}{{ *}}@tv2f32
+; ALL-LABEL: {{_?}}tv2f32:{{ *(;|//) *}}@tv2f32
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -82,7 +82,7 @@ entry:
define <16 x i8> @tv16i8() {
entry:
-; ALL-LABEL: {{_?}}tv16i8:{{ *}}{{(;|//)}}{{ *}}@tv16i8
+; ALL-LABEL: {{_?}}tv16i8:{{ *(;|//) *}}@tv16i8
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -92,7 +92,7 @@ entry:
define <8 x i16> @tv8i16() {
entry:
-; ALL-LABEL: {{_?}}tv8i16:{{ *}}{{(;|//)}}{{ *}}@tv8i16
+; ALL-LABEL: {{_?}}tv8i16:{{ *(;|//) *}}@tv8i16
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -102,7 +102,7 @@ entry:
define <4 x i32> @tv4i32() {
entry:
-; ALL-LABEL: {{_?}}tv4i32:{{ *}}{{(;|//)}}{{ *}}@tv4i32
+; ALL-LABEL: {{_?}}tv4i32:{{ *(;|//) *}}@tv4i32
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -112,7 +112,7 @@ entry:
define <2 x i64> @tv2i64() {
entry:
-; ALL-LABEL: {{_?}}tv2i64:{{ *}}{{(;|//)}}{{ *}}@tv2i64
+; ALL-LABEL: {{_?}}tv2i64:{{ *(;|//) *}}@tv2i64
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -122,7 +122,7 @@ entry:
define <4 x float> @tv4f32() {
entry:
-; ALL-LABEL: {{_?}}tv4f32:{{ *}}{{(;|//)}}{{ *}}@tv4f32
+; ALL-LABEL: {{_?}}tv4f32:{{ *(;|//) *}}@tv4f32
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -132,7 +132,7 @@ entry:
define <2 x double> @tv2d64() {
entry:
-; ALL-LABEL: {{_?}}tv2d64:{{ *}}{{(;|//)}}{{ *}}@tv2d64
+; ALL-LABEL: {{_?}}tv2d64:{{ *(;|//) *}}@tv2d64
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
@@ -142,7 +142,7 @@ entry:
; We used to produce spills+reloads for a Q register with zero cycle zeroing
; enabled.
-; ALL-LABEL: {{_?}}foo:{{ *}}{{(;|//)}}{{ *}}@foo
+; ALL-LABEL: {{_?}}foo:{{ *(;|//) *}}@foo
; ALL-NOT: str q{{[0-9]+}}
; ALL-NOT: ldr q{{[0-9]+}}
define double @foo(i32 %n) {
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
index abfd79e092395..1469e9486df16 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
@@ -10,35 +10,35 @@
define i8 @ti8() {
entry:
-; ALL-LABEL: {{_?}}ti8:{{ *}}{{(;|//)}}{{ *}}@ti8
+; ALL-LABEL: {{_?}}ti8:{{ *(;|//) *}}@ti8
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; ZCZ-GPR32: mov w0, #0{{ *(;|//) *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *(;|//) *}}=0x0
ret i8 0
}
define i16 @ti16() {
entry:
-; ALL-LABEL: {{_?}}ti16:{{ *}}{{(;|//)}}{{ *}}@ti16
+; ALL-LABEL: {{_?}}ti16:{{ *(;|//) *}}@ti16
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; ZCZ-GPR32: mov w0, #0{{ *(;|//) *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *(;|//) *}}=0x0
ret i16 0
}
define i32 @ti32() {
entry:
-; ALL-LABEL: {{_?}}ti32:{{ *}}{{(;|//)}}{{ *}}@ti32
+; ALL-LABEL: {{_?}}ti32:{{ *(;|//) *}}@ti32
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; ZCZ-GPR32: mov w0, #0{{ *(;|//) *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *(;|//) *}}=0x0
ret i32 0
}
define i64 @ti64() {
entry:
-; ALL-LABEL: {{_?}}ti64:{{ *}}{{(;|//)}}{{ *}}@ti64
+; ALL-LABEL: {{_?}}ti64:{{ *(;|//) *}}@ti64
; NOZCZ-GPR32-NOZCZ-GPR64: mov x0, xzr
-; ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; ZCZ-GPR64: mov x0, #0{{ *(;|//) *}}=0x0
ret i64 0
}
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