[llvm] 982dc4f - [X86] combineINSERT_SUBVECTOR - peek through BITCAST and EXTRACT_SUBVECTOR when trying to find shuffle combine candidates (#201781)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 5 02:27:57 PDT 2026
Author: Simon Pilgrim
Date: 2026-06-05T10:27:52+01:00
New Revision: 982dc4f20cce5c6b92b1d9e3235ecf84cc84e149
URL: https://github.com/llvm/llvm-project/commit/982dc4f20cce5c6b92b1d9e3235ecf84cc84e149
DIFF: https://github.com/llvm/llvm-project/commit/982dc4f20cce5c6b92b1d9e3235ecf84cc84e149.diff
LOG: [X86] combineINSERT_SUBVECTOR - peek through BITCAST and EXTRACT_SUBVECTOR when trying to find shuffle combine candidates (#201781)
Helps with some expanded CONCAT_VECTORS cases where both halves came
from wider shuffles.
More yak shaving for #199445
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
llvm/test/CodeGen/X86/x86-interleaved-access.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 230ef00300257..6148cf36e61e0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61717,9 +61717,16 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
}
}
+ auto peekThroughBitcastsAndExtracts = [](SDValue V) {
+ while (V.getOpcode() == ISD::BITCAST ||
+ V.getOpcode() == ISD::EXTRACT_SUBVECTOR)
+ V = V.getOperand(0);
+ return V;
+ };
+
// Attempt to recursively combine to a shuffle.
if (isTargetShuffle(peekThroughBitcasts(Vec).getOpcode()) &&
- isTargetShuffle(peekThroughBitcasts(SubVec).getOpcode())) {
+ isTargetShuffle(peekThroughBitcastsAndExtracts(SubVec).getOpcode())) {
SDValue Op(N, 0);
if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
return Res;
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
index 674bad2c7aa87..1ca16ee2ce56f 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
@@ -1178,8 +1178,8 @@ define void @store_i8_stride3_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
; AVX512-NEXT: vpshufb %ymm4, %ymm0, %ymm0
; AVX512-NEXT: vmovdqa %ymm1, 32(%rcx)
-; AVX512-NEXT: vmovdqa %ymm0, 64(%rcx)
; AVX512-NEXT: vmovdqa %ymm3, (%rcx)
+; AVX512-NEXT: vmovdqa %ymm0, 64(%rcx)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
;
@@ -1205,8 +1205,8 @@ define void @store_i8_stride3_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
; AVX512-FCP-NEXT: vpshufb %ymm4, %ymm0, %ymm0
; AVX512-FCP-NEXT: vmovdqa %ymm1, 32(%rcx)
-; AVX512-FCP-NEXT: vmovdqa %ymm0, 64(%rcx)
; AVX512-FCP-NEXT: vmovdqa %ymm3, (%rcx)
+; AVX512-FCP-NEXT: vmovdqa %ymm0, 64(%rcx)
; AVX512-FCP-NEXT: vzeroupper
; AVX512-FCP-NEXT: retq
;
@@ -1232,8 +1232,8 @@ define void @store_i8_stride3_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
; AVX512DQ-NEXT: vpshufb %ymm4, %ymm0, %ymm0
; AVX512DQ-NEXT: vmovdqa %ymm1, 32(%rcx)
-; AVX512DQ-NEXT: vmovdqa %ymm0, 64(%rcx)
; AVX512DQ-NEXT: vmovdqa %ymm3, (%rcx)
+; AVX512DQ-NEXT: vmovdqa %ymm0, 64(%rcx)
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
;
@@ -1259,8 +1259,8 @@ define void @store_i8_stride3_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
; AVX512DQ-FCP-NEXT: vpshufb %ymm4, %ymm0, %ymm0
; AVX512DQ-FCP-NEXT: vmovdqa %ymm1, 32(%rcx)
-; AVX512DQ-FCP-NEXT: vmovdqa %ymm0, 64(%rcx)
; AVX512DQ-FCP-NEXT: vmovdqa %ymm3, (%rcx)
+; AVX512DQ-FCP-NEXT: vmovdqa %ymm0, 64(%rcx)
; AVX512DQ-FCP-NEXT: vzeroupper
; AVX512DQ-FCP-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
index 21b98dbb3843e..3810bbd83ff28 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
@@ -1101,11 +1101,9 @@ define void @store_i8_stride4_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-NEXT: vpunpckhwd {{.*#+}} ymm1 = ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15]
; AVX512BW-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11]
; AVX512BW-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15]
-; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm2
-; AVX512BW-NEXT: vinserti128 $1, %xmm0, %ymm4, %ymm5
-; AVX512BW-NEXT: vinserti64x4 $1, %ymm5, %zmm2, %zmm2
; AVX512BW-NEXT: vinserti64x4 $1, %ymm0, %zmm4, %zmm0
; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm1
+; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm1[0,1,4,5],zmm0[0,1,4,5]
; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[2,3,6,7],zmm0[2,3,6,7]
; AVX512BW-NEXT: vmovdqa64 %zmm0, 64(%r8)
; AVX512BW-NEXT: vmovdqa64 %zmm2, (%r8)
@@ -1126,11 +1124,9 @@ define void @store_i8_stride4_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-FCP-NEXT: vpunpckhwd {{.*#+}} ymm1 = ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15]
; AVX512BW-FCP-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11]
; AVX512BW-FCP-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15]
-; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm2
-; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm0, %ymm4, %ymm5
-; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm5, %zmm2, %zmm2
; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm4, %zmm0
; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm1
+; AVX512BW-FCP-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm1[0,1,4,5],zmm0[0,1,4,5]
; AVX512BW-FCP-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[2,3,6,7],zmm0[2,3,6,7]
; AVX512BW-FCP-NEXT: vmovdqa64 %zmm0, 64(%r8)
; AVX512BW-FCP-NEXT: vmovdqa64 %zmm2, (%r8)
@@ -1151,11 +1147,9 @@ define void @store_i8_stride4_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-NEXT: vpunpckhwd {{.*#+}} ymm1 = ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15]
; AVX512DQ-BW-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11]
; AVX512DQ-BW-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15]
-; AVX512DQ-BW-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm2
-; AVX512DQ-BW-NEXT: vinserti128 $1, %xmm0, %ymm4, %ymm5
-; AVX512DQ-BW-NEXT: vinserti64x4 $1, %ymm5, %zmm2, %zmm2
; AVX512DQ-BW-NEXT: vinserti64x4 $1, %ymm0, %zmm4, %zmm0
; AVX512DQ-BW-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm1
+; AVX512DQ-BW-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm1[0,1,4,5],zmm0[0,1,4,5]
; AVX512DQ-BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[2,3,6,7],zmm0[2,3,6,7]
; AVX512DQ-BW-NEXT: vmovdqa64 %zmm0, 64(%r8)
; AVX512DQ-BW-NEXT: vmovdqa64 %zmm2, (%r8)
@@ -1176,11 +1170,9 @@ define void @store_i8_stride4_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-FCP-NEXT: vpunpckhwd {{.*#+}} ymm1 = ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15]
; AVX512DQ-BW-FCP-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11]
; AVX512DQ-BW-FCP-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15]
-; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm2
-; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm0, %ymm4, %ymm5
-; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm5, %zmm2, %zmm2
; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm4, %zmm0
; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm1
+; AVX512DQ-BW-FCP-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm1[0,1,4,5],zmm0[0,1,4,5]
; AVX512DQ-BW-FCP-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[2,3,6,7],zmm0[2,3,6,7]
; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm0, 64(%r8)
; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm2, (%r8)
@@ -1398,10 +1390,10 @@ define void @store_i8_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm8[2,3],ymm1[2,3]
; AVX2-NEXT: vmovdqa %ymm3, 192(%r8)
; AVX2-NEXT: vmovdqa %ymm1, 224(%r8)
-; AVX2-NEXT: vmovdqa %ymm2, 64(%r8)
-; AVX2-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX2-NEXT: vmovdqa %ymm7, 128(%r8)
; AVX2-NEXT: vmovdqa %ymm9, 160(%r8)
+; AVX2-NEXT: vmovdqa %ymm2, 64(%r8)
+; AVX2-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX2-NEXT: vmovdqa %ymm4, (%r8)
; AVX2-NEXT: vmovdqa %ymm5, 32(%r8)
; AVX2-NEXT: vzeroupper
@@ -1443,10 +1435,10 @@ define void @store_i8_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FP-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm8[2,3],ymm1[2,3]
; AVX2-FP-NEXT: vmovdqa %ymm3, 192(%r8)
; AVX2-FP-NEXT: vmovdqa %ymm1, 224(%r8)
-; AVX2-FP-NEXT: vmovdqa %ymm2, 64(%r8)
-; AVX2-FP-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX2-FP-NEXT: vmovdqa %ymm7, 128(%r8)
; AVX2-FP-NEXT: vmovdqa %ymm9, 160(%r8)
+; AVX2-FP-NEXT: vmovdqa %ymm2, 64(%r8)
+; AVX2-FP-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX2-FP-NEXT: vmovdqa %ymm4, (%r8)
; AVX2-FP-NEXT: vmovdqa %ymm5, 32(%r8)
; AVX2-FP-NEXT: vzeroupper
@@ -1488,10 +1480,10 @@ define void @store_i8_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FCP-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm8[2,3],ymm1[2,3]
; AVX2-FCP-NEXT: vmovdqa %ymm3, 192(%r8)
; AVX2-FCP-NEXT: vmovdqa %ymm1, 224(%r8)
-; AVX2-FCP-NEXT: vmovdqa %ymm2, 64(%r8)
-; AVX2-FCP-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX2-FCP-NEXT: vmovdqa %ymm7, 128(%r8)
; AVX2-FCP-NEXT: vmovdqa %ymm9, 160(%r8)
+; AVX2-FCP-NEXT: vmovdqa %ymm2, 64(%r8)
+; AVX2-FCP-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX2-FCP-NEXT: vmovdqa %ymm4, (%r8)
; AVX2-FCP-NEXT: vmovdqa %ymm5, 32(%r8)
; AVX2-FCP-NEXT: vzeroupper
@@ -1533,10 +1525,10 @@ define void @store_i8_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm8[2,3],ymm1[2,3]
; AVX512-NEXT: vmovdqa %ymm5, 192(%r8)
; AVX512-NEXT: vmovdqa %ymm1, 224(%r8)
-; AVX512-NEXT: vmovdqa %ymm4, 64(%r8)
-; AVX512-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX512-NEXT: vmovdqa %ymm7, 128(%r8)
; AVX512-NEXT: vmovdqa %ymm9, 160(%r8)
+; AVX512-NEXT: vmovdqa %ymm4, 64(%r8)
+; AVX512-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX512-NEXT: vmovdqa %ymm2, (%r8)
; AVX512-NEXT: vmovdqa %ymm3, 32(%r8)
; AVX512-NEXT: vzeroupper
@@ -1578,10 +1570,10 @@ define void @store_i8_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm8[2,3],ymm1[2,3]
; AVX512-FCP-NEXT: vmovdqa %ymm5, 192(%r8)
; AVX512-FCP-NEXT: vmovdqa %ymm1, 224(%r8)
-; AVX512-FCP-NEXT: vmovdqa %ymm4, 64(%r8)
-; AVX512-FCP-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX512-FCP-NEXT: vmovdqa %ymm7, 128(%r8)
; AVX512-FCP-NEXT: vmovdqa %ymm9, 160(%r8)
+; AVX512-FCP-NEXT: vmovdqa %ymm4, 64(%r8)
+; AVX512-FCP-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX512-FCP-NEXT: vmovdqa %ymm2, (%r8)
; AVX512-FCP-NEXT: vmovdqa %ymm3, 32(%r8)
; AVX512-FCP-NEXT: vzeroupper
@@ -1623,10 +1615,10 @@ define void @store_i8_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm8[2,3],ymm1[2,3]
; AVX512DQ-NEXT: vmovdqa %ymm5, 192(%r8)
; AVX512DQ-NEXT: vmovdqa %ymm1, 224(%r8)
-; AVX512DQ-NEXT: vmovdqa %ymm4, 64(%r8)
-; AVX512DQ-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX512DQ-NEXT: vmovdqa %ymm7, 128(%r8)
; AVX512DQ-NEXT: vmovdqa %ymm9, 160(%r8)
+; AVX512DQ-NEXT: vmovdqa %ymm4, 64(%r8)
+; AVX512DQ-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX512DQ-NEXT: vmovdqa %ymm2, (%r8)
; AVX512DQ-NEXT: vmovdqa %ymm3, 32(%r8)
; AVX512DQ-NEXT: vzeroupper
@@ -1668,10 +1660,10 @@ define void @store_i8_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm8[2,3],ymm1[2,3]
; AVX512DQ-FCP-NEXT: vmovdqa %ymm5, 192(%r8)
; AVX512DQ-FCP-NEXT: vmovdqa %ymm1, 224(%r8)
-; AVX512DQ-FCP-NEXT: vmovdqa %ymm4, 64(%r8)
-; AVX512DQ-FCP-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX512DQ-FCP-NEXT: vmovdqa %ymm7, 128(%r8)
; AVX512DQ-FCP-NEXT: vmovdqa %ymm9, 160(%r8)
+; AVX512DQ-FCP-NEXT: vmovdqa %ymm4, 64(%r8)
+; AVX512DQ-FCP-NEXT: vmovdqa %ymm0, 96(%r8)
; AVX512DQ-FCP-NEXT: vmovdqa %ymm2, (%r8)
; AVX512DQ-FCP-NEXT: vmovdqa %ymm3, 32(%r8)
; AVX512DQ-FCP-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
index 995607a6857bd..f31e815e186c3 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
@@ -220,9 +220,8 @@ define <16 x float> @shuffle_f32_v16f32_00_08_00_08_00_08_00_08_00_08_00_08_00_0
; FAST: # %bb.0:
; FAST-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; FAST-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; FAST-NEXT: vmovaps {{.*#+}} ymm2 = [0,16,0,16,0,16,0,16]
+; FAST-NEXT: vbroadcastsd {{.*#+}} zmm2 = [0,16,0,16,0,16,0,16,0,16,0,16,0,16,0,16]
; FAST-NEXT: vpermt2ps %zmm1, %zmm2, %zmm0
-; FAST-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
; FAST-NEXT: retq
%v0 = insertelement <8 x float> poison, float %a0, i64 0
%v1 = insertelement <8 x float> poison, float %a1, i64 0
diff --git a/llvm/test/CodeGen/X86/x86-interleaved-access.ll b/llvm/test/CodeGen/X86/x86-interleaved-access.ll
index 01c575ff401ed..70533c7e9ab27 100644
--- a/llvm/test/CodeGen/X86/x86-interleaved-access.ll
+++ b/llvm/test/CodeGen/X86/x86-interleaved-access.ll
@@ -285,11 +285,9 @@ define void @interleaved_store_vf32_i8_stride4(<32 x i8> %x1, <32 x i8> %x2, <32
; AVX512-NEXT: vpunpckhwd {{.*#+}} ymm1 = ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15]
; AVX512-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11]
; AVX512-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15]
-; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm2
-; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm4, %ymm5
-; AVX512-NEXT: vinserti64x4 $1, %ymm5, %zmm2, %zmm2
; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm4, %zmm0
; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm1
+; AVX512-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm1[0,1,4,5],zmm0[0,1,4,5]
; AVX512-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[2,3,6,7],zmm0[2,3,6,7]
; AVX512-NEXT: vmovdqa64 %zmm0, 64(%rdi)
; AVX512-NEXT: vmovdqa64 %zmm2, (%rdi)
@@ -1544,10 +1542,10 @@ define void @interleaved_store_vf64_i8_stride4(<64 x i8> %a, <64 x i8> %b, <64 x
; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm8[2,3],ymm1[2,3]
; AVX2-NEXT: vmovdqa %ymm1, 224(%rdi)
; AVX2-NEXT: vmovdqa %ymm3, 192(%rdi)
-; AVX2-NEXT: vmovdqa %ymm0, 96(%rdi)
-; AVX2-NEXT: vmovdqa %ymm2, 64(%rdi)
; AVX2-NEXT: vmovdqa %ymm9, 160(%rdi)
; AVX2-NEXT: vmovdqa %ymm7, 128(%rdi)
+; AVX2-NEXT: vmovdqa %ymm0, 96(%rdi)
+; AVX2-NEXT: vmovdqa %ymm2, 64(%rdi)
; AVX2-NEXT: vmovdqa %ymm5, 32(%rdi)
; AVX2-NEXT: vmovdqa %ymm4, (%rdi)
; AVX2-NEXT: vzeroupper
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