[llvm] d146ef7 - [RISCV] Enable combineAddMulh for vectors to improve div by constant. (#201657)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 4 21:28:30 PDT 2026
Author: Craig Topper
Date: 2026-06-04T21:28:25-07:00
New Revision: d146ef738a7bdde3b44bbbf23487f7de69dcfecb
URL: https://github.com/llvm/llvm-project/commit/d146ef738a7bdde3b44bbbf23487f7de69dcfecb
DIFF: https://github.com/llvm/llvm-project/commit/d146ef738a7bdde3b44bbbf23487f7de69dcfecb.diff
LOG: [RISCV] Enable combineAddMulh for vectors to improve div by constant. (#201657)
I modified the constant in some RVV division tests for coverage. I can
add new tests cases if that's preferred.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoP.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/test/CodeGen/RISCV/rvp-simd-32.ll
llvm/test/CodeGen/RISCV/rvp-simd-64.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d56cb0dd50474..690af51594056 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16391,11 +16391,11 @@ static SDValue combineAddOfBooleanXor(SDNode *N, SelectionDAG &DAG) {
// = X * 2^32 + hi * 2^32 + lo
// = (X + hi) * 2^32 + lo
// So mulhsu computes (X + hi).
-// TODO: Support vectors.
static SDValue combineAddMulh(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
EVT VT = N->getValueType(0);
- if (!Subtarget.hasStdExtZmmul() || VT != Subtarget.getXLenVT())
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ if (!TLI.isOperationLegal(ISD::MULHS, VT))
return SDValue();
using namespace SDPatternMatch;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index feb52f0c63fff..c2a8be1f17718 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2148,6 +2148,8 @@ let append Predicates = [IsRV32] in {
(PNSRLI_B (PWMUL_B GPR:$rs1, GPR:$rs2), 8)>;
def : Pat<(v4i8 (mulhu GPR:$rs1, GPR:$rs2)),
(PNSRLI_B (PWMULU_B GPR:$rs1, GPR:$rs2), 8)>;
+ def : Pat<(v4i8 (riscv_mulhsu GPR:$rs1, GPR:$rs2)),
+ (PNSRLI_B (PWMULSU_B GPR:$rs1, GPR:$rs2), 8)>;
// 8/16-bit bitreverse patterns
// FIXME: Use BREV8 with Zbkb.
@@ -2463,6 +2465,9 @@ let append Predicates = [IsRV64] in {
def : Pat<(v8i8 (mulhu GPR:$rs1, GPR:$rs2)),
(PPAIRO_B (PMULU_H_B00 GPR:$rs1, GPR:$rs2),
(PMULU_H_B11 GPR:$rs1, GPR:$rs2))>;
+ def : Pat<(v8i8 (riscv_mulhsu GPR:$rs1, GPR:$rs2)),
+ (PPAIRO_B (PMULSU_H_B00 GPR:$rs1, GPR:$rs2),
+ (PMULSU_H_B11 GPR:$rs1, GPR:$rs2))>;
// 32-bit logical shift left/right patterns
def : PatGprImm<riscv_pshl, PSLLI_W, uimm5, v2i32>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 2bba293d3f31e..3c8ab6bad5452 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1118,10 +1118,12 @@ defm : VPatBinarySDNode_VV_VX<mul, "PseudoVMUL">;
defm : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH", IntegerVectorsExceptI64>;
defm : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU", IntegerVectorsExceptI64>;
+defm : VPatBinarySDNode_VV_VX<riscv_mulhsu, "PseudoVMULHSU", IntegerVectorsExceptI64>;
let Predicates = [HasVInstructionsFullMultiply] in {
defm : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH", I64IntegerVectors>;
defm : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU", I64IntegerVectors>;
+ defm : VPatBinarySDNode_VV_VX<riscv_mulhsu, "PseudoVMULHSU", I64IntegerVectors>;
}
// 11.11. Vector Integer Divide Instructions
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index efc11fe524717..708df92cdd2c2 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -1526,6 +1526,21 @@ define <2 x i16> @test_psdiv_h(<2 x i16> %a, <2 x i16> %b) {
ret <2 x i16> %res
}
+define <2 x i16> @test_psdiv_mulhsu_h(<2 x i16> %a) {
+; CHECK-LABEL: test_psdiv_mulhsu_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048569
+; CHECK-NEXT: addi a1, a1, -1911
+; CHECK-NEXT: pmv.hs a1, a1
+; CHECK-NEXT: pmulhsu.h a0, a0, a1
+; CHECK-NEXT: psrai.h a0, a0, 3
+; CHECK-NEXT: psrli.h a1, a0, 15
+; CHECK-NEXT: padd.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = sdiv <2 x i16> %a, splat (i16 15)
+ ret <2 x i16> %res
+}
+
define <4 x i8> @test_psdiv_b(<4 x i8> %a, <4 x i8> %b) {
; RV32-LABEL: test_psdiv_b:
; RV32: # %bb.0:
@@ -1603,6 +1618,31 @@ define <2 x i16> @test_pudiv_h(<2 x i16> %a, <2 x i16> %b) {
ret <2 x i16> %res
}
+define <4 x i8> @test_psdiv_mulhsu_b(<4 x i8> %a) {
+; RV32-LABEL: test_psdiv_mulhsu_b:
+; RV32: # %bb.0:
+; RV32-NEXT: pli.b a1, -119
+; RV32-NEXT: pwmulsu.b a0, a0, a1
+; RV32-NEXT: pncvth.b a0, a0
+; RV32-NEXT: psrai.b a0, a0, 3
+; RV32-NEXT: psrli.b a1, a0, 7
+; RV32-NEXT: padd.b a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psdiv_mulhsu_b:
+; RV64: # %bb.0:
+; RV64-NEXT: pli.b a1, -119
+; RV64-NEXT: pmulsu.h.b11 a2, a0, a1
+; RV64-NEXT: pmulsu.h.b00 a0, a0, a1
+; RV64-NEXT: ppairo.b a0, a0, a2
+; RV64-NEXT: psrai.b a0, a0, 3
+; RV64-NEXT: psrli.b a1, a0, 7
+; RV64-NEXT: padd.b a0, a0, a1
+; RV64-NEXT: ret
+ %res = sdiv <4 x i8> %a, splat (i8 15)
+ ret <4 x i8> %res
+}
+
define <4 x i8> @test_pudiv_b(<4 x i8> %a, <4 x i8> %b) {
; RV32-LABEL: test_pudiv_b:
; RV32: # %bb.0:
@@ -2139,10 +2179,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB148_2
+; CHECK-NEXT: bnez a3, .LBB150_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB148_2:
+; CHECK-NEXT: .LBB150_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %res
@@ -2153,10 +2193,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB149_2
+; CHECK-NEXT: bnez a3, .LBB151_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB149_2:
+; CHECK-NEXT: .LBB151_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 04e7049c79e7a..bcb48f5dcfc74 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -2893,6 +2893,49 @@ define <4 x i16> @test_psdiv_h(<4 x i16> %a, <4 x i16> %b) {
ret <4 x i16> %res
}
+define <4 x i16> @test_psdiv_mulhsu_h(<4 x i16> %a) {
+; RV32-LABEL: test_psdiv_mulhsu_h:
+; RV32: # %bb.0:
+; RV32-NEXT: srai a2, a1, 16
+; RV32-NEXT: lui a3, 559241
+; RV32-NEXT: sext.h a1, a1
+; RV32-NEXT: srai a4, a0, 16
+; RV32-NEXT: sext.h a0, a0
+; RV32-NEXT: addi a3, a3, -1911
+; RV32-NEXT: mulhsu a2, a2, a3
+; RV32-NEXT: mulhsu a1, a1, a3
+; RV32-NEXT: mulhsu a4, a4, a3
+; RV32-NEXT: mulhsu a0, a0, a3
+; RV32-NEXT: srli a3, a2, 31
+; RV32-NEXT: srai a2, a2, 3
+; RV32-NEXT: add a2, a2, a3
+; RV32-NEXT: srli a3, a1, 31
+; RV32-NEXT: srai a1, a1, 3
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: srli a3, a4, 31
+; RV32-NEXT: srai a4, a4, 3
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: srli a4, a0, 31
+; RV32-NEXT: srai a0, a0, 3
+; RV32-NEXT: add a0, a0, a4
+; RV32-NEXT: pack a1, a1, a2
+; RV32-NEXT: pack a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psdiv_mulhsu_h:
+; RV64: # %bb.0:
+; RV64-NEXT: lui a1, 1048569
+; RV64-NEXT: addi a1, a1, -1911
+; RV64-NEXT: pmv.hs a1, a1
+; RV64-NEXT: pmulhsu.h a0, a0, a1
+; RV64-NEXT: psrai.h a0, a0, 3
+; RV64-NEXT: psrli.h a1, a0, 15
+; RV64-NEXT: padd.h a0, a0, a1
+; RV64-NEXT: ret
+ %res = sdiv <4 x i16> %a, splat (i16 15)
+ ret <4 x i16> %res
+}
+
define <8 x i8> @test_psdiv_b(<8 x i8> %a, <8 x i8> %b) {
; RV32-LABEL: test_psdiv_b:
; RV32: # %bb.0:
@@ -2986,6 +3029,77 @@ define <8 x i8> @test_psdiv_b(<8 x i8> %a, <8 x i8> %b) {
ret <8 x i8> %res
}
+define <8 x i8> @test_psdiv_mulhsu_b(<8 x i8> %a) {
+; RV32-LABEL: test_psdiv_mulhsu_b:
+; RV32: # %bb.0:
+; RV32-NEXT: srai a2, a1, 24
+; RV32-NEXT: lui a3, 559241
+; RV32-NEXT: slli a4, a1, 8
+; RV32-NEXT: sext.b a5, a1
+; RV32-NEXT: slli a1, a1, 16
+; RV32-NEXT: srai a6, a0, 24
+; RV32-NEXT: slli a7, a0, 8
+; RV32-NEXT: sext.b t0, a0
+; RV32-NEXT: slli a0, a0, 16
+; RV32-NEXT: addi a3, a3, -1911
+; RV32-NEXT: srai a4, a4, 24
+; RV32-NEXT: srai a1, a1, 24
+; RV32-NEXT: srai a7, a7, 24
+; RV32-NEXT: srai a0, a0, 24
+; RV32-NEXT: mulhsu a2, a2, a3
+; RV32-NEXT: mulhsu a4, a4, a3
+; RV32-NEXT: mulhsu a5, a5, a3
+; RV32-NEXT: mulhsu a1, a1, a3
+; RV32-NEXT: mulhsu a6, a6, a3
+; RV32-NEXT: mulhsu a7, a7, a3
+; RV32-NEXT: mulhsu t0, t0, a3
+; RV32-NEXT: mulhsu a0, a0, a3
+; RV32-NEXT: srli a3, a2, 31
+; RV32-NEXT: srai a2, a2, 3
+; RV32-NEXT: add a2, a2, a3
+; RV32-NEXT: srli a3, a4, 31
+; RV32-NEXT: srai a4, a4, 3
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: srli a4, a5, 31
+; RV32-NEXT: srai a5, a5, 3
+; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: srli a5, a1, 31
+; RV32-NEXT: srai a1, a1, 3
+; RV32-NEXT: add a1, a1, a5
+; RV32-NEXT: srli a5, a6, 31
+; RV32-NEXT: srai a6, a6, 3
+; RV32-NEXT: add a5, a6, a5
+; RV32-NEXT: srli a6, a7, 31
+; RV32-NEXT: srai a7, a7, 3
+; RV32-NEXT: add a6, a7, a6
+; RV32-NEXT: srli a7, t0, 31
+; RV32-NEXT: srai t0, t0, 3
+; RV32-NEXT: add a7, t0, a7
+; RV32-NEXT: srli t0, a0, 31
+; RV32-NEXT: srai a0, a0, 3
+; RV32-NEXT: add a0, a0, t0
+; RV32-NEXT: ppaire.b a2, a3, a2
+; RV32-NEXT: ppaire.b a1, a4, a1
+; RV32-NEXT: ppaire.b a3, a6, a5
+; RV32-NEXT: ppaire.b a0, a7, a0
+; RV32-NEXT: pack a1, a1, a2
+; RV32-NEXT: pack a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psdiv_mulhsu_b:
+; RV64: # %bb.0:
+; RV64-NEXT: pli.b a1, -119
+; RV64-NEXT: pmulsu.h.b11 a2, a0, a1
+; RV64-NEXT: pmulsu.h.b00 a0, a0, a1
+; RV64-NEXT: ppairo.b a0, a0, a2
+; RV64-NEXT: psrai.b a0, a0, 3
+; RV64-NEXT: psrli.b a1, a0, 7
+; RV64-NEXT: padd.b a0, a0, a1
+; RV64-NEXT: ret
+ %res = sdiv <8 x i8> %a, splat (i8 15)
+ ret <8 x i8> %res
+}
+
define <2 x i32> @test_psdiv_w(<2 x i32> %a, <2 x i32> %b) {
; RV32-LABEL: test_psdiv_w:
; RV32: # %bb.0:
@@ -3005,6 +3119,35 @@ define <2 x i32> @test_psdiv_w(<2 x i32> %a, <2 x i32> %b) {
ret <2 x i32> %res
}
+define <2 x i32> @test_psdiv_mulhsu_w(<2 x i32> %a) {
+; RV32-LABEL: test_psdiv_mulhsu_w:
+; RV32: # %bb.0:
+; RV32-NEXT: lui a2, 599186
+; RV32-NEXT: addi a2, a2, 1171
+; RV32-NEXT: mulhsu a1, a1, a2
+; RV32-NEXT: mulhsu a0, a0, a2
+; RV32-NEXT: srli a2, a1, 31
+; RV32-NEXT: srai a1, a1, 2
+; RV32-NEXT: srli a3, a0, 31
+; RV32-NEXT: srai a0, a0, 2
+; RV32-NEXT: add a1, a1, a2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psdiv_mulhsu_w:
+; RV64: # %bb.0:
+; RV64-NEXT: lui a1, 599186
+; RV64-NEXT: addi a1, a1, 1171
+; RV64-NEXT: pmv.ws a1, a1
+; RV64-NEXT: pmulhsu.w a0, a0, a1
+; RV64-NEXT: psrai.w a0, a0, 2
+; RV64-NEXT: psrli.w a1, a0, 31
+; RV64-NEXT: padd.w a0, a0, a1
+; RV64-NEXT: ret
+ %res = sdiv <2 x i32> %a, splat (i32 7)
+ ret <2 x i32> %res
+}
+
define <4 x i16> @test_pudiv_h(<4 x i16> %a, <4 x i16> %b) {
; RV32-LABEL: test_pudiv_h:
; RV32: # %bb.0:
@@ -4239,12 +4382,12 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; RV32-LABEL: test_select_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB215_2
+; RV32-NEXT: bnez a5, .LBB218_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB215_2:
+; RV32-NEXT: .LBB218_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4253,10 +4396,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB215_2
+; RV64-NEXT: bnez a3, .LBB218_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB215_2:
+; RV64-NEXT: .LBB218_2:
; RV64-NEXT: ret
%res = select i1 %cond, <4 x i16> %a, <4 x i16> %b
ret <4 x i16> %res
@@ -4266,12 +4409,12 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; RV32-LABEL: test_select_v8i8:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB216_2
+; RV32-NEXT: bnez a5, .LBB219_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB216_2:
+; RV32-NEXT: .LBB219_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4280,10 +4423,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB216_2
+; RV64-NEXT: bnez a3, .LBB219_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB216_2:
+; RV64-NEXT: .LBB219_2:
; RV64-NEXT: ret
%res = select i1 %cond, <8 x i8> %a, <8 x i8> %b
ret <8 x i8> %res
@@ -4293,12 +4436,12 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; RV32-LABEL: test_select_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB217_2
+; RV32-NEXT: bnez a5, .LBB220_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB217_2:
+; RV32-NEXT: .LBB220_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4307,10 +4450,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB217_2
+; RV64-NEXT: bnez a3, .LBB220_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB217_2:
+; RV64-NEXT: .LBB220_2:
; RV64-NEXT: ret
%res = select i1 %cond, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %res
@@ -4358,16 +4501,16 @@ define <2 x i32> @test_vselect_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; RV32: # %bb.0:
; RV32-NEXT: pmslt.dw a6, a2, a0
; RV32-NEXT: mv a0, a4
-; RV32-NEXT: beqz a7, .LBB220_3
+; RV32-NEXT: beqz a7, .LBB223_3
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: beqz a6, .LBB220_4
-; RV32-NEXT: .LBB220_2:
+; RV32-NEXT: beqz a6, .LBB223_4
+; RV32-NEXT: .LBB223_2:
; RV32-NEXT: mv a1, a5
; RV32-NEXT: ret
-; RV32-NEXT: .LBB220_3:
+; RV32-NEXT: .LBB223_3:
; RV32-NEXT: mv a5, a3
-; RV32-NEXT: bnez a6, .LBB220_2
-; RV32-NEXT: .LBB220_4:
+; RV32-NEXT: bnez a6, .LBB223_2
+; RV32-NEXT: .LBB223_4:
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a5
; RV32-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
index de15e185998c4..bd481f6a374d5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
@@ -530,11 +530,10 @@ define <vscale x 1 x i32> @vdiv_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %
define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; RV32-LABEL: vdiv_vi_nxv1i32_0:
; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
+; RV32-NEXT: lui a0, 599186
+; RV32-NEXT: addi a0, a0, 1171
; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmulh.vx v9, v8, a0
-; RV32-NEXT: vsub.vv v8, v9, v8
+; RV32-NEXT: vmulhsu.vx v8, v8, a0
; RV32-NEXT: vsrl.vi v9, v8, 31
; RV32-NEXT: vsra.vi v8, v8, 2
; RV32-NEXT: vadd.vv v8, v8, v9
@@ -542,16 +541,15 @@ define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
;
; RV64-LABEL: vdiv_vi_nxv1i32_0:
; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
+; RV64-NEXT: lui a0, 599186
+; RV64-NEXT: addi a0, a0, 1171
; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmulh.vx v9, v8, a0
-; RV64-NEXT: vsub.vv v8, v9, v8
+; RV64-NEXT: vmulhsu.vx v8, v8, a0
; RV64-NEXT: vsra.vi v8, v8, 2
; RV64-NEXT: vsrl.vi v9, v8, 31
; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: ret
- %vc = sdiv <vscale x 1 x i32> %va, splat (i32 -7)
+ %vc = sdiv <vscale x 1 x i32> %va, splat (i32 7)
ret <vscale x 1 x i32> %vc
}
@@ -1039,19 +1037,18 @@ define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16
-; RV32-V-NEXT: lui a0, 748983
-; RV32-V-NEXT: lui a1, 898779
-; RV32-V-NEXT: addi a0, a0, -586
-; RV32-V-NEXT: addi a1, a1, 1755
-; RV32-V-NEXT: sw a1, 8(sp)
-; RV32-V-NEXT: sw a0, 12(sp)
-; RV32-V-NEXT: addi a0, sp, 8
-; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; RV32-V-NEXT: vlse64.v v16, (a0), zero
+; RV32-V-NEXT: lui a0, 559241
+; RV32-V-NEXT: addi a1, sp, 8
+; RV32-V-NEXT: addi a2, a0, -1912
+; RV32-V-NEXT: addi a0, a0, -1911
+; RV32-V-NEXT: sw a0, 8(sp)
+; RV32-V-NEXT: sw a2, 12(sp)
+; RV32-V-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-V-NEXT: vlse64.v v16, (a1), zero
; RV32-V-NEXT: li a0, 63
-; RV32-V-NEXT: vmulh.vv v8, v8, v16
+; RV32-V-NEXT: vmulhsu.vv v8, v8, v16
; RV32-V-NEXT: vsrl.vx v16, v8, a0
-; RV32-V-NEXT: vsra.vi v8, v8, 1
+; RV32-V-NEXT: vsra.vi v8, v8, 3
; RV32-V-NEXT: vadd.vv v8, v8, v16
; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: .cfi_def_cfa_offset 0
@@ -1059,23 +1056,25 @@ define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
;
; ZVE64X-LABEL: vdiv_vi_nxv8i64_0:
; ZVE64X: # %bb.0:
-; ZVE64X-NEXT: li a0, -7
+; ZVE64X-NEXT: li a0, 15
; ZVE64X-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; ZVE64X-NEXT: vdiv.vx v8, v8, a0
; ZVE64X-NEXT: ret
;
; RV64-V-LABEL: vdiv_vi_nxv8i64_0:
; RV64-V: # %bb.0:
-; RV64-V-NEXT: lui a0, %hi(.LCPI67_0)
-; RV64-V-NEXT: ld a0, %lo(.LCPI67_0)(a0)
-; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; RV64-V-NEXT: vmulh.vx v8, v8, a0
-; RV64-V-NEXT: li a0, 63
-; RV64-V-NEXT: vsrl.vx v16, v8, a0
-; RV64-V-NEXT: vsra.vi v8, v8, 1
+; RV64-V-NEXT: lui a0, 559241
+; RV64-V-NEXT: addi a0, a0, -1911
+; RV64-V-NEXT: slli a1, a0, 32
+; RV64-V-NEXT: add a0, a0, a1
+; RV64-V-NEXT: li a1, 63
+; RV64-V-NEXT: vsetvli a2, zero, e64, m8, ta, ma
+; RV64-V-NEXT: vmulhsu.vx v8, v8, a0
+; RV64-V-NEXT: vsrl.vx v16, v8, a1
+; RV64-V-NEXT: vsra.vi v8, v8, 3
; RV64-V-NEXT: vadd.vv v8, v8, v16
; RV64-V-NEXT: ret
- %vc = sdiv <vscale x 8 x i64> %va, splat (i64 -7)
+ %vc = sdiv <vscale x 8 x i64> %va, splat (i64 15)
ret <vscale x 8 x i64> %vc
}
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