[llvm] [X86] Fix crash in LowerMSTORE on AVX512F with VLX (PR #201609)

[Phoebe Wang via llvm-commits]

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@@ -0,0 +1,149 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefix=AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=AVX512VL
+
+; On AVX512F targets without VLX (e.g. KNL), masked stores are widened to 512
+; bits during custom lowering. A maxnum/minnum store-back fuses the legacy CMPP
+; vector comparison into the masked store, so the mask arrives as vNi32 rather
+; than vNi1. The lowering must accept and convert the wide mask, not assert.
+
+define void @maxnum_v4f32_masked_store(<4 x float> %a, ptr %ptr) {
+; AVX512F-LABEL: maxnum_v4f32_masked_store:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    vmovups (%rdi), %xmm1
+; AVX512F-NEXT:    vmaxps %xmm0, %xmm1, %xmm1
+; AVX512F-NEXT:    vcmpordps %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT:    vptestmd %zmm0, %zmm0, %k1
+; AVX512F-NEXT:    vmovups %zmm1, (%rdi) {%k1}
+; AVX512F-NEXT:    vzeroupper
+; AVX512F-NEXT:    retq
+;
+; AVX512VL-LABEL: maxnum_v4f32_masked_store:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vmovups (%rdi), %xmm1
+; AVX512VL-NEXT:    vmaxps %xmm0, %xmm1, %xmm1
+; AVX512VL-NEXT:    vcmpordps %xmm0, %xmm0, %k1
+; AVX512VL-NEXT:    vmovups %xmm1, (%rdi) {%k1}
+; AVX512VL-NEXT:    retq
+  %b = load <4 x float>, ptr %ptr, align 4
+  %m = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
+  store <4 x float> %m, ptr %ptr, align 4
+  ret void
+}
+
+define void @maxnum_v2f64_masked_store(<2 x double> %a, ptr %ptr) {
+; AVX512F-LABEL: maxnum_v2f64_masked_store:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    vmovupd (%rdi), %xmm1
+; AVX512F-NEXT:    vmaxpd %xmm0, %xmm1, %xmm1
+; AVX512F-NEXT:    vcmpordpd %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT:    vptestmq %zmm0, %zmm0, %k1
+; AVX512F-NEXT:    vmovupd %zmm1, (%rdi) {%k1}
+; AVX512F-NEXT:    vzeroupper
+; AVX512F-NEXT:    retq
+;
+; AVX512VL-LABEL: maxnum_v2f64_masked_store:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vmovupd (%rdi), %xmm1
+; AVX512VL-NEXT:    vmaxpd %xmm0, %xmm1, %xmm1
+; AVX512VL-NEXT:    vcmpordpd %xmm0, %xmm0, %k1
+; AVX512VL-NEXT:    vmovupd %xmm1, (%rdi) {%k1}
+; AVX512VL-NEXT:    retq
+  %b = load <2 x double>, ptr %ptr, align 8
+  %m = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b)
+  store <2 x double> %m, ptr %ptr, align 8
+  ret void
+}
+
+define void @minnum_v4f32_masked_store(<4 x float> %a, ptr %ptr) {
+; AVX512F-LABEL: minnum_v4f32_masked_store:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    vmovups (%rdi), %xmm1
+; AVX512F-NEXT:    vminps %xmm0, %xmm1, %xmm1
+; AVX512F-NEXT:    vcmpordps %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT:    vptestmd %zmm0, %zmm0, %k1
+; AVX512F-NEXT:    vmovups %zmm1, (%rdi) {%k1}
+; AVX512F-NEXT:    vzeroupper
+; AVX512F-NEXT:    retq
+;
+; AVX512VL-LABEL: minnum_v4f32_masked_store:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vmovups (%rdi), %xmm1
+; AVX512VL-NEXT:    vminps %xmm0, %xmm1, %xmm1
+; AVX512VL-NEXT:    vcmpordps %xmm0, %xmm0, %k1
+; AVX512VL-NEXT:    vmovups %xmm1, (%rdi) {%k1}
+; AVX512VL-NEXT:    retq
+  %b = load <4 x float>, ptr %ptr, align 4
+  %m = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
+  store <4 x float> %m, ptr %ptr, align 4
+  ret void
+}
+
+define void @minnum_v2f64_masked_store(<2 x double> %a, ptr %ptr) {
+; AVX512F-LABEL: minnum_v2f64_masked_store:
+; AVX512F:       # %bb.0:
+; AVX512F-NEXT:    vmovupd (%rdi), %xmm1
+; AVX512F-NEXT:    vminpd %xmm0, %xmm1, %xmm1
+; AVX512F-NEXT:    vcmpordpd %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT:    vptestmq %zmm0, %zmm0, %k1
+; AVX512F-NEXT:    vmovupd %zmm1, (%rdi) {%k1}
+; AVX512F-NEXT:    vzeroupper
+; AVX512F-NEXT:    retq
+;
+; AVX512VL-LABEL: minnum_v2f64_masked_store:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vmovupd (%rdi), %xmm1
+; AVX512VL-NEXT:    vminpd %xmm0, %xmm1, %xmm1
+; AVX512VL-NEXT:    vcmpordpd %xmm0, %xmm0, %k1
+; AVX512VL-NEXT:    vmovupd %xmm1, (%rdi) {%k1}
+; AVX512VL-NEXT:    retq
+  %b = load <2 x double>, ptr %ptr, align 8
+  %m = call <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b)
+  store <2 x double> %m, ptr %ptr, align 8
+  ret void
+}
+
+; Explicit masked store using a setcc mask (reaches LowerMSTORE with an i1 mask).
+define void @explicit_masked_store_setcc(<4 x float> %a, <4 x float> %data, ptr %ptr) {
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phoebewang wrote:

This passes without the change: https://godbolt.org/z/EYaebqxzq

https://github.com/llvm/llvm-project/pull/201609