[compiler-rt] [LLVM][compiler-rt][RISCV] Refactor RISC-V CPU features (PR #199438)

[Brad Smith via llvm-commits]

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@@ -0,0 +1,27 @@
+// On platforms that have not implemented this yet, we provide an implementation
+// that does not claim support for any features by leaving
+// __riscv_feature_bits.feature_bits initialized to 0.
+
+static int FeaturesBitCached = 0;
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brad0 wrote:

and I will remove that one variable now since it does not do anything.

https://github.com/llvm/llvm-project/pull/199438