[llvm] [AMDGPU] Make SGPR occupancy the exact inverse of getMaxNumSGPRs (PR #201342)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 4 08:18:59 PDT 2026
https://github.com/michaelselehov updated https://github.com/llvm/llvm-project/pull/201342
>From 61348e57919c915ae9214cd7b36c9b6f5c99c7b9 Mon Sep 17 00:00:00 2001
From: mselehov <mselehov at amd.com>
Date: Wed, 3 Jun 2026 06:29:25 -0500
Subject: [PATCH 1/5] [AMDGPU] Make SGPR occupancy the exact inverse of
getMaxNumSGPRs
The SGPR->occupancy table ignored the allocation granule and the
trap-handler reservation, so it disagreed with getMaxNumSGPRs() (e.g.
80 and 81 SGPRs reported the same occupancy and hid the cliff). Compute
occupancy by inverting the per-wave SGPR budget instead, sharing one
helper (getSGPRBudgetPerWave) with getMaxNumSGPRs()/getMinNumSGPRs() so
the budget and its inverse cannot drift apart. Thread that budget
(total/granule/trap reserve) through the occupancy MCExpr because the
asm printer's MCSubtargetInfo does not carry the implicit amdhsa
+trap-handler feature.
This aligns the SGPR-limited occupancy heuristic with the register
budget for all pre-GFX10 targets (including non-trap), which accounts
for the codegen test updates.
Assisted-by: Claude Opus
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 21 +-
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 3 +-
.../AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp | 29 +-
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 82 +-
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 22 +-
.../CodeGen/AMDGPU/agpr-register-count.ll | 4 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 12600 ++++++++--------
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 2423 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll | 88 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll | 40 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 935 +-
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll | 1375 +-
llvm/test/CodeGen/AMDGPU/load-constant-i32.ll | 481 +-
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll | 855 +-
llvm/test/CodeGen/AMDGPU/load-global-i16.ll | 310 +-
llvm/test/CodeGen/AMDGPU/load-global-i8.ll | 22 +-
.../machine-scheduler-sink-trivial-remats.mir | 18 +-
llvm/test/CodeGen/AMDGPU/occupancy-levels.ll | 17 +-
.../AMDGPU/resource-optimization-remarks.ll | 4 +-
.../AMDGPU/schedule-amdgpu-tracker-physreg.ll | 4 +-
.../AMDGPU/long-branch-reg-all-sgpr-used.ll | 4 +-
.../AMDGPU/machine-function-info-after-pei.ll | 2 +-
llvm/test/MC/AMDGPU/occupancy_mcexpr.s | 73 +-
23 files changed, 9840 insertions(+), 9572 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index d32cdb6d960fc..45036661fbf2c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -436,16 +436,25 @@ const AMDGPUMCExpr *createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
unsigned TargetTotalNumVGPRs = IsaInfo::getTotalNumVGPRs(STM);
unsigned Generation = STM.getGeneration();
+ // SGPR budget of the code generator's subtarget, so the printed occupancy
+ // matches what codegen assumed. In particular STM carries the implicit
+ // amdhsa trap-handler feature, which the asm printer's MCSubtargetInfo does
+ // not, so the reservation has to be threaded through explicitly here.
+ unsigned SGPRTotal = IsaInfo::getTotalNumSGPRs(STM);
+ unsigned SGPRGranule = IsaInfo::getSGPRAllocGranule(STM);
+ unsigned SGPRTrapReserve = STM.hasTrapHandler() ? IsaInfo::TRAP_NUM_SGPRS : 0;
+
auto CreateExpr = [&Ctx](unsigned Value) {
return MCConstantExpr::create(Value, Ctx);
};
- return AMDGPUMCExpr::create(AMDGPUMCExpr::AGVK_Occupancy,
- {CreateExpr(MaxWaves), CreateExpr(Granule),
- CreateExpr(TargetTotalNumVGPRs),
- CreateExpr(Generation), CreateExpr(InitOcc),
- NumSGPRs, NumVGPRs},
- Ctx);
+ return AMDGPUMCExpr::create(
+ AMDGPUMCExpr::AGVK_Occupancy,
+ {CreateExpr(MaxWaves), CreateExpr(Granule),
+ CreateExpr(TargetTotalNumVGPRs), CreateExpr(Generation),
+ CreateExpr(InitOcc), NumSGPRs, NumVGPRs, CreateExpr(SGPRTotal),
+ CreateExpr(SGPRGranule), CreateExpr(SGPRTrapReserve)},
+ Ctx);
}
void AMDGPUAsmPrinter::validateMCResourceInfo(Function &F) {
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index f47cb4ee50970..5d736aa3ad528 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -423,8 +423,7 @@ bool GCNSubtarget::useVGPRIndexMode() const {
bool GCNSubtarget::useAA() const { return UseAA; }
unsigned GCNSubtarget::getOccupancyWithNumSGPRs(unsigned SGPRs) const {
- return AMDGPU::IsaInfo::getOccupancyWithNumSGPRs(SGPRs, getMaxWavesPerEU(),
- getGeneration());
+ return AMDGPU::IsaInfo::getOccupancyWithNumSGPRs(*this, SGPRs);
}
unsigned
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
index 9a4c4ebddd50b..86501cab0d479 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
@@ -167,7 +167,12 @@ bool AMDGPUMCExpr::evaluateAlignTo(MCValue &Res, const MCAssembler *Asm) const {
bool AMDGPUMCExpr::evaluateOccupancy(MCValue &Res,
const MCAssembler *Asm) const {
uint64_t InitOccupancy, MaxWaves, Granule, TargetTotalNumVGPRs, Generation,
- NumSGPRs, NumVGPRs;
+ NumSGPRs, NumVGPRs, SGPRTotal, SGPRGranule, SGPRTrapReserve;
+
+ // createOccupancy() always emits exactly these ten operands; bail out rather
+ // than read out of bounds if a hand-written expression has a different arity.
+ if (Args.size() != 10)
+ return false;
bool Success = evaluateMCExprs(
Args.slice(0, 5), Asm,
@@ -178,12 +183,24 @@ bool AMDGPUMCExpr::evaluateOccupancy(MCValue &Res,
if (!Success || !evaluateMCExprs(Args.slice(5, 2), Asm, {NumSGPRs, NumVGPRs}))
return false;
+ // Arguments 8 to 10 carry the SGPR budget of the code-generator's subtarget
+ // (total SGPRs, allocation granule, and the trap-handler reservation). They
+ // let the SGPR-limited occupancy be computed exactly as the code generator
+ // does (in particular trap-handler aware), instead of from the asm printer's
+ // MCSubtargetInfo which does not carry the implicit amdhsa features.
+ if (!evaluateMCExprs(Args.slice(7, 3), Asm,
+ {SGPRTotal, SGPRGranule, SGPRTrapReserve}))
+ return false;
+
unsigned Occupancy = InitOccupancy;
- if (NumSGPRs)
- Occupancy = std::min(
- Occupancy, IsaInfo::getOccupancyWithNumSGPRs(
- NumSGPRs, MaxWaves,
- static_cast<AMDGPUSubtarget::Generation>(Generation)));
+ // Mirror the GFX10+ rule of the getOccupancyWithNumSGPRs(MCSubtargetInfo)
+ // overload: on GFX10+ the SGPR file is large enough that SGPRs never limit
+ // occupancy. The MC layer only has the decoded Generation here, so it tests
+ // that rather than an MCSubtargetInfo.
+ if (NumSGPRs && Generation < AMDGPUSubtarget::GFX10)
+ Occupancy = std::min(Occupancy, IsaInfo::getOccupancyWithNumSGPRs(
+ NumSGPRs, MaxWaves, SGPRTotal,
+ SGPRGranule, SGPRTrapReserve));
if (NumVGPRs)
Occupancy = std::min(Occupancy,
IsaInfo::getNumWavesPerEUWithNumVGPRs(
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 33df51e8a7e07..23254f0ffc5e1 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1334,6 +1334,27 @@ unsigned getAddressableNumSGPRs(const MCSubtargetInfo &STI) {
return 104;
}
+// Per-wave SGPRs reserved for the trap handler when it is enabled, in the same
+// units as the budget computations below.
+static unsigned getSGPRTrapHandlerReserve(const MCSubtargetInfo &STI) {
+ return STI.getFeatureBits().test(FeatureTrapHandler) ? TRAP_NUM_SGPRS : 0;
+}
+
+// SGPRs usable per wave when \p WavesPerEU waves share the register file,
+// before any addressable clamp: the trap-handler reservation is taken off the
+// top and the remainder is rounded down to the allocation \p Granule. This is
+// the single source of truth shared by getMinNumSGPRs(), getMaxNumSGPRs() and
+// the occupancy inverse getOccupancyWithNumSGPRs(), so the budget and its
+// inverse cannot drift apart.
+static unsigned getSGPRBudgetPerWave(unsigned TotalNumSGPRs,
+ unsigned WavesPerEU, unsigned TrapReserve,
+ unsigned Granule) {
+ assert(WavesPerEU != 0 && Granule != 0);
+ unsigned Budget = TotalNumSGPRs / WavesPerEU;
+ Budget -= std::min(Budget, TrapReserve);
+ return alignDown(Budget, Granule);
+}
+
unsigned getMinNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU) {
assert(WavesPerEU != 0);
@@ -1344,10 +1365,11 @@ unsigned getMinNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU) {
if (WavesPerEU >= getMaxWavesPerEU(STI))
return 0;
- unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
- if (STI.getFeatureBits().test(FeatureTrapHandler))
- MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
- MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
+ unsigned MinNumSGPRs =
+ getSGPRBudgetPerWave(getTotalNumSGPRs(STI), WavesPerEU + 1,
+ getSGPRTrapHandlerReserve(STI),
+ getSGPRAllocGranule(STI)) +
+ 1;
return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
}
@@ -1361,10 +1383,9 @@ unsigned getMaxNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
return Addressable ? AddressableNumSGPRs : 108;
if (Version.Major >= 8 && !Addressable)
AddressableNumSGPRs = 112;
- unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
- if (STI.getFeatureBits().test(FeatureTrapHandler))
- MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
- MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
+ unsigned MaxNumSGPRs = getSGPRBudgetPerWave(getTotalNumSGPRs(STI), WavesPerEU,
+ getSGPRTrapHandlerReserve(STI),
+ getSGPRAllocGranule(STI));
return std::min(MaxNumSGPRs, AddressableNumSGPRs);
}
@@ -1499,30 +1520,31 @@ unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
}
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
- AMDGPUSubtarget::Generation Gen) {
- if (Gen >= AMDGPUSubtarget::GFX10)
+ unsigned TotalNumSGPRs, unsigned Granule,
+ unsigned TrapReserve) {
+ // Invert getMaxNumSGPRs(): find the largest number of waves W whose per-wave
+ // SGPR budget still accommodates \p SGPRs. Higher occupancy means a smaller
+ // budget, so search from the maximum downwards and return the first fit. The
+ // budget is computed by the same helper getMaxNumSGPRs() uses, so the two
+ // stay exact inverses (modulo the addressable clamp, which is intentionally
+ // not applied here - see the header).
+ for (unsigned Waves = MaxWaves; Waves > 1; --Waves)
+ if (SGPRs <=
+ getSGPRBudgetPerWave(TotalNumSGPRs, Waves, TrapReserve, Granule))
+ return Waves;
+ return 1;
+}
+
+unsigned getOccupancyWithNumSGPRs(const MCSubtargetInfo &STI, unsigned SGPRs) {
+ unsigned MaxWaves = getMaxWavesPerEU(STI);
+
+ // On GFX10+ the SGPR file is large enough that SGPRs never limit occupancy.
+ if (getIsaVersion(STI.getCPU()).Major >= 10)
return MaxWaves;
- if (Gen >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
- if (SGPRs <= 80)
- return 10;
- if (SGPRs <= 88)
- return 9;
- if (SGPRs <= 100)
- return 8;
- return 7;
- }
- if (SGPRs <= 48)
- return 10;
- if (SGPRs <= 56)
- return 9;
- if (SGPRs <= 64)
- return 8;
- if (SGPRs <= 72)
- return 7;
- if (SGPRs <= 80)
- return 6;
- return 5;
+ return getOccupancyWithNumSGPRs(SGPRs, MaxWaves, getTotalNumSGPRs(STI),
+ getSGPRAllocGranule(STI),
+ getSGPRTrapHandlerReserve(STI));
}
unsigned getMinNumVGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 1f7084c8d25ae..f73e1c995e49f 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -375,10 +375,26 @@ unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
unsigned MaxWaves,
unsigned TotalNumVGPRs);
-/// \returns Occupancy for a given \p SGPRs usage, \p MaxWaves possible, and \p
-/// Gen.
+/// \returns Occupancy (waves per EU) limited by \p SGPRs usage for subtarget
+/// \p STI. This is the inverse of getMaxNumSGPRs(): it returns the largest
+/// number of waves W for which \p SGPRs still fits the per-wave SGPR budget
+/// (total SGPRs / W, minus the trap-handler reservation when enabled, rounded
+/// down to the allocation granule). Unlike getMaxNumSGPRs() the budget is not
+/// clamped to the addressable SGPR count, because the reported allocated SGPR
+/// count (which is what callers pass in) can legitimately exceed it.
+unsigned getOccupancyWithNumSGPRs(const MCSubtargetInfo &STI, unsigned SGPRs);
+
+/// \returns Occupancy (waves per EU) limited by \p SGPRs usage, computed from
+/// explicit budget parameters rather than a subtarget: the \p MaxWaves cap, the
+/// \p TotalNumSGPRs in the file, the allocation \p Granule, and the
+/// trap-handler \p TrapReserve (0 when the trap handler is disabled). This is
+/// the subtarget-free core shared by the MCSubtargetInfo overload and the
+/// occupancy MCExpr, so that the asm printer reports the same trap-aware
+/// occupancy the code generator assumes. Callers must apply the GFX10+ "SGPRs
+/// never limit occupancy" rule themselves before calling this.
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
- AMDGPUSubtarget::Generation Gen);
+ unsigned TotalNumSGPRs, unsigned Granule,
+ unsigned TrapReserve);
/// \returns Number of VGPR blocks needed for given subtarget \p STI when
/// \p NumVGPRs are used. We actually return the number of blocks -1, since
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
index dffde8d25c5f6..ea8c9406b2e11 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
@@ -165,8 +165,8 @@ declare void @undef_func()
; GFX90A: VGPRBlocks: (alignto(max(max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 1), 8)/8)-1
; GCN: NumVGPRsForWavesPerEU: max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0)
; GFX90A: AccumOffset: ((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1+1)*4
-; GFX908: Occupancy: occupancy(10, 4, 256, 8, 10, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0))
-; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 8, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0))
+; GFX908: Occupancy: occupancy(10, 4, 256, 8, 10, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 800, 16, 16)
+; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 8, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 800, 16, 16)
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: (((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1)&~65536)&63
define amdgpu_kernel void @kernel_call_undef_func() #0 {
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 8fb907a94fb4a..2d5fc5cf22425 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -7962,389 +7962,521 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: s_cmp_lg_u32 s44, 0
; SI-NEXT: v_readfirstlane_b32 s44, v1
-; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
-; SI-NEXT: s_cbranch_scc0 .LBB13_4
+; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
+; SI-NEXT: s_cbranch_scc0 .LBB13_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s46, s5, 24
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v22, s46, 42
+; SI-NEXT: v_writelane_b32 v22, s46, 6
; SI-NEXT: s_lshr_b32 s46, s5, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 43
-; SI-NEXT: s_lshr_b32 s46, s5, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 44
-; SI-NEXT: s_lshr_b32 s46, s7, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 45
-; SI-NEXT: s_lshr_b32 s46, s7, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 46
-; SI-NEXT: s_lshr_b32 s46, s7, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 47
-; SI-NEXT: s_lshr_b32 s46, s9, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 48
-; SI-NEXT: s_lshr_b32 s46, s9, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 49
-; SI-NEXT: s_lshr_b32 s46, s11, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 50
-; SI-NEXT: s_lshr_b32 s46, s11, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 51
-; SI-NEXT: s_lshr_b32 s46, s11, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 52
-; SI-NEXT: s_lshr_b32 s46, s13, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 53
-; SI-NEXT: s_lshr_b32 s46, s13, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 54
-; SI-NEXT: s_lshr_b32 s46, s13, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 55
+; SI-NEXT: v_writelane_b32 v22, s46, 7
; SI-NEXT: s_lshr_b32 s46, s15, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 56
-; SI-NEXT: s_lshr_b32 s46, s15, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 57
-; SI-NEXT: s_lshr_b32 s46, s15, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 58
-; SI-NEXT: s_lshr_b32 s46, s41, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 59
-; SI-NEXT: s_lshr_b32 s46, s41, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 60
-; SI-NEXT: s_lshr_b32 s46, s41, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 61
-; SI-NEXT: s_lshr_b32 s46, s43, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 62
-; SI-NEXT: s_lshr_b32 s46, s43, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 63
-; SI-NEXT: s_lshr_b32 s46, s43, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 0
-; SI-NEXT: s_lshr_b32 s46, s45, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 1
-; SI-NEXT: s_lshr_b32 s46, s45, 16
-; SI-NEXT: v_writelane_b32 v21, s46, 2
-; SI-NEXT: s_lshr_b32 s46, s45, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 3
-; SI-NEXT: s_lshr_b32 s46, s29, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 4
-; SI-NEXT: s_lshr_b32 s46, s29, 16
-; SI-NEXT: v_writelane_b32 v21, s46, 5
-; SI-NEXT: s_lshr_b32 s46, s29, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 6
-; SI-NEXT: s_lshr_b32 s46, s27, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 7
-; SI-NEXT: s_lshr_b32 s46, s27, 16
-; SI-NEXT: v_writelane_b32 v21, s46, 8
-; SI-NEXT: s_lshr_b32 s46, s27, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 9
-; SI-NEXT: s_lshr_b32 s46, s25, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 10
-; SI-NEXT: s_lshr_b32 s46, s25, 16
-; SI-NEXT: v_writelane_b32 v21, s46, 11
-; SI-NEXT: s_lshr_b32 s46, s25, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 12
-; SI-NEXT: s_lshr_b32 s46, s23, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 13
-; SI-NEXT: s_lshr_b32 s46, s23, 16
-; SI-NEXT: v_writelane_b32 v21, s46, 14
-; SI-NEXT: s_lshr_b32 s46, s23, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 15
-; SI-NEXT: s_lshr_b32 s46, s21, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 16
-; SI-NEXT: s_lshr_b32 s46, s21, 16
-; SI-NEXT: v_writelane_b32 v21, s46, 17
+; SI-NEXT: v_writelane_b32 v22, s46, 8
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 40
-; SI-NEXT: v_writelane_b32 v22, s47, 41
+; SI-NEXT: v_writelane_b32 v22, s46, 2
+; SI-NEXT: v_writelane_b32 v22, s47, 3
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 38
-; SI-NEXT: v_writelane_b32 v22, s47, 39
+; SI-NEXT: v_writelane_b32 v22, s46, 4
+; SI-NEXT: v_writelane_b32 v22, s47, 5
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8
-; SI-NEXT: v_writelane_b32 v22, s46, 36
-; SI-NEXT: v_writelane_b32 v22, s47, 37
+; SI-NEXT: v_writelane_b32 v22, s46, 0
+; SI-NEXT: v_writelane_b32 v22, s47, 1
; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 34
-; SI-NEXT: v_writelane_b32 v22, s47, 35
+; SI-NEXT: v_writelane_b32 v21, s46, 62
+; SI-NEXT: v_writelane_b32 v21, s47, 63
; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 32
-; SI-NEXT: v_writelane_b32 v22, s47, 33
+; SI-NEXT: v_writelane_b32 v21, s46, 60
+; SI-NEXT: v_writelane_b32 v21, s47, 61
; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8
-; SI-NEXT: v_writelane_b32 v22, s46, 30
-; SI-NEXT: v_writelane_b32 v22, s47, 31
+; SI-NEXT: v_writelane_b32 v21, s46, 58
+; SI-NEXT: v_writelane_b32 v21, s47, 59
; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 28
-; SI-NEXT: v_writelane_b32 v22, s47, 29
+; SI-NEXT: v_writelane_b32 v21, s46, 56
+; SI-NEXT: v_writelane_b32 v21, s47, 57
; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 26
-; SI-NEXT: v_writelane_b32 v22, s47, 27
+; SI-NEXT: v_writelane_b32 v21, s46, 54
+; SI-NEXT: v_writelane_b32 v21, s47, 55
; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8
-; SI-NEXT: v_writelane_b32 v22, s46, 24
-; SI-NEXT: v_writelane_b32 v22, s47, 25
+; SI-NEXT: v_writelane_b32 v21, s46, 52
+; SI-NEXT: v_writelane_b32 v21, s47, 53
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 22
-; SI-NEXT: v_writelane_b32 v22, s47, 23
+; SI-NEXT: v_writelane_b32 v21, s46, 50
+; SI-NEXT: v_writelane_b32 v21, s47, 51
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 20
-; SI-NEXT: v_writelane_b32 v22, s47, 21
+; SI-NEXT: v_writelane_b32 v21, s46, 48
+; SI-NEXT: v_writelane_b32 v21, s47, 49
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8
-; SI-NEXT: v_writelane_b32 v22, s46, 18
-; SI-NEXT: v_writelane_b32 v22, s47, 19
+; SI-NEXT: v_writelane_b32 v21, s46, 46
+; SI-NEXT: v_writelane_b32 v21, s47, 47
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 16
-; SI-NEXT: v_writelane_b32 v22, s47, 17
+; SI-NEXT: v_writelane_b32 v21, s46, 44
+; SI-NEXT: v_writelane_b32 v21, s47, 45
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 14
-; SI-NEXT: v_writelane_b32 v22, s47, 15
+; SI-NEXT: v_writelane_b32 v21, s46, 42
+; SI-NEXT: v_writelane_b32 v21, s47, 43
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8
-; SI-NEXT: v_writelane_b32 v22, s46, 12
-; SI-NEXT: v_writelane_b32 v22, s47, 13
+; SI-NEXT: v_writelane_b32 v21, s46, 40
+; SI-NEXT: v_writelane_b32 v21, s47, 41
; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 10
-; SI-NEXT: v_writelane_b32 v22, s47, 11
+; SI-NEXT: v_writelane_b32 v21, s46, 38
+; SI-NEXT: v_writelane_b32 v21, s47, 39
; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 8
-; SI-NEXT: v_writelane_b32 v22, s47, 9
+; SI-NEXT: v_writelane_b32 v21, s46, 36
+; SI-NEXT: v_writelane_b32 v21, s47, 37
; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8
-; SI-NEXT: v_writelane_b32 v22, s46, 6
-; SI-NEXT: v_writelane_b32 v22, s47, 7
+; SI-NEXT: v_writelane_b32 v21, s46, 34
+; SI-NEXT: v_writelane_b32 v21, s47, 35
; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 4
-; SI-NEXT: v_writelane_b32 v22, s47, 5
+; SI-NEXT: v_writelane_b32 v21, s46, 32
+; SI-NEXT: v_writelane_b32 v21, s47, 33
; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 2
-; SI-NEXT: v_writelane_b32 v22, s47, 3
+; SI-NEXT: v_writelane_b32 v21, s46, 30
+; SI-NEXT: v_writelane_b32 v21, s47, 31
; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8
-; SI-NEXT: v_writelane_b32 v22, s46, 0
-; SI-NEXT: s_lshr_b32 s50, s9, 24
-; SI-NEXT: s_lshr_b32 s51, s21, 8
-; SI-NEXT: s_lshr_b32 s48, s19, 24
-; SI-NEXT: s_lshr_b32 s52, s19, 16
-; SI-NEXT: s_lshr_b32 s53, s19, 8
-; SI-NEXT: s_lshr_b32 s54, s17, 24
-; SI-NEXT: s_lshr_b32 s55, s17, 16
-; SI-NEXT: s_lshr_b32 s49, s17, 8
-; SI-NEXT: v_writelane_b32 v22, s47, 1
-; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24
-; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8
-; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24
-; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16
-; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8
-; SI-NEXT: s_lshr_b64 s[84:85], s[28:29], 24
-; SI-NEXT: s_lshr_b64 s[86:87], s[28:29], 16
-; SI-NEXT: s_lshr_b64 s[96:97], s[28:29], 8
-; SI-NEXT: s_lshr_b64 s[98:99], s[26:27], 24
+; SI-NEXT: v_writelane_b32 v21, s46, 28
+; SI-NEXT: v_writelane_b32 v21, s47, 29
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v21, s46, 26
+; SI-NEXT: v_writelane_b32 v21, s47, 27
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 8
+; SI-NEXT: v_writelane_b32 v21, s46, 24
+; SI-NEXT: v_writelane_b32 v21, s47, 25
+; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 24
+; SI-NEXT: v_writelane_b32 v21, s46, 22
+; SI-NEXT: v_writelane_b32 v21, s47, 23
+; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 16
+; SI-NEXT: v_writelane_b32 v21, s46, 20
+; SI-NEXT: v_writelane_b32 v21, s47, 21
+; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 8
+; SI-NEXT: v_writelane_b32 v21, s46, 18
+; SI-NEXT: v_writelane_b32 v21, s47, 19
+; SI-NEXT: s_lshr_b64 s[46:47], s[28:29], 24
+; SI-NEXT: v_writelane_b32 v21, s46, 16
+; SI-NEXT: v_writelane_b32 v21, s47, 17
+; SI-NEXT: s_lshr_b64 s[46:47], s[28:29], 16
+; SI-NEXT: v_writelane_b32 v21, s46, 14
+; SI-NEXT: v_writelane_b32 v21, s47, 15
+; SI-NEXT: s_lshr_b64 s[46:47], s[28:29], 8
+; SI-NEXT: v_writelane_b32 v21, s46, 12
+; SI-NEXT: v_writelane_b32 v21, s47, 13
+; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 24
+; SI-NEXT: v_writelane_b32 v21, s46, 10
+; SI-NEXT: v_writelane_b32 v21, s47, 11
; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16
-; SI-NEXT: s_lshr_b64 s[56:57], s[26:27], 8
-; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 24
-; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
-; SI-NEXT: s_lshr_b64 s[62:63], s[24:25], 8
+; SI-NEXT: v_writelane_b32 v21, s46, 8
+; SI-NEXT: s_lshr_b32 s74, s7, 24
+; SI-NEXT: v_writelane_b32 v21, s47, 9
+; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 8
; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24
+; SI-NEXT: s_lshr_b32 s76, s7, 16
+; SI-NEXT: v_writelane_b32 v21, s46, 6
+; SI-NEXT: s_mov_b32 s73, s74
; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16
+; SI-NEXT: s_lshr_b32 s78, s7, 8
+; SI-NEXT: v_writelane_b32 v21, s47, 7
+; SI-NEXT: s_lshr_b64 s[46:47], s[24:25], 24
+; SI-NEXT: s_mov_b32 s75, s76
; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 8
+; SI-NEXT: s_lshr_b32 s88, s9, 24
+; SI-NEXT: v_writelane_b32 v21, s46, 4
+; SI-NEXT: s_mov_b32 s77, s78
; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24
+; SI-NEXT: s_lshr_b32 s90, s9, 16
+; SI-NEXT: v_writelane_b32 v21, s47, 5
+; SI-NEXT: s_lshr_b64 s[46:47], s[24:25], 16
+; SI-NEXT: s_mov_b32 s79, s88
; SI-NEXT: s_lshr_b64 s[88:89], s[20:21], 16
+; SI-NEXT: s_lshr_b32 s92, s9, 8
+; SI-NEXT: v_writelane_b32 v21, s46, 2
+; SI-NEXT: s_mov_b32 s89, s90
; SI-NEXT: s_lshr_b64 s[90:91], s[20:21], 8
+; SI-NEXT: s_lshr_b32 s94, s11, 24
+; SI-NEXT: s_lshr_b32 s36, s13, 24
+; SI-NEXT: v_writelane_b32 v21, s47, 3
+; SI-NEXT: s_lshr_b64 s[46:47], s[24:25], 8
+; SI-NEXT: s_mov_b32 s91, s92
; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 24
+; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24
+; SI-NEXT: s_lshr_b32 vcc_lo, s11, 16
+; SI-NEXT: s_lshr_b32 vcc_hi, s11, 8
+; SI-NEXT: s_lshr_b32 s38, s13, 16
+; SI-NEXT: v_writelane_b32 v21, s46, 0
+; SI-NEXT: s_mov_b32 s93, s94
; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[30:31], s[18:19], 8
-; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24
+; SI-NEXT: s_mov_b32 s35, s36
; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16
-; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8
-; SI-NEXT: s_cbranch_execnz .LBB13_3
-; SI-NEXT: .LBB13_2: ; %cmp.true
+; SI-NEXT: s_lshr_b32 s63, s5, 8
+; SI-NEXT: s_lshr_b32 s39, s13, 8
+; SI-NEXT: s_lshr_b32 s87, s15, 16
+; SI-NEXT: s_lshr_b32 s55, s15, 8
+; SI-NEXT: s_lshr_b32 s97, s41, 24
+; SI-NEXT: s_lshr_b32 s54, s41, 16
+; SI-NEXT: s_lshr_b32 s99, s41, 8
+; SI-NEXT: s_lshr_b32 s85, s43, 24
+; SI-NEXT: s_lshr_b32 s98, s43, 16
+; SI-NEXT: s_lshr_b32 s53, s43, 8
+; SI-NEXT: s_lshr_b32 s96, s45, 24
+; SI-NEXT: s_lshr_b32 s86, s45, 16
+; SI-NEXT: s_lshr_b32 s49, s45, 8
+; SI-NEXT: s_lshr_b32 s64, s29, 24
+; SI-NEXT: s_lshr_b32 s65, s29, 16
+; SI-NEXT: s_lshr_b32 s66, s29, 8
+; SI-NEXT: s_lshr_b32 s67, s27, 24
+; SI-NEXT: s_lshr_b32 s58, s27, 16
+; SI-NEXT: s_lshr_b32 s59, s27, 8
+; SI-NEXT: s_lshr_b32 s60, s25, 24
+; SI-NEXT: s_lshr_b32 s61, s25, 16
+; SI-NEXT: s_lshr_b32 s62, s25, 8
+; SI-NEXT: s_lshr_b32 s68, s23, 24
+; SI-NEXT: s_lshr_b32 s69, s23, 16
+; SI-NEXT: s_lshr_b32 s48, s23, 8
+; SI-NEXT: s_lshr_b32 s50, s21, 24
+; SI-NEXT: s_lshr_b32 s51, s21, 16
+; SI-NEXT: s_lshr_b32 s70, s21, 8
+; SI-NEXT: s_lshr_b32 s71, s19, 24
+; SI-NEXT: s_lshr_b32 s80, s19, 16
+; SI-NEXT: s_lshr_b32 s81, s19, 8
+; SI-NEXT: s_lshr_b32 s82, s17, 24
+; SI-NEXT: s_lshr_b32 s83, s17, 16
+; SI-NEXT: s_lshr_b32 s52, s17, 8
+; SI-NEXT: s_lshr_b64 s[56:57], s[42:43], 24
+; SI-NEXT: v_writelane_b32 v21, s47, 1
+; SI-NEXT: s_mov_b32 s95, vcc_lo
+; SI-NEXT: s_mov_b32 s31, vcc_hi
+; SI-NEXT: s_mov_b32 s37, s38
+; SI-NEXT: s_lshr_b64 s[46:47], s[16:17], 8
+; SI-NEXT: s_mov_b64 vcc, 0
+; SI-NEXT: s_branch .LBB13_3
+; SI-NEXT: .LBB13_2:
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr39
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: ; implicit-def: $sgpr85
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; kill: killed $sgpr46
+; SI-NEXT: s_mov_b64 vcc, -1
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_writelane_b32 v21, s56, 0
+; SI-NEXT: v_writelane_b32 v21, s57, 1
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; kill: killed $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v21, s56, 2
+; SI-NEXT: v_writelane_b32 v21, s57, 3
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: ; implicit-def: $sgpr83
+; SI-NEXT: ; implicit-def: $sgpr82
+; SI-NEXT: ; implicit-def: $sgpr81
+; SI-NEXT: ; implicit-def: $sgpr80
+; SI-NEXT: ; implicit-def: $sgpr71
+; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: ; implicit-def: $sgpr51
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr48
+; SI-NEXT: ; implicit-def: $sgpr69
+; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr67
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr49
+; SI-NEXT: ; implicit-def: $sgpr86
+; SI-NEXT: ; implicit-def: $sgpr96
+; SI-NEXT: ; implicit-def: $sgpr53
+; SI-NEXT: ; implicit-def: $sgpr98
+; SI-NEXT: ; implicit-def: $sgpr99
+; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr97
+; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr87
+; SI-NEXT: ; implicit-def: $sgpr37
+; SI-NEXT: ; implicit-def: $sgpr35
+; SI-NEXT: ; implicit-def: $sgpr31
+; SI-NEXT: ; implicit-def: $sgpr95
+; SI-NEXT: ; implicit-def: $sgpr93
+; SI-NEXT: ; implicit-def: $sgpr91
+; SI-NEXT: ; implicit-def: $sgpr89
+; SI-NEXT: ; implicit-def: $sgpr79
+; SI-NEXT: ; implicit-def: $sgpr77
+; SI-NEXT: ; implicit-def: $sgpr75
+; SI-NEXT: ; implicit-def: $sgpr73
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; kill: killed $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr36
+; SI-NEXT: ; implicit-def: $sgpr34
+; SI-NEXT: ; implicit-def: $sgpr30
+; SI-NEXT: ; implicit-def: $sgpr94
+; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: ; implicit-def: $sgpr90
+; SI-NEXT: ; implicit-def: $sgpr88
+; SI-NEXT: ; implicit-def: $sgpr78
+; SI-NEXT: ; implicit-def: $sgpr76
+; SI-NEXT: ; implicit-def: $sgpr74
+; SI-NEXT: ; implicit-def: $sgpr72
+; SI-NEXT: v_writelane_b32 v21, s56, 4
+; SI-NEXT: v_writelane_b32 v21, s57, 5
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 6
+; SI-NEXT: v_writelane_b32 v21, s57, 7
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 8
+; SI-NEXT: v_writelane_b32 v21, s57, 9
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 10
+; SI-NEXT: v_writelane_b32 v21, s57, 11
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 12
+; SI-NEXT: v_writelane_b32 v21, s57, 13
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 14
+; SI-NEXT: v_writelane_b32 v21, s57, 15
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 16
+; SI-NEXT: v_writelane_b32 v21, s57, 17
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 18
+; SI-NEXT: v_writelane_b32 v21, s57, 19
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 20
+; SI-NEXT: v_writelane_b32 v21, s57, 21
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 22
+; SI-NEXT: v_writelane_b32 v21, s57, 23
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 24
+; SI-NEXT: v_writelane_b32 v21, s57, 25
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s56, 26
+; SI-NEXT: v_writelane_b32 v21, s57, 27
+; SI-NEXT: v_writelane_b32 v21, s38, 28
+; SI-NEXT: v_writelane_b32 v21, s39, 29
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: v_writelane_b32 v21, s38, 30
+; SI-NEXT: v_writelane_b32 v21, s39, 31
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: v_writelane_b32 v21, s38, 32
+; SI-NEXT: v_writelane_b32 v21, s39, 33
+; SI-NEXT: v_writelane_b32 v21, s84, 34
+; SI-NEXT: v_writelane_b32 v21, s85, 35
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: v_writelane_b32 v21, s84, 36
+; SI-NEXT: v_writelane_b32 v21, s85, 37
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 38
+; SI-NEXT: v_writelane_b32 v21, s85, 39
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 40
+; SI-NEXT: v_writelane_b32 v21, s85, 41
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 42
+; SI-NEXT: v_writelane_b32 v21, s85, 43
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 44
+; SI-NEXT: v_writelane_b32 v21, s85, 45
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 46
+; SI-NEXT: v_writelane_b32 v21, s85, 47
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 48
+; SI-NEXT: v_writelane_b32 v21, s85, 49
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 50
+; SI-NEXT: v_writelane_b32 v21, s85, 51
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 52
+; SI-NEXT: v_writelane_b32 v21, s85, 53
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 54
+; SI-NEXT: v_writelane_b32 v21, s85, 55
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 56
+; SI-NEXT: v_writelane_b32 v21, s85, 57
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 58
+; SI-NEXT: v_writelane_b32 v21, s85, 59
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 60
+; SI-NEXT: v_writelane_b32 v21, s85, 61
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v21, s84, 62
+; SI-NEXT: v_writelane_b32 v21, s85, 63
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v22, s84, 0
+; SI-NEXT: v_writelane_b32 v22, s85, 1
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: v_writelane_b32 v22, s84, 2
+; SI-NEXT: v_writelane_b32 v22, s85, 3
+; SI-NEXT: v_writelane_b32 v22, s38, 4
+; SI-NEXT: v_writelane_b32 v22, s39, 5
+; SI-NEXT: .LBB13_3: ; %Flow
+; SI-NEXT: s_andn2_b64 vcc, exec, vcc
+; SI-NEXT: s_mov_b32 s38, s98
+; SI-NEXT: s_mov_b32 s98, s85
+; SI-NEXT: s_mov_b32 s84, s56
+; SI-NEXT: s_mov_b32 s56, s53
+; SI-NEXT: s_mov_b32 s85, s86
+; SI-NEXT: s_mov_b32 s86, s49
+; SI-NEXT: s_mov_b32 s49, s64
+; SI-NEXT: s_mov_b32 s64, s65
+; SI-NEXT: s_mov_b32 s65, s66
+; SI-NEXT: s_mov_b32 s66, s67
+; SI-NEXT: s_mov_b32 s67, s58
+; SI-NEXT: s_cbranch_vccnz .LBB13_5
+; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s5, s5, 3
; SI-NEXT: s_add_i32 s4, s4, 3
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 40
-; SI-NEXT: v_writelane_b32 v22, s47, 41
+; SI-NEXT: v_writelane_b32 v22, s46, 2
+; SI-NEXT: v_writelane_b32 v22, s47, 3
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 38
-; SI-NEXT: v_writelane_b32 v22, s47, 39
+; SI-NEXT: v_writelane_b32 v22, s46, 4
+; SI-NEXT: v_writelane_b32 v22, s47, 5
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8
-; SI-NEXT: v_writelane_b32 v22, s46, 36
-; SI-NEXT: v_writelane_b32 v22, s47, 37
-; SI-NEXT: s_lshr_b32 s46, s5, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 42
-; SI-NEXT: s_lshr_b32 s46, s5, 16
; SI-NEXT: s_add_i32 s7, s7, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 43
-; SI-NEXT: s_lshr_b32 s46, s5, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 44
-; SI-NEXT: s_lshr_b32 s46, s7, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 45
-; SI-NEXT: s_lshr_b32 s46, s7, 16
-; SI-NEXT: s_add_i32 s9, s9, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 46
-; SI-NEXT: s_lshr_b32 s46, s7, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 47
-; SI-NEXT: s_lshr_b32 s46, s9, 16
-; SI-NEXT: s_add_i32 s11, s11, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 48
-; SI-NEXT: s_lshr_b32 s46, s9, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 49
-; SI-NEXT: s_lshr_b32 s46, s11, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 50
-; SI-NEXT: s_lshr_b32 s46, s11, 16
-; SI-NEXT: s_add_i32 s13, s13, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 51
-; SI-NEXT: s_lshr_b32 s46, s11, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 52
-; SI-NEXT: s_lshr_b32 s46, s13, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 53
-; SI-NEXT: s_lshr_b32 s46, s13, 16
-; SI-NEXT: s_add_i32 s15, s15, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 54
-; SI-NEXT: s_lshr_b32 s46, s13, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 55
-; SI-NEXT: s_lshr_b32 s46, s15, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 56
-; SI-NEXT: s_lshr_b32 s46, s15, 16
-; SI-NEXT: s_add_i32 s41, s41, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 57
-; SI-NEXT: s_lshr_b32 s46, s15, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 58
-; SI-NEXT: s_lshr_b32 s46, s41, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 59
-; SI-NEXT: s_lshr_b32 s46, s41, 16
-; SI-NEXT: s_add_i32 s43, s43, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 60
-; SI-NEXT: s_lshr_b32 s46, s41, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 61
-; SI-NEXT: s_lshr_b32 s46, s43, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 62
-; SI-NEXT: s_lshr_b32 s46, s43, 16
-; SI-NEXT: s_add_i32 s45, s45, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 63
-; SI-NEXT: s_lshr_b32 s46, s43, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 0
-; SI-NEXT: s_lshr_b32 s46, s45, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 1
-; SI-NEXT: s_lshr_b32 s46, s45, 16
-; SI-NEXT: s_add_i32 s29, s29, 3
-; SI-NEXT: v_writelane_b32 v21, s46, 2
-; SI-NEXT: s_lshr_b32 s46, s45, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 3
-; SI-NEXT: s_lshr_b32 s46, s29, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 4
-; SI-NEXT: s_lshr_b32 s46, s29, 16
-; SI-NEXT: s_add_i32 s27, s27, 3
-; SI-NEXT: v_writelane_b32 v21, s46, 5
-; SI-NEXT: s_lshr_b32 s46, s29, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 6
-; SI-NEXT: s_lshr_b32 s46, s27, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 7
-; SI-NEXT: s_lshr_b32 s46, s27, 16
-; SI-NEXT: s_add_i32 s25, s25, 3
-; SI-NEXT: v_writelane_b32 v21, s46, 8
-; SI-NEXT: s_lshr_b32 s46, s27, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 9
-; SI-NEXT: s_lshr_b32 s46, s25, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 10
-; SI-NEXT: s_lshr_b32 s46, s25, 16
-; SI-NEXT: s_add_i32 s23, s23, 3
-; SI-NEXT: v_writelane_b32 v21, s46, 11
-; SI-NEXT: s_lshr_b32 s46, s25, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 12
-; SI-NEXT: s_lshr_b32 s46, s23, 24
-; SI-NEXT: v_writelane_b32 v21, s46, 13
-; SI-NEXT: s_lshr_b32 s46, s23, 16
-; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: v_writelane_b32 v21, s46, 14
-; SI-NEXT: s_lshr_b32 s46, s23, 8
-; SI-NEXT: v_writelane_b32 v21, s46, 15
-; SI-NEXT: s_lshr_b32 s46, s21, 24
; SI-NEXT: s_add_i32 s6, s6, 3
-; SI-NEXT: v_writelane_b32 v21, s46, 16
-; SI-NEXT: s_lshr_b32 s46, s21, 16
-; SI-NEXT: v_writelane_b32 v21, s46, 17
+; SI-NEXT: v_writelane_b32 v22, s46, 0
+; SI-NEXT: v_writelane_b32 v22, s47, 1
; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 34
-; SI-NEXT: v_writelane_b32 v22, s47, 35
+; SI-NEXT: v_writelane_b32 v21, s46, 62
+; SI-NEXT: v_writelane_b32 v21, s47, 63
; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 32
-; SI-NEXT: v_writelane_b32 v22, s47, 33
+; SI-NEXT: v_writelane_b32 v21, s46, 60
+; SI-NEXT: v_writelane_b32 v21, s47, 61
; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8
+; SI-NEXT: s_add_i32 s9, s9, 3
; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 30
-; SI-NEXT: v_writelane_b32 v22, s47, 31
+; SI-NEXT: v_writelane_b32 v21, s46, 58
+; SI-NEXT: v_writelane_b32 v21, s47, 59
; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 28
-; SI-NEXT: v_writelane_b32 v22, s47, 29
+; SI-NEXT: v_writelane_b32 v21, s46, 56
+; SI-NEXT: v_writelane_b32 v21, s47, 57
; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 26
-; SI-NEXT: v_writelane_b32 v22, s47, 27
+; SI-NEXT: v_writelane_b32 v21, s46, 54
+; SI-NEXT: v_writelane_b32 v21, s47, 55
; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8
+; SI-NEXT: s_add_i32 s11, s11, 3
; SI-NEXT: s_add_i32 s10, s10, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 24
-; SI-NEXT: v_writelane_b32 v22, s47, 25
+; SI-NEXT: v_writelane_b32 v21, s46, 52
+; SI-NEXT: v_writelane_b32 v21, s47, 53
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 22
-; SI-NEXT: v_writelane_b32 v22, s47, 23
+; SI-NEXT: v_writelane_b32 v21, s46, 50
+; SI-NEXT: v_writelane_b32 v21, s47, 51
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 20
-; SI-NEXT: v_writelane_b32 v22, s47, 21
+; SI-NEXT: v_writelane_b32 v21, s46, 48
+; SI-NEXT: v_writelane_b32 v21, s47, 49
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8
+; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_add_i32 s12, s12, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 18
-; SI-NEXT: v_writelane_b32 v22, s47, 19
+; SI-NEXT: v_writelane_b32 v21, s46, 46
+; SI-NEXT: v_writelane_b32 v21, s47, 47
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 16
-; SI-NEXT: v_writelane_b32 v22, s47, 17
+; SI-NEXT: v_writelane_b32 v21, s46, 44
+; SI-NEXT: v_writelane_b32 v21, s47, 45
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 14
-; SI-NEXT: v_writelane_b32 v22, s47, 15
+; SI-NEXT: v_writelane_b32 v21, s46, 42
+; SI-NEXT: v_writelane_b32 v21, s47, 43
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8
+; SI-NEXT: s_add_i32 s15, s15, 3
; SI-NEXT: s_add_i32 s14, s14, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 12
-; SI-NEXT: v_writelane_b32 v22, s47, 13
+; SI-NEXT: v_writelane_b32 v21, s46, 40
+; SI-NEXT: v_writelane_b32 v21, s47, 41
; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 10
-; SI-NEXT: v_writelane_b32 v22, s47, 11
+; SI-NEXT: v_writelane_b32 v21, s46, 38
+; SI-NEXT: v_writelane_b32 v21, s47, 39
; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 8
-; SI-NEXT: v_writelane_b32 v22, s47, 9
+; SI-NEXT: v_writelane_b32 v21, s46, 36
+; SI-NEXT: v_writelane_b32 v21, s47, 37
; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8
+; SI-NEXT: s_add_i32 s41, s41, 3
; SI-NEXT: s_add_i32 s40, s40, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 6
-; SI-NEXT: v_writelane_b32 v22, s47, 7
+; SI-NEXT: v_writelane_b32 v21, s46, 34
+; SI-NEXT: v_writelane_b32 v21, s47, 35
; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24
-; SI-NEXT: v_writelane_b32 v22, s46, 4
-; SI-NEXT: v_writelane_b32 v22, s47, 5
+; SI-NEXT: v_writelane_b32 v21, s46, 32
+; SI-NEXT: v_writelane_b32 v21, s47, 33
; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16
-; SI-NEXT: v_writelane_b32 v22, s46, 2
-; SI-NEXT: v_writelane_b32 v22, s47, 3
+; SI-NEXT: v_writelane_b32 v21, s46, 30
+; SI-NEXT: v_writelane_b32 v21, s47, 31
; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8
+; SI-NEXT: s_add_i32 s43, s43, 3
+; SI-NEXT: s_add_i32 s42, s42, 3
+; SI-NEXT: v_writelane_b32 v21, s46, 28
+; SI-NEXT: v_writelane_b32 v21, s47, 29
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v21, s46, 26
+; SI-NEXT: v_writelane_b32 v21, s47, 27
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 8
+; SI-NEXT: s_add_i32 s45, s45, 3
+; SI-NEXT: s_add_i32 s44, s44, 3
+; SI-NEXT: v_writelane_b32 v21, s46, 24
+; SI-NEXT: v_writelane_b32 v21, s47, 25
+; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 24
+; SI-NEXT: v_writelane_b32 v21, s46, 22
+; SI-NEXT: v_writelane_b32 v21, s47, 23
+; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 16
+; SI-NEXT: v_writelane_b32 v21, s46, 20
+; SI-NEXT: v_writelane_b32 v21, s47, 21
+; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 8
+; SI-NEXT: s_add_i32 s29, s29, 3
+; SI-NEXT: s_add_i32 s28, s28, 3
+; SI-NEXT: v_writelane_b32 v21, s46, 18
+; SI-NEXT: v_writelane_b32 v21, s47, 19
+; SI-NEXT: s_lshr_b64 s[46:47], s[28:29], 24
+; SI-NEXT: v_writelane_b32 v21, s46, 16
+; SI-NEXT: v_writelane_b32 v21, s47, 17
+; SI-NEXT: s_lshr_b64 s[46:47], s[28:29], 16
+; SI-NEXT: v_writelane_b32 v21, s46, 14
+; SI-NEXT: v_writelane_b32 v21, s47, 15
+; SI-NEXT: s_lshr_b64 s[46:47], s[28:29], 8
+; SI-NEXT: s_add_i32 s27, s27, 3
+; SI-NEXT: s_add_i32 s26, s26, 3
+; SI-NEXT: v_writelane_b32 v21, s46, 12
+; SI-NEXT: v_writelane_b32 v21, s47, 13
+; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 24
+; SI-NEXT: v_writelane_b32 v21, s46, 10
+; SI-NEXT: v_writelane_b32 v21, s47, 11
+; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16
+; SI-NEXT: v_writelane_b32 v21, s46, 8
+; SI-NEXT: v_writelane_b32 v21, s47, 9
+; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 8
+; SI-NEXT: s_add_i32 s25, s25, 3
+; SI-NEXT: s_add_i32 s24, s24, 3
+; SI-NEXT: v_writelane_b32 v21, s46, 6
+; SI-NEXT: v_writelane_b32 v21, s47, 7
+; SI-NEXT: s_lshr_b64 s[46:47], s[24:25], 24
+; SI-NEXT: v_writelane_b32 v21, s46, 4
+; SI-NEXT: v_writelane_b32 v21, s47, 5
+; SI-NEXT: s_lshr_b64 s[46:47], s[24:25], 16
+; SI-NEXT: v_writelane_b32 v21, s46, 2
+; SI-NEXT: v_writelane_b32 v21, s47, 3
+; SI-NEXT: s_lshr_b64 s[46:47], s[24:25], 8
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: v_writelane_b32 v21, s46, 0
+; SI-NEXT: v_writelane_b32 v21, s47, 1
+; SI-NEXT: s_lshr_b64 s[46:47], s[16:17], 8
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s20, s20, 3
+; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s22, s22, 3
-; SI-NEXT: s_add_i32 s24, s24, 3
-; SI-NEXT: s_add_i32 s26, s26, 3
-; SI-NEXT: s_add_i32 s28, s28, 3
-; SI-NEXT: s_add_i32 s44, s44, 3
-; SI-NEXT: s_add_i32 s42, s42, 3
-; SI-NEXT: v_writelane_b32 v22, s46, 0
-; SI-NEXT: s_lshr_b32 s50, s9, 24
-; SI-NEXT: s_lshr_b32 s51, s21, 8
-; SI-NEXT: s_lshr_b32 s48, s19, 24
-; SI-NEXT: s_lshr_b32 s52, s19, 16
-; SI-NEXT: s_lshr_b32 s53, s19, 8
-; SI-NEXT: s_lshr_b32 s54, s17, 24
-; SI-NEXT: s_lshr_b32 s55, s17, 16
-; SI-NEXT: s_lshr_b32 s49, s17, 8
-; SI-NEXT: v_writelane_b32 v22, s47, 1
-; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24
-; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8
-; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24
-; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16
-; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8
-; SI-NEXT: s_lshr_b64 s[84:85], s[28:29], 24
-; SI-NEXT: s_lshr_b64 s[86:87], s[28:29], 16
-; SI-NEXT: s_lshr_b64 s[96:97], s[28:29], 8
-; SI-NEXT: s_lshr_b64 s[98:99], s[26:27], 24
-; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16
-; SI-NEXT: s_lshr_b64 s[56:57], s[26:27], 8
-; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 24
-; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
-; SI-NEXT: s_lshr_b64 s[62:63], s[24:25], 8
+; SI-NEXT: s_lshr_b32 s47, s5, 24
+; SI-NEXT: s_lshr_b64 s[84:85], s[42:43], 24
; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24
; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 8
@@ -8356,270 +8488,339 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: s_lshr_b64 s[30:31], s[18:19], 8
; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24
; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16
-; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8
-; SI-NEXT: .LBB13_3: ; %end
-; SI-NEXT: s_lshl_b32 s47, s38, 8
+; SI-NEXT: v_writelane_b32 v22, s47, 6
+; SI-NEXT: s_lshr_b32 s47, s5, 16
+; SI-NEXT: v_writelane_b32 v22, s47, 7
+; SI-NEXT: s_lshr_b32 s63, s5, 8
+; SI-NEXT: s_lshr_b32 s73, s7, 24
+; SI-NEXT: s_lshr_b32 s75, s7, 16
+; SI-NEXT: s_lshr_b32 s77, s7, 8
+; SI-NEXT: s_lshr_b32 s79, s9, 24
+; SI-NEXT: s_lshr_b32 s89, s9, 16
+; SI-NEXT: s_lshr_b32 s91, s9, 8
+; SI-NEXT: s_lshr_b32 s93, s11, 24
+; SI-NEXT: s_lshr_b32 s95, s11, 16
+; SI-NEXT: s_lshr_b32 s31, s11, 8
+; SI-NEXT: s_lshr_b32 s35, s13, 24
+; SI-NEXT: s_lshr_b32 s37, s13, 16
+; SI-NEXT: s_lshr_b32 s39, s13, 8
+; SI-NEXT: s_lshr_b32 s47, s15, 24
+; SI-NEXT: s_lshr_b32 s87, s15, 16
+; SI-NEXT: s_lshr_b32 s55, s15, 8
+; SI-NEXT: s_lshr_b32 s97, s41, 24
+; SI-NEXT: s_lshr_b32 s54, s41, 16
+; SI-NEXT: s_lshr_b32 s99, s41, 8
+; SI-NEXT: s_lshr_b32 s98, s43, 24
+; SI-NEXT: s_lshr_b32 s38, s43, 16
+; SI-NEXT: s_lshr_b32 s56, s43, 8
+; SI-NEXT: s_lshr_b32 s96, s45, 24
+; SI-NEXT: s_lshr_b32 s85, s45, 16
+; SI-NEXT: s_lshr_b32 s86, s45, 8
+; SI-NEXT: s_lshr_b32 s49, s29, 24
+; SI-NEXT: s_lshr_b32 s64, s29, 16
+; SI-NEXT: s_lshr_b32 s65, s29, 8
+; SI-NEXT: s_lshr_b32 s66, s27, 24
+; SI-NEXT: s_lshr_b32 s67, s27, 16
+; SI-NEXT: s_lshr_b32 s59, s27, 8
+; SI-NEXT: s_lshr_b32 s60, s25, 24
+; SI-NEXT: s_lshr_b32 s61, s25, 16
+; SI-NEXT: s_lshr_b32 s62, s25, 8
+; SI-NEXT: s_lshr_b32 s68, s23, 24
+; SI-NEXT: s_lshr_b32 s69, s23, 16
+; SI-NEXT: s_lshr_b32 s48, s23, 8
+; SI-NEXT: s_lshr_b32 s50, s21, 24
+; SI-NEXT: s_lshr_b32 s51, s21, 16
+; SI-NEXT: s_lshr_b32 s70, s21, 8
+; SI-NEXT: s_lshr_b32 s71, s19, 24
+; SI-NEXT: s_lshr_b32 s80, s19, 16
+; SI-NEXT: s_lshr_b32 s81, s19, 8
+; SI-NEXT: s_lshr_b32 s82, s17, 24
+; SI-NEXT: s_lshr_b32 s83, s17, 16
+; SI-NEXT: s_lshr_b32 s52, s17, 8
+; SI-NEXT: v_writelane_b32 v22, s47, 8
+; SI-NEXT: .LBB13_5: ; %end
; SI-NEXT: s_and_b32 s16, s16, 0xff
+; SI-NEXT: s_lshl_b32 s47, s46, 8
; SI-NEXT: s_or_b32 s16, s16, s47
; SI-NEXT: s_and_b32 s47, s36, 0xff
-; SI-NEXT: s_lshl_b32 s57, s34, 24
; SI-NEXT: s_lshl_b32 s47, s47, 16
-; SI-NEXT: s_or_b32 s47, s57, s47
+; SI-NEXT: s_lshl_b32 s57, s34, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s47, s57, s47
; SI-NEXT: s_or_b32 s16, s16, s47
; SI-NEXT: v_mov_b32_e32 v1, s16
; SI-NEXT: s_and_b32 s16, s17, 0xff
-; SI-NEXT: s_lshl_b32 s17, s49, 8
+; SI-NEXT: s_lshl_b32 s17, s52, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s55, 0xff
+; SI-NEXT: s_and_b32 s17, s83, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s47, s54, 24
-; SI-NEXT: s_or_b32 s17, s47, s17
+; SI-NEXT: s_lshl_b32 s47, s82, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s47, s17
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: v_mov_b32_e32 v2, s16
-; SI-NEXT: s_lshl_b32 s16, s30, 8
-; SI-NEXT: s_and_b32 s17, s18, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_and_b32 s16, s18, 0xff
+; SI-NEXT: s_lshl_b32 s17, s30, 8
+; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s94, 0xff
-; SI-NEXT: s_lshl_b32 s18, s92, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s92, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v3, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s19, 0xff
-; SI-NEXT: s_lshl_b32 s17, s53, 8
+; SI-NEXT: s_lshl_b32 s17, s81, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s52, 0xff
+; SI-NEXT: s_and_b32 s17, s80, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s48, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s71, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s20, 0xff
+; SI-NEXT: s_lshl_b32 s17, s90, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v4, s16
-; SI-NEXT: s_lshl_b32 s16, s90, 8
-; SI-NEXT: s_and_b32 s17, s20, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s88, 0xff
-; SI-NEXT: s_lshl_b32 s18, s78, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s78, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v5, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s21, 0xff
-; SI-NEXT: s_lshl_b32 s17, s51, 8
+; SI-NEXT: s_lshl_b32 s17, s70, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 17
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 16
+; SI-NEXT: s_and_b32 s17, s51, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s50, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s22, 0xff
+; SI-NEXT: s_lshl_b32 s17, s76, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v6, s16
-; SI-NEXT: s_lshl_b32 s16, s76, 8
-; SI-NEXT: s_and_b32 s17, s22, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s74, 0xff
-; SI-NEXT: s_lshl_b32 s18, s72, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s72, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 15
-; SI-NEXT: v_mov_b32_e32 v7, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s23, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s48, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 14
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 13
+; SI-NEXT: s_and_b32 s17, s69, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: s_lshl_b32 s18, s68, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 0
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v8, s16
-; SI-NEXT: s_lshl_b32 s16, s62, 8
-; SI-NEXT: s_and_b32 s17, s24, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s17, s60, 0xff
-; SI-NEXT: s_lshl_b32 s18, s58, 24
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 2
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s24, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 3
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s17, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v21, 4
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 12
-; SI-NEXT: v_mov_b32_e32 v9, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s25, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s62, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 11
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 10
+; SI-NEXT: s_and_b32 s17, s61, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 5
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: s_lshl_b32 s18, s60, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 6
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v10, s16
-; SI-NEXT: s_lshl_b32 s16, s56, 8
-; SI-NEXT: s_and_b32 s17, s26, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s17, s46, 0xff
-; SI-NEXT: s_lshl_b32 s18, s98, 24
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 8
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s26, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 9
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s17, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v21, 10
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 9
-; SI-NEXT: v_mov_b32_e32 v11, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s27, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s59, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 8
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 7
+; SI-NEXT: s_and_b32 s17, s67, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 11
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: s_lshl_b32 s18, s66, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 12
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 13
+; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v12, s16
-; SI-NEXT: s_lshl_b32 s16, s96, 8
-; SI-NEXT: s_and_b32 s17, s28, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s17, s86, 0xff
-; SI-NEXT: s_lshl_b32 s18, s84, 24
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 14
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s28, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 15
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s17, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v21, 16
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 6
-; SI-NEXT: v_mov_b32_e32 v13, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s29, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s65, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 5
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 4
+; SI-NEXT: s_and_b32 s17, s64, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 17
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: s_lshl_b32 s18, s49, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 18
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 19
+; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v14, s16
-; SI-NEXT: s_lshl_b32 s16, s82, 8
-; SI-NEXT: s_and_b32 s17, s44, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s17, s80, 0xff
-; SI-NEXT: s_lshl_b32 s18, s70, 24
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 20
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s44, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 21
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s17, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v21, 22
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 3
-; SI-NEXT: v_mov_b32_e32 v15, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s45, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s86, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 2
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 1
-; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
+; SI-NEXT: s_and_b32 s17, s85, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 23
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s96, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 24
+; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
-; SI-NEXT: v_mov_b32_e32 v16, s16
-; SI-NEXT: s_lshl_b32 s16, s68, 8
-; SI-NEXT: s_and_b32 s17, s42, 0xff
-; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s17, s66, 0xff
-; SI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
-; SI-NEXT: s_lshl_b32 s18, s64, 24
-; SI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
+; SI-NEXT: v_readlane_b32 s19, v21, 25
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s42, 0xff
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 26
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s17, s18, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
+; SI-NEXT: s_lshl_b32 s18, s84, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 0
-; SI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s43, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
+; SI-NEXT: s_lshl_b32 s17, s56, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 63
-; SI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 62
-; SI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
+; SI-NEXT: s_and_b32 s17, s38, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 27
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
+; SI-NEXT: s_lshl_b32 s18, s98, 24
; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: v_readlane_b32 s18, v22, 0
-; SI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0
+; SI-NEXT: v_readlane_b32 s18, v21, 28
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: v_readlane_b32 s19, v22, 1
-; SI-NEXT: buffer_store_dword v16, v1, s[0:3], 0 offen
+; SI-NEXT: v_readlane_b32 s19, v21, 29
; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_lshl_b32 s17, s18, 8
-; SI-NEXT: v_readlane_b32 s18, v22, 2
+; SI-NEXT: v_readlane_b32 s18, v21, 30
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s40, 0xff
-; SI-NEXT: v_readlane_b32 s19, v22, 3
+; SI-NEXT: v_readlane_b32 s19, v21, 31
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s18, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 4
+; SI-NEXT: v_readlane_b32 s18, v21, 32
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 61
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s41, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s99, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 60
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 59
+; SI-NEXT: s_and_b32 s17, s54, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: s_lshl_b32 s18, s97, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x48, v0
@@ -8627,16 +8828,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
-; SI-NEXT: v_readlane_b32 s16, v22, 6
+; SI-NEXT: v_readlane_b32 s16, v21, 34
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_readlane_b32 s17, v22, 7
+; SI-NEXT: v_readlane_b32 s17, v21, 35
; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: v_readlane_b32 s19, v22, 5
+; SI-NEXT: v_readlane_b32 s19, v21, 33
; SI-NEXT: s_or_b32 s14, s14, s16
-; SI-NEXT: v_readlane_b32 s16, v22, 8
-; SI-NEXT: v_readlane_b32 s17, v22, 9
+; SI-NEXT: v_readlane_b32 s16, v21, 36
+; SI-NEXT: v_readlane_b32 s17, v21, 37
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 10
+; SI-NEXT: v_readlane_b32 s18, v21, 38
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s17, s18, 24
; SI-NEXT: s_and_b32 s14, s14, 0xffff
@@ -8647,12 +8848,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s14
; SI-NEXT: s_and_b32 s14, s15, 0xff
-; SI-NEXT: v_readlane_b32 s15, v22, 58
-; SI-NEXT: s_lshl_b32 s15, s15, 8
+; SI-NEXT: s_lshl_b32 s15, s55, 8
; SI-NEXT: s_or_b32 s14, s14, s15
-; SI-NEXT: v_readlane_b32 s15, v22, 57
-; SI-NEXT: s_and_b32 s15, s15, 0xff
-; SI-NEXT: v_readlane_b32 s16, v22, 56
+; SI-NEXT: s_and_b32 s15, s87, 0xff
+; SI-NEXT: v_readlane_b32 s16, v22, 8
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_lshl_b32 s16, s16, 24
; SI-NEXT: s_and_b32 s14, s14, 0xffff
@@ -8662,15 +8861,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s14
-; SI-NEXT: v_readlane_b32 s14, v22, 12
+; SI-NEXT: v_readlane_b32 s14, v21, 40
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s15, v22, 13
+; SI-NEXT: v_readlane_b32 s15, v21, 41
; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_or_b32 s12, s12, s14
-; SI-NEXT: v_readlane_b32 s14, v22, 14
-; SI-NEXT: v_readlane_b32 s15, v22, 15
+; SI-NEXT: v_readlane_b32 s14, v21, 42
+; SI-NEXT: v_readlane_b32 s15, v21, 43
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_readlane_b32 s16, v22, 16
+; SI-NEXT: v_readlane_b32 s16, v21, 44
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_lshl_b32 s15, s16, 24
; SI-NEXT: s_and_b32 s12, s12, 0xffff
@@ -8681,14 +8880,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s12
; SI-NEXT: s_and_b32 s12, s13, 0xff
-; SI-NEXT: v_readlane_b32 s13, v22, 55
-; SI-NEXT: s_lshl_b32 s13, s13, 8
+; SI-NEXT: s_lshl_b32 s13, s39, 8
; SI-NEXT: s_or_b32 s12, s12, s13
-; SI-NEXT: v_readlane_b32 s13, v22, 54
-; SI-NEXT: s_and_b32 s13, s13, 0xff
-; SI-NEXT: v_readlane_b32 s14, v22, 53
+; SI-NEXT: s_and_b32 s13, s37, 0xff
; SI-NEXT: s_lshl_b32 s13, s13, 16
-; SI-NEXT: s_lshl_b32 s14, s14, 24
+; SI-NEXT: s_lshl_b32 s14, s35, 24
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_or_b32 s13, s14, s13
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x58, v0
@@ -8696,15 +8892,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s12
-; SI-NEXT: v_readlane_b32 s12, v22, 18
+; SI-NEXT: v_readlane_b32 s12, v21, 46
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s13, v22, 19
+; SI-NEXT: v_readlane_b32 s13, v21, 47
; SI-NEXT: s_lshl_b32 s12, s12, 8
; SI-NEXT: s_or_b32 s10, s10, s12
-; SI-NEXT: v_readlane_b32 s12, v22, 20
-; SI-NEXT: v_readlane_b32 s13, v22, 21
+; SI-NEXT: v_readlane_b32 s12, v21, 48
+; SI-NEXT: v_readlane_b32 s13, v21, 49
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s14, v22, 22
+; SI-NEXT: v_readlane_b32 s14, v21, 50
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_lshl_b32 s13, s14, 24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
@@ -8715,14 +8911,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: s_and_b32 s10, s11, 0xff
-; SI-NEXT: v_readlane_b32 s11, v22, 52
-; SI-NEXT: s_lshl_b32 s11, s11, 8
+; SI-NEXT: s_lshl_b32 s11, s31, 8
; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: v_readlane_b32 s11, v22, 51
-; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: v_readlane_b32 s12, v22, 50
+; SI-NEXT: s_and_b32 s11, s95, 0xff
; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: s_lshl_b32 s12, s12, 24
+; SI-NEXT: s_lshl_b32 s12, s93, 24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_or_b32 s11, s12, s11
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x60, v0
@@ -8730,15 +8923,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s10
-; SI-NEXT: v_readlane_b32 s10, v22, 24
+; SI-NEXT: v_readlane_b32 s10, v21, 52
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s11, v22, 25
+; SI-NEXT: v_readlane_b32 s11, v21, 53
; SI-NEXT: s_lshl_b32 s10, s10, 8
; SI-NEXT: s_or_b32 s8, s8, s10
-; SI-NEXT: v_readlane_b32 s10, v22, 26
-; SI-NEXT: v_readlane_b32 s11, v22, 27
+; SI-NEXT: v_readlane_b32 s10, v21, 54
+; SI-NEXT: v_readlane_b32 s11, v21, 55
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s12, v22, 28
+; SI-NEXT: v_readlane_b32 s12, v21, 56
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_lshl_b32 s11, s12, 24
; SI-NEXT: s_and_b32 s8, s8, 0xffff
@@ -8749,13 +8942,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s8
; SI-NEXT: s_and_b32 s8, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v22, 49
-; SI-NEXT: s_lshl_b32 s9, s9, 8
+; SI-NEXT: s_lshl_b32 s9, s91, 8
; SI-NEXT: s_or_b32 s8, s8, s9
-; SI-NEXT: v_readlane_b32 s9, v22, 48
-; SI-NEXT: s_and_b32 s9, s9, 0xff
+; SI-NEXT: s_and_b32 s9, s89, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 16
-; SI-NEXT: s_lshl_b32 s10, s50, 24
+; SI-NEXT: s_lshl_b32 s10, s79, 24
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x68, v0
@@ -8763,15 +8954,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s8
-; SI-NEXT: v_readlane_b32 s8, v22, 30
+; SI-NEXT: v_readlane_b32 s8, v21, 58
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s9, v22, 31
+; SI-NEXT: v_readlane_b32 s9, v21, 59
; SI-NEXT: s_lshl_b32 s8, s8, 8
; SI-NEXT: s_or_b32 s6, s6, s8
-; SI-NEXT: v_readlane_b32 s8, v22, 32
-; SI-NEXT: v_readlane_b32 s9, v22, 33
+; SI-NEXT: v_readlane_b32 s8, v21, 60
+; SI-NEXT: v_readlane_b32 s9, v21, 61
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s10, v22, 34
+; SI-NEXT: v_readlane_b32 s10, v21, 62
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_lshl_b32 s9, s10, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
@@ -8782,14 +8973,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_and_b32 s6, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v22, 47
-; SI-NEXT: s_lshl_b32 s7, s7, 8
+; SI-NEXT: s_lshl_b32 s7, s77, 8
; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: v_readlane_b32 s7, v22, 46
-; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: v_readlane_b32 s8, v22, 45
+; SI-NEXT: s_and_b32 s7, s75, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s8, s8, 24
+; SI-NEXT: s_lshl_b32 s8, s73, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x70, v0
@@ -8797,15 +8985,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
-; SI-NEXT: v_readlane_b32 s6, v22, 36
+; SI-NEXT: v_readlane_b32 s6, v22, 0
; SI-NEXT: s_and_b32 s4, s4, 0xff
-; SI-NEXT: v_readlane_b32 s7, v22, 37
+; SI-NEXT: v_readlane_b32 s7, v22, 1
; SI-NEXT: s_lshl_b32 s6, s6, 8
; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: v_readlane_b32 s6, v22, 38
-; SI-NEXT: v_readlane_b32 s7, v22, 39
+; SI-NEXT: v_readlane_b32 s6, v22, 4
+; SI-NEXT: v_readlane_b32 s7, v22, 5
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s8, v22, 40
+; SI-NEXT: v_readlane_b32 s8, v22, 2
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s7, s8, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
@@ -8816,12 +9004,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: s_and_b32 s4, s5, 0xff
-; SI-NEXT: v_readlane_b32 s5, v22, 44
-; SI-NEXT: s_lshl_b32 s5, s5, 8
+; SI-NEXT: s_lshl_b32 s5, s63, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_readlane_b32 s5, v22, 43
+; SI-NEXT: v_readlane_b32 s5, v22, 7
; SI-NEXT: s_and_b32 s5, s5, 0xff
-; SI-NEXT: v_readlane_b32 s6, v22, 42
+; SI-NEXT: v_readlane_b32 s6, v22, 6
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s6, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
@@ -8832,12 +9019,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: v_readlane_b32 s30, v20, 34
-; SI-NEXT: v_readlane_b32 s19, v22, 11
-; SI-NEXT: v_readlane_b32 s17, v22, 17
-; SI-NEXT: v_readlane_b32 s15, v22, 23
-; SI-NEXT: v_readlane_b32 s13, v22, 29
-; SI-NEXT: v_readlane_b32 s11, v22, 35
-; SI-NEXT: v_readlane_b32 s9, v22, 41
+; SI-NEXT: v_readlane_b32 s19, v21, 39
+; SI-NEXT: v_readlane_b32 s17, v21, 45
+; SI-NEXT: v_readlane_b32 s15, v21, 51
+; SI-NEXT: v_readlane_b32 s13, v21, 57
+; SI-NEXT: v_readlane_b32 s11, v21, 63
+; SI-NEXT: v_readlane_b32 s9, v22, 3
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: v_readlane_b32 s31, v20, 35
; SI-NEXT: v_readlane_b32 s99, v20, 33
@@ -8881,187 +9068,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
-; SI-NEXT: .LBB13_4:
-; SI-NEXT: ; implicit-def: $sgpr51
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v22, s50, 0
-; SI-NEXT: v_writelane_b32 v22, s51, 1
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 2
-; SI-NEXT: v_writelane_b32 v22, s51, 3
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 4
-; SI-NEXT: v_writelane_b32 v22, s51, 5
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 6
-; SI-NEXT: v_writelane_b32 v22, s51, 7
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 8
-; SI-NEXT: v_writelane_b32 v22, s51, 9
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 10
-; SI-NEXT: v_writelane_b32 v22, s51, 11
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 12
-; SI-NEXT: v_writelane_b32 v22, s51, 13
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 14
-; SI-NEXT: v_writelane_b32 v22, s51, 15
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 16
-; SI-NEXT: v_writelane_b32 v22, s51, 17
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 18
-; SI-NEXT: v_writelane_b32 v22, s51, 19
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 20
-; SI-NEXT: v_writelane_b32 v22, s51, 21
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 22
-; SI-NEXT: v_writelane_b32 v22, s51, 23
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 24
-; SI-NEXT: v_writelane_b32 v22, s51, 25
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 26
-; SI-NEXT: v_writelane_b32 v22, s51, 27
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 28
-; SI-NEXT: v_writelane_b32 v22, s51, 29
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 30
-; SI-NEXT: v_writelane_b32 v22, s51, 31
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 32
-; SI-NEXT: v_writelane_b32 v22, s51, 33
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 34
-; SI-NEXT: v_writelane_b32 v22, s51, 35
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 36
-; SI-NEXT: v_writelane_b32 v22, s51, 37
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 38
-; SI-NEXT: v_writelane_b32 v22, s51, 39
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr49
-; SI-NEXT: ; implicit-def: $sgpr55
-; SI-NEXT: ; implicit-def: $sgpr54
-; SI-NEXT: ; implicit-def: $sgpr53
-; SI-NEXT: ; implicit-def: $sgpr52
-; SI-NEXT: ; implicit-def: $sgpr48
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr38
-; SI-NEXT: ; implicit-def: $sgpr36
-; SI-NEXT: ; implicit-def: $sgpr34
-; SI-NEXT: ; implicit-def: $sgpr30
-; SI-NEXT: ; implicit-def: $sgpr94
-; SI-NEXT: ; implicit-def: $sgpr92
-; SI-NEXT: ; implicit-def: $sgpr90
-; SI-NEXT: ; implicit-def: $sgpr88
-; SI-NEXT: ; implicit-def: $sgpr78
-; SI-NEXT: ; implicit-def: $sgpr76
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr56
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s50, 40
-; SI-NEXT: ; implicit-def: $sgpr98
-; SI-NEXT: ; implicit-def: $sgpr96
-; SI-NEXT: ; implicit-def: $sgpr86
-; SI-NEXT: ; implicit-def: $sgpr84
-; SI-NEXT: ; implicit-def: $sgpr82
-; SI-NEXT: ; implicit-def: $sgpr80
-; SI-NEXT: ; implicit-def: $sgpr70
-; SI-NEXT: ; implicit-def: $sgpr68
-; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: ; implicit-def: $sgpr64
-; SI-NEXT: v_writelane_b32 v22, s51, 41
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: s_branch .LBB13_2
;
; VI-LABEL: bitcast_v32i32_to_v128i8_scalar:
; VI: ; %bb.0:
@@ -9501,103 +9507,103 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v6, s69
; VI-NEXT: v_perm_b32 v17, s84, v17, v1
; VI-NEXT: v_or_b32_e32 v2, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: v_perm_b32 v7, s20, v6, v1
; VI-NEXT: v_mov_b32_e32 v26, s68
; VI-NEXT: v_readlane_b32 s16, v33, 57
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; VI-NEXT: v_mov_b32_e32 v8, s65
; VI-NEXT: v_perm_b32 v26, s16, v26, v1
; VI-NEXT: v_or_b32_e32 v2, v7, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: v_perm_b32 v6, s21, v8, v1
; VI-NEXT: v_mov_b32_e32 v19, s34
; VI-NEXT: v_readlane_b32 s16, v33, 56
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
; VI-NEXT: v_mov_b32_e32 v8, s55
; VI-NEXT: v_perm_b32 v19, s16, v19, v1
; VI-NEXT: v_or_b32_e32 v2, v6, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: v_perm_b32 v10, s22, v8, v1
; VI-NEXT: v_mov_b32_e32 v27, s71
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
; VI-NEXT: v_mov_b32_e32 v11, s52
; VI-NEXT: v_perm_b32 v27, s70, v27, v1
; VI-NEXT: v_or_b32_e32 v2, v10, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: v_perm_b32 v8, s23, v11, v1
; VI-NEXT: v_mov_b32_e32 v20, s30
; VI-NEXT: v_readlane_b32 s16, v33, 55
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
; VI-NEXT: v_mov_b32_e32 v11, s54
; VI-NEXT: v_perm_b32 v20, s16, v20, v1
; VI-NEXT: v_readlane_b32 s16, v33, 53
; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: v_perm_b32 v12, s24, v11, v1
; VI-NEXT: v_mov_b32_e32 v28, s16
; VI-NEXT: v_readlane_b32 s16, v33, 54
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
; VI-NEXT: v_mov_b32_e32 v14, s66
; VI-NEXT: v_perm_b32 v28, s16, v28, v1
; VI-NEXT: v_or_b32_e32 v2, v12, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: v_perm_b32 v11, s25, v14, v1
; VI-NEXT: v_mov_b32_e32 v21, s90
; VI-NEXT: v_readlane_b32 s16, v33, 52
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
; VI-NEXT: v_mov_b32_e32 v14, s51
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 50
; VI-NEXT: v_or_b32_e32 v2, v11, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: v_perm_b32 v15, s26, v14, v1
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 51
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
; VI-NEXT: v_mov_b32_e32 v16, s86
; VI-NEXT: v_perm_b32 v29, s16, v29, v1
; VI-NEXT: v_or_b32_e32 v2, v15, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: v_perm_b32 v14, s27, v16, v1
; VI-NEXT: v_mov_b32_e32 v22, s88
; VI-NEXT: v_readlane_b32 s16, v33, 49
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; VI-NEXT: v_mov_b32_e32 v16, s50
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 47
; VI-NEXT: v_or_b32_e32 v2, v14, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: v_perm_b32 v18, s28, v16, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 48
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; VI-NEXT: v_mov_b32_e32 v23, s64
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 46
; VI-NEXT: v_or_b32_e32 v2, v18, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: v_perm_b32 v16, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 45
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
-; VI-NEXT: v_perm_b32 v3, s16, v23, v1
+; VI-NEXT: v_perm_b32 v23, s16, v23, v1
; VI-NEXT: v_or_b32_e32 v2, v16, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 44
@@ -10167,10 +10173,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s38, s19, 16
; GFX9-NEXT: s_lshr_b32 s68, s19, 8
; GFX9-NEXT: s_lshr_b32 s54, s18, 16
-; GFX9-NEXT: s_lshr_b32 s69, s18, 8
+; GFX9-NEXT: s_lshr_b32 s71, s18, 8
; GFX9-NEXT: s_lshr_b32 s52, s17, 24
; GFX9-NEXT: s_lshr_b32 s50, s17, 16
-; GFX9-NEXT: s_lshr_b32 s71, s17, 8
+; GFX9-NEXT: s_lshr_b32 s69, s17, 8
; GFX9-NEXT: s_lshr_b32 s51, s16, 16
; GFX9-NEXT: s_lshr_b32 s85, s16, 8
; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
@@ -10347,10 +10353,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s38, s19, 16
; GFX9-NEXT: s_lshr_b32 s68, s19, 8
; GFX9-NEXT: s_lshr_b32 s54, s18, 16
-; GFX9-NEXT: s_lshr_b32 s69, s18, 8
+; GFX9-NEXT: s_lshr_b32 s71, s18, 8
; GFX9-NEXT: s_lshr_b32 s52, s17, 24
; GFX9-NEXT: s_lshr_b32 s50, s17, 16
-; GFX9-NEXT: s_lshr_b32 s71, s17, 8
+; GFX9-NEXT: s_lshr_b32 s69, s17, 8
; GFX9-NEXT: s_lshr_b32 s51, s16, 16
; GFX9-NEXT: s_lshr_b32 s85, s16, 8
; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
@@ -10370,21 +10376,21 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24
; GFX9-NEXT: .LBB13_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v8, s36
+; GFX9-NEXT: v_mov_b32_e32 v7, s36
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s85
-; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
+; GFX9-NEXT: v_perm_b32 v7, s51, v7, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v21, s52
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v4, s71
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s69
; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v7
; GFX9-NEXT: v_perm_b32 v2, s17, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v11, s34
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
-; GFX9-NEXT: v_mov_b32_e32 v4, s69
+; GFX9-NEXT: v_mov_b32_e32 v4, s71
; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
@@ -10401,13 +10407,13 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v6, s70
; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
+; GFX9-NEXT: v_perm_b32 v8, s20, v6, v1
; GFX9-NEXT: v_mov_b32_e32 v23, s49
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v14
; GFX9-NEXT: v_mov_b32_e32 v9, s80
; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v8, v2
; GFX9-NEXT: v_perm_b32 v6, s21, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v15, s94
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
@@ -10450,20 +10456,20 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; GFX9-NEXT: v_mov_b32_e32 v19, s53
; GFX9-NEXT: v_perm_b32 v26, s16, v26, v1
-; GFX9-NEXT: v_readlane_b32 s16, v30, 47
; GFX9-NEXT: v_or_b32_e32 v2, v18, v2
; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
; GFX9-NEXT: v_mov_b32_e32 v20, s88
-; GFX9-NEXT: v_mov_b32_e32 v28, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 48
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v26
; GFX9-NEXT: v_mov_b32_e32 v27, s83
-; GFX9-NEXT: v_perm_b32 v3, s16, v20, v1
+; GFX9-NEXT: v_perm_b32 v20, s16, v20, v1
+; GFX9-NEXT: v_readlane_b32 s16, v30, 47
; GFX9-NEXT: v_or_b32_e32 v2, v19, v2
+; GFX9-NEXT: v_mov_b32_e32 v28, s16
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v2, s28, v27, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v20
; GFX9-NEXT: v_readlane_b32 s16, v30, 45
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s16
@@ -10694,10 +10700,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: ; kill: killed $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr85
; GFX9-NEXT: ; implicit-def: $sgpr51
-; GFX9-NEXT: ; implicit-def: $sgpr71
+; GFX9-NEXT: ; implicit-def: $sgpr69
; GFX9-NEXT: ; implicit-def: $sgpr50
; GFX9-NEXT: ; implicit-def: $sgpr52
-; GFX9-NEXT: ; implicit-def: $sgpr69
+; GFX9-NEXT: ; implicit-def: $sgpr71
; GFX9-NEXT: ; implicit-def: $sgpr54
; GFX9-NEXT: ; implicit-def: $sgpr68
; GFX9-NEXT: ; implicit-def: $sgpr38
@@ -77726,159 +77732,159 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s46, s5, 24
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v22, s46, 40
-; SI-NEXT: s_lshr_b32 s46, s5, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 41
-; SI-NEXT: s_lshr_b32 s46, s5, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 42
-; SI-NEXT: s_lshr_b32 s46, s7, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 43
-; SI-NEXT: s_lshr_b32 s46, s7, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 44
-; SI-NEXT: s_lshr_b32 s46, s7, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 45
-; SI-NEXT: s_lshr_b32 s46, s9, 24
; SI-NEXT: v_writelane_b32 v22, s46, 46
-; SI-NEXT: s_lshr_b32 s46, s9, 16
+; SI-NEXT: s_lshr_b32 s46, s5, 16
; SI-NEXT: v_writelane_b32 v22, s46, 47
-; SI-NEXT: s_lshr_b32 s46, s9, 8
+; SI-NEXT: s_lshr_b32 s46, s5, 8
; SI-NEXT: v_writelane_b32 v22, s46, 48
-; SI-NEXT: s_lshr_b32 s46, s11, 24
+; SI-NEXT: s_lshr_b32 s46, s7, 24
; SI-NEXT: v_writelane_b32 v22, s46, 49
-; SI-NEXT: s_lshr_b32 s46, s11, 16
+; SI-NEXT: s_lshr_b32 s46, s7, 16
; SI-NEXT: v_writelane_b32 v22, s46, 50
-; SI-NEXT: s_lshr_b32 s46, s11, 8
+; SI-NEXT: s_lshr_b32 s46, s7, 8
; SI-NEXT: v_writelane_b32 v22, s46, 51
-; SI-NEXT: s_lshr_b32 s46, s13, 24
+; SI-NEXT: s_lshr_b32 s46, s9, 24
; SI-NEXT: v_writelane_b32 v22, s46, 52
-; SI-NEXT: s_lshr_b32 s46, s13, 16
+; SI-NEXT: s_lshr_b32 s46, s9, 16
; SI-NEXT: v_writelane_b32 v22, s46, 53
-; SI-NEXT: s_lshr_b32 s46, s13, 8
+; SI-NEXT: s_lshr_b32 s46, s9, 8
; SI-NEXT: v_writelane_b32 v22, s46, 54
-; SI-NEXT: s_lshr_b32 s46, s15, 24
+; SI-NEXT: s_lshr_b32 s46, s11, 24
; SI-NEXT: v_writelane_b32 v22, s46, 55
-; SI-NEXT: s_lshr_b32 s46, s15, 16
+; SI-NEXT: s_lshr_b32 s46, s11, 16
; SI-NEXT: v_writelane_b32 v22, s46, 56
-; SI-NEXT: s_lshr_b32 s46, s15, 8
+; SI-NEXT: s_lshr_b32 s46, s11, 8
; SI-NEXT: v_writelane_b32 v22, s46, 57
-; SI-NEXT: s_lshr_b32 s46, s41, 24
+; SI-NEXT: s_lshr_b32 s46, s13, 24
; SI-NEXT: v_writelane_b32 v22, s46, 58
-; SI-NEXT: s_lshr_b32 s46, s41, 16
+; SI-NEXT: s_lshr_b32 s46, s13, 16
; SI-NEXT: v_writelane_b32 v22, s46, 59
-; SI-NEXT: s_lshr_b32 s46, s41, 8
+; SI-NEXT: s_lshr_b32 s46, s13, 8
; SI-NEXT: v_writelane_b32 v22, s46, 60
-; SI-NEXT: s_lshr_b32 s46, s43, 24
+; SI-NEXT: s_lshr_b32 s46, s15, 24
; SI-NEXT: v_writelane_b32 v22, s46, 61
-; SI-NEXT: s_lshr_b32 s46, s43, 16
+; SI-NEXT: s_lshr_b32 s46, s15, 16
; SI-NEXT: v_writelane_b32 v22, s46, 62
-; SI-NEXT: s_lshr_b32 s46, s43, 8
+; SI-NEXT: s_lshr_b32 s46, s15, 8
; SI-NEXT: v_writelane_b32 v22, s46, 63
-; SI-NEXT: s_lshr_b32 s46, s45, 24
+; SI-NEXT: s_lshr_b32 s46, s41, 24
; SI-NEXT: v_writelane_b32 v21, s46, 0
-; SI-NEXT: s_lshr_b32 s46, s45, 16
+; SI-NEXT: s_lshr_b32 s46, s41, 16
; SI-NEXT: v_writelane_b32 v21, s46, 1
-; SI-NEXT: s_lshr_b32 s46, s45, 8
+; SI-NEXT: s_lshr_b32 s46, s41, 8
; SI-NEXT: v_writelane_b32 v21, s46, 2
-; SI-NEXT: s_lshr_b32 s46, s29, 24
+; SI-NEXT: s_lshr_b32 s46, s43, 24
; SI-NEXT: v_writelane_b32 v21, s46, 3
-; SI-NEXT: s_lshr_b32 s46, s29, 16
+; SI-NEXT: s_lshr_b32 s46, s43, 16
; SI-NEXT: v_writelane_b32 v21, s46, 4
-; SI-NEXT: s_lshr_b32 s46, s29, 8
+; SI-NEXT: s_lshr_b32 s46, s43, 8
; SI-NEXT: v_writelane_b32 v21, s46, 5
-; SI-NEXT: s_lshr_b32 s46, s27, 24
+; SI-NEXT: s_lshr_b32 s46, s45, 24
; SI-NEXT: v_writelane_b32 v21, s46, 6
-; SI-NEXT: s_lshr_b32 s46, s27, 16
+; SI-NEXT: s_lshr_b32 s46, s45, 16
; SI-NEXT: v_writelane_b32 v21, s46, 7
-; SI-NEXT: s_lshr_b32 s46, s27, 8
+; SI-NEXT: s_lshr_b32 s46, s45, 8
; SI-NEXT: v_writelane_b32 v21, s46, 8
-; SI-NEXT: s_lshr_b32 s46, s25, 24
+; SI-NEXT: s_lshr_b32 s46, s29, 24
; SI-NEXT: v_writelane_b32 v21, s46, 9
-; SI-NEXT: s_lshr_b32 s46, s25, 16
+; SI-NEXT: s_lshr_b32 s46, s29, 16
; SI-NEXT: v_writelane_b32 v21, s46, 10
-; SI-NEXT: s_lshr_b32 s46, s25, 8
+; SI-NEXT: s_lshr_b32 s46, s29, 8
; SI-NEXT: v_writelane_b32 v21, s46, 11
-; SI-NEXT: s_lshr_b32 s46, s23, 24
+; SI-NEXT: s_lshr_b32 s46, s27, 24
; SI-NEXT: v_writelane_b32 v21, s46, 12
-; SI-NEXT: s_lshr_b32 s46, s23, 16
+; SI-NEXT: s_lshr_b32 s46, s27, 16
; SI-NEXT: v_writelane_b32 v21, s46, 13
-; SI-NEXT: s_lshr_b32 s46, s23, 8
+; SI-NEXT: s_lshr_b32 s46, s27, 8
; SI-NEXT: v_writelane_b32 v21, s46, 14
-; SI-NEXT: s_lshr_b32 s46, s21, 24
+; SI-NEXT: s_lshr_b32 s46, s25, 24
; SI-NEXT: v_writelane_b32 v21, s46, 15
-; SI-NEXT: s_lshr_b32 s46, s21, 16
+; SI-NEXT: s_lshr_b32 s46, s25, 16
; SI-NEXT: v_writelane_b32 v21, s46, 16
-; SI-NEXT: s_lshr_b32 s46, s21, 8
+; SI-NEXT: s_lshr_b32 s46, s25, 8
; SI-NEXT: v_writelane_b32 v21, s46, 17
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
+; SI-NEXT: v_writelane_b32 v22, s46, 44
+; SI-NEXT: v_writelane_b32 v22, s47, 45
+; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8
+; SI-NEXT: v_writelane_b32 v22, s46, 42
+; SI-NEXT: v_writelane_b32 v22, s47, 43
+; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24
+; SI-NEXT: v_writelane_b32 v22, s46, 40
+; SI-NEXT: v_writelane_b32 v22, s47, 41
+; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16
; SI-NEXT: v_writelane_b32 v22, s46, 38
; SI-NEXT: v_writelane_b32 v22, s47, 39
-; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8
; SI-NEXT: v_writelane_b32 v22, s46, 36
; SI-NEXT: v_writelane_b32 v22, s47, 37
-; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24
; SI-NEXT: v_writelane_b32 v22, s46, 34
; SI-NEXT: v_writelane_b32 v22, s47, 35
-; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16
; SI-NEXT: v_writelane_b32 v22, s46, 32
; SI-NEXT: v_writelane_b32 v22, s47, 33
-; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8
; SI-NEXT: v_writelane_b32 v22, s46, 30
; SI-NEXT: v_writelane_b32 v22, s47, 31
-; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24
; SI-NEXT: v_writelane_b32 v22, s46, 28
; SI-NEXT: v_writelane_b32 v22, s47, 29
-; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
; SI-NEXT: v_writelane_b32 v22, s46, 26
; SI-NEXT: v_writelane_b32 v22, s47, 27
-; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8
; SI-NEXT: v_writelane_b32 v22, s46, 24
; SI-NEXT: v_writelane_b32 v22, s47, 25
-; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24
; SI-NEXT: v_writelane_b32 v22, s46, 22
; SI-NEXT: v_writelane_b32 v22, s47, 23
-; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
; SI-NEXT: v_writelane_b32 v22, s46, 20
; SI-NEXT: v_writelane_b32 v22, s47, 21
-; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8
; SI-NEXT: v_writelane_b32 v22, s46, 18
; SI-NEXT: v_writelane_b32 v22, s47, 19
-; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24
; SI-NEXT: v_writelane_b32 v22, s46, 16
; SI-NEXT: v_writelane_b32 v22, s47, 17
-; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16
; SI-NEXT: v_writelane_b32 v22, s46, 14
; SI-NEXT: v_writelane_b32 v22, s47, 15
-; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8
; SI-NEXT: v_writelane_b32 v22, s46, 12
; SI-NEXT: v_writelane_b32 v22, s47, 13
-; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24
; SI-NEXT: v_writelane_b32 v22, s46, 10
; SI-NEXT: v_writelane_b32 v22, s47, 11
-; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16
; SI-NEXT: v_writelane_b32 v22, s46, 8
; SI-NEXT: v_writelane_b32 v22, s47, 9
-; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8
; SI-NEXT: v_writelane_b32 v22, s46, 6
; SI-NEXT: v_writelane_b32 v22, s47, 7
-; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 24
; SI-NEXT: v_writelane_b32 v22, s46, 4
; SI-NEXT: v_writelane_b32 v22, s47, 5
-; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 16
; SI-NEXT: v_writelane_b32 v22, s46, 2
; SI-NEXT: v_writelane_b32 v22, s47, 3
-; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 8
; SI-NEXT: v_writelane_b32 v22, s46, 0
-; SI-NEXT: s_lshr_b32 s49, s19, 24
-; SI-NEXT: s_lshr_b32 s48, s19, 16
-; SI-NEXT: s_lshr_b32 s50, s19, 8
-; SI-NEXT: s_lshr_b32 s51, s17, 24
-; SI-NEXT: s_lshr_b32 s52, s17, 16
+; SI-NEXT: s_lshr_b32 s48, s23, 24
+; SI-NEXT: s_lshr_b32 s49, s23, 16
+; SI-NEXT: s_lshr_b32 s54, s23, 8
+; SI-NEXT: s_lshr_b32 s55, s21, 24
+; SI-NEXT: s_lshr_b32 s50, s21, 16
+; SI-NEXT: s_lshr_b32 s51, s21, 8
+; SI-NEXT: s_lshr_b32 s52, s19, 24
+; SI-NEXT: s_lshr_b32 s64, s19, 16
+; SI-NEXT: s_lshr_b32 s65, s19, 8
+; SI-NEXT: s_lshr_b32 s66, s17, 24
+; SI-NEXT: s_lshr_b32 s67, s17, 16
; SI-NEXT: s_lshr_b32 s53, s17, 8
-; SI-NEXT: s_lshr_b64 s[54:55], s[4:5], 16
+; SI-NEXT: s_lshr_b64 s[68:69], s[4:5], 16
; SI-NEXT: v_writelane_b32 v22, s47, 1
-; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24
-; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8
; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24
; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16
; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8
@@ -77938,159 +77944,159 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
; SI-NEXT: s_lshr_b32 s46, s5, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 40
-; SI-NEXT: s_lshr_b32 s46, s5, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 41
-; SI-NEXT: s_lshr_b32 s46, s5, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 42
-; SI-NEXT: s_lshr_b32 s46, s7, 24
-; SI-NEXT: v_writelane_b32 v22, s46, 43
-; SI-NEXT: s_lshr_b32 s46, s7, 16
-; SI-NEXT: v_writelane_b32 v22, s46, 44
-; SI-NEXT: s_lshr_b32 s46, s7, 8
-; SI-NEXT: v_writelane_b32 v22, s46, 45
-; SI-NEXT: s_lshr_b32 s46, s9, 24
; SI-NEXT: v_writelane_b32 v22, s46, 46
-; SI-NEXT: s_lshr_b32 s46, s9, 16
+; SI-NEXT: s_lshr_b32 s46, s5, 16
; SI-NEXT: v_writelane_b32 v22, s46, 47
-; SI-NEXT: s_lshr_b32 s46, s9, 8
+; SI-NEXT: s_lshr_b32 s46, s5, 8
; SI-NEXT: v_writelane_b32 v22, s46, 48
-; SI-NEXT: s_lshr_b32 s46, s11, 24
+; SI-NEXT: s_lshr_b32 s46, s7, 24
; SI-NEXT: v_writelane_b32 v22, s46, 49
-; SI-NEXT: s_lshr_b32 s46, s11, 16
+; SI-NEXT: s_lshr_b32 s46, s7, 16
; SI-NEXT: v_writelane_b32 v22, s46, 50
-; SI-NEXT: s_lshr_b32 s46, s11, 8
+; SI-NEXT: s_lshr_b32 s46, s7, 8
; SI-NEXT: v_writelane_b32 v22, s46, 51
-; SI-NEXT: s_lshr_b32 s46, s13, 24
+; SI-NEXT: s_lshr_b32 s46, s9, 24
; SI-NEXT: v_writelane_b32 v22, s46, 52
-; SI-NEXT: s_lshr_b32 s46, s13, 16
+; SI-NEXT: s_lshr_b32 s46, s9, 16
; SI-NEXT: v_writelane_b32 v22, s46, 53
-; SI-NEXT: s_lshr_b32 s46, s13, 8
+; SI-NEXT: s_lshr_b32 s46, s9, 8
; SI-NEXT: v_writelane_b32 v22, s46, 54
-; SI-NEXT: s_lshr_b32 s46, s15, 24
+; SI-NEXT: s_lshr_b32 s46, s11, 24
; SI-NEXT: v_writelane_b32 v22, s46, 55
-; SI-NEXT: s_lshr_b32 s46, s15, 16
+; SI-NEXT: s_lshr_b32 s46, s11, 16
; SI-NEXT: v_writelane_b32 v22, s46, 56
-; SI-NEXT: s_lshr_b32 s46, s15, 8
+; SI-NEXT: s_lshr_b32 s46, s11, 8
; SI-NEXT: v_writelane_b32 v22, s46, 57
-; SI-NEXT: s_lshr_b32 s46, s41, 24
+; SI-NEXT: s_lshr_b32 s46, s13, 24
; SI-NEXT: v_writelane_b32 v22, s46, 58
-; SI-NEXT: s_lshr_b32 s46, s41, 16
+; SI-NEXT: s_lshr_b32 s46, s13, 16
; SI-NEXT: v_writelane_b32 v22, s46, 59
-; SI-NEXT: s_lshr_b32 s46, s41, 8
+; SI-NEXT: s_lshr_b32 s46, s13, 8
; SI-NEXT: v_writelane_b32 v22, s46, 60
-; SI-NEXT: s_lshr_b32 s46, s43, 24
+; SI-NEXT: s_lshr_b32 s46, s15, 24
; SI-NEXT: v_writelane_b32 v22, s46, 61
-; SI-NEXT: s_lshr_b32 s46, s43, 16
+; SI-NEXT: s_lshr_b32 s46, s15, 16
; SI-NEXT: v_writelane_b32 v22, s46, 62
-; SI-NEXT: s_lshr_b32 s46, s43, 8
+; SI-NEXT: s_lshr_b32 s46, s15, 8
; SI-NEXT: v_writelane_b32 v22, s46, 63
-; SI-NEXT: s_lshr_b32 s46, s45, 24
+; SI-NEXT: s_lshr_b32 s46, s41, 24
; SI-NEXT: v_writelane_b32 v21, s46, 0
-; SI-NEXT: s_lshr_b32 s46, s45, 16
+; SI-NEXT: s_lshr_b32 s46, s41, 16
; SI-NEXT: v_writelane_b32 v21, s46, 1
-; SI-NEXT: s_lshr_b32 s46, s45, 8
+; SI-NEXT: s_lshr_b32 s46, s41, 8
; SI-NEXT: v_writelane_b32 v21, s46, 2
-; SI-NEXT: s_lshr_b32 s46, s29, 24
+; SI-NEXT: s_lshr_b32 s46, s43, 24
; SI-NEXT: v_writelane_b32 v21, s46, 3
-; SI-NEXT: s_lshr_b32 s46, s29, 16
+; SI-NEXT: s_lshr_b32 s46, s43, 16
; SI-NEXT: v_writelane_b32 v21, s46, 4
-; SI-NEXT: s_lshr_b32 s46, s29, 8
+; SI-NEXT: s_lshr_b32 s46, s43, 8
; SI-NEXT: v_writelane_b32 v21, s46, 5
-; SI-NEXT: s_lshr_b32 s46, s27, 24
+; SI-NEXT: s_lshr_b32 s46, s45, 24
; SI-NEXT: v_writelane_b32 v21, s46, 6
-; SI-NEXT: s_lshr_b32 s46, s27, 16
+; SI-NEXT: s_lshr_b32 s46, s45, 16
; SI-NEXT: v_writelane_b32 v21, s46, 7
-; SI-NEXT: s_lshr_b32 s46, s27, 8
+; SI-NEXT: s_lshr_b32 s46, s45, 8
; SI-NEXT: v_writelane_b32 v21, s46, 8
-; SI-NEXT: s_lshr_b32 s46, s25, 24
+; SI-NEXT: s_lshr_b32 s46, s29, 24
; SI-NEXT: v_writelane_b32 v21, s46, 9
-; SI-NEXT: s_lshr_b32 s46, s25, 16
+; SI-NEXT: s_lshr_b32 s46, s29, 16
; SI-NEXT: v_writelane_b32 v21, s46, 10
-; SI-NEXT: s_lshr_b32 s46, s25, 8
+; SI-NEXT: s_lshr_b32 s46, s29, 8
; SI-NEXT: v_writelane_b32 v21, s46, 11
-; SI-NEXT: s_lshr_b32 s46, s23, 24
+; SI-NEXT: s_lshr_b32 s46, s27, 24
; SI-NEXT: v_writelane_b32 v21, s46, 12
-; SI-NEXT: s_lshr_b32 s46, s23, 16
+; SI-NEXT: s_lshr_b32 s46, s27, 16
; SI-NEXT: v_writelane_b32 v21, s46, 13
-; SI-NEXT: s_lshr_b32 s46, s23, 8
+; SI-NEXT: s_lshr_b32 s46, s27, 8
; SI-NEXT: v_writelane_b32 v21, s46, 14
-; SI-NEXT: s_lshr_b32 s46, s21, 24
+; SI-NEXT: s_lshr_b32 s46, s25, 24
; SI-NEXT: v_writelane_b32 v21, s46, 15
-; SI-NEXT: s_lshr_b32 s46, s21, 16
+; SI-NEXT: s_lshr_b32 s46, s25, 16
; SI-NEXT: v_writelane_b32 v21, s46, 16
-; SI-NEXT: s_lshr_b32 s46, s21, 8
+; SI-NEXT: s_lshr_b32 s46, s25, 8
; SI-NEXT: v_writelane_b32 v21, s46, 17
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
+; SI-NEXT: v_writelane_b32 v22, s46, 44
+; SI-NEXT: v_writelane_b32 v22, s47, 45
+; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8
+; SI-NEXT: v_writelane_b32 v22, s46, 42
+; SI-NEXT: v_writelane_b32 v22, s47, 43
+; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24
+; SI-NEXT: v_writelane_b32 v22, s46, 40
+; SI-NEXT: v_writelane_b32 v22, s47, 41
+; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16
; SI-NEXT: v_writelane_b32 v22, s46, 38
; SI-NEXT: v_writelane_b32 v22, s47, 39
-; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8
; SI-NEXT: v_writelane_b32 v22, s46, 36
; SI-NEXT: v_writelane_b32 v22, s47, 37
-; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24
; SI-NEXT: v_writelane_b32 v22, s46, 34
; SI-NEXT: v_writelane_b32 v22, s47, 35
-; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16
; SI-NEXT: v_writelane_b32 v22, s46, 32
; SI-NEXT: v_writelane_b32 v22, s47, 33
-; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8
; SI-NEXT: v_writelane_b32 v22, s46, 30
; SI-NEXT: v_writelane_b32 v22, s47, 31
-; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24
; SI-NEXT: v_writelane_b32 v22, s46, 28
; SI-NEXT: v_writelane_b32 v22, s47, 29
-; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
; SI-NEXT: v_writelane_b32 v22, s46, 26
; SI-NEXT: v_writelane_b32 v22, s47, 27
-; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8
; SI-NEXT: v_writelane_b32 v22, s46, 24
; SI-NEXT: v_writelane_b32 v22, s47, 25
-; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24
; SI-NEXT: v_writelane_b32 v22, s46, 22
; SI-NEXT: v_writelane_b32 v22, s47, 23
-; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
; SI-NEXT: v_writelane_b32 v22, s46, 20
; SI-NEXT: v_writelane_b32 v22, s47, 21
-; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8
; SI-NEXT: v_writelane_b32 v22, s46, 18
; SI-NEXT: v_writelane_b32 v22, s47, 19
-; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24
; SI-NEXT: v_writelane_b32 v22, s46, 16
; SI-NEXT: v_writelane_b32 v22, s47, 17
-; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16
; SI-NEXT: v_writelane_b32 v22, s46, 14
; SI-NEXT: v_writelane_b32 v22, s47, 15
-; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8
; SI-NEXT: v_writelane_b32 v22, s46, 12
; SI-NEXT: v_writelane_b32 v22, s47, 13
-; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24
; SI-NEXT: v_writelane_b32 v22, s46, 10
; SI-NEXT: v_writelane_b32 v22, s47, 11
-; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16
; SI-NEXT: v_writelane_b32 v22, s46, 8
; SI-NEXT: v_writelane_b32 v22, s47, 9
-; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8
; SI-NEXT: v_writelane_b32 v22, s46, 6
; SI-NEXT: v_writelane_b32 v22, s47, 7
-; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 24
; SI-NEXT: v_writelane_b32 v22, s46, 4
; SI-NEXT: v_writelane_b32 v22, s47, 5
-; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 16
; SI-NEXT: v_writelane_b32 v22, s46, 2
; SI-NEXT: v_writelane_b32 v22, s47, 3
-; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 8
; SI-NEXT: v_writelane_b32 v22, s46, 0
-; SI-NEXT: s_lshr_b32 s49, s19, 24
-; SI-NEXT: s_lshr_b32 s48, s19, 16
-; SI-NEXT: s_lshr_b32 s50, s19, 8
-; SI-NEXT: s_lshr_b32 s51, s17, 24
-; SI-NEXT: s_lshr_b32 s52, s17, 16
+; SI-NEXT: s_lshr_b32 s48, s23, 24
+; SI-NEXT: s_lshr_b32 s49, s23, 16
+; SI-NEXT: s_lshr_b32 s54, s23, 8
+; SI-NEXT: s_lshr_b32 s55, s21, 24
+; SI-NEXT: s_lshr_b32 s50, s21, 16
+; SI-NEXT: s_lshr_b32 s51, s21, 8
+; SI-NEXT: s_lshr_b32 s52, s19, 24
+; SI-NEXT: s_lshr_b32 s64, s19, 16
+; SI-NEXT: s_lshr_b32 s65, s19, 8
+; SI-NEXT: s_lshr_b32 s66, s17, 24
+; SI-NEXT: s_lshr_b32 s67, s17, 16
; SI-NEXT: s_lshr_b32 s53, s17, 8
-; SI-NEXT: s_lshr_b64 s[54:55], s[4:5], 16
+; SI-NEXT: s_lshr_b64 s[68:69], s[4:5], 16
; SI-NEXT: v_writelane_b32 v22, s47, 1
-; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24
-; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8
; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24
; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16
; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8
@@ -78116,267 +78122,282 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16
; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8
; SI-NEXT: .LBB57_3: ; %end
-; SI-NEXT: s_lshl_b32 s47, s38, 8
; SI-NEXT: s_and_b32 s16, s16, 0xff
+; SI-NEXT: s_lshl_b32 s47, s38, 8
; SI-NEXT: s_or_b32 s16, s16, s47
; SI-NEXT: s_and_b32 s47, s36, 0xff
-; SI-NEXT: s_lshl_b32 s57, s34, 24
; SI-NEXT: s_lshl_b32 s47, s47, 16
-; SI-NEXT: s_or_b32 s47, s57, s47
+; SI-NEXT: s_lshl_b32 s57, s34, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s47, s57, s47
; SI-NEXT: s_or_b32 s16, s16, s47
; SI-NEXT: v_mov_b32_e32 v1, s16
; SI-NEXT: s_and_b32 s16, s17, 0xff
; SI-NEXT: s_lshl_b32 s17, s53, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s52, 0xff
+; SI-NEXT: s_and_b32 s17, s67, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s47, s51, 24
-; SI-NEXT: s_or_b32 s17, s47, s17
+; SI-NEXT: s_lshl_b32 s47, s66, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s47, s17
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: v_mov_b32_e32 v2, s16
-; SI-NEXT: s_lshl_b32 s16, s30, 8
-; SI-NEXT: s_and_b32 s17, s18, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_and_b32 s16, s18, 0xff
+; SI-NEXT: s_lshl_b32 s17, s30, 8
+; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s94, 0xff
-; SI-NEXT: s_lshl_b32 s18, s92, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s92, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v3, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s19, 0xff
-; SI-NEXT: s_lshl_b32 s17, s50, 8
+; SI-NEXT: s_lshl_b32 s17, s65, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s48, 0xff
+; SI-NEXT: s_and_b32 s17, s64, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s49, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s52, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s20, 0xff
+; SI-NEXT: s_lshl_b32 s17, s90, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v4, s16
-; SI-NEXT: s_lshl_b32 s16, s90, 8
-; SI-NEXT: s_and_b32 s17, s20, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s88, 0xff
-; SI-NEXT: s_lshl_b32 s18, s78, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s78, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 17
-; SI-NEXT: v_mov_b32_e32 v5, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s21, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s51, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 16
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 15
+; SI-NEXT: s_and_b32 s17, s50, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s55, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s22, 0xff
+; SI-NEXT: s_lshl_b32 s17, s76, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v6, s16
-; SI-NEXT: s_lshl_b32 s16, s76, 8
-; SI-NEXT: s_and_b32 s17, s22, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s74, 0xff
-; SI-NEXT: s_lshl_b32 s18, s72, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s72, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 14
-; SI-NEXT: v_mov_b32_e32 v7, s16
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s23, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s54, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 13
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 12
+; SI-NEXT: s_and_b32 s17, s49, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s48, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s24, 0xff
+; SI-NEXT: s_lshl_b32 s17, s62, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v8, s16
-; SI-NEXT: s_lshl_b32 s16, s62, 8
-; SI-NEXT: s_and_b32 s17, s24, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s60, 0xff
-; SI-NEXT: s_lshl_b32 s18, s58, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s58, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 11
-; SI-NEXT: v_mov_b32_e32 v9, s16
+; SI-NEXT: v_readlane_b32 s17, v21, 17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s25, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 10
+; SI-NEXT: v_readlane_b32 s17, v21, 16
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 9
+; SI-NEXT: v_readlane_b32 s18, v21, 15
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s26, 0xff
+; SI-NEXT: s_lshl_b32 s17, s56, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v10, s16
-; SI-NEXT: s_lshl_b32 s16, s56, 8
-; SI-NEXT: s_and_b32 s17, s26, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s46, 0xff
-; SI-NEXT: s_lshl_b32 s18, s98, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s98, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 8
-; SI-NEXT: v_mov_b32_e32 v11, s16
+; SI-NEXT: v_readlane_b32 s17, v21, 14
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s27, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 7
+; SI-NEXT: v_readlane_b32 s17, v21, 13
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 6
+; SI-NEXT: v_readlane_b32 s18, v21, 12
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s28, 0xff
+; SI-NEXT: s_lshl_b32 s17, s96, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v12, s16
-; SI-NEXT: s_lshl_b32 s16, s96, 8
-; SI-NEXT: s_and_b32 s17, s28, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s86, 0xff
-; SI-NEXT: s_lshl_b32 s18, s84, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s84, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 5
-; SI-NEXT: v_mov_b32_e32 v13, s16
+; SI-NEXT: v_readlane_b32 s17, v21, 11
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s29, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 4
+; SI-NEXT: v_readlane_b32 s17, v21, 10
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 3
+; SI-NEXT: v_readlane_b32 s18, v21, 9
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s44, 0xff
+; SI-NEXT: s_lshl_b32 s17, s82, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v14, s16
-; SI-NEXT: s_lshl_b32 s16, s82, 8
-; SI-NEXT: s_and_b32 s17, s44, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s80, 0xff
-; SI-NEXT: s_lshl_b32 s18, s70, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s70, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 2
-; SI-NEXT: v_mov_b32_e32 v15, s16
+; SI-NEXT: v_readlane_b32 s17, v21, 8
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s45, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v21, 1
+; SI-NEXT: v_readlane_b32 s17, v21, 7
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 0
-; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
+; SI-NEXT: v_readlane_b32 s18, v21, 6
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v22, 0
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
+; SI-NEXT: v_readlane_b32 s19, v22, 1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
-; SI-NEXT: v_mov_b32_e32 v16, s16
-; SI-NEXT: s_lshl_b32 s16, s68, 8
-; SI-NEXT: s_and_b32 s17, s42, 0xff
-; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s17, s66, 0xff
-; SI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
-; SI-NEXT: s_lshl_b32 s18, s64, 24
-; SI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v22, 2
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s42, 0xff
+; SI-NEXT: v_readlane_b32 s19, v22, 3
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s17, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 4
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 63
-; SI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
+; SI-NEXT: v_readlane_b32 s17, v21, 5
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s43, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 62
-; SI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
+; SI-NEXT: v_readlane_b32 s17, v21, 4
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 61
-; SI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
+; SI-NEXT: v_readlane_b32 s18, v21, 3
+; SI-NEXT: v_readlane_b32 s19, v22, 5
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: v_readlane_b32 s18, v22, 0
-; SI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0
+; SI-NEXT: v_readlane_b32 s18, v22, 6
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: v_readlane_b32 s19, v22, 1
-; SI-NEXT: buffer_store_dword v16, v1, s[0:3], 0 offen
+; SI-NEXT: v_readlane_b32 s19, v22, 7
; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_lshl_b32 s17, s18, 8
-; SI-NEXT: v_readlane_b32 s18, v22, 2
+; SI-NEXT: v_readlane_b32 s18, v22, 8
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s40, 0xff
-; SI-NEXT: v_readlane_b32 s19, v22, 3
+; SI-NEXT: v_readlane_b32 s19, v22, 9
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s18, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 4
+; SI-NEXT: v_readlane_b32 s18, v22, 10
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 60
+; SI-NEXT: v_readlane_b32 s17, v21, 2
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s41, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 59
+; SI-NEXT: v_readlane_b32 s17, v21, 1
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 58
+; SI-NEXT: v_readlane_b32 s18, v21, 0
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
@@ -78386,16 +78407,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
-; SI-NEXT: v_readlane_b32 s16, v22, 6
+; SI-NEXT: v_readlane_b32 s16, v22, 12
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_readlane_b32 s17, v22, 7
+; SI-NEXT: v_readlane_b32 s17, v22, 13
; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: v_readlane_b32 s19, v22, 5
+; SI-NEXT: v_readlane_b32 s19, v22, 11
; SI-NEXT: s_or_b32 s14, s14, s16
-; SI-NEXT: v_readlane_b32 s16, v22, 8
-; SI-NEXT: v_readlane_b32 s17, v22, 9
+; SI-NEXT: v_readlane_b32 s16, v22, 14
+; SI-NEXT: v_readlane_b32 s17, v22, 15
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 10
+; SI-NEXT: v_readlane_b32 s18, v22, 16
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s17, s18, 24
; SI-NEXT: s_and_b32 s14, s14, 0xffff
@@ -78406,12 +78427,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s14
; SI-NEXT: s_and_b32 s14, s15, 0xff
-; SI-NEXT: v_readlane_b32 s15, v22, 57
+; SI-NEXT: v_readlane_b32 s15, v22, 63
; SI-NEXT: s_lshl_b32 s15, s15, 8
; SI-NEXT: s_or_b32 s14, s14, s15
-; SI-NEXT: v_readlane_b32 s15, v22, 56
+; SI-NEXT: v_readlane_b32 s15, v22, 62
; SI-NEXT: s_and_b32 s15, s15, 0xff
-; SI-NEXT: v_readlane_b32 s16, v22, 55
+; SI-NEXT: v_readlane_b32 s16, v22, 61
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_lshl_b32 s16, s16, 24
; SI-NEXT: s_and_b32 s14, s14, 0xffff
@@ -78421,15 +78442,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s14
-; SI-NEXT: v_readlane_b32 s14, v22, 12
+; SI-NEXT: v_readlane_b32 s14, v22, 18
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s15, v22, 13
+; SI-NEXT: v_readlane_b32 s15, v22, 19
; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_or_b32 s12, s12, s14
-; SI-NEXT: v_readlane_b32 s14, v22, 14
-; SI-NEXT: v_readlane_b32 s15, v22, 15
+; SI-NEXT: v_readlane_b32 s14, v22, 20
+; SI-NEXT: v_readlane_b32 s15, v22, 21
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_readlane_b32 s16, v22, 16
+; SI-NEXT: v_readlane_b32 s16, v22, 22
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_lshl_b32 s15, s16, 24
; SI-NEXT: s_and_b32 s12, s12, 0xffff
@@ -78440,12 +78461,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s12
; SI-NEXT: s_and_b32 s12, s13, 0xff
-; SI-NEXT: v_readlane_b32 s13, v22, 54
+; SI-NEXT: v_readlane_b32 s13, v22, 60
; SI-NEXT: s_lshl_b32 s13, s13, 8
; SI-NEXT: s_or_b32 s12, s12, s13
-; SI-NEXT: v_readlane_b32 s13, v22, 53
+; SI-NEXT: v_readlane_b32 s13, v22, 59
; SI-NEXT: s_and_b32 s13, s13, 0xff
-; SI-NEXT: v_readlane_b32 s14, v22, 52
+; SI-NEXT: v_readlane_b32 s14, v22, 58
; SI-NEXT: s_lshl_b32 s13, s13, 16
; SI-NEXT: s_lshl_b32 s14, s14, 24
; SI-NEXT: s_and_b32 s12, s12, 0xffff
@@ -78455,15 +78476,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s12
-; SI-NEXT: v_readlane_b32 s12, v22, 18
+; SI-NEXT: v_readlane_b32 s12, v22, 24
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s13, v22, 19
+; SI-NEXT: v_readlane_b32 s13, v22, 25
; SI-NEXT: s_lshl_b32 s12, s12, 8
; SI-NEXT: s_or_b32 s10, s10, s12
-; SI-NEXT: v_readlane_b32 s12, v22, 20
-; SI-NEXT: v_readlane_b32 s13, v22, 21
+; SI-NEXT: v_readlane_b32 s12, v22, 26
+; SI-NEXT: v_readlane_b32 s13, v22, 27
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s14, v22, 22
+; SI-NEXT: v_readlane_b32 s14, v22, 28
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_lshl_b32 s13, s14, 24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
@@ -78474,12 +78495,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: s_and_b32 s10, s11, 0xff
-; SI-NEXT: v_readlane_b32 s11, v22, 51
+; SI-NEXT: v_readlane_b32 s11, v22, 57
; SI-NEXT: s_lshl_b32 s11, s11, 8
; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: v_readlane_b32 s11, v22, 50
+; SI-NEXT: v_readlane_b32 s11, v22, 56
; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: v_readlane_b32 s12, v22, 49
+; SI-NEXT: v_readlane_b32 s12, v22, 55
; SI-NEXT: s_lshl_b32 s11, s11, 16
; SI-NEXT: s_lshl_b32 s12, s12, 24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
@@ -78489,15 +78510,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s10
-; SI-NEXT: v_readlane_b32 s10, v22, 24
+; SI-NEXT: v_readlane_b32 s10, v22, 30
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s11, v22, 25
+; SI-NEXT: v_readlane_b32 s11, v22, 31
; SI-NEXT: s_lshl_b32 s10, s10, 8
; SI-NEXT: s_or_b32 s8, s8, s10
-; SI-NEXT: v_readlane_b32 s10, v22, 26
-; SI-NEXT: v_readlane_b32 s11, v22, 27
+; SI-NEXT: v_readlane_b32 s10, v22, 32
+; SI-NEXT: v_readlane_b32 s11, v22, 33
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s12, v22, 28
+; SI-NEXT: v_readlane_b32 s12, v22, 34
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_lshl_b32 s11, s12, 24
; SI-NEXT: s_and_b32 s8, s8, 0xffff
@@ -78508,12 +78529,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s8
; SI-NEXT: s_and_b32 s8, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v22, 48
+; SI-NEXT: v_readlane_b32 s9, v22, 54
; SI-NEXT: s_lshl_b32 s9, s9, 8
; SI-NEXT: s_or_b32 s8, s8, s9
-; SI-NEXT: v_readlane_b32 s9, v22, 47
+; SI-NEXT: v_readlane_b32 s9, v22, 53
; SI-NEXT: s_and_b32 s9, s9, 0xff
-; SI-NEXT: v_readlane_b32 s10, v22, 46
+; SI-NEXT: v_readlane_b32 s10, v22, 52
; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_lshl_b32 s10, s10, 24
; SI-NEXT: s_and_b32 s8, s8, 0xffff
@@ -78523,15 +78544,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s8
-; SI-NEXT: v_readlane_b32 s8, v22, 30
+; SI-NEXT: v_readlane_b32 s8, v22, 36
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s9, v22, 31
+; SI-NEXT: v_readlane_b32 s9, v22, 37
; SI-NEXT: s_lshl_b32 s8, s8, 8
; SI-NEXT: s_or_b32 s6, s6, s8
-; SI-NEXT: v_readlane_b32 s8, v22, 32
-; SI-NEXT: v_readlane_b32 s9, v22, 33
+; SI-NEXT: v_readlane_b32 s8, v22, 38
+; SI-NEXT: v_readlane_b32 s9, v22, 39
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s10, v22, 34
+; SI-NEXT: v_readlane_b32 s10, v22, 40
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_lshl_b32 s9, s10, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
@@ -78542,12 +78563,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_and_b32 s6, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v22, 45
+; SI-NEXT: v_readlane_b32 s7, v22, 51
; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: v_readlane_b32 s7, v22, 44
+; SI-NEXT: v_readlane_b32 s7, v22, 50
; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: v_readlane_b32 s8, v22, 43
+; SI-NEXT: v_readlane_b32 s8, v22, 49
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_lshl_b32 s8, s8, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
@@ -78557,13 +78578,13 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
-; SI-NEXT: v_readlane_b32 s6, v22, 36
+; SI-NEXT: v_readlane_b32 s6, v22, 42
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 8
-; SI-NEXT: v_readlane_b32 s7, v22, 37
+; SI-NEXT: v_readlane_b32 s7, v22, 43
; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_and_b32 s6, s54, 0xff
-; SI-NEXT: v_readlane_b32 s8, v22, 38
+; SI-NEXT: s_and_b32 s6, s68, 0xff
+; SI-NEXT: v_readlane_b32 s8, v22, 44
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s7, s8, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
@@ -78574,12 +78595,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: s_and_b32 s4, s5, 0xff
-; SI-NEXT: v_readlane_b32 s5, v22, 42
+; SI-NEXT: v_readlane_b32 s5, v22, 48
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_readlane_b32 s5, v22, 41
+; SI-NEXT: v_readlane_b32 s5, v22, 47
; SI-NEXT: s_and_b32 s5, s5, 0xff
-; SI-NEXT: v_readlane_b32 s6, v22, 40
+; SI-NEXT: v_readlane_b32 s6, v22, 46
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s6, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
@@ -78590,12 +78611,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: v_readlane_b32 s30, v20, 34
-; SI-NEXT: v_readlane_b32 s19, v22, 11
-; SI-NEXT: v_readlane_b32 s17, v22, 17
-; SI-NEXT: v_readlane_b32 s15, v22, 23
-; SI-NEXT: v_readlane_b32 s13, v22, 29
-; SI-NEXT: v_readlane_b32 s11, v22, 35
-; SI-NEXT: v_readlane_b32 s9, v22, 39
+; SI-NEXT: v_readlane_b32 s19, v22, 17
+; SI-NEXT: v_readlane_b32 s17, v22, 23
+; SI-NEXT: v_readlane_b32 s15, v22, 29
+; SI-NEXT: v_readlane_b32 s13, v22, 35
+; SI-NEXT: v_readlane_b32 s11, v22, 41
+; SI-NEXT: v_readlane_b32 s9, v22, 45
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: v_readlane_b32 s31, v20, 35
; SI-NEXT: v_readlane_b32 s99, v20, 33
@@ -78640,185 +78661,185 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB57_4:
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v22, s54, 0
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s55, 1
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr54
-; SI-NEXT: ; implicit-def: $sgpr53
-; SI-NEXT: ; implicit-def: $sgpr52
-; SI-NEXT: ; implicit-def: $sgpr51
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; implicit-def: $sgpr48
-; SI-NEXT: ; implicit-def: $sgpr49
-; SI-NEXT: ; implicit-def: $sgpr38
-; SI-NEXT: ; implicit-def: $sgpr36
-; SI-NEXT: ; implicit-def: $sgpr34
-; SI-NEXT: ; implicit-def: $sgpr30
-; SI-NEXT: ; implicit-def: $sgpr94
-; SI-NEXT: ; implicit-def: $sgpr92
-; SI-NEXT: ; implicit-def: $sgpr90
-; SI-NEXT: ; implicit-def: $sgpr88
-; SI-NEXT: ; implicit-def: $sgpr78
-; SI-NEXT: ; implicit-def: $sgpr76
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr56
-; SI-NEXT: ; implicit-def: $sgpr98
-; SI-NEXT: ; implicit-def: $sgpr96
-; SI-NEXT: ; implicit-def: $sgpr86
-; SI-NEXT: ; implicit-def: $sgpr84
-; SI-NEXT: ; implicit-def: $sgpr82
-; SI-NEXT: ; implicit-def: $sgpr80
-; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: v_writelane_b32 v22, s68, 0
+; SI-NEXT: v_writelane_b32 v22, s69, 1
; SI-NEXT: ; implicit-def: $sgpr68
-; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: ; implicit-def: $sgpr64
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 2
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s55, 3
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 4
+; SI-NEXT: v_writelane_b32 v22, s68, 2
+; SI-NEXT: v_writelane_b32 v22, s69, 3
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s55, 5
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 4
+; SI-NEXT: v_writelane_b32 v22, s69, 5
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 6
-; SI-NEXT: v_writelane_b32 v22, s55, 7
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 6
+; SI-NEXT: v_writelane_b32 v22, s69, 7
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 8
-; SI-NEXT: v_writelane_b32 v22, s55, 9
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 8
+; SI-NEXT: v_writelane_b32 v22, s69, 9
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 10
-; SI-NEXT: v_writelane_b32 v22, s55, 11
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 10
+; SI-NEXT: v_writelane_b32 v22, s69, 11
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 12
-; SI-NEXT: v_writelane_b32 v22, s55, 13
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 12
+; SI-NEXT: v_writelane_b32 v22, s69, 13
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 14
-; SI-NEXT: v_writelane_b32 v22, s55, 15
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 14
+; SI-NEXT: v_writelane_b32 v22, s69, 15
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 16
-; SI-NEXT: v_writelane_b32 v22, s55, 17
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 16
+; SI-NEXT: v_writelane_b32 v22, s69, 17
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 18
-; SI-NEXT: v_writelane_b32 v22, s55, 19
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 18
+; SI-NEXT: v_writelane_b32 v22, s69, 19
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 20
-; SI-NEXT: v_writelane_b32 v22, s55, 21
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 20
+; SI-NEXT: v_writelane_b32 v22, s69, 21
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 22
-; SI-NEXT: v_writelane_b32 v22, s55, 23
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 22
+; SI-NEXT: v_writelane_b32 v22, s69, 23
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 24
-; SI-NEXT: v_writelane_b32 v22, s55, 25
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 24
+; SI-NEXT: v_writelane_b32 v22, s69, 25
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 26
-; SI-NEXT: v_writelane_b32 v22, s55, 27
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 26
+; SI-NEXT: v_writelane_b32 v22, s69, 27
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 28
-; SI-NEXT: v_writelane_b32 v22, s55, 29
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 28
+; SI-NEXT: v_writelane_b32 v22, s69, 29
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 30
-; SI-NEXT: v_writelane_b32 v22, s55, 31
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 30
+; SI-NEXT: v_writelane_b32 v22, s69, 31
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 32
-; SI-NEXT: v_writelane_b32 v22, s55, 33
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 32
+; SI-NEXT: v_writelane_b32 v22, s69, 33
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 34
-; SI-NEXT: v_writelane_b32 v22, s55, 35
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: v_writelane_b32 v22, s68, 34
+; SI-NEXT: v_writelane_b32 v22, s69, 35
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; kill: killed $sgpr46
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 36
-; SI-NEXT: v_writelane_b32 v22, s55, 37
+; SI-NEXT: ; implicit-def: $sgpr53
+; SI-NEXT: ; implicit-def: $sgpr67
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: ; implicit-def: $sgpr51
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr55
; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr49
+; SI-NEXT: ; implicit-def: $sgpr48
; SI-NEXT: ; kill: killed $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: ; implicit-def: $sgpr36
+; SI-NEXT: ; implicit-def: $sgpr34
+; SI-NEXT: ; implicit-def: $sgpr30
+; SI-NEXT: ; implicit-def: $sgpr94
+; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: ; implicit-def: $sgpr90
+; SI-NEXT: ; implicit-def: $sgpr88
+; SI-NEXT: ; implicit-def: $sgpr78
+; SI-NEXT: ; implicit-def: $sgpr76
+; SI-NEXT: ; implicit-def: $sgpr74
+; SI-NEXT: ; implicit-def: $sgpr72
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; kill: killed $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: v_writelane_b32 v22, s54, 38
-; SI-NEXT: v_writelane_b32 v22, s55, 39
-; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: v_writelane_b32 v22, s68, 36
+; SI-NEXT: v_writelane_b32 v22, s69, 37
+; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: ; implicit-def: $sgpr98
+; SI-NEXT: ; implicit-def: $sgpr96
+; SI-NEXT: ; implicit-def: $sgpr86
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: ; implicit-def: $sgpr82
+; SI-NEXT: ; implicit-def: $sgpr80
+; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: v_writelane_b32 v22, s68, 38
+; SI-NEXT: v_writelane_b32 v22, s69, 39
+; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: v_writelane_b32 v22, s68, 40
+; SI-NEXT: v_writelane_b32 v22, s69, 41
+; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: v_writelane_b32 v22, s68, 42
+; SI-NEXT: v_writelane_b32 v22, s69, 43
+; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: v_writelane_b32 v22, s68, 44
+; SI-NEXT: v_writelane_b32 v22, s69, 45
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: s_branch .LBB57_2
;
; VI-LABEL: bitcast_v16i64_to_v128i8_scalar:
@@ -79259,103 +79280,103 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v6, s69
; VI-NEXT: v_perm_b32 v17, s84, v17, v1
; VI-NEXT: v_or_b32_e32 v2, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: v_perm_b32 v7, s20, v6, v1
; VI-NEXT: v_mov_b32_e32 v26, s68
; VI-NEXT: v_readlane_b32 s16, v33, 57
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; VI-NEXT: v_mov_b32_e32 v8, s65
; VI-NEXT: v_perm_b32 v26, s16, v26, v1
; VI-NEXT: v_or_b32_e32 v2, v7, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: v_perm_b32 v6, s21, v8, v1
; VI-NEXT: v_mov_b32_e32 v19, s34
; VI-NEXT: v_readlane_b32 s16, v33, 56
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
; VI-NEXT: v_mov_b32_e32 v8, s55
; VI-NEXT: v_perm_b32 v19, s16, v19, v1
; VI-NEXT: v_or_b32_e32 v2, v6, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: v_perm_b32 v10, s22, v8, v1
; VI-NEXT: v_mov_b32_e32 v27, s71
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
; VI-NEXT: v_mov_b32_e32 v11, s52
; VI-NEXT: v_perm_b32 v27, s70, v27, v1
; VI-NEXT: v_or_b32_e32 v2, v10, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: v_perm_b32 v8, s23, v11, v1
; VI-NEXT: v_mov_b32_e32 v20, s30
; VI-NEXT: v_readlane_b32 s16, v33, 55
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
; VI-NEXT: v_mov_b32_e32 v11, s54
; VI-NEXT: v_perm_b32 v20, s16, v20, v1
; VI-NEXT: v_readlane_b32 s16, v33, 53
; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: v_perm_b32 v12, s24, v11, v1
; VI-NEXT: v_mov_b32_e32 v28, s16
; VI-NEXT: v_readlane_b32 s16, v33, 54
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
; VI-NEXT: v_mov_b32_e32 v14, s66
; VI-NEXT: v_perm_b32 v28, s16, v28, v1
; VI-NEXT: v_or_b32_e32 v2, v12, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: v_perm_b32 v11, s25, v14, v1
; VI-NEXT: v_mov_b32_e32 v21, s90
; VI-NEXT: v_readlane_b32 s16, v33, 52
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
; VI-NEXT: v_mov_b32_e32 v14, s51
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 50
; VI-NEXT: v_or_b32_e32 v2, v11, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: v_perm_b32 v15, s26, v14, v1
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 51
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
; VI-NEXT: v_mov_b32_e32 v16, s86
; VI-NEXT: v_perm_b32 v29, s16, v29, v1
; VI-NEXT: v_or_b32_e32 v2, v15, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: v_perm_b32 v14, s27, v16, v1
; VI-NEXT: v_mov_b32_e32 v22, s88
; VI-NEXT: v_readlane_b32 s16, v33, 49
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; VI-NEXT: v_mov_b32_e32 v16, s50
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 47
; VI-NEXT: v_or_b32_e32 v2, v14, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: v_perm_b32 v18, s28, v16, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 48
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; VI-NEXT: v_mov_b32_e32 v23, s64
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 46
; VI-NEXT: v_or_b32_e32 v2, v18, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: v_perm_b32 v16, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 45
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
-; VI-NEXT: v_perm_b32 v3, s16, v23, v1
+; VI-NEXT: v_perm_b32 v23, s16, v23, v1
; VI-NEXT: v_or_b32_e32 v2, v16, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 44
@@ -79925,10 +79946,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s38, s19, 16
; GFX9-NEXT: s_lshr_b32 s68, s19, 8
; GFX9-NEXT: s_lshr_b32 s54, s18, 16
-; GFX9-NEXT: s_lshr_b32 s69, s18, 8
+; GFX9-NEXT: s_lshr_b32 s71, s18, 8
; GFX9-NEXT: s_lshr_b32 s52, s17, 24
; GFX9-NEXT: s_lshr_b32 s50, s17, 16
-; GFX9-NEXT: s_lshr_b32 s71, s17, 8
+; GFX9-NEXT: s_lshr_b32 s69, s17, 8
; GFX9-NEXT: s_lshr_b32 s51, s16, 16
; GFX9-NEXT: s_lshr_b32 s85, s16, 8
; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
@@ -80105,10 +80126,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s38, s19, 16
; GFX9-NEXT: s_lshr_b32 s68, s19, 8
; GFX9-NEXT: s_lshr_b32 s54, s18, 16
-; GFX9-NEXT: s_lshr_b32 s69, s18, 8
+; GFX9-NEXT: s_lshr_b32 s71, s18, 8
; GFX9-NEXT: s_lshr_b32 s52, s17, 24
; GFX9-NEXT: s_lshr_b32 s50, s17, 16
-; GFX9-NEXT: s_lshr_b32 s71, s17, 8
+; GFX9-NEXT: s_lshr_b32 s69, s17, 8
; GFX9-NEXT: s_lshr_b32 s51, s16, 16
; GFX9-NEXT: s_lshr_b32 s85, s16, 8
; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
@@ -80128,21 +80149,21 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24
; GFX9-NEXT: .LBB57_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v8, s36
+; GFX9-NEXT: v_mov_b32_e32 v7, s36
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s85
-; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
+; GFX9-NEXT: v_perm_b32 v7, s51, v7, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v21, s52
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v4, s71
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s69
; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v7
; GFX9-NEXT: v_perm_b32 v2, s17, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v11, s34
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
-; GFX9-NEXT: v_mov_b32_e32 v4, s69
+; GFX9-NEXT: v_mov_b32_e32 v4, s71
; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
@@ -80159,13 +80180,13 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v6, s70
; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
+; GFX9-NEXT: v_perm_b32 v8, s20, v6, v1
; GFX9-NEXT: v_mov_b32_e32 v23, s49
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v14
; GFX9-NEXT: v_mov_b32_e32 v9, s80
; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v8, v2
; GFX9-NEXT: v_perm_b32 v6, s21, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v15, s94
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
@@ -80208,20 +80229,20 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17
; GFX9-NEXT: v_mov_b32_e32 v19, s53
; GFX9-NEXT: v_perm_b32 v26, s16, v26, v1
-; GFX9-NEXT: v_readlane_b32 s16, v30, 47
; GFX9-NEXT: v_or_b32_e32 v2, v18, v2
; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
; GFX9-NEXT: v_mov_b32_e32 v20, s88
-; GFX9-NEXT: v_mov_b32_e32 v28, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 48
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v26
; GFX9-NEXT: v_mov_b32_e32 v27, s83
-; GFX9-NEXT: v_perm_b32 v3, s16, v20, v1
+; GFX9-NEXT: v_perm_b32 v20, s16, v20, v1
+; GFX9-NEXT: v_readlane_b32 s16, v30, 47
; GFX9-NEXT: v_or_b32_e32 v2, v19, v2
+; GFX9-NEXT: v_mov_b32_e32 v28, s16
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v2, s28, v27, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v20
; GFX9-NEXT: v_readlane_b32 s16, v30, 45
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s16
@@ -80452,10 +80473,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: ; kill: killed $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr85
; GFX9-NEXT: ; implicit-def: $sgpr51
-; GFX9-NEXT: ; implicit-def: $sgpr71
+; GFX9-NEXT: ; implicit-def: $sgpr69
; GFX9-NEXT: ; implicit-def: $sgpr50
; GFX9-NEXT: ; implicit-def: $sgpr52
-; GFX9-NEXT: ; implicit-def: $sgpr69
+; GFX9-NEXT: ; implicit-def: $sgpr71
; GFX9-NEXT: ; implicit-def: $sgpr54
; GFX9-NEXT: ; implicit-def: $sgpr68
; GFX9-NEXT: ; implicit-def: $sgpr38
@@ -109637,9 +109658,9 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -109894,167 +109915,155 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8
; SI-NEXT: s_cbranch_execnz .LBB73_4
; SI-NEXT: .LBB73_2: ; %cmp.true
-; SI-NEXT: v_add_f64 v[33:34], s[4:5], 1.0
-; SI-NEXT: v_add_f64 v[3:4], s[8:9], 1.0
-; SI-NEXT: v_lshr_b64 v[9:10], v[33:34], 24
-; SI-NEXT: v_add_f64 v[5:6], s[10:11], 1.0
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[9:10], v[33:34], 16
-; SI-NEXT: v_add_f64 v[1:2], s[6:7], 1.0
-; SI-NEXT: v_add_f64 v[17:18], s[12:13], 1.0
-; SI-NEXT: v_add_f64 v[7:8], s[40:41], 1.0
-; SI-NEXT: v_lshr_b64 v[53:54], v[3:4], 16
-; SI-NEXT: v_add_f64 v[40:41], s[42:43], 1.0
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: v_lshr_b64 v[54:55], v[3:4], 8
-; SI-NEXT: v_lshr_b64 v[44:45], v[5:6], 8
-; SI-NEXT: v_add_f64 v[21:22], s[44:45], 1.0
-; SI-NEXT: v_readfirstlane_b32 s11, v6
-; SI-NEXT: v_readfirstlane_b32 s5, v34
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[9:10], v[33:34], 8
-; SI-NEXT: v_lshr_b64 v[34:35], v[1:2], 16
-; SI-NEXT: v_lshr_b64 v[11:12], v[5:6], 24
-; SI-NEXT: v_lshr_b64 v[49:50], v[5:6], 16
-; SI-NEXT: v_mov_b32_e32 v55, v5
-; SI-NEXT: v_lshr_b64 v[45:46], v[17:18], 24
-; SI-NEXT: v_lshr_b64 v[58:59], v[17:18], 16
-; SI-NEXT: v_lshr_b64 v[5:6], v[7:8], 24
-; SI-NEXT: v_readfirstlane_b32 s13, v18
-; SI-NEXT: v_lshr_b64 v[59:60], v[17:18], 8
-; SI-NEXT: v_mov_b32_e32 v35, v17
-; SI-NEXT: v_lshr_b64 v[17:18], v[7:8], 16
-; SI-NEXT: v_lshr_b64 v[15:16], v[7:8], 8
-; SI-NEXT: v_mov_b32_e32 v46, v7
-; SI-NEXT: v_lshr_b64 v[6:7], v[40:41], 8
-; SI-NEXT: v_readfirstlane_b32 s41, v8
-; SI-NEXT: v_lshr_b64 v[7:8], v[21:22], 8
-; SI-NEXT: v_add_f64 v[28:29], s[28:29], 1.0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[28:29], 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[28:29], 16
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[28:29], 8
-; SI-NEXT: v_add_f64 v[47:48], s[26:27], 1.0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[47:48], 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[47:48], 16
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[47:48], 8
-; SI-NEXT: v_add_f64 v[51:52], s[24:25], 1.0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[51:52], 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[51:52], 16
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[51:52], 8
-; SI-NEXT: v_add_f64 v[42:43], s[22:23], 1.0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[42:43], 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[42:43], 16
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: v_add_f64 v[1:2], s[4:5], 1.0
+; SI-NEXT: v_add_f64 v[3:4], s[6:7], 1.0
+; SI-NEXT: v_lshr_b64 v[15:16], v[1:2], 24
+; SI-NEXT: v_add_f64 v[5:6], s[8:9], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[1:2], 16
+; SI-NEXT: v_add_f64 v[7:8], s[10:11], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[1:2], 8
+; SI-NEXT: v_add_f64 v[9:10], s[12:13], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[3:4], 24
+; SI-NEXT: v_add_f64 v[11:12], s[14:15], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[3:4], 16
+; SI-NEXT: v_add_f64 v[13:14], s[40:41], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[3:4], 8
+; SI-NEXT: v_readfirstlane_b32 s41, v14
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[5:6], 24
+; SI-NEXT: v_add_f64 v[17:18], s[42:43], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[5:6], 16
+; SI-NEXT: v_add_f64 v[48:49], s[26:27], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[5:6], 8
+; SI-NEXT: v_add_f64 v[25:26], s[44:45], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[15:16], v[7:8], 24
+; SI-NEXT: v_add_f64 v[31:32], s[28:29], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[42:43], 8
-; SI-NEXT: v_add_f64 v[56:57], s[20:21], 1.0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[7:8], 16
+; SI-NEXT: v_add_f64 v[54:55], s[24:25], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[56:57], 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[7:8], 8
+; SI-NEXT: v_lshr_b64 v[34:35], v[48:49], 24
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[56:57], 16
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[9:10], 24
+; SI-NEXT: v_add_f64 v[43:44], s[22:23], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[56:57], 8
-; SI-NEXT: v_add_f64 v[19:20], s[18:19], 1.0
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[9:10], 16
+; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 24
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[19:20], 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[9:10], 8
+; SI-NEXT: v_lshr_b64 v[35:36], v[48:49], 16
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[19:20], 16
-; SI-NEXT: v_add_f64 v[24:25], s[16:17], 1.0
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[11:12], 24
+; SI-NEXT: v_add_f64 v[58:59], s[20:21], 1.0
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[9:10], v[1:2], 24
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[11:12], 16
+; SI-NEXT: v_readfirstlane_b32 s27, v49
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[24:25], 24
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[11:12], 8
+; SI-NEXT: v_readfirstlane_b32 s29, v32
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[9:10], v[1:2], 8
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_lshr_b64 v[15:16], v[13:14], 24
+; SI-NEXT: v_readfirstlane_b32 s45, v26
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[7:8], v[24:25], 8
-; SI-NEXT: v_mov_b32_e32 v8, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_lshr_b64 v[26:27], v[21:22], 16
-; SI-NEXT: v_add_f64 v[38:39], s[14:15], 1.0
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: v_lshr_b64 v[12:13], v[38:39], 8
-; SI-NEXT: v_lshr_b64 v[13:14], v[40:41], 24
-; SI-NEXT: v_mov_b32_e32 v14, v34
+; SI-NEXT: v_lshr_b64 v[15:16], v[13:14], 16
+; SI-NEXT: v_readfirstlane_b32 s43, v18
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshr_b64 v[16:17], v[40:41], 16
-; SI-NEXT: v_readfirstlane_b32 s17, v25
-; SI-NEXT: v_readfirstlane_b32 s45, v22
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[17:18], v[21:22], 24
-; SI-NEXT: v_lshr_b64 v[22:23], v[24:25], 16
-; SI-NEXT: v_lshr_b64 v[30:31], v[38:39], 24
-; SI-NEXT: v_readfirstlane_b32 s19, v20
-; SI-NEXT: v_readfirstlane_b32 s21, v57
-; SI-NEXT: v_readfirstlane_b32 s23, v43
-; SI-NEXT: v_readfirstlane_b32 s25, v52
-; SI-NEXT: v_readfirstlane_b32 s27, v48
-; SI-NEXT: v_readfirstlane_b32 s29, v29
-; SI-NEXT: v_readfirstlane_b32 s43, v41
-; SI-NEXT: v_readfirstlane_b32 s15, v39
-; SI-NEXT: v_readfirstlane_b32 s9, v4
-; SI-NEXT: v_readfirstlane_b32 s7, v2
-; SI-NEXT: v_lshr_b64 v[36:37], v[3:4], 24
-; SI-NEXT: v_lshr_b64 v[31:32], v[38:39], 16
-; SI-NEXT: v_mov_b32_e32 v50, v38
-; SI-NEXT: v_lshr_b64 v[38:39], v[19:20], 8
+; SI-NEXT: v_lshr_b64 v[14:15], v[13:14], 8
+; SI-NEXT: v_lshr_b64 v[56:57], v[17:18], 8
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[14:15], v[17:18], 24
+; SI-NEXT: v_lshr_b64 v[23:24], v[31:32], 16
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[14:15], v[17:18], 16
+; SI-NEXT: v_lshr_b64 v[18:19], v[25:26], 8
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[14:15], v[25:26], 24
+; SI-NEXT: v_lshr_b64 v[15:16], v[25:26], 16
+; SI-NEXT: v_lshr_b64 v[26:27], v[31:32], 8
+; SI-NEXT: v_lshr_b64 v[32:33], v[48:49], 8
+; SI-NEXT: v_lshr_b64 v[36:37], v[54:55], 24
+; SI-NEXT: v_lshr_b64 v[49:50], v[54:55], 8
+; SI-NEXT: v_add_f64 v[20:21], s[18:19], 1.0
+; SI-NEXT: v_lshr_b64 v[37:38], v[54:55], 16
+; SI-NEXT: v_lshr_b64 v[50:51], v[43:44], 24
+; SI-NEXT: v_add_f64 v[28:29], s[16:17], 1.0
+; SI-NEXT: v_lshr_b64 v[51:52], v[43:44], 16
+; SI-NEXT: v_lshr_b64 v[38:39], v[58:59], 24
+; SI-NEXT: v_readfirstlane_b32 s23, v44
+; SI-NEXT: v_lshr_b64 v[52:53], v[43:44], 8
+; SI-NEXT: v_lshr_b64 v[39:40], v[58:59], 16
+; SI-NEXT: v_lshr_b64 v[44:45], v[20:21], 8
+; SI-NEXT: v_lshr_b64 v[40:41], v[20:21], 24
+; SI-NEXT: v_lshr_b64 v[45:46], v[28:29], 24
+; SI-NEXT: v_readfirstlane_b32 s17, v29
+; SI-NEXT: v_readfirstlane_b32 s19, v21
+; SI-NEXT: v_readfirstlane_b32 s21, v59
+; SI-NEXT: v_readfirstlane_b32 s25, v55
+; SI-NEXT: v_readfirstlane_b32 s15, v12
+; SI-NEXT: v_readfirstlane_b32 s13, v10
+; SI-NEXT: v_readfirstlane_b32 s11, v8
+; SI-NEXT: v_readfirstlane_b32 s9, v6
+; SI-NEXT: v_readfirstlane_b32 s7, v4
+; SI-NEXT: v_readfirstlane_b32 s5, v2
+; SI-NEXT: v_lshr_b64 v[59:60], v[58:59], 8
+; SI-NEXT: v_lshr_b64 v[41:42], v[20:21], 16
+; SI-NEXT: v_lshr_b64 v[46:47], v[28:29], 16
+; SI-NEXT: v_lshr_b64 v[29:30], v[28:29], 8
; SI-NEXT: s_lshr_b32 s10, s5, 24
; SI-NEXT: s_lshr_b32 s12, s5, 16
; SI-NEXT: s_lshr_b32 s14, s5, 8
@@ -110103,20 +110112,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: s_lshr_b32 s8, s17, 24
; SI-NEXT: s_lshr_b32 vcc_lo, s17, 16
; SI-NEXT: s_lshr_b32 s6, s17, 8
-; SI-NEXT: v_mov_b32_e32 v37, v12
-; SI-NEXT: v_mov_b32_e32 v18, v6
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_mov_b32_e32 v27, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_mov_b32_e32 v34, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_mov_b32_e32 v25, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_branch .LBB73_5
; SI-NEXT: .LBB73_3:
; SI-NEXT: ; implicit-def: $sgpr46
@@ -110299,37 +110294,54 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: ; implicit-def: $sgpr48
; SI-NEXT: s_branch .LBB73_2
; SI-NEXT: .LBB73_4:
-; SI-NEXT: v_mov_b32_e32 v1, s34
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v3, s6
+; SI-NEXT: v_mov_b32_e32 v2, s66
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s94
-; SI-NEXT: v_mov_b32_e32 v3, s8
-; SI-NEXT: v_mov_b32_e32 v7, s38
-; SI-NEXT: v_mov_b32_e32 v22, s36
-; SI-NEXT: v_mov_b32_e32 v38, s30
-; SI-NEXT: v_mov_b32_e32 v24, s16
-; SI-NEXT: v_mov_b32_e32 v19, s18
-; SI-NEXT: v_mov_b32_e32 v56, s20
-; SI-NEXT: v_mov_b32_e32 v42, s22
-; SI-NEXT: v_mov_b32_e32 v51, s24
-; SI-NEXT: v_mov_b32_e32 v47, s26
-; SI-NEXT: v_mov_b32_e32 v28, s28
-; SI-NEXT: v_mov_b32_e32 v21, s44
-; SI-NEXT: v_mov_b32_e32 v40, s42
-; SI-NEXT: v_mov_b32_e32 v46, s40
-; SI-NEXT: v_mov_b32_e32 v50, s14
-; SI-NEXT: v_mov_b32_e32 v35, s12
-; SI-NEXT: v_mov_b32_e32 v55, s10
-; SI-NEXT: v_mov_b32_e32 v33, s4
-; SI-NEXT: v_mov_b32_e32 v26, s80
-; SI-NEXT: v_mov_b32_e32 v17, s70
-; SI-NEXT: v_mov_b32_e32 v18, s68
-; SI-NEXT: v_mov_b32_e32 v16, s66
-; SI-NEXT: v_mov_b32_e32 v13, s64
-; SI-NEXT: v_mov_b32_e32 v15, s54
-; SI-NEXT: v_mov_b32_e32 v5, s50
-; SI-NEXT: v_mov_b32_e32 v34, s48
+; SI-NEXT: v_mov_b32_e32 v2, s64
+; SI-NEXT: v_mov_b32_e32 v35, s46
+; SI-NEXT: v_readlane_b32 s46, v62, 0
+; SI-NEXT: v_readlane_b32 s47, v62, 1
+; SI-NEXT: v_mov_b32_e32 v29, s38
+; SI-NEXT: v_mov_b32_e32 v46, s36
+; SI-NEXT: v_mov_b32_e32 v45, s34
+; SI-NEXT: v_mov_b32_e32 v44, s30
+; SI-NEXT: v_mov_b32_e32 v41, s94
+; SI-NEXT: v_mov_b32_e32 v40, s92
+; SI-NEXT: v_mov_b32_e32 v59, s90
+; SI-NEXT: v_mov_b32_e32 v39, s88
+; SI-NEXT: v_mov_b32_e32 v38, s78
+; SI-NEXT: v_mov_b32_e32 v52, s76
+; SI-NEXT: v_mov_b32_e32 v51, s74
+; SI-NEXT: v_mov_b32_e32 v50, s72
+; SI-NEXT: v_mov_b32_e32 v49, s62
+; SI-NEXT: v_mov_b32_e32 v37, s60
+; SI-NEXT: v_mov_b32_e32 v36, s58
+; SI-NEXT: v_mov_b32_e32 v32, s56
+; SI-NEXT: v_mov_b32_e32 v28, s16
+; SI-NEXT: v_mov_b32_e32 v20, s18
+; SI-NEXT: v_mov_b32_e32 v58, s20
+; SI-NEXT: v_mov_b32_e32 v43, s22
+; SI-NEXT: v_mov_b32_e32 v54, s24
+; SI-NEXT: v_mov_b32_e32 v48, s26
+; SI-NEXT: v_mov_b32_e32 v31, s28
+; SI-NEXT: v_mov_b32_e32 v25, s44
+; SI-NEXT: v_mov_b32_e32 v17, s42
+; SI-NEXT: v_mov_b32_e32 v13, s40
+; SI-NEXT: v_mov_b32_e32 v11, s14
+; SI-NEXT: v_mov_b32_e32 v9, s12
+; SI-NEXT: v_mov_b32_e32 v7, s10
+; SI-NEXT: v_mov_b32_e32 v5, s8
+; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_mov_b32_e32 v34, s98
+; SI-NEXT: v_mov_b32_e32 v26, s96
+; SI-NEXT: v_mov_b32_e32 v23, s86
+; SI-NEXT: v_mov_b32_e32 v22, s84
+; SI-NEXT: v_mov_b32_e32 v18, s82
+; SI-NEXT: v_mov_b32_e32 v15, s80
+; SI-NEXT: v_mov_b32_e32 v14, s70
+; SI-NEXT: v_mov_b32_e32 v56, s68
; SI-NEXT: v_readlane_b32 s10, v62, 34
; SI-NEXT: v_readlane_b32 s12, v62, 35
; SI-NEXT: v_readlane_b32 s14, v62, 36
@@ -110343,16 +110355,31 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: v_readlane_b32 s40, v62, 44
; SI-NEXT: v_readlane_b32 s42, v62, 45
; SI-NEXT: v_readlane_b32 s44, v62, 46
+; SI-NEXT: v_readlane_b32 s56, v62, 49
; SI-NEXT: v_readlane_b32 s57, v62, 50
+; SI-NEXT: v_readlane_b32 s58, v62, 51
; SI-NEXT: v_readlane_b32 s59, v62, 52
+; SI-NEXT: v_readlane_b32 s60, v62, 53
; SI-NEXT: v_readlane_b32 s61, v62, 54
+; SI-NEXT: v_readlane_b32 s62, v62, 55
; SI-NEXT: v_readlane_b32 s63, v62, 56
+; SI-NEXT: v_readlane_b32 s72, v62, 57
; SI-NEXT: v_readlane_b32 s73, v62, 58
+; SI-NEXT: v_readlane_b32 s74, v62, 59
; SI-NEXT: v_readlane_b32 s75, v62, 60
+; SI-NEXT: v_readlane_b32 s76, v62, 61
; SI-NEXT: v_readlane_b32 s77, v62, 62
+; SI-NEXT: v_readlane_b32 s78, v62, 63
; SI-NEXT: v_readlane_b32 s79, v61, 0
+; SI-NEXT: v_readlane_b32 s88, v61, 1
; SI-NEXT: v_readlane_b32 s89, v61, 2
+; SI-NEXT: v_readlane_b32 s90, v61, 3
; SI-NEXT: v_readlane_b32 s91, v61, 4
+; SI-NEXT: v_readlane_b32 s92, v61, 5
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s54
; SI-NEXT: v_readlane_b32 s93, v61, 6
; SI-NEXT: v_readlane_b32 s94, v61, 7
; SI-NEXT: v_readlane_b32 s95, v61, 8
@@ -110364,481 +110391,418 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: v_readlane_b32 s37, v61, 14
; SI-NEXT: v_readlane_b32 s8, v61, 15
; SI-NEXT: v_readlane_b32 vcc_lo, v61, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s92
-; SI-NEXT: v_readlane_b32 s92, v61, 5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s90
-; SI-NEXT: v_readlane_b32 s90, v61, 3
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s88
-; SI-NEXT: v_readlane_b32 s88, v61, 1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s78
-; SI-NEXT: v_readlane_b32 s78, v62, 63
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s76
-; SI-NEXT: v_readlane_b32 s76, v62, 61
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s74
-; SI-NEXT: v_readlane_b32 s74, v62, 59
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s72
-; SI-NEXT: v_readlane_b32 s72, v62, 57
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s62
-; SI-NEXT: v_readlane_b32 s62, v62, 55
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: v_readlane_b32 s6, v61, 17
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s60
-; SI-NEXT: v_readlane_b32 s60, v62, 53
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v2, s52
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s58
-; SI-NEXT: v_readlane_b32 s58, v62, 51
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v2, s50
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v1, s56
-; SI-NEXT: v_readlane_b32 s56, v62, 49
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s46
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v2, s98
-; SI-NEXT: v_readlane_b32 s46, v62, 0
-; SI-NEXT: v_readlane_b32 s47, v62, 1
-; SI-NEXT: v_mov_b32_e32 v37, s46
; SI-NEXT: v_readlane_b32 s46, v62, 2
; SI-NEXT: v_readlane_b32 s47, v62, 3
-; SI-NEXT: v_mov_b32_e32 v31, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 4
; SI-NEXT: v_readlane_b32 s47, v62, 5
-; SI-NEXT: v_mov_b32_e32 v30, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 6
; SI-NEXT: v_readlane_b32 s47, v62, 7
-; SI-NEXT: v_mov_b32_e32 v59, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 8
; SI-NEXT: v_readlane_b32 s47, v62, 9
-; SI-NEXT: v_mov_b32_e32 v58, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 10
; SI-NEXT: v_readlane_b32 s47, v62, 11
-; SI-NEXT: v_mov_b32_e32 v45, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 12
; SI-NEXT: v_readlane_b32 s47, v62, 13
-; SI-NEXT: v_mov_b32_e32 v44, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 14
; SI-NEXT: v_readlane_b32 s47, v62, 15
-; SI-NEXT: v_mov_b32_e32 v49, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 16
; SI-NEXT: v_readlane_b32 s47, v62, 17
-; SI-NEXT: v_mov_b32_e32 v11, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 18
; SI-NEXT: v_readlane_b32 s47, v62, 19
-; SI-NEXT: v_mov_b32_e32 v54, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 20
; SI-NEXT: v_readlane_b32 s47, v62, 21
-; SI-NEXT: v_mov_b32_e32 v53, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 22
; SI-NEXT: v_readlane_b32 s47, v62, 23
-; SI-NEXT: v_mov_b32_e32 v36, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 24
; SI-NEXT: v_readlane_b32 s47, v62, 25
-; SI-NEXT: v_mov_b32_e32 v8, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 26
; SI-NEXT: v_readlane_b32 s47, v62, 27
-; SI-NEXT: v_mov_b32_e32 v14, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 28
; SI-NEXT: v_readlane_b32 s47, v62, 29
-; SI-NEXT: v_mov_b32_e32 v27, s46
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_mov_b32_e32 v2, s46
; SI-NEXT: v_readlane_b32 s46, v62, 30
; SI-NEXT: v_readlane_b32 s47, v62, 31
-; SI-NEXT: v_mov_b32_e32 v9, s46
-; SI-NEXT: v_readlane_b32 s46, v62, 32
-; SI-NEXT: v_readlane_b32 s47, v62, 33
-; SI-NEXT: v_mov_b32_e32 v1, s6
-; SI-NEXT: v_mov_b32_e32 v25, s46
-; SI-NEXT: v_readlane_b32 s46, v62, 47
-; SI-NEXT: v_readlane_b32 s47, v62, 48
-; SI-NEXT: v_readlane_b32 s6, v61, 17
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v2, s96
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v2, s86
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v2, s84
+; SI-NEXT: v_mov_b32_e32 v2, s46
+; SI-NEXT: v_readlane_b32 s46, v62, 32
+; SI-NEXT: v_readlane_b32 s47, v62, 33
+; SI-NEXT: v_readlane_b32 s47, v62, 48
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v2, s82
+; SI-NEXT: v_mov_b32_e32 v2, s48
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_mov_b32_e32 v2, s52
+; SI-NEXT: v_mov_b32_e32 v2, s46
+; SI-NEXT: v_readlane_b32 s46, v62, 47
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: .LBB73_5: ; %end
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v7
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v24
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v28
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v29
; SI-NEXT: s_and_b32 s4, s17, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 8
; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v22
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v46
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, vcc_lo, 0xff
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v45
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s8, s8, 24
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s37, 8
-; SI-NEXT: s_lshl_b32 s8, s35, 24
-; SI-NEXT: v_readlane_b32 s99, v63, 33
-; SI-NEXT: v_readlane_b32 s98, v63, 32
-; SI-NEXT: v_readlane_b32 s97, v63, 31
-; SI-NEXT: v_readlane_b32 s96, v63, 30
-; SI-NEXT: v_readlane_b32 s87, v63, 29
-; SI-NEXT: v_readlane_b32 s86, v63, 28
-; SI-NEXT: v_readlane_b32 s85, v63, 27
-; SI-NEXT: v_readlane_b32 s84, v63, 26
-; SI-NEXT: v_readlane_b32 s83, v63, 25
-; SI-NEXT: v_readlane_b32 s82, v63, 24
-; SI-NEXT: v_readlane_b32 s81, v63, 23
-; SI-NEXT: v_readlane_b32 s80, v63, 22
-; SI-NEXT: v_readlane_b32 s71, v63, 21
-; SI-NEXT: v_readlane_b32 s70, v63, 20
-; SI-NEXT: v_readlane_b32 s69, v63, 19
-; SI-NEXT: v_readlane_b32 s68, v63, 18
-; SI-NEXT: v_readlane_b32 s67, v63, 17
-; SI-NEXT: v_readlane_b32 s66, v63, 16
-; SI-NEXT: v_readlane_b32 s65, v63, 15
-; SI-NEXT: v_readlane_b32 s64, v63, 14
-; SI-NEXT: v_readlane_b32 s55, v63, 13
-; SI-NEXT: v_readlane_b32 s54, v63, 12
-; SI-NEXT: v_readlane_b32 s53, v63, 11
-; SI-NEXT: v_readlane_b32 s52, v63, 10
-; SI-NEXT: v_readlane_b32 s51, v63, 9
-; SI-NEXT: v_readlane_b32 s50, v63, 8
-; SI-NEXT: v_readlane_b32 s49, v63, 7
-; SI-NEXT: v_readlane_b32 s48, v63, 6
-; SI-NEXT: v_readlane_b32 s39, v63, 5
-; SI-NEXT: v_readlane_b32 s38, v63, 4
-; SI-NEXT: v_readlane_b32 s37, v63, 3
-; SI-NEXT: v_readlane_b32 s35, v63, 1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v19
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v20
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v44
; SI-NEXT: s_and_b32 s4, s19, 0xff
+; SI-NEXT: s_lshl_b32 s6, s37, 8
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v41
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s36, 0xff
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v40
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
+; SI-NEXT: s_lshl_b32 s8, s35, 24
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s34, 8
-; SI-NEXT: s_lshl_b32 s8, s30, 24
-; SI-NEXT: v_readlane_b32 s36, v63, 2
-; SI-NEXT: v_readlane_b32 s34, v63, 0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 8, v0
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v56
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v58
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v59
; SI-NEXT: s_and_b32 s4, s21, 0xff
+; SI-NEXT: s_lshl_b32 s6, s34, 8
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v39
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s31, 0xff
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v38
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
+; SI-NEXT: s_lshl_b32 s8, s30, 24
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s95, 8
-; SI-NEXT: s_lshl_b32 s8, s93, 24
-; SI-NEXT: v_readlane_b32 s30, v63, 34
-; SI-NEXT: v_readlane_b32 s31, v63, 35
-; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 16, v0
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v42
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v43
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v52
; SI-NEXT: s_and_b32 s4, s23, 0xff
+; SI-NEXT: s_lshl_b32 s6, s95, 8
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v51
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s94, 0xff
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v50
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
+; SI-NEXT: s_lshl_b32 s8, s93, 24
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s92, 8
-; SI-NEXT: s_lshl_b32 s8, s90, 24
-; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 24, v0
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v51
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v54
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v49
; SI-NEXT: s_and_b32 s4, s25, 0xff
+; SI-NEXT: s_lshl_b32 s6, s92, 8
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v37
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s91, 0xff
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v36
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
+; SI-NEXT: s_lshl_b32 s8, s90, 24
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s89, 8
-; SI-NEXT: s_lshl_b32 s8, s79, 24
-; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 32, v0
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v47
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v48
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v32
; SI-NEXT: s_and_b32 s4, s27, 0xff
+; SI-NEXT: s_lshl_b32 s6, s89, 8
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v35
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s88, 0xff
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v34
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
+; SI-NEXT: s_lshl_b32 s8, s79, 24
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s78, 8
-; SI-NEXT: s_lshl_b32 s8, s76, 24
-; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 40, v0
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v28
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v31
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v26
; SI-NEXT: s_and_b32 s4, s29, 0xff
+; SI-NEXT: s_lshl_b32 s6, s78, 8
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v23
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s77, 0xff
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v22
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
+; SI-NEXT: s_lshl_b32 s8, s76, 24
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s75, 8
-; SI-NEXT: s_lshl_b32 s8, s73, 24
-; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 48, v0
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v21
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v25
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v18
; SI-NEXT: s_and_b32 s4, s45, 0xff
+; SI-NEXT: s_lshl_b32 s6, s75, 8
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v15
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s74, 0xff
-; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_and_b32 s4, s4, 0xffff
-; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s72, 8
-; SI-NEXT: s_lshl_b32 s8, s62, 24
-; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v17
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v14
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: s_lshl_b32 s6, s6, 16
+; SI-NEXT: s_lshl_b32 s8, s73, 24
; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: s_or_b32 s6, s8, s6
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 56, v0
+; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v40
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v17
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v18
-; SI-NEXT: s_and_b32 s4, s43, 0xff
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v56
; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v16
+; SI-NEXT: s_and_b32 s4, s43, 0xff
+; SI-NEXT: s_lshl_b32 s6, s72, 8
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s63, 0xff
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v13
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
+; SI-NEXT: s_lshl_b32 s8, s62, 24
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
+; SI-NEXT: s_or_b32 s4, s4, s6
+; SI-NEXT: s_lshl_b32 s6, s61, 8
+; SI-NEXT: s_lshl_b32 s8, s59, 24
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_readlane_b32 s30, v63, 34
+; SI-NEXT: v_readlane_b32 s31, v63, 35
+; SI-NEXT: v_readlane_b32 s99, v63, 33
+; SI-NEXT: v_readlane_b32 s98, v63, 32
+; SI-NEXT: v_readlane_b32 s97, v63, 31
+; SI-NEXT: v_readlane_b32 s96, v63, 30
+; SI-NEXT: v_readlane_b32 s87, v63, 29
+; SI-NEXT: v_readlane_b32 s86, v63, 28
+; SI-NEXT: v_readlane_b32 s85, v63, 27
+; SI-NEXT: v_readlane_b32 s84, v63, 26
+; SI-NEXT: v_readlane_b32 s83, v63, 25
+; SI-NEXT: v_readlane_b32 s82, v63, 24
+; SI-NEXT: v_readlane_b32 s81, v63, 23
+; SI-NEXT: v_readlane_b32 s80, v63, 22
+; SI-NEXT: v_readlane_b32 s71, v63, 21
+; SI-NEXT: v_readlane_b32 s70, v63, 20
+; SI-NEXT: v_readlane_b32 s69, v63, 19
+; SI-NEXT: v_readlane_b32 s68, v63, 18
+; SI-NEXT: v_readlane_b32 s67, v63, 17
+; SI-NEXT: v_readlane_b32 s66, v63, 16
+; SI-NEXT: v_readlane_b32 s65, v63, 15
+; SI-NEXT: v_readlane_b32 s64, v63, 14
+; SI-NEXT: v_readlane_b32 s55, v63, 13
+; SI-NEXT: v_readlane_b32 s54, v63, 12
+; SI-NEXT: v_readlane_b32 s53, v63, 11
+; SI-NEXT: v_readlane_b32 s52, v63, 10
+; SI-NEXT: v_readlane_b32 s51, v63, 9
+; SI-NEXT: v_readlane_b32 s50, v63, 8
+; SI-NEXT: v_readlane_b32 s49, v63, 7
+; SI-NEXT: v_readlane_b32 s48, v63, 6
+; SI-NEXT: v_readlane_b32 s39, v63, 5
+; SI-NEXT: v_readlane_b32 s38, v63, 4
+; SI-NEXT: v_readlane_b32 s37, v63, 3
+; SI-NEXT: v_readlane_b32 s36, v63, 2
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v14
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 64, v0
-; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v46
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v15
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v13
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s4, s41, 0xff
-; SI-NEXT: s_lshl_b32 s6, s61, 8
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s60, 0xff
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v5
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s8, s59, 24
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_lshl_b32 s6, s58, 8
; SI-NEXT: s_lshl_b32 s8, s56, 24
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v36
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v4, 0xff, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v12
; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x48, v0
@@ -110847,148 +110811,199 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v37
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v11
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s4, s15, 0xff
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v31
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s57, 0xff
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v30
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
+; SI-NEXT: s_or_b32 s4, s4, s6
+; SI-NEXT: s_lshl_b32 s6, s47, 8
+; SI-NEXT: s_lshl_b32 s8, s44, 24
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v10
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x50, v0
-; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v35
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v59
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v9
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s4, s13, 0xff
-; SI-NEXT: s_lshl_b32 s6, s47, 8
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v58
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s46, 0xff
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v45
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s8, s44, 24
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
+; SI-NEXT: s_or_b32 s4, s4, s6
+; SI-NEXT: s_lshl_b32 s6, s42, 8
+; SI-NEXT: s_lshl_b32 s8, s28, 24
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v8
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x58, v0
-; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v55
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v44
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v7
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s4, s11, 0xff
-; SI-NEXT: s_lshl_b32 s6, s42, 8
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v49
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s40, 0xff
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v11
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s8, s28, 24
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
+; SI-NEXT: s_or_b32 s4, s4, s6
+; SI-NEXT: s_lshl_b32 s6, s26, 8
+; SI-NEXT: s_lshl_b32 s8, s22, 24
+; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6
+; SI-NEXT: v_or_b32_e32 v4, v6, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x60, v0
-; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v5
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v54
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s4, s9, 0xff
-; SI-NEXT: s_lshl_b32 s6, s26, 8
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v53
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s24, 0xff
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s8, s22, 24
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s8, s6
+; SI-NEXT: s_or_b32 s4, s4, s6
+; SI-NEXT: s_lshl_b32 s6, s20, 8
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x68, v0
-; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v8
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s4, s7, 0xff
-; SI-NEXT: s_lshl_b32 s6, s20, 8
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v14
; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: s_and_b32 s6, s18, 0xff
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v27
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s7, s16, 24
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: s_or_b32 s4, s4, s6
+; SI-NEXT: s_lshl_b32 s6, s10, 24
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0
-; SI-NEXT: s_or_b32 s4, s4, s6
; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0
; SI-NEXT: v_mov_b32_e32 v3, s4
; SI-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v9
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s4, s5, 0xff
; SI-NEXT: s_lshl_b32 s5, s14, 8
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v34
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: s_and_b32 s5, s12, 0xff
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v25
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s6, s10, 24
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0
-; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: s_waitcnt expcnt(0)
@@ -111008,9 +111023,9 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -145185,1445 +145200,1424 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_writelane_b32 v40, s34, 0
-; SI-NEXT: v_writelane_b32 v40, s35, 1
-; SI-NEXT: v_writelane_b32 v40, s36, 2
-; SI-NEXT: v_writelane_b32 v40, s37, 3
-; SI-NEXT: v_writelane_b32 v40, s38, 4
-; SI-NEXT: v_writelane_b32 v40, s39, 5
-; SI-NEXT: v_writelane_b32 v40, s48, 6
-; SI-NEXT: v_writelane_b32 v40, s49, 7
-; SI-NEXT: v_writelane_b32 v40, s50, 8
-; SI-NEXT: v_writelane_b32 v40, s51, 9
-; SI-NEXT: v_writelane_b32 v40, s52, 10
-; SI-NEXT: v_writelane_b32 v40, s53, 11
-; SI-NEXT: v_writelane_b32 v40, s54, 12
-; SI-NEXT: v_writelane_b32 v40, s55, 13
-; SI-NEXT: v_writelane_b32 v40, s64, 14
-; SI-NEXT: v_writelane_b32 v40, s65, 15
-; SI-NEXT: v_writelane_b32 v40, s66, 16
-; SI-NEXT: v_writelane_b32 v40, s67, 17
-; SI-NEXT: v_writelane_b32 v40, s68, 18
-; SI-NEXT: v_writelane_b32 v40, s69, 19
-; SI-NEXT: v_writelane_b32 v40, s70, 20
-; SI-NEXT: v_writelane_b32 v40, s71, 21
-; SI-NEXT: v_writelane_b32 v40, s80, 22
-; SI-NEXT: v_writelane_b32 v40, s81, 23
-; SI-NEXT: v_writelane_b32 v40, s82, 24
-; SI-NEXT: v_writelane_b32 v40, s83, 25
-; SI-NEXT: v_writelane_b32 v40, s84, 26
-; SI-NEXT: v_writelane_b32 v40, s85, 27
-; SI-NEXT: v_writelane_b32 v40, s86, 28
-; SI-NEXT: v_writelane_b32 v40, s87, 29
-; SI-NEXT: v_writelane_b32 v40, s96, 30
-; SI-NEXT: v_writelane_b32 v40, s97, 31
-; SI-NEXT: v_writelane_b32 v40, s98, 32
-; SI-NEXT: v_writelane_b32 v40, s99, 33
-; SI-NEXT: v_writelane_b32 v40, s30, 34
-; SI-NEXT: v_writelane_b32 v40, s31, 35
-; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_writelane_b32 v45, s34, 0
+; SI-NEXT: v_writelane_b32 v45, s35, 1
+; SI-NEXT: v_writelane_b32 v45, s36, 2
+; SI-NEXT: v_writelane_b32 v45, s37, 3
+; SI-NEXT: v_writelane_b32 v45, s38, 4
+; SI-NEXT: v_writelane_b32 v45, s39, 5
+; SI-NEXT: v_writelane_b32 v45, s48, 6
+; SI-NEXT: v_writelane_b32 v45, s49, 7
+; SI-NEXT: v_writelane_b32 v45, s50, 8
+; SI-NEXT: v_writelane_b32 v45, s51, 9
+; SI-NEXT: v_writelane_b32 v45, s52, 10
+; SI-NEXT: v_writelane_b32 v45, s53, 11
+; SI-NEXT: v_writelane_b32 v45, s54, 12
+; SI-NEXT: v_writelane_b32 v45, s55, 13
+; SI-NEXT: v_writelane_b32 v45, s64, 14
+; SI-NEXT: v_writelane_b32 v45, s65, 15
+; SI-NEXT: v_writelane_b32 v45, s66, 16
+; SI-NEXT: v_writelane_b32 v45, s67, 17
+; SI-NEXT: v_writelane_b32 v45, s68, 18
+; SI-NEXT: v_writelane_b32 v45, s69, 19
+; SI-NEXT: v_writelane_b32 v45, s70, 20
+; SI-NEXT: v_writelane_b32 v45, s71, 21
+; SI-NEXT: v_writelane_b32 v45, s80, 22
+; SI-NEXT: v_writelane_b32 v45, s81, 23
+; SI-NEXT: v_writelane_b32 v45, s82, 24
+; SI-NEXT: v_writelane_b32 v45, s83, 25
+; SI-NEXT: v_writelane_b32 v45, s84, 26
+; SI-NEXT: v_writelane_b32 v45, s85, 27
+; SI-NEXT: v_writelane_b32 v45, s86, 28
+; SI-NEXT: v_writelane_b32 v45, s87, 29
+; SI-NEXT: v_writelane_b32 v45, s96, 30
+; SI-NEXT: v_writelane_b32 v45, s97, 31
+; SI-NEXT: v_writelane_b32 v45, s98, 32
+; SI-NEXT: v_writelane_b32 v45, s99, 33
+; SI-NEXT: v_writelane_b32 v45, s30, 34
+; SI-NEXT: v_writelane_b32 v45, s31, 35
+; SI-NEXT: ; implicit-def: $vgpr47 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s4, v30
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v43, s29, 0
-; SI-NEXT: v_writelane_b32 v43, s28, 1
-; SI-NEXT: v_writelane_b32 v43, s27, 2
-; SI-NEXT: v_writelane_b32 v43, s26, 3
-; SI-NEXT: v_writelane_b32 v43, s25, 4
-; SI-NEXT: v_writelane_b32 v43, s24, 5
-; SI-NEXT: v_writelane_b32 v43, s23, 6
-; SI-NEXT: v_writelane_b32 v43, s22, 7
-; SI-NEXT: v_writelane_b32 v43, s21, 8
-; SI-NEXT: v_writelane_b32 v43, s4, 9
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_writelane_b32 v47, s29, 0
+; SI-NEXT: v_writelane_b32 v47, s28, 1
+; SI-NEXT: v_writelane_b32 v47, s27, 2
+; SI-NEXT: v_writelane_b32 v47, s26, 3
+; SI-NEXT: v_writelane_b32 v47, s25, 4
+; SI-NEXT: v_writelane_b32 v47, s24, 5
+; SI-NEXT: v_writelane_b32 v47, s23, 6
+; SI-NEXT: v_writelane_b32 v47, s22, 7
+; SI-NEXT: v_writelane_b32 v47, s21, 8
+; SI-NEXT: v_writelane_b32 v47, s20, 9
+; SI-NEXT: v_writelane_b32 v47, s19, 10
+; SI-NEXT: v_writelane_b32 v47, s18, 11
+; SI-NEXT: v_writelane_b32 v47, s17, 12
+; SI-NEXT: v_writelane_b32 v47, s4, 13
; SI-NEXT: v_readfirstlane_b32 s4, v29
-; SI-NEXT: v_writelane_b32 v43, s4, 10
+; SI-NEXT: v_writelane_b32 v47, s4, 14
; SI-NEXT: v_readfirstlane_b32 s4, v28
-; SI-NEXT: v_readfirstlane_b32 s77, v18
-; SI-NEXT: v_readfirstlane_b32 s51, v17
-; SI-NEXT: v_readfirstlane_b32 s73, v16
-; SI-NEXT: v_readfirstlane_b32 s42, v15
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:232
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220
-; SI-NEXT: v_writelane_b32 v43, s4, 11
+; SI-NEXT: v_writelane_b32 v47, s4, 15
; SI-NEXT: v_readfirstlane_b32 s4, v27
-; SI-NEXT: v_writelane_b32 v43, s4, 12
+; SI-NEXT: v_writelane_b32 v47, s4, 16
; SI-NEXT: v_readfirstlane_b32 s4, v26
-; SI-NEXT: v_writelane_b32 v43, s4, 13
+; SI-NEXT: v_writelane_b32 v47, s4, 17
; SI-NEXT: v_readfirstlane_b32 s4, v25
-; SI-NEXT: v_writelane_b32 v43, s4, 14
+; SI-NEXT: v_writelane_b32 v47, s4, 18
; SI-NEXT: v_readfirstlane_b32 s4, v24
-; SI-NEXT: v_readfirstlane_b32 s45, v14
-; SI-NEXT: v_readfirstlane_b32 s64, v13
-; SI-NEXT: v_readfirstlane_b32 s38, v12
-; SI-NEXT: v_readfirstlane_b32 s50, v11
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:204
-; SI-NEXT: v_writelane_b32 v43, s4, 15
+; SI-NEXT: v_writelane_b32 v47, s4, 19
; SI-NEXT: v_readfirstlane_b32 s4, v23
-; SI-NEXT: v_writelane_b32 v43, s4, 16
+; SI-NEXT: v_writelane_b32 v47, s4, 20
; SI-NEXT: v_readfirstlane_b32 s4, v22
-; SI-NEXT: v_writelane_b32 v43, s4, 17
+; SI-NEXT: v_writelane_b32 v47, s4, 21
; SI-NEXT: v_readfirstlane_b32 s4, v21
-; SI-NEXT: v_writelane_b32 v43, s4, 18
+; SI-NEXT: v_writelane_b32 v47, s4, 22
; SI-NEXT: v_readfirstlane_b32 s4, v20
-; SI-NEXT: v_readfirstlane_b32 s54, v10
-; SI-NEXT: v_readfirstlane_b32 s55, v9
-; SI-NEXT: v_readfirstlane_b32 s88, v8
-; SI-NEXT: v_readfirstlane_b32 s49, v7
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:196
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:188
-; SI-NEXT: v_writelane_b32 v43, s4, 19
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:324
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:316
+; SI-NEXT: v_writelane_b32 v47, s4, 23
; SI-NEXT: v_readfirstlane_b32 s4, v19
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:324
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:316
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:304
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:300
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:296
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:292
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:284
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:280
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:276
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:268
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:264
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:260
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:252
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:248
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:244
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:332
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:236
-; SI-NEXT: v_readfirstlane_b32 s52, v2
-; SI-NEXT: v_readfirstlane_b32 s74, v1
-; SI-NEXT: v_readfirstlane_b32 s75, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176
-; SI-NEXT: v_writelane_b32 v43, s4, 20
-; SI-NEXT: s_mov_b32 s10, s16
-; SI-NEXT: v_readfirstlane_b32 s53, v6
-; SI-NEXT: v_readfirstlane_b32 s76, v5
-; SI-NEXT: v_readfirstlane_b32 s60, v4
-; SI-NEXT: v_readfirstlane_b32 s48, v3
-; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s37, v18
-; SI-NEXT: v_readfirstlane_b32 s31, v17
-; SI-NEXT: v_readfirstlane_b32 s62, v16
+; SI-NEXT: v_writelane_b32 v47, s4, 24
+; SI-NEXT: v_readfirstlane_b32 s4, v18
+; SI-NEXT: v_writelane_b32 v47, s4, 25
+; SI-NEXT: v_readfirstlane_b32 s4, v17
+; SI-NEXT: v_writelane_b32 v47, s4, 26
+; SI-NEXT: v_readfirstlane_b32 s4, v16
+; SI-NEXT: v_writelane_b32 v47, s4, 27
; SI-NEXT: v_readfirstlane_b32 s4, v15
-; SI-NEXT: v_writelane_b32 v43, s4, 21
-; SI-NEXT: v_readfirstlane_b32 s7, v19
-; SI-NEXT: v_readfirstlane_b32 s43, v20
-; SI-NEXT: v_readfirstlane_b32 s56, v21
-; SI-NEXT: v_readfirstlane_b32 s57, v22
-; SI-NEXT: v_readfirstlane_b32 s26, v23
+; SI-NEXT: v_writelane_b32 v47, s4, 28
; SI-NEXT: v_readfirstlane_b32 s4, v14
-; SI-NEXT: v_writelane_b32 v43, s4, 22
-; SI-NEXT: v_readfirstlane_b32 s4, v13
-; SI-NEXT: v_writelane_b32 v43, s4, 23
-; SI-NEXT: v_readfirstlane_b32 s4, v12
-; SI-NEXT: v_writelane_b32 v43, s4, 24
-; SI-NEXT: v_readfirstlane_b32 s4, v11
-; SI-NEXT: v_writelane_b32 v43, s4, 25
-; SI-NEXT: v_readfirstlane_b32 s22, v31
-; SI-NEXT: v_readfirstlane_b32 s34, v32
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_readfirstlane_b32 s39, v33
+; SI-NEXT: s_mov_b32 s7, s16
+; SI-NEXT: v_writelane_b32 v47, s4, 29
+; SI-NEXT: v_readfirstlane_b32 s18, v13
+; SI-NEXT: v_readfirstlane_b32 s16, v12
+; SI-NEXT: v_readfirstlane_b32 s70, v0
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:244
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240
+; SI-NEXT: v_readfirstlane_b32 s23, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:288
+; SI-NEXT: v_readfirstlane_b32 s19, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:284
+; SI-NEXT: v_readfirstlane_b32 s25, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:280
+; SI-NEXT: v_readfirstlane_b32 s11, v9
+; SI-NEXT: v_readfirstlane_b32 s48, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:276
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:264
+; SI-NEXT: v_readfirstlane_b32 s50, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272
+; SI-NEXT: v_readfirstlane_b32 s22, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:300
+; SI-NEXT: v_readfirstlane_b32 s14, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:296
+; SI-NEXT: v_readfirstlane_b32 s24, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:292
+; SI-NEXT: ; implicit-def: $vgpr46 : SGPR spill to VGPR lane
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 vcc_lo, v1
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:256
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248
+; SI-NEXT: v_readfirstlane_b32 vcc_hi, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260
+; SI-NEXT: v_readfirstlane_b32 s75, v22
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:220
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:216
+; SI-NEXT: v_readfirstlane_b32 s29, v24
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:208
+; SI-NEXT: v_readfirstlane_b32 s4, v21
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:228
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:224
+; SI-NEXT: v_readfirstlane_b32 s92, v19
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:236
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:232
+; SI-NEXT: v_writelane_b32 v47, s4, 30
+; SI-NEXT: v_readfirstlane_b32 s53, v14
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:64
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_readfirstlane_b32 s28, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:56
+; SI-NEXT: v_readfirstlane_b32 s61, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:156
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:152
+; SI-NEXT: v_readfirstlane_b32 s41, v7
+; SI-NEXT: v_readfirstlane_b32 s88, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:136
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:144
+; SI-NEXT: v_readfirstlane_b32 s20, v5
+; SI-NEXT: v_readfirstlane_b32 s95, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:104
+; SI-NEXT: v_readfirstlane_b32 s31, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:120
+; SI-NEXT: v_readfirstlane_b32 s76, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:112
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:128
+; SI-NEXT: v_readfirstlane_b32 s34, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:188
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:184
+; SI-NEXT: v_readfirstlane_b32 s40, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:176
+; SI-NEXT: v_readfirstlane_b32 s59, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:168
+; SI-NEXT: v_readfirstlane_b32 s79, v18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:200
+; SI-NEXT: v_readfirstlane_b32 s93, v17
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:196
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192
+; SI-NEXT: v_readfirstlane_b32 s89, v10
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:160
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_readfirstlane_b32 s65, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:88
+; SI-NEXT: v_readfirstlane_b32 s27, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:72
+; SI-NEXT: v_readfirstlane_b32 s68, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:80
+; SI-NEXT: v_readfirstlane_b32 s47, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:96
+; SI-NEXT: v_readfirstlane_b32 s54, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:8
+; SI-NEXT: v_readfirstlane_b32 s67, v29
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32
+; SI-NEXT: v_readfirstlane_b32 s37, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24
+; SI-NEXT: v_readfirstlane_b32 s91, v25
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16
+; SI-NEXT: v_readfirstlane_b32 s17, v19
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:40
+; SI-NEXT: v_readfirstlane_b32 s64, v23
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:32
+; SI-NEXT: v_readfirstlane_b32 s94, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
+; SI-NEXT: v_readfirstlane_b32 s13, v14
+; SI-NEXT: v_writelane_b32 v46, s13, 0
+; SI-NEXT: v_readfirstlane_b32 s15, v52
+; SI-NEXT: v_readfirstlane_b32 s12, v0
+; SI-NEXT: v_readfirstlane_b32 s72, v33
+; SI-NEXT: v_readfirstlane_b32 s99, v53
+; SI-NEXT: v_readfirstlane_b32 s4, v35
+; SI-NEXT: v_writelane_b32 v47, s4, 31
+; SI-NEXT: v_readfirstlane_b32 s39, v24
+; SI-NEXT: v_readfirstlane_b32 s38, v8
+; SI-NEXT: v_readfirstlane_b32 s58, v39
+; SI-NEXT: v_readfirstlane_b32 s4, v4
+; SI-NEXT: v_writelane_b32 v47, s4, 32
+; SI-NEXT: v_readfirstlane_b32 s4, v9
+; SI-NEXT: v_writelane_b32 v47, s4, 33
+; SI-NEXT: v_writelane_b32 v47, s7, 34
+; SI-NEXT: v_readfirstlane_b32 s60, v3
+; SI-NEXT: v_writelane_b32 v47, s18, 35
+; SI-NEXT: v_readfirstlane_b32 s63, v37
+; SI-NEXT: v_writelane_b32 v47, s16, 36
+; SI-NEXT: v_readfirstlane_b32 s73, v38
+; SI-NEXT: v_writelane_b32 v47, s11, 37
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_readfirstlane_b32 s6, v5
+; SI-NEXT: v_writelane_b32 v47, s23, 38
+; SI-NEXT: v_readfirstlane_b32 s78, v36
+; SI-NEXT: v_writelane_b32 v47, s48, 39
+; SI-NEXT: v_writelane_b32 v47, s50, 40
+; SI-NEXT: v_readfirstlane_b32 s30, v15
+; SI-NEXT: v_writelane_b32 v47, s14, 41
+; SI-NEXT: v_readfirstlane_b32 s26, v28
+; SI-NEXT: v_writelane_b32 v47, s19, 42
+; SI-NEXT: v_writelane_b32 v47, s24, 43
+; SI-NEXT: v_writelane_b32 v47, s25, 44
+; SI-NEXT: v_writelane_b32 v47, s22, 45
+; SI-NEXT: v_readfirstlane_b32 s49, v30
+; SI-NEXT: v_writelane_b32 v47, vcc_lo, 46
+; SI-NEXT: v_writelane_b32 v47, vcc_hi, 47
+; SI-NEXT: v_writelane_b32 v47, s70, 48
+; SI-NEXT: v_readfirstlane_b32 s21, v11
+; SI-NEXT: v_readfirstlane_b32 s51, v17
+; SI-NEXT: v_readfirstlane_b32 s66, v26
+; SI-NEXT: v_readfirstlane_b32 s52, v27
+; SI-NEXT: v_readfirstlane_b32 s69, v16
+; SI-NEXT: v_readfirstlane_b32 s55, v18
+; SI-NEXT: v_readfirstlane_b32 s77, v31
+; SI-NEXT: v_readfirstlane_b32 s74, v10
+; SI-NEXT: v_readfirstlane_b32 s46, v32
+; SI-NEXT: v_readfirstlane_b32 s36, v7
+; SI-NEXT: v_readfirstlane_b32 s90, v34
+; SI-NEXT: v_readfirstlane_b32 s35, v6
+; SI-NEXT: v_readfirstlane_b32 s56, v12
+; SI-NEXT: v_readfirstlane_b32 s44, v49
+; SI-NEXT: v_readfirstlane_b32 s57, v13
+; SI-NEXT: v_readfirstlane_b32 s9, v51
+; SI-NEXT: v_writelane_b32 v46, s9, 1
+; SI-NEXT: v_writelane_b32 v46, s15, 2
+; SI-NEXT: v_readfirstlane_b32 s42, v1
+; SI-NEXT: v_writelane_b32 v46, s12, 3
+; SI-NEXT: v_writelane_b32 v46, s42, 4
+; SI-NEXT: v_readfirstlane_b32 s43, v50
+; SI-NEXT: v_writelane_b32 v46, s44, 5
+; SI-NEXT: v_writelane_b32 v46, s43, 6
+; SI-NEXT: v_readfirstlane_b32 s45, v2
+; SI-NEXT: v_writelane_b32 v46, s57, 7
+; SI-NEXT: v_writelane_b32 v46, s45, 8
+; SI-NEXT: v_readfirstlane_b32 s62, v48
+; SI-NEXT: v_writelane_b32 v46, s58, 9
+; SI-NEXT: v_writelane_b32 v46, s62, 10
+; SI-NEXT: v_writelane_b32 v46, s56, 11
+; SI-NEXT: v_writelane_b32 v46, s60, 12
+; SI-NEXT: v_writelane_b32 v46, s63, 13
+; SI-NEXT: v_writelane_b32 v46, s73, 14
+; SI-NEXT: v_writelane_b32 v46, s6, 15
+; SI-NEXT: v_writelane_b32 v46, s78, 16
+; SI-NEXT: v_writelane_b32 v46, s72, 17
+; SI-NEXT: v_writelane_b32 v46, s30, 18
+; SI-NEXT: v_writelane_b32 v46, s26, 19
+; SI-NEXT: v_writelane_b32 v46, s27, 20
+; SI-NEXT: v_writelane_b32 v46, s53, 21
+; SI-NEXT: v_writelane_b32 v46, s65, 22
+; SI-NEXT: v_writelane_b32 v46, s49, 23
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s93, v35
+; SI-NEXT: v_readfirstlane_b32 s71, v29
+; SI-NEXT: v_writelane_b32 v46, s17, 24
+; SI-NEXT: v_readfirstlane_b32 s80, v43
+; SI-NEXT: v_writelane_b32 v47, s71, 49
+; SI-NEXT: v_writelane_b32 v46, s54, 25
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s92, v36
-; SI-NEXT: v_readfirstlane_b32 s4, v10
-; SI-NEXT: v_writelane_b32 v43, s4, 26
-; SI-NEXT: v_readfirstlane_b32 s4, v9
-; SI-NEXT: v_writelane_b32 v43, s4, 27
-; SI-NEXT: v_readfirstlane_b32 s4, v8
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_readfirstlane_b32 s30, v37
-; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_readfirstlane_b32 s90, v38
+; SI-NEXT: v_readfirstlane_b32 s81, v44
+; SI-NEXT: v_writelane_b32 v47, s80, 50
+; SI-NEXT: v_writelane_b32 v46, s21, 26
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_readfirstlane_b32 s58, v39
+; SI-NEXT: v_readfirstlane_b32 s82, v25
+; SI-NEXT: v_writelane_b32 v47, s81, 51
+; SI-NEXT: v_writelane_b32 v46, s64, 27
+; SI-NEXT: v_readfirstlane_b32 s83, v41
+; SI-NEXT: v_writelane_b32 v47, s82, 52
+; SI-NEXT: v_writelane_b32 v46, s67, 28
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_readfirstlane_b32 s47, v48
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v49
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_readfirstlane_b32 s61, v50
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
-; SI-NEXT: v_writelane_b32 v43, s4, 28
-; SI-NEXT: v_readfirstlane_b32 s4, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:16
-; SI-NEXT: v_readfirstlane_b32 s72, v34
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80
-; SI-NEXT: v_readfirstlane_b32 s16, v24
-; SI-NEXT: v_readfirstlane_b32 s59, v25
-; SI-NEXT: v_readfirstlane_b32 s6, v26
-; SI-NEXT: v_readfirstlane_b32 s79, v27
-; SI-NEXT: v_readfirstlane_b32 s89, v28
-; SI-NEXT: v_readfirstlane_b32 s35, v29
-; SI-NEXT: v_readfirstlane_b32 s36, v30
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:168
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:156
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:148
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:136
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:124
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:116
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:112
-; SI-NEXT: v_writelane_b32 v43, s4, 29
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s4, v1
-; SI-NEXT: v_writelane_b32 v43, s4, 30
-; SI-NEXT: v_readfirstlane_b32 s4, v0
-; SI-NEXT: v_readfirstlane_b32 s94, v51
-; SI-NEXT: v_writelane_b32 v43, s4, 31
-; SI-NEXT: v_readfirstlane_b32 s4, v2
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: v_writelane_b32 v43, s4, 32
-; SI-NEXT: v_writelane_b32 v43, s18, 33
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_writelane_b32 v43, s19, 34
-; SI-NEXT: v_writelane_b32 v43, s17, 35
-; SI-NEXT: v_writelane_b32 v43, s10, 36
-; SI-NEXT: v_writelane_b32 v43, s20, 37
-; SI-NEXT: v_writelane_b32 v43, s74, 38
-; SI-NEXT: v_writelane_b32 v43, s75, 39
-; SI-NEXT: v_writelane_b32 v43, s76, 40
-; SI-NEXT: v_writelane_b32 v43, s60, 41
-; SI-NEXT: v_writelane_b32 v43, s55, 42
-; SI-NEXT: v_writelane_b32 v43, s88, 43
-; SI-NEXT: v_writelane_b32 v43, s64, 44
-; SI-NEXT: v_writelane_b32 v43, s38, 45
-; SI-NEXT: v_writelane_b32 v43, s51, 46
-; SI-NEXT: v_writelane_b32 v43, s73, 47
-; SI-NEXT: v_writelane_b32 v43, s48, 48
-; SI-NEXT: v_writelane_b32 v43, s49, 49
-; SI-NEXT: v_writelane_b32 v43, s50, 50
-; SI-NEXT: v_writelane_b32 v43, s42, 51
-; SI-NEXT: v_writelane_b32 v43, s52, 52
-; SI-NEXT: v_writelane_b32 v43, s53, 53
-; SI-NEXT: v_writelane_b32 v43, s54, 54
-; SI-NEXT: v_writelane_b32 v43, s45, 55
-; SI-NEXT: v_writelane_b32 v43, s77, 56
-; SI-NEXT: v_readfirstlane_b32 s24, v11
-; SI-NEXT: v_readfirstlane_b32 s87, v12
-; SI-NEXT: v_readfirstlane_b32 s86, v13
-; SI-NEXT: v_readfirstlane_b32 s85, v7
-; SI-NEXT: v_readfirstlane_b32 s71, v8
-; SI-NEXT: v_readfirstlane_b32 s70, v9
-; SI-NEXT: v_writelane_b32 v42, s70, 0
-; SI-NEXT: v_readfirstlane_b32 s80, v10
-; SI-NEXT: v_writelane_b32 v42, s71, 1
-; SI-NEXT: v_readfirstlane_b32 s81, v39
-; SI-NEXT: v_writelane_b32 v42, s80, 2
-; SI-NEXT: v_readfirstlane_b32 s82, v37
-; SI-NEXT: v_writelane_b32 v42, s81, 3
-; SI-NEXT: v_readfirstlane_b32 s83, v36
-; SI-NEXT: v_writelane_b32 v42, s82, 4
-; SI-NEXT: v_readfirstlane_b32 s84, v38
-; SI-NEXT: v_writelane_b32 v42, s83, 5
-; SI-NEXT: v_writelane_b32 v42, s84, 6
-; SI-NEXT: v_writelane_b32 v42, s85, 7
-; SI-NEXT: v_writelane_b32 v42, s86, 8
-; SI-NEXT: v_readfirstlane_b32 s96, v14
-; SI-NEXT: v_writelane_b32 v42, s87, 9
-; SI-NEXT: v_readfirstlane_b32 s97, v35
-; SI-NEXT: v_writelane_b32 v42, s96, 10
-; SI-NEXT: v_readfirstlane_b32 s98, v33
-; SI-NEXT: v_writelane_b32 v42, s97, 11
-; SI-NEXT: v_readfirstlane_b32 s99, v32
-; SI-NEXT: v_writelane_b32 v42, s98, 12
-; SI-NEXT: v_readfirstlane_b32 s9, v34
-; SI-NEXT: v_writelane_b32 v42, s99, 13
-; SI-NEXT: v_writelane_b32 v42, s9, 14
-; SI-NEXT: v_readfirstlane_b32 s27, v17
-; SI-NEXT: v_writelane_b32 v42, s24, 15
-; SI-NEXT: v_readfirstlane_b32 s11, v16
-; SI-NEXT: v_writelane_b32 v42, s27, 16
-; SI-NEXT: v_readfirstlane_b32 s28, v18
-; SI-NEXT: v_writelane_b32 v42, s11, 17
-; SI-NEXT: v_readfirstlane_b32 s13, v31
-; SI-NEXT: v_writelane_b32 v42, s28, 18
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_readfirstlane_b32 s8, v29
-; SI-NEXT: v_writelane_b32 v42, s13, 19
-; SI-NEXT: v_readfirstlane_b32 s44, v28
-; SI-NEXT: v_writelane_b32 v42, s8, 20
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_readfirstlane_b32 s12, v30
-; SI-NEXT: v_writelane_b32 v42, s44, 21
-; SI-NEXT: v_readfirstlane_b32 s41, v15
-; SI-NEXT: v_writelane_b32 v42, s12, 22
-; SI-NEXT: v_readfirstlane_b32 s63, v25
-; SI-NEXT: v_writelane_b32 v42, s41, 23
-; SI-NEXT: v_readfirstlane_b32 s14, v26
-; SI-NEXT: v_writelane_b32 v42, s63, 24
-; SI-NEXT: v_readfirstlane_b32 s91, v27
-; SI-NEXT: v_writelane_b32 v42, s14, 25
-; SI-NEXT: v_readfirstlane_b32 s15, v21
-; SI-NEXT: v_writelane_b32 v42, s91, 26
-; SI-NEXT: v_readfirstlane_b32 s40, v20
-; SI-NEXT: v_writelane_b32 v42, s15, 27
-; SI-NEXT: v_readfirstlane_b32 s21, v22
-; SI-NEXT: v_writelane_b32 v42, s40, 28
-; SI-NEXT: v_readfirstlane_b32 s29, v23
-; SI-NEXT: v_writelane_b32 v42, s21, 29
-; SI-NEXT: v_readfirstlane_b32 s5, v5
-; SI-NEXT: v_writelane_b32 v42, s29, 30
-; SI-NEXT: v_readfirstlane_b32 s95, v4
-; SI-NEXT: v_writelane_b32 v42, s5, 31
-; SI-NEXT: v_writelane_b32 v42, s95, 32
-; SI-NEXT: v_readfirstlane_b32 s25, v6
-; SI-NEXT: v_writelane_b32 v42, s62, 33
-; SI-NEXT: v_readfirstlane_b32 s78, v19
-; SI-NEXT: v_writelane_b32 v42, s25, 34
-; SI-NEXT: v_writelane_b32 v42, s78, 35
-; SI-NEXT: v_writelane_b32 v42, s34, 36
-; SI-NEXT: v_writelane_b32 v42, s39, 37
-; SI-NEXT: v_readfirstlane_b32 s23, v3
-; SI-NEXT: v_writelane_b32 v42, s72, 38
-; SI-NEXT: v_writelane_b32 v42, s23, 39
-; SI-NEXT: v_writelane_b32 v42, s89, 40
-; SI-NEXT: v_writelane_b32 v42, s79, 41
-; SI-NEXT: v_writelane_b32 v42, s35, 42
-; SI-NEXT: v_writelane_b32 v42, s36, 43
-; SI-NEXT: v_writelane_b32 v42, s16, 44
-; SI-NEXT: v_writelane_b32 v42, s26, 45
-; SI-NEXT: v_writelane_b32 v42, s59, 46
-; SI-NEXT: v_writelane_b32 v42, s6, 47
-; SI-NEXT: v_writelane_b32 v42, s43, 48
-; SI-NEXT: v_writelane_b32 v42, s7, 49
-; SI-NEXT: v_writelane_b32 v42, s56, 50
-; SI-NEXT: v_readfirstlane_b32 s46, v24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_readfirstlane_b32 vcc_lo, v2
-; SI-NEXT: v_writelane_b32 v42, s57, 51
-; SI-NEXT: v_readfirstlane_b32 vcc_hi, v1
-; SI-NEXT: v_writelane_b32 v43, vcc_lo, 57
-; SI-NEXT: v_writelane_b32 v42, s46, 52
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s65, v51
-; SI-NEXT: v_writelane_b32 v43, vcc_hi, 58
-; SI-NEXT: v_writelane_b32 v42, s31, 53
-; SI-NEXT: v_readfirstlane_b32 s66, v49
-; SI-NEXT: v_writelane_b32 v43, s65, 59
-; SI-NEXT: v_writelane_b32 v42, s37, 54
-; SI-NEXT: v_readfirstlane_b32 s67, v48
-; SI-NEXT: v_writelane_b32 v43, s66, 60
-; SI-NEXT: v_writelane_b32 v42, s47, 55
-; SI-NEXT: v_readfirstlane_b32 s68, v50
-; SI-NEXT: v_writelane_b32 v43, s67, 61
-; SI-NEXT: v_writelane_b32 v42, s30, 56
-; SI-NEXT: v_readfirstlane_b32 s69, v0
-; SI-NEXT: v_writelane_b32 v43, s68, 62
-; SI-NEXT: v_writelane_b32 v42, s61, 57
-; SI-NEXT: v_writelane_b32 v43, s69, 63
-; SI-NEXT: v_writelane_b32 v42, s94, 58
+; SI-NEXT: v_readfirstlane_b32 s84, v42
+; SI-NEXT: v_writelane_b32 v47, s83, 53
+; SI-NEXT: v_writelane_b32 v46, s51, 29
+; SI-NEXT: v_readfirstlane_b32 s85, v22
+; SI-NEXT: v_writelane_b32 v47, s84, 54
+; SI-NEXT: v_writelane_b32 v46, s66, 30
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_readfirstlane_b32 s86, v23
+; SI-NEXT: v_writelane_b32 v47, s85, 55
+; SI-NEXT: v_writelane_b32 v46, s68, 31
+; SI-NEXT: v_readfirstlane_b32 s87, v55
+; SI-NEXT: v_writelane_b32 v47, s86, 56
+; SI-NEXT: v_writelane_b32 v46, s28, 32
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_readfirstlane_b32 s96, v40
+; SI-NEXT: v_writelane_b32 v47, s87, 57
+; SI-NEXT: v_writelane_b32 v46, s52, 33
+; SI-NEXT: v_readfirstlane_b32 s97, v21
+; SI-NEXT: v_writelane_b32 v47, s96, 58
+; SI-NEXT: v_writelane_b32 v46, s37, 34
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_readfirstlane_b32 s98, v20
+; SI-NEXT: v_writelane_b32 v47, s97, 59
+; SI-NEXT: v_writelane_b32 v46, s69, 35
+; SI-NEXT: v_writelane_b32 v47, s98, 60
+; SI-NEXT: v_writelane_b32 v46, s94, 36
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_readfirstlane_b32 s10, v54
+; SI-NEXT: v_writelane_b32 v47, s99, 61
+; SI-NEXT: v_writelane_b32 v46, s91, 37
+; SI-NEXT: v_readfirstlane_b32 s8, v19
+; SI-NEXT: v_writelane_b32 v47, s10, 62
+; SI-NEXT: v_writelane_b32 v46, s39, 38
+; SI-NEXT: v_writelane_b32 v47, s8, 63
+; SI-NEXT: v_writelane_b32 v46, s55, 39
; SI-NEXT: s_cbranch_scc0 .LBB89_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: s_and_b32 s4, s10, 0xff
+; SI-NEXT: v_writelane_b32 v46, s38, 42
+; SI-NEXT: s_and_b32 s4, s7, 0xff
+; SI-NEXT: v_readlane_b32 s5, v47, 12
+; SI-NEXT: v_writelane_b32 v46, s20, 43
; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_mov_b32 s10, s23
-; SI-NEXT: s_mov_b32 s23, s5
-; SI-NEXT: s_lshl_b32 s5, s17, 24
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_writelane_b32 v42, s4, 59
-; SI-NEXT: s_and_b32 s4, s18, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 24
+; SI-NEXT: v_writelane_b32 v46, s90, 44
+; SI-NEXT: v_writelane_b32 v46, s88, 45
+; SI-NEXT: s_or_b32 s88, s5, s4
+; SI-NEXT: v_readlane_b32 s4, v47, 11
+; SI-NEXT: s_and_b32 s4, s4, 0xff
+; SI-NEXT: v_readlane_b32 s5, v47, 10
; SI-NEXT: s_lshl_b32 s4, s4, 16
-; SI-NEXT: s_lshl_b32 s5, s19, 24
-; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_readlane_b32 s5, v43, 8
-; SI-NEXT: v_writelane_b32 v42, s4, 60
-; SI-NEXT: s_and_b32 s4, s20, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 24
+; SI-NEXT: s_or_b32 s38, s5, s4
+; SI-NEXT: v_readlane_b32 s4, v47, 9
+; SI-NEXT: v_readlane_b32 s5, v47, 8
+; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
+; SI-NEXT: v_writelane_b32 v46, s36, 46
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_readlane_b32 s5, v43, 7
-; SI-NEXT: s_and_b32 s5, s5, 0xff
-; SI-NEXT: v_readlane_b32 s6, v43, 6
+; SI-NEXT: v_writelane_b32 v46, s4, 47
+; SI-NEXT: v_readlane_b32 s4, v47, 7
+; SI-NEXT: s_and_b32 s5, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 6
+; SI-NEXT: s_mov_b32 s90, s6
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s6, s6, 24
-; SI-NEXT: v_writelane_b32 v42, s4, 61
-; SI-NEXT: s_mov_b32 s4, s57
-; SI-NEXT: s_or_b32 s57, s6, s5
-; SI-NEXT: v_readlane_b32 s5, v43, 5
-; SI-NEXT: s_and_b32 s5, s5, 0xff
-; SI-NEXT: v_readlane_b32 s6, v43, 4
+; SI-NEXT: s_lshl_b32 s6, s4, 24
+; SI-NEXT: v_readlane_b32 s4, v47, 5
+; SI-NEXT: s_or_b32 s20, s6, s5
+; SI-NEXT: s_and_b32 s5, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 4
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s6, s6, 24
+; SI-NEXT: s_lshl_b32 s6, s4, 24
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_writelane_b32 v42, s5, 62
-; SI-NEXT: v_readlane_b32 s5, v43, 3
-; SI-NEXT: s_and_b32 s5, s5, 0xff
-; SI-NEXT: v_readlane_b32 s6, v43, 2
+; SI-NEXT: v_readlane_b32 s4, v47, 3
+; SI-NEXT: v_writelane_b32 v46, s5, 41
+; SI-NEXT: s_and_b32 s5, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 2
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s6, s6, 24
-; SI-NEXT: s_or_b32 s59, s6, s5
-; SI-NEXT: v_readlane_b32 s5, v43, 1
-; SI-NEXT: v_readlane_b32 s6, v43, 0
-; SI-NEXT: s_and_b32 s5, s5, 0xff
-; SI-NEXT: s_lshl_b32 s6, s6, 8
-; SI-NEXT: s_or_b32 s5, s5, s6
-; SI-NEXT: s_and_b32 s6, s75, 0xff
+; SI-NEXT: s_lshl_b32 s6, s4, 24
+; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: v_readlane_b32 s4, v47, 1
+; SI-NEXT: v_writelane_b32 v46, s5, 40
+; SI-NEXT: s_and_b32 s5, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 0
+; SI-NEXT: s_lshl_b32 s6, s4, 8
+; SI-NEXT: s_or_b32 s4, s5, s6
+; SI-NEXT: s_and_b32 s6, s70, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s7, s74, 24
-; SI-NEXT: v_writelane_b32 v42, s5, 63
-; SI-NEXT: s_or_b32 s5, s7, s6
-; SI-NEXT: s_and_b32 s6, s52, 0xff
+; SI-NEXT: s_lshl_b32 s7, vcc_lo, 24
+; SI-NEXT: v_writelane_b32 v46, s4, 48
+; SI-NEXT: s_or_b32 s4, s7, s6
+; SI-NEXT: s_and_b32 s6, vcc_hi, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s7, s48, 24
-; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
-; SI-NEXT: s_lshl_b32 s7, s76, 24
-; SI-NEXT: v_writelane_b32 v41, s6, 0
-; SI-NEXT: s_and_b32 s6, s60, 0xff
+; SI-NEXT: s_lshl_b32 s7, s22, 24
+; SI-NEXT: v_writelane_b32 v46, s4, 49
+; SI-NEXT: s_or_b32 s4, s7, s6
+; SI-NEXT: s_and_b32 s6, s50, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_or_b32 s20, s7, s6
-; SI-NEXT: s_and_b32 s6, s53, 0xff
-; SI-NEXT: s_lshl_b32 s7, s49, 8
-; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: s_and_b32 s7, s88, 0xff
-; SI-NEXT: s_mov_b32 s75, s16
+; SI-NEXT: s_lshl_b32 s7, s48, 24
+; SI-NEXT: s_or_b32 s22, s7, s6
+; SI-NEXT: s_and_b32 s6, s25, 0xff
+; SI-NEXT: s_lshl_b32 s7, s19, 8
+; SI-NEXT: s_or_b32 s70, s6, s7
+; SI-NEXT: s_and_b32 s7, s23, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s16, s55, 24
-; SI-NEXT: s_or_b32 s74, s16, s7
-; SI-NEXT: s_and_b32 s7, s54, 0xff
+; SI-NEXT: s_lshl_b32 s11, s11, 24
+; SI-NEXT: s_or_b32 s23, s11, s7
+; SI-NEXT: s_and_b32 s7, s24, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s16, s50, 24
-; SI-NEXT: s_or_b32 s49, s16, s7
-; SI-NEXT: s_and_b32 s7, s38, 0xff
+; SI-NEXT: s_lshl_b32 s11, s14, 24
+; SI-NEXT: v_writelane_b32 v46, s4, 50
+; SI-NEXT: s_or_b32 s4, s11, s7
+; SI-NEXT: s_and_b32 s7, s16, 0xff
+; SI-NEXT: v_writelane_b32 v46, s4, 51
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s16, s64, 24
-; SI-NEXT: s_or_b32 s76, s16, s7
-; SI-NEXT: s_and_b32 s7, s45, 0xff
-; SI-NEXT: s_lshl_b32 s16, s42, 8
-; SI-NEXT: s_or_b32 s7, s7, s16
-; SI-NEXT: s_and_b32 s16, s73, 0xff
+; SI-NEXT: s_lshl_b32 s11, s18, 24
+; SI-NEXT: v_readlane_b32 s4, v47, 29
+; SI-NEXT: s_or_b32 s6, s11, s7
+; SI-NEXT: s_and_b32 s7, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 28
+; SI-NEXT: s_lshl_b32 s11, s4, 8
+; SI-NEXT: v_readlane_b32 s4, v47, 27
+; SI-NEXT: s_or_b32 s7, s7, s11
+; SI-NEXT: s_and_b32 s11, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 26
+; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_lshl_b32 s14, s4, 24
+; SI-NEXT: v_readlane_b32 s4, v47, 25
+; SI-NEXT: s_or_b32 s25, s14, s11
+; SI-NEXT: s_and_b32 s11, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 24
+; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_lshl_b32 s14, s4, 24
+; SI-NEXT: v_readlane_b32 s4, v47, 23
+; SI-NEXT: s_or_b32 s24, s14, s11
+; SI-NEXT: s_and_b32 s11, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 22
+; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_lshl_b32 s14, s4, 24
+; SI-NEXT: v_readlane_b32 s4, v47, 21
+; SI-NEXT: s_or_b32 s48, s14, s11
+; SI-NEXT: s_and_b32 s11, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 20
+; SI-NEXT: s_lshl_b32 s14, s4, 8
+; SI-NEXT: v_readlane_b32 s4, v47, 19
+; SI-NEXT: s_or_b32 s5, s11, s14
+; SI-NEXT: s_and_b32 s11, s4, 0xff
+; SI-NEXT: v_readlane_b32 s4, v47, 18
+; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_lshl_b32 s14, s4, 24
+; SI-NEXT: s_or_b32 s4, s14, s11
+; SI-NEXT: v_readlane_b32 s11, v47, 17
+; SI-NEXT: s_and_b32 s11, s11, 0xff
+; SI-NEXT: v_readlane_b32 s14, v47, 16
+; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_lshl_b32 s16, s14, 24
+; SI-NEXT: s_or_b32 s50, s16, s11
+; SI-NEXT: v_readlane_b32 s11, v47, 15
+; SI-NEXT: s_and_b32 s16, s11, 0xff
+; SI-NEXT: v_readlane_b32 s11, v47, 14
; SI-NEXT: s_lshl_b32 s16, s16, 16
-; SI-NEXT: s_lshl_b32 s17, s51, 24
-; SI-NEXT: s_or_b32 s52, s17, s16
-; SI-NEXT: s_and_b32 s16, s77, 0xff
-; SI-NEXT: v_readlane_b32 s17, v43, 20
+; SI-NEXT: s_lshl_b32 s18, s11, 24
+; SI-NEXT: v_readlane_b32 s11, v47, 13
+; SI-NEXT: s_or_b32 s14, s18, s16
+; SI-NEXT: s_and_b32 s16, s11, 0xff
+; SI-NEXT: s_lshl_b32 s18, s81, 8
+; SI-NEXT: s_or_b32 s18, s16, s18
+; SI-NEXT: s_and_b32 s16, s71, 0xff
; SI-NEXT: s_lshl_b32 s16, s16, 16
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_or_b32 s38, s17, s16
-; SI-NEXT: v_readlane_b32 s16, v43, 19
-; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: v_readlane_b32 s17, v43, 18
+; SI-NEXT: s_lshl_b32 s19, s80, 24
+; SI-NEXT: s_or_b32 s80, s19, s16
+; SI-NEXT: s_and_b32 s16, s85, 0xff
; SI-NEXT: s_lshl_b32 s16, s16, 16
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_or_b32 s54, s17, s16
-; SI-NEXT: v_readlane_b32 s16, v43, 17
-; SI-NEXT: v_readlane_b32 s17, v43, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v43, 15
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v43, 14
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s50, s18, s17
-; SI-NEXT: v_readlane_b32 s17, v43, 13
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v43, 12
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s55, s18, s17
-; SI-NEXT: v_readlane_b32 s17, v43, 11
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: v_readlane_b32 s18, v43, 10
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s53, s18, s17
-; SI-NEXT: v_readlane_b32 s17, v43, 9
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: s_lshl_b32 s18, s65, 8
-; SI-NEXT: s_or_b32 s18, s17, s18
-; SI-NEXT: s_and_b32 s17, vcc_lo, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, vcc_hi, 24
-; SI-NEXT: s_or_b32 s65, s19, s17
-; SI-NEXT: s_and_b32 s17, s69, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s68, 24
-; SI-NEXT: s_or_b32 s64, s19, s17
-; SI-NEXT: s_and_b32 s17, s66, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s67, 24
-; SI-NEXT: s_or_b32 s88, s19, s17
-; SI-NEXT: s_and_b32 s17, s81, 0xff
-; SI-NEXT: s_lshl_b32 s19, s80, 8
-; SI-NEXT: s_or_b32 vcc_lo, s17, s19
-; SI-NEXT: s_and_b32 s17, s70, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s71, 24
-; SI-NEXT: s_or_b32 s60, s19, s17
-; SI-NEXT: s_and_b32 s17, s85, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s19, s84, 24
-; SI-NEXT: s_or_b32 s48, s19, s17
-; SI-NEXT: s_and_b32 s17, s82, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_or_b32 s71, s19, s16
+; SI-NEXT: s_and_b32 s16, s82, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s19, s83, 24
-; SI-NEXT: s_or_b32 s80, s19, s17
-; SI-NEXT: s_and_b32 s17, s97, 0xff
+; SI-NEXT: s_or_b32 s81, s19, s16
+; SI-NEXT: s_and_b32 s16, s97, 0xff
; SI-NEXT: s_lshl_b32 s19, s96, 8
-; SI-NEXT: s_or_b32 vcc_hi, s17, s19
-; SI-NEXT: s_and_b32 s17, s86, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_or_b32 vcc_lo, s16, s19
+; SI-NEXT: s_and_b32 s16, s86, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s19, s87, 24
-; SI-NEXT: s_or_b32 s82, s19, s17
-; SI-NEXT: s_and_b32 s17, s24, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s9, 24
-; SI-NEXT: s_or_b32 s9, s19, s17
-; SI-NEXT: s_and_b32 s17, s98, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_or_b32 s82, s19, s16
+; SI-NEXT: s_and_b32 s16, s8, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s10, 24
+; SI-NEXT: s_or_b32 s10, s19, s16
+; SI-NEXT: s_and_b32 s16, s98, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s19, s99, 24
-; SI-NEXT: s_or_b32 s24, s19, s17
-; SI-NEXT: s_and_b32 s17, s13, 0xff
-; SI-NEXT: s_lshl_b32 s19, s28, 8
-; SI-NEXT: s_or_b32 s84, s17, s19
-; SI-NEXT: s_and_b32 s17, s27, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s11, 24
-; SI-NEXT: s_or_b32 s13, s19, s17
-; SI-NEXT: s_and_b32 s17, s41, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s12, 24
-; SI-NEXT: s_or_b32 s11, s19, s17
-; SI-NEXT: s_and_b32 s17, s8, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s44, 24
-; SI-NEXT: s_or_b32 s8, s19, s17
-; SI-NEXT: s_and_b32 s17, s91, 0xff
-; SI-NEXT: s_lshl_b32 s19, s14, 8
-; SI-NEXT: s_or_b32 s85, s17, s19
-; SI-NEXT: s_and_b32 s17, s63, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s46, 24
-; SI-NEXT: s_or_b32 s12, s19, s17
-; SI-NEXT: s_and_b32 s17, s29, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s21, 24
-; SI-NEXT: s_or_b32 s14, s19, s17
-; SI-NEXT: s_and_b32 s17, s15, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s40, 24
-; SI-NEXT: s_or_b32 s29, s19, s17
-; SI-NEXT: s_and_b32 s17, s78, 0xff
-; SI-NEXT: s_lshl_b32 s19, s25, 8
-; SI-NEXT: s_or_b32 s86, s17, s19
-; SI-NEXT: s_and_b32 s17, s23, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s95, 24
-; SI-NEXT: s_or_b32 s95, s19, s17
-; SI-NEXT: s_and_b32 s17, s10, 0xff
-; SI-NEXT: v_readlane_b32 s15, v43, 32
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s15, 24
-; SI-NEXT: v_readlane_b32 s15, v43, 31
-; SI-NEXT: s_mov_b32 s77, s52
-; SI-NEXT: s_or_b32 s52, s19, s17
-; SI-NEXT: s_and_b32 s17, s15, 0xff
-; SI-NEXT: v_readlane_b32 s15, v43, 30
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s15, 24
-; SI-NEXT: v_readlane_b32 s15, v43, 29
-; SI-NEXT: s_mov_b32 s91, s54
-; SI-NEXT: s_or_b32 s54, s19, s17
-; SI-NEXT: s_and_b32 s17, s15, 0xff
-; SI-NEXT: v_readlane_b32 s15, v43, 28
+; SI-NEXT: s_or_b32 s83, s19, s16
+; SI-NEXT: s_and_b32 s16, s12, 0xff
; SI-NEXT: s_lshl_b32 s19, s15, 8
-; SI-NEXT: v_readlane_b32 s15, v43, 27
-; SI-NEXT: s_or_b32 s87, s17, s19
-; SI-NEXT: s_and_b32 s17, s15, 0xff
-; SI-NEXT: v_readlane_b32 s15, v43, 26
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s15, 24
-; SI-NEXT: v_readlane_b32 s15, v43, 25
-; SI-NEXT: s_or_b32 s27, s19, s17
-; SI-NEXT: s_and_b32 s17, s15, 0xff
-; SI-NEXT: v_readlane_b32 s15, v43, 24
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s15, 24
-; SI-NEXT: v_readlane_b32 s15, v43, 23
-; SI-NEXT: s_or_b32 s42, s19, s17
-; SI-NEXT: s_and_b32 s17, s15, 0xff
-; SI-NEXT: v_readlane_b32 s15, v43, 22
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s15, 24
-; SI-NEXT: v_readlane_b32 s15, v43, 21
-; SI-NEXT: s_or_b32 s78, s19, s17
-; SI-NEXT: s_and_b32 s17, s15, 0xff
+; SI-NEXT: s_or_b32 vcc_hi, s16, s19
+; SI-NEXT: s_and_b32 s16, s13, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s9, 24
+; SI-NEXT: s_or_b32 s13, s19, s16
+; SI-NEXT: s_and_b32 s16, s57, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s43, 24
+; SI-NEXT: s_or_b32 s12, s19, s16
+; SI-NEXT: s_and_b32 s16, s42, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s44, 24
+; SI-NEXT: s_or_b32 s96, s19, s16
+; SI-NEXT: s_and_b32 s16, s56, 0xff
; SI-NEXT: s_lshl_b32 s19, s62, 8
-; SI-NEXT: s_or_b32 s23, s17, s19
-; SI-NEXT: s_and_b32 s17, s31, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s37, 24
-; SI-NEXT: s_or_b32 s67, s19, s17
-; SI-NEXT: s_and_b32 s17, s94, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s61, 24
-; SI-NEXT: s_or_b32 s66, s19, s17
-; SI-NEXT: s_and_b32 s17, s47, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_or_b32 s84, s16, s19
+; SI-NEXT: s_and_b32 s16, s45, 0xff
+; SI-NEXT: v_readlane_b32 s8, v47, 33
+; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s19, s58, 24
-; SI-NEXT: s_or_b32 s68, s19, s17
-; SI-NEXT: s_and_b32 s17, s90, 0xff
-; SI-NEXT: s_lshl_b32 s19, s30, 8
-; SI-NEXT: s_or_b32 s25, s17, s19
-; SI-NEXT: s_and_b32 s17, s92, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s93, 24
-; SI-NEXT: s_or_b32 s70, s19, s17
-; SI-NEXT: s_and_b32 s17, s72, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_mov_b32 s62, s22
+; SI-NEXT: s_or_b32 s22, s19, s16
+; SI-NEXT: s_and_b32 s16, s8, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s73, 24
+; SI-NEXT: s_or_b32 s8, s19, s16
+; SI-NEXT: s_and_b32 s16, s60, 0xff
+; SI-NEXT: v_readlane_b32 s9, v47, 32
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s63, 24
+; SI-NEXT: s_or_b32 s15, s19, s16
+; SI-NEXT: s_and_b32 s16, s9, 0xff
+; SI-NEXT: s_lshl_b32 s19, s78, 8
+; SI-NEXT: s_or_b32 s85, s16, s19
+; SI-NEXT: s_and_b32 s16, s90, 0xff
+; SI-NEXT: v_readlane_b32 s9, v47, 31
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s9, 24
+; SI-NEXT: s_mov_b32 s58, s24
+; SI-NEXT: v_readlane_b32 s90, v46, 44
+; SI-NEXT: s_or_b32 s24, s19, s16
+; SI-NEXT: s_and_b32 s16, s35, 0xff
+; SI-NEXT: v_readlane_b32 s36, v46, 46
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s90, 24
+; SI-NEXT: s_or_b32 s9, s19, s16
+; SI-NEXT: s_and_b32 s16, s36, 0xff
+; SI-NEXT: s_mov_b32 s57, s38
+; SI-NEXT: v_readlane_b32 s38, v46, 42
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s72, 24
+; SI-NEXT: s_or_b32 s11, s19, s16
+; SI-NEXT: s_and_b32 s16, s38, 0xff
+; SI-NEXT: s_lshl_b32 s19, s46, 8
+; SI-NEXT: s_or_b32 s86, s16, s19
+; SI-NEXT: s_and_b32 s16, s74, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s77, 24
+; SI-NEXT: s_or_b32 s43, s19, s16
+; SI-NEXT: s_and_b32 s16, s21, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s49, 24
+; SI-NEXT: s_or_b32 s44, s19, s16
+; SI-NEXT: s_and_b32 s16, s30, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s26, 24
+; SI-NEXT: s_or_b32 s42, s19, s16
+; SI-NEXT: s_and_b32 s16, s69, 0xff
+; SI-NEXT: s_lshl_b32 s19, s52, 8
+; SI-NEXT: s_or_b32 s87, s16, s19
+; SI-NEXT: s_and_b32 s16, s51, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s66, 24
+; SI-NEXT: s_or_b32 s45, s19, s16
+; SI-NEXT: s_and_b32 s16, s55, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s19, s39, 24
-; SI-NEXT: s_or_b32 s69, s19, s17
-; SI-NEXT: s_and_b32 s17, s34, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s22, 24
-; SI-NEXT: s_or_b32 s71, s19, s17
-; SI-NEXT: s_and_b32 s17, s36, 0xff
-; SI-NEXT: s_lshl_b32 s19, s35, 8
-; SI-NEXT: s_mov_b32 s73, s20
-; SI-NEXT: s_or_b32 s20, s17, s19
-; SI-NEXT: s_and_b32 s17, s89, 0xff
-; SI-NEXT: s_mov_b32 s51, s5
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_mov_b32 s66, s15
+; SI-NEXT: s_or_b32 s15, s19, s16
+; SI-NEXT: s_and_b32 s16, s67, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s54, 24
+; SI-NEXT: s_or_b32 s30, s19, s16
+; SI-NEXT: s_and_b32 s16, s91, 0xff
+; SI-NEXT: s_lshl_b32 s19, s37, 8
+; SI-NEXT: s_mov_b32 s63, s23
+; SI-NEXT: s_or_b32 s23, s16, s19
+; SI-NEXT: s_and_b32 s16, s64, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s17, 24
+; SI-NEXT: s_or_b32 s67, s19, s16
+; SI-NEXT: s_and_b32 s16, s94, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s28, 24
+; SI-NEXT: s_mov_b32 s55, s13
+; SI-NEXT: s_or_b32 s13, s19, s16
+; SI-NEXT: s_and_b32 s16, s53, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s27, 24
+; SI-NEXT: s_or_b32 s21, s19, s16
+; SI-NEXT: s_and_b32 s16, s68, 0xff
+; SI-NEXT: s_lshl_b32 s19, s65, 8
+; SI-NEXT: s_or_b32 s26, s16, s19
+; SI-NEXT: s_and_b32 s16, s47, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s95, 24
+; SI-NEXT: s_mov_b32 s54, s12
+; SI-NEXT: s_or_b32 s12, s19, s16
+; SI-NEXT: s_and_b32 s16, s76, 0xff
+; SI-NEXT: s_mov_b32 s60, s20
+; SI-NEXT: v_readlane_b32 s20, v46, 43
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s31, 24
+; SI-NEXT: s_mov_b32 s56, s88
+; SI-NEXT: v_readlane_b32 s88, v46, 45
+; SI-NEXT: s_mov_b32 s27, s9
+; SI-NEXT: s_or_b32 s9, s19, s16
+; SI-NEXT: s_and_b32 s16, s20, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s88, 24
+; SI-NEXT: s_mov_b32 s91, s71
+; SI-NEXT: s_or_b32 s71, s19, s16
+; SI-NEXT: s_and_b32 s16, s41, 0xff
+; SI-NEXT: s_lshl_b32 s19, s61, 8
+; SI-NEXT: s_mov_b32 s78, s25
+; SI-NEXT: s_or_b32 s25, s16, s19
+; SI-NEXT: s_and_b32 s16, s89, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s59, 24
+; SI-NEXT: s_mov_b32 s39, s81
+; SI-NEXT: s_or_b32 s81, s19, s16
+; SI-NEXT: s_and_b32 s16, s40, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s34, 24
+; SI-NEXT: s_mov_b32 s51, s80
+; SI-NEXT: s_or_b32 s80, s19, s16
+; SI-NEXT: s_and_b32 s16, s93, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s19, s79, 24
-; SI-NEXT: v_readlane_b32 s5, v42, 47
-; SI-NEXT: s_or_b32 s81, s19, s17
-; SI-NEXT: s_and_b32 s17, s5, 0xff
-; SI-NEXT: v_readlane_b32 s5, v42, 46
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s5, 24
-; SI-NEXT: s_mov_b32 s63, s80
-; SI-NEXT: s_or_b32 s80, s19, s17
-; SI-NEXT: s_and_b32 s17, s75, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s19, s26, 24
-; SI-NEXT: s_mov_b32 s75, s82
-; SI-NEXT: s_or_b32 s82, s19, s17
-; SI-NEXT: s_and_b32 s17, s4, 0xff
-; SI-NEXT: s_lshl_b32 s19, s56, 8
-; SI-NEXT: v_readlane_b32 s4, v42, 49
-; SI-NEXT: s_or_b32 s26, s17, s19
-; SI-NEXT: s_and_b32 s17, s43, 0xff
-; SI-NEXT: s_lshl_b32 s19, s4, 24
-; SI-NEXT: v_readlane_b32 s4, v42, 61
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s21, s4, 16
-; SI-NEXT: v_readlane_b32 s4, v42, 63
-; SI-NEXT: s_mov_b32 s28, s48
-; SI-NEXT: s_mov_b32 s41, s38
-; SI-NEXT: s_mov_b32 s48, s50
-; SI-NEXT: s_mov_b32 s50, s57
-; SI-NEXT: v_readlane_b32 s38, v42, 59
-; SI-NEXT: v_readlane_b32 s45, v42, 62
-; SI-NEXT: s_mov_b32 s15, s58
-; SI-NEXT: v_readlane_b32 s47, v41, 0
-; SI-NEXT: s_mov_b32 s57, s90
-; SI-NEXT: s_mov_b32 s90, s92
-; SI-NEXT: s_mov_b32 s30, s93
-; SI-NEXT: v_readlane_b32 s58, v42, 60
-; SI-NEXT: s_mov_b32 s39, s22
-; SI-NEXT: s_or_b32 s83, s19, s17
-; SI-NEXT: s_lshl_b32 s44, s4, 16
-; SI-NEXT: s_lshl_b32 s19, s6, 16
-; SI-NEXT: s_lshl_b32 s17, s7, 16
+; SI-NEXT: v_readlane_b32 s97, v47, 30
+; SI-NEXT: s_mov_b32 s52, s82
+; SI-NEXT: s_or_b32 s82, s19, s16
+; SI-NEXT: s_and_b32 s16, s29, 0xff
+; SI-NEXT: s_lshl_b32 s19, s75, 8
+; SI-NEXT: s_mov_b32 s37, s4
+; SI-NEXT: s_mov_b32 s68, s24
+; SI-NEXT: s_or_b32 s24, s16, s19
+; SI-NEXT: s_and_b32 s16, s97, 0xff
+; SI-NEXT: v_readlane_b32 s4, v46, 47
; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s19, s92, 24
+; SI-NEXT: s_lshl_b32 s94, s4, 16
+; SI-NEXT: v_readlane_b32 s4, v46, 48
+; SI-NEXT: s_mov_b32 s64, s96
+; SI-NEXT: s_mov_b32 s53, s83
+; SI-NEXT: s_mov_b32 s65, s22
+; SI-NEXT: s_mov_b32 s49, s76
+; SI-NEXT: s_mov_b32 s73, s92
+; SI-NEXT: s_mov_b32 s72, s6
+; SI-NEXT: s_or_b32 s83, s19, s16
+; SI-NEXT: s_lshl_b32 s22, s4, 16
+; SI-NEXT: s_lshl_b32 s19, s70, 16
+; SI-NEXT: s_lshl_b32 s16, s7, 16
+; SI-NEXT: s_lshl_b32 s17, s5, 16
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_lshl_b32 s99, vcc_lo, 16
-; SI-NEXT: s_lshl_b32 s98, vcc_hi, 16
-; SI-NEXT: s_lshl_b32 s7, s84, 16
-; SI-NEXT: s_lshl_b32 s6, s85, 16
+; SI-NEXT: s_lshl_b32 s7, vcc_lo, 16
+; SI-NEXT: s_lshl_b32 s6, vcc_hi, 16
+; SI-NEXT: s_lshl_b32 s99, s84, 16
+; SI-NEXT: s_lshl_b32 s98, s85, 16
; SI-NEXT: s_lshl_b32 s97, s86, 16
; SI-NEXT: s_lshl_b32 s96, s87, 16
; SI-NEXT: s_lshl_b32 s87, s23, 16
-; SI-NEXT: s_lshl_b32 s86, s25, 16
-; SI-NEXT: s_lshl_b32 s85, s20, 16
-; SI-NEXT: s_lshl_b32 s84, s26, 16
-; SI-NEXT: s_mov_b32 s26, s24
+; SI-NEXT: s_lshl_b32 s86, s26, 16
+; SI-NEXT: v_readlane_b32 s26, v46, 50
+; SI-NEXT: v_readlane_b32 s28, v46, 49
+; SI-NEXT: s_lshl_b32 s85, s25, 16
+; SI-NEXT: v_readlane_b32 s25, v46, 51
+; SI-NEXT: s_lshl_b32 s84, s24, 16
; SI-NEXT: s_cbranch_execnz .LBB89_3
; SI-NEXT: .LBB89_2: ; %cmp.true
-; SI-NEXT: v_readlane_b32 s4, v42, 51
-; SI-NEXT: s_add_i32 s59, s4, 3
-; SI-NEXT: v_readlane_b32 s5, v42, 50
-; SI-NEXT: v_readlane_b32 s6, v42, 48
-; SI-NEXT: s_and_b32 s4, s59, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 8
-; SI-NEXT: s_add_i32 s56, s6, 3
+; SI-NEXT: s_add_i32 s4, s29, 3
+; SI-NEXT: v_readlane_b32 s6, v47, 30
+; SI-NEXT: s_and_b32 s4, s4, 0xff
+; SI-NEXT: s_lshl_b32 s5, s75, 8
+; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_readlane_b32 s5, v42, 49
-; SI-NEXT: s_and_b32 s6, s56, 0xff
-; SI-NEXT: s_lshl_b32 s5, s5, 24
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s5, s73, 24
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_addk_i32 s4, 0x300
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: s_add_i32 s29, s40, 3
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_readlane_b32 s5, v42, 47
-; SI-NEXT: s_add_i32 s47, s5, 3
-; SI-NEXT: v_readlane_b32 s6, v42, 46
-; SI-NEXT: v_readlane_b32 s7, v42, 44
-; SI-NEXT: s_and_b32 s5, s47, 0xff
-; SI-NEXT: s_lshl_b32 s6, s6, 8
-; SI-NEXT: s_add_i32 s44, s7, 3
+; SI-NEXT: s_and_b32 s5, s29, 0xff
+; SI-NEXT: s_lshl_b32 s6, s34, 8
+; SI-NEXT: s_add_i32 s7, s93, 3
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_readlane_b32 s6, v42, 45
-; SI-NEXT: s_and_b32 s7, s44, 0xff
-; SI-NEXT: s_lshl_b32 s6, s6, 24
+; SI-NEXT: s_and_b32 s7, s7, 0xff
+; SI-NEXT: s_lshl_b32 s6, s79, 24
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_addk_i32 s5, 0x300
; SI-NEXT: s_or_b32 s6, s6, s7
; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_add_i32 s40, s41, 3
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_readlane_b32 s6, v42, 43
-; SI-NEXT: s_add_i32 s43, s6, 3
-; SI-NEXT: v_readlane_b32 s7, v42, 42
-; SI-NEXT: v_readlane_b32 s8, v42, 40
-; SI-NEXT: s_and_b32 s6, s43, 0xff
-; SI-NEXT: s_lshl_b32 s7, s7, 8
-; SI-NEXT: s_add_i32 s40, s8, 3
+; SI-NEXT: s_and_b32 s6, s40, 0xff
+; SI-NEXT: s_lshl_b32 s7, s61, 8
+; SI-NEXT: s_add_i32 s10, s89, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: v_readlane_b32 s7, v42, 41
-; SI-NEXT: s_and_b32 s16, s40, 0xff
-; SI-NEXT: s_lshl_b32 s7, s7, 24
-; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_and_b32 s10, s10, 0xff
+; SI-NEXT: s_lshl_b32 s7, s59, 24
+; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_addk_i32 s6, 0x300
-; SI-NEXT: s_or_b32 s7, s7, s16
+; SI-NEXT: s_or_b32 s7, s7, s10
; SI-NEXT: s_and_b32 s6, s6, 0xffff
+; SI-NEXT: s_add_i32 s59, s49, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: v_readlane_b32 s7, v42, 38
-; SI-NEXT: v_readlane_b32 s8, v42, 37
-; SI-NEXT: s_add_i32 s14, s7, 3
-; SI-NEXT: s_lshl_b32 s13, s8, 8
-; SI-NEXT: v_readlane_b32 s8, v42, 36
-; SI-NEXT: s_and_b32 s7, s14, 0xff
-; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: s_or_b32 s7, s13, s7
+; SI-NEXT: s_and_b32 s7, s59, 0xff
+; SI-NEXT: s_lshl_b32 s10, s31, 8
+; SI-NEXT: s_add_i32 s8, s20, 3
+; SI-NEXT: s_or_b32 s7, s10, s7
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: s_lshl_b32 s9, s39, 24
+; SI-NEXT: s_lshl_b32 s10, s88, 24
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_addk_i32 s7, 0x300
-; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_or_b32 s9, s8, s7
-; SI-NEXT: s_add_i32 s24, s57, 3
-; SI-NEXT: v_readlane_b32 s8, v42, 56
-; SI-NEXT: s_and_b32 s7, s24, 0xff
-; SI-NEXT: s_lshl_b32 s8, s8, 8
-; SI-NEXT: s_add_i32 s13, s90, 3
-; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: s_and_b32 s13, s13, 0xff
-; SI-NEXT: s_lshl_b32 s8, s30, 24
-; SI-NEXT: s_lshl_b32 s13, s13, 16
-; SI-NEXT: s_addk_i32 s7, 0x300
-; SI-NEXT: s_or_b32 s8, s8, s13
+; SI-NEXT: s_or_b32 s8, s10, s8
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: v_readlane_b32 s8, v42, 58
-; SI-NEXT: v_readlane_b32 s10, v42, 57
-; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: s_lshl_b32 s13, s10, 8
-; SI-NEXT: v_readlane_b32 s10, v42, 55
-; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: s_add_i32 s14, s10, 3
-; SI-NEXT: s_or_b32 s8, s13, s8
-; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: s_lshl_b32 s13, s15, 24
+; SI-NEXT: v_readlane_b32 s8, v46, 31
+; SI-NEXT: s_add_i32 s89, s8, 3
+; SI-NEXT: v_readlane_b32 s9, v46, 22
+; SI-NEXT: s_and_b32 s8, s89, 0xff
+; SI-NEXT: s_lshl_b32 s10, s9, 8
+; SI-NEXT: s_add_i32 s43, s47, 3
+; SI-NEXT: s_or_b32 s8, s10, s8
+; SI-NEXT: s_and_b32 s11, s43, 0xff
+; SI-NEXT: s_lshl_b32 s10, s95, 24
+; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_addk_i32 s8, 0x300
+; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_and_b32 s8, s8, 0xffff
+; SI-NEXT: s_or_b32 s10, s10, s8
+; SI-NEXT: v_readlane_b32 s8, v46, 36
+; SI-NEXT: s_add_i32 s31, s8, 3
+; SI-NEXT: v_readlane_b32 s9, v46, 32
+; SI-NEXT: s_and_b32 s8, s31, 0xff
+; SI-NEXT: s_lshl_b32 s11, s9, 8
+; SI-NEXT: v_readlane_b32 s9, v46, 20
+; SI-NEXT: s_or_b32 s8, s11, s8
+; SI-NEXT: s_lshl_b32 s11, s9, 24
+; SI-NEXT: v_readlane_b32 s9, v46, 21
+; SI-NEXT: s_add_i32 s60, s9, 3
+; SI-NEXT: s_and_b32 s14, s60, 0xff
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s13, s13, s14
+; SI-NEXT: s_or_b32 s11, s11, s14
; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_or_b32 s13, s13, s8
-; SI-NEXT: v_readlane_b32 s8, v43, 21
-; SI-NEXT: s_add_i32 s27, s8, 3
-; SI-NEXT: v_readlane_b32 s10, v42, 33
-; SI-NEXT: s_and_b32 s8, s27, 0xff
-; SI-NEXT: s_lshl_b32 s14, s10, 8
-; SI-NEXT: v_readlane_b32 s10, v42, 54
+; SI-NEXT: s_or_b32 s11, s11, s8
+; SI-NEXT: v_readlane_b32 s8, v46, 37
+; SI-NEXT: s_add_i32 s34, s8, 3
+; SI-NEXT: v_readlane_b32 s9, v46, 34
+; SI-NEXT: s_and_b32 s8, s34, 0xff
+; SI-NEXT: s_lshl_b32 s14, s9, 8
+; SI-NEXT: v_readlane_b32 s9, v46, 24
; SI-NEXT: s_or_b32 s8, s14, s8
-; SI-NEXT: s_lshl_b32 s14, s10, 24
-; SI-NEXT: v_readlane_b32 s10, v42, 53
-; SI-NEXT: s_add_i32 s16, s10, 3
-; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s14, s9, 24
+; SI-NEXT: v_readlane_b32 s9, v46, 27
+; SI-NEXT: s_add_i32 s76, s9, 3
+; SI-NEXT: s_and_b32 s15, s76, 0xff
+; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s14, s14, s16
+; SI-NEXT: s_or_b32 s14, s14, s15
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_or_b32 s14, s14, s8
-; SI-NEXT: v_readlane_b32 s8, v43, 25
-; SI-NEXT: s_add_i32 s10, s8, 3
-; SI-NEXT: s_and_b32 s8, s10, 0xff
-; SI-NEXT: v_readlane_b32 s10, v43, 24
-; SI-NEXT: v_readlane_b32 s11, v43, 23
-; SI-NEXT: s_lshl_b32 s10, s10, 8
-; SI-NEXT: s_add_i32 s16, s11, 3
-; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v43, 22
-; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 24
+; SI-NEXT: v_readlane_b32 s8, v46, 39
+; SI-NEXT: s_add_i32 s39, s8, 3
+; SI-NEXT: v_readlane_b32 s9, v46, 38
+; SI-NEXT: s_and_b32 s8, s39, 0xff
+; SI-NEXT: s_lshl_b32 s15, s9, 8
+; SI-NEXT: v_readlane_b32 s9, v46, 25
+; SI-NEXT: s_or_b32 s8, s15, s8
+; SI-NEXT: s_lshl_b32 s15, s9, 24
+; SI-NEXT: v_readlane_b32 s9, v46, 28
+; SI-NEXT: s_add_i32 s78, s9, 3
+; SI-NEXT: s_and_b32 s16, s78, 0xff
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s10, s10, s16
+; SI-NEXT: s_or_b32 s15, s15, s16
; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_or_b32 s16, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v43, 29
-; SI-NEXT: s_add_i32 s12, s8, 3
-; SI-NEXT: v_readlane_b32 s10, v43, 28
-; SI-NEXT: v_readlane_b32 s11, v43, 27
-; SI-NEXT: s_and_b32 s8, s12, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 8
-; SI-NEXT: s_add_i32 s12, s11, 3
-; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v43, 26
+; SI-NEXT: s_or_b32 s15, s15, s8
+; SI-NEXT: v_readlane_b32 s8, v46, 35
+; SI-NEXT: s_add_i32 s30, s8, 3
+; SI-NEXT: v_readlane_b32 s9, v46, 33
+; SI-NEXT: s_and_b32 s8, s30, 0xff
+; SI-NEXT: s_lshl_b32 s16, s9, 8
+; SI-NEXT: v_readlane_b32 s9, v46, 30
+; SI-NEXT: s_or_b32 s8, s16, s8
+; SI-NEXT: s_lshl_b32 s16, s9, 24
+; SI-NEXT: v_readlane_b32 s9, v46, 29
+; SI-NEXT: s_add_i32 s79, s9, 3
+; SI-NEXT: s_and_b32 s17, s79, 0xff
+; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_addk_i32 s8, 0x300
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s8, s8, 0xffff
+; SI-NEXT: s_or_b32 s16, s16, s8
+; SI-NEXT: v_readlane_b32 s8, v46, 26
+; SI-NEXT: s_add_i32 s75, s8, 3
+; SI-NEXT: v_readlane_b32 s9, v46, 23
+; SI-NEXT: s_and_b32 s8, s75, 0xff
+; SI-NEXT: s_lshl_b32 s17, s9, 8
+; SI-NEXT: v_readlane_b32 s9, v46, 19
+; SI-NEXT: s_or_b32 s8, s17, s8
+; SI-NEXT: s_lshl_b32 s17, s9, 24
+; SI-NEXT: v_readlane_b32 s9, v46, 18
+; SI-NEXT: s_add_i32 s56, s9, 3
+; SI-NEXT: s_and_b32 s18, s56, 0xff
+; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_addk_i32 s8, 0x300
+; SI-NEXT: s_or_b32 s17, s17, s18
+; SI-NEXT: s_and_b32 s8, s8, 0xffff
+; SI-NEXT: s_add_i32 s45, s38, 3
+; SI-NEXT: s_or_b32 s23, s17, s8
+; SI-NEXT: s_and_b32 s8, s45, 0xff
+; SI-NEXT: s_lshl_b32 s17, s46, 8
+; SI-NEXT: s_add_i32 s12, s74, 3
+; SI-NEXT: s_or_b32 s8, s17, s8
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 24
+; SI-NEXT: s_lshl_b32 s13, s77, 24
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s10, s10, s12
+; SI-NEXT: s_or_b32 s12, s13, s12
; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_or_b32 s17, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v42, 39
-; SI-NEXT: s_add_i32 s15, s8, 3
-; SI-NEXT: v_readlane_b32 s10, v43, 32
-; SI-NEXT: v_readlane_b32 s11, v43, 31
-; SI-NEXT: s_and_b32 s8, s15, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 8
-; SI-NEXT: s_add_i32 s20, s11, 3
-; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v43, 30
-; SI-NEXT: s_and_b32 s11, s20, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 24
-; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_add_i32 s9, s35, 3
+; SI-NEXT: s_or_b32 s24, s12, s8
+; SI-NEXT: s_and_b32 s8, s9, 0xff
+; SI-NEXT: s_lshl_b32 s9, s90, 8
+; SI-NEXT: s_add_i32 s21, s36, 3
+; SI-NEXT: s_or_b32 s8, s9, s8
+; SI-NEXT: v_readlane_b32 s9, v46, 17
+; SI-NEXT: s_and_b32 s12, s21, 0xff
+; SI-NEXT: s_lshl_b32 s9, s9, 24
+; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_or_b32 s9, s9, s12
; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_or_b32 s15, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v42, 35
-; SI-NEXT: s_add_i32 s28, s8, 3
-; SI-NEXT: v_readlane_b32 s10, v42, 34
-; SI-NEXT: v_readlane_b32 s11, v42, 31
-; SI-NEXT: s_and_b32 s8, s28, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 8
+; SI-NEXT: s_or_b32 s27, s9, s8
+; SI-NEXT: s_add_i32 s8, s6, 0x3000000
+; SI-NEXT: v_readlane_b32 s6, v47, 32
+; SI-NEXT: s_add_i32 s9, s7, 0x3000000
+; SI-NEXT: s_add_i32 s12, s11, 0x3000000
+; SI-NEXT: s_add_i32 s6, s6, 3
+; SI-NEXT: v_readlane_b32 s7, v46, 16
+; SI-NEXT: v_readlane_b32 s11, v46, 15
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_add_i32 s11, s11, 3
-; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v42, 32
+; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: v_readlane_b32 s7, v47, 31
; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 24
+; SI-NEXT: s_addk_i32 s6, 0x300
+; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_or_b32 s20, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v42, 30
-; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: v_readlane_b32 s10, v42, 29
-; SI-NEXT: v_readlane_b32 s11, v42, 27
-; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 8
+; SI-NEXT: s_and_b32 s6, s6, 0xffff
+; SI-NEXT: s_or_b32 s7, s7, s11
+; SI-NEXT: s_or_b32 s29, s7, s6
+; SI-NEXT: v_readlane_b32 s6, v47, 33
+; SI-NEXT: s_add_i32 s6, s6, 3
+; SI-NEXT: v_readlane_b32 s7, v46, 14
+; SI-NEXT: v_readlane_b32 s11, v46, 12
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_add_i32 s11, s11, 3
-; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v42, 28
+; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: v_readlane_b32 s7, v46, 13
; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 24
+; SI-NEXT: s_addk_i32 s6, 0x300
+; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_or_b32 s23, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v42, 26
-; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: v_readlane_b32 s10, v42, 25
-; SI-NEXT: v_readlane_b32 s11, v42, 24
-; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 8
+; SI-NEXT: s_and_b32 s6, s6, 0xffff
+; SI-NEXT: s_or_b32 s7, s7, s11
+; SI-NEXT: s_or_b32 s40, s7, s6
+; SI-NEXT: v_readlane_b32 s6, v46, 11
+; SI-NEXT: s_add_i32 s6, s6, 3
+; SI-NEXT: v_readlane_b32 s7, v46, 10
+; SI-NEXT: v_readlane_b32 s11, v46, 8
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_add_i32 s11, s11, 3
-; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v42, 52
+; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: v_readlane_b32 s7, v46, 9
; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 24
+; SI-NEXT: s_addk_i32 s6, 0x300
+; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_or_b32 s18, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v42, 23
-; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: v_readlane_b32 s10, v42, 22
-; SI-NEXT: v_readlane_b32 s11, v42, 20
-; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 8
+; SI-NEXT: s_and_b32 s6, s6, 0xffff
+; SI-NEXT: s_or_b32 s7, s7, s11
+; SI-NEXT: s_or_b32 s42, s7, s6
+; SI-NEXT: v_readlane_b32 s6, v46, 7
+; SI-NEXT: s_add_i32 s6, s6, 3
+; SI-NEXT: v_readlane_b32 s7, v46, 6
+; SI-NEXT: v_readlane_b32 s11, v46, 4
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_add_i32 s11, s11, 3
-; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v42, 21
+; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: v_readlane_b32 s7, v46, 5
; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 24
+; SI-NEXT: s_addk_i32 s6, 0x300
+; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_or_b32 s24, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v42, 19
-; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: v_readlane_b32 s10, v42, 18
-; SI-NEXT: s_add_i32 s12, s14, 0x3000000
-; SI-NEXT: s_add_i32 s14, s17, 0x3000000
-; SI-NEXT: v_readlane_b32 s17, v42, 16
-; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: s_lshl_b32 s10, s10, 8
-; SI-NEXT: s_add_i32 s17, s17, 3
-; SI-NEXT: s_or_b32 s19, s10, s8
-; SI-NEXT: s_add_i32 s11, s13, 0x3000000
-; SI-NEXT: s_add_i32 s13, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 17
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: s_addk_i32 s19, 0x300
-; SI-NEXT: s_lshl_b32 s16, s16, 24
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_add_i32 s10, s7, 0x3000000
-; SI-NEXT: s_and_b32 s7, s19, 0xffff
-; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_or_b32 s7, s16, s7
-; SI-NEXT: v_readlane_b32 s16, v42, 15
-; SI-NEXT: s_add_i32 s8, s6, 0x3000000
-; SI-NEXT: s_add_i32 s6, s18, 0x3000000
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 14
-; SI-NEXT: v_readlane_b32 s18, v42, 12
-; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 13
-; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_or_b32 s25, s17, s16
-; SI-NEXT: v_readlane_b32 s16, v42, 11
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 10
-; SI-NEXT: v_readlane_b32 s18, v42, 8
-; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 9
-; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_or_b32 s26, s17, s16
-; SI-NEXT: v_readlane_b32 s16, v42, 7
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 6
-; SI-NEXT: v_readlane_b32 s18, v42, 4
-; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 5
-; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_or_b32 s27, s17, s16
-; SI-NEXT: v_readlane_b32 s16, v42, 3
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 2
-; SI-NEXT: v_readlane_b32 s18, v42, 0
-; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 1
-; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_or_b32 s28, s17, s16
-; SI-NEXT: v_readlane_b32 s16, v43, 63
+; SI-NEXT: s_and_b32 s6, s6, 0xffff
+; SI-NEXT: s_or_b32 s7, s7, s11
+; SI-NEXT: s_or_b32 s43, s7, s6
+; SI-NEXT: v_readlane_b32 s6, v46, 3
+; SI-NEXT: s_add_i32 s6, s6, 3
+; SI-NEXT: v_readlane_b32 s7, v46, 2
+; SI-NEXT: v_readlane_b32 s11, v46, 0
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s7, s7, 8
+; SI-NEXT: s_add_i32 s11, s11, 3
+; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: v_readlane_b32 s7, v46, 1
+; SI-NEXT: s_and_b32 s11, s11, 0xff
+; SI-NEXT: s_addk_i32 s6, 0x300
+; SI-NEXT: s_lshl_b32 s7, s7, 24
+; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_and_b32 s6, s6, 0xffff
+; SI-NEXT: s_or_b32 s7, s7, s11
+; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: v_readlane_b32 s7, v47, 63
+; SI-NEXT: s_add_i32 s13, s14, 0x3000000
+; SI-NEXT: s_add_i32 s7, s7, 3
+; SI-NEXT: v_readlane_b32 s11, v47, 62
+; SI-NEXT: v_readlane_b32 s14, v47, 60
+; SI-NEXT: s_and_b32 s7, s7, 0xff
+; SI-NEXT: s_lshl_b32 s11, s11, 8
+; SI-NEXT: s_add_i32 s14, s14, 3
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: v_readlane_b32 s11, v47, 61
+; SI-NEXT: s_and_b32 s14, s14, 0xff
+; SI-NEXT: s_addk_i32 s7, 0x300
+; SI-NEXT: s_lshl_b32 s11, s11, 24
+; SI-NEXT: s_lshl_b32 s14, s14, 16
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s11, s11, s14
+; SI-NEXT: s_or_b32 s44, s11, s7
+; SI-NEXT: v_readlane_b32 s7, v47, 59
+; SI-NEXT: s_add_i32 s7, s7, 3
+; SI-NEXT: v_readlane_b32 s11, v47, 58
+; SI-NEXT: v_readlane_b32 s14, v47, 56
+; SI-NEXT: s_and_b32 s7, s7, 0xff
+; SI-NEXT: s_lshl_b32 s11, s11, 8
+; SI-NEXT: s_add_i32 s14, s14, 3
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: v_readlane_b32 s11, v47, 57
+; SI-NEXT: s_and_b32 s14, s14, 0xff
+; SI-NEXT: s_addk_i32 s7, 0x300
+; SI-NEXT: s_lshl_b32 s11, s11, 24
+; SI-NEXT: s_lshl_b32 s14, s14, 16
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_or_b32 s11, s11, s14
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: v_readlane_b32 s11, v47, 55
+; SI-NEXT: s_add_i32 s21, s16, 0x3000000
+; SI-NEXT: s_add_i32 s11, s11, 3
+; SI-NEXT: v_readlane_b32 s14, v47, 54
+; SI-NEXT: v_readlane_b32 s16, v47, 52
+; SI-NEXT: s_and_b32 s11, s11, 0xff
+; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v43, 62
-; SI-NEXT: v_readlane_b32 s18, v43, 60
+; SI-NEXT: s_or_b32 s11, s14, s11
+; SI-NEXT: v_readlane_b32 s14, v47, 53
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v43, 61
-; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s29, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v43, 9
+; SI-NEXT: s_addk_i32 s11, 0x300
+; SI-NEXT: s_lshl_b32 s14, s14, 24
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_and_b32 s11, s11, 0xffff
+; SI-NEXT: s_or_b32 s14, s14, s16
+; SI-NEXT: s_or_b32 s11, s14, s11
+; SI-NEXT: s_add_i32 s45, s11, 0x3000000
+; SI-NEXT: v_readlane_b32 s11, v47, 13
+; SI-NEXT: s_add_i32 s11, s11, 3
+; SI-NEXT: v_readlane_b32 s14, v47, 51
+; SI-NEXT: v_readlane_b32 s16, v47, 49
+; SI-NEXT: s_and_b32 s11, s11, 0xff
+; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v43, 59
-; SI-NEXT: v_readlane_b32 s18, v43, 57
+; SI-NEXT: s_or_b32 s11, s14, s11
+; SI-NEXT: v_readlane_b32 s14, v47, 50
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v43, 58
-; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s18, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v43, 13
+; SI-NEXT: s_addk_i32 s11, 0x300
+; SI-NEXT: s_lshl_b32 s14, s14, 24
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_and_b32 s11, s11, 0xffff
+; SI-NEXT: s_or_b32 s14, s14, s16
+; SI-NEXT: s_or_b32 s11, s14, s11
+; SI-NEXT: s_add_i32 s18, s11, 0x3000000
+; SI-NEXT: v_readlane_b32 s11, v47, 17
+; SI-NEXT: s_add_i32 s11, s11, 3
+; SI-NEXT: v_readlane_b32 s14, v47, 16
+; SI-NEXT: v_readlane_b32 s16, v47, 15
+; SI-NEXT: s_and_b32 s11, s11, 0xff
+; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v43, 12
-; SI-NEXT: v_readlane_b32 s19, v43, 11
+; SI-NEXT: s_or_b32 s11, s14, s11
+; SI-NEXT: v_readlane_b32 s14, v47, 14
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_addk_i32 s11, 0x300
+; SI-NEXT: s_lshl_b32 s14, s14, 24
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_and_b32 s11, s11, 0xffff
+; SI-NEXT: s_or_b32 s14, s14, s16
+; SI-NEXT: s_or_b32 s11, s14, s11
+; SI-NEXT: v_readlane_b32 s14, v47, 21
+; SI-NEXT: s_add_i32 s14, s14, 3
+; SI-NEXT: v_readlane_b32 s16, v47, 20
+; SI-NEXT: v_readlane_b32 s17, v47, 19
+; SI-NEXT: s_and_b32 s14, s14, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 8
+; SI-NEXT: s_add_i32 s17, s17, 3
+; SI-NEXT: s_or_b32 s14, s16, s14
+; SI-NEXT: v_readlane_b32 s16, v47, 18
+; SI-NEXT: s_and_b32 s17, s17, 0xff
+; SI-NEXT: s_addk_i32 s14, 0x300
+; SI-NEXT: s_lshl_b32 s16, s16, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_and_b32 s14, s14, 0xffff
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_or_b32 s14, s16, s14
+; SI-NEXT: s_add_i32 s17, s14, 0x3000000
+; SI-NEXT: v_readlane_b32 s14, v47, 25
+; SI-NEXT: s_add_i32 s14, s14, 3
+; SI-NEXT: v_readlane_b32 s16, v47, 24
+; SI-NEXT: v_readlane_b32 s19, v47, 23
+; SI-NEXT: s_and_b32 s14, s14, 0xff
+; SI-NEXT: s_lshl_b32 s16, s16, 8
; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v43, 10
+; SI-NEXT: s_or_b32 s14, s16, s14
+; SI-NEXT: v_readlane_b32 s16, v47, 22
; SI-NEXT: s_and_b32 s19, s19, 0xff
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
+; SI-NEXT: s_addk_i32 s14, 0x300
+; SI-NEXT: s_lshl_b32 s16, s16, 24
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s19
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s40, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v43, 17
+; SI-NEXT: s_and_b32 s14, s14, 0xffff
+; SI-NEXT: s_or_b32 s16, s16, s19
+; SI-NEXT: s_or_b32 s14, s16, s14
+; SI-NEXT: v_readlane_b32 s16, v47, 29
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v43, 16
-; SI-NEXT: v_readlane_b32 s19, v43, 15
+; SI-NEXT: v_readlane_b32 s19, v47, 28
+; SI-NEXT: v_readlane_b32 s20, v47, 27
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v43, 14
-; SI-NEXT: s_and_b32 s19, s19, 0xff
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s19
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v43, 56
-; SI-NEXT: s_add_i32 s17, s17, 3
-; SI-NEXT: v_readlane_b32 s19, v43, 20
-; SI-NEXT: v_readlane_b32 s21, v43, 19
-; SI-NEXT: s_and_b32 s17, s17, 0xff
; SI-NEXT: s_lshl_b32 s19, s19, 8
-; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: s_or_b32 s17, s19, s17
-; SI-NEXT: v_readlane_b32 s19, v43, 18
-; SI-NEXT: s_and_b32 s21, s21, 0xff
-; SI-NEXT: s_addk_i32 s17, 0x300
-; SI-NEXT: s_lshl_b32 s19, s19, 24
-; SI-NEXT: s_lshl_b32 s21, s21, 16
-; SI-NEXT: s_and_b32 s17, s17, 0xffff
-; SI-NEXT: s_or_b32 s19, s19, s21
-; SI-NEXT: s_or_b32 s17, s19, s17
-; SI-NEXT: s_add_i32 s41, s17, 0x3000000
-; SI-NEXT: v_readlane_b32 s17, v43, 55
-; SI-NEXT: s_add_i32 s17, s17, 3
-; SI-NEXT: v_readlane_b32 s19, v43, 51
-; SI-NEXT: v_readlane_b32 s21, v43, 47
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: s_lshl_b32 s19, s19, 8
-; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: s_or_b32 s17, s19, s17
-; SI-NEXT: v_readlane_b32 s19, v43, 46
-; SI-NEXT: s_and_b32 s21, s21, 0xff
-; SI-NEXT: s_addk_i32 s17, 0x300
+; SI-NEXT: s_add_i32 s20, s20, 3
+; SI-NEXT: s_or_b32 s16, s19, s16
+; SI-NEXT: v_readlane_b32 s19, v47, 26
+; SI-NEXT: s_and_b32 s20, s20, 0xff
+; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s19, s19, 24
-; SI-NEXT: s_lshl_b32 s21, s21, 16
-; SI-NEXT: s_and_b32 s17, s17, 0xffff
-; SI-NEXT: s_or_b32 s19, s19, s21
-; SI-NEXT: s_or_b32 s17, s19, s17
-; SI-NEXT: v_readlane_b32 s19, v43, 54
+; SI-NEXT: s_lshl_b32 s20, s20, 16
+; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s19, s19, s20
+; SI-NEXT: s_or_b32 s16, s19, s16
+; SI-NEXT: v_readlane_b32 s19, v47, 43
; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: v_readlane_b32 s21, v43, 50
-; SI-NEXT: v_readlane_b32 s22, v43, 45
+; SI-NEXT: v_readlane_b32 s20, v47, 41
+; SI-NEXT: v_readlane_b32 s22, v47, 36
; SI-NEXT: s_and_b32 s19, s19, 0xff
-; SI-NEXT: s_lshl_b32 s21, s21, 8
+; SI-NEXT: s_lshl_b32 s20, s20, 8
; SI-NEXT: s_add_i32 s22, s22, 3
-; SI-NEXT: s_or_b32 s19, s21, s19
-; SI-NEXT: v_readlane_b32 s21, v43, 44
+; SI-NEXT: s_or_b32 s19, s20, s19
+; SI-NEXT: v_readlane_b32 s20, v47, 35
; SI-NEXT: s_and_b32 s22, s22, 0xff
; SI-NEXT: s_addk_i32 s19, 0x300
-; SI-NEXT: s_lshl_b32 s21, s21, 24
+; SI-NEXT: s_lshl_b32 s20, s20, 24
; SI-NEXT: s_lshl_b32 s22, s22, 16
; SI-NEXT: s_and_b32 s19, s19, 0xffff
-; SI-NEXT: s_or_b32 s21, s21, s22
-; SI-NEXT: s_or_b32 s19, s21, s19
-; SI-NEXT: s_add_i32 s42, s19, 0x3000000
-; SI-NEXT: v_readlane_b32 s19, v43, 53
+; SI-NEXT: s_or_b32 s20, s20, s22
+; SI-NEXT: s_or_b32 s19, s20, s19
+; SI-NEXT: s_add_i32 s25, s19, 0x3000000
+; SI-NEXT: v_readlane_b32 s19, v47, 44
; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: v_readlane_b32 s21, v43, 49
-; SI-NEXT: v_readlane_b32 s22, v43, 43
+; SI-NEXT: v_readlane_b32 s20, v47, 42
+; SI-NEXT: v_readlane_b32 s22, v47, 38
; SI-NEXT: s_and_b32 s19, s19, 0xff
-; SI-NEXT: s_lshl_b32 s21, s21, 8
+; SI-NEXT: s_lshl_b32 s20, s20, 8
; SI-NEXT: s_add_i32 s22, s22, 3
-; SI-NEXT: s_or_b32 s19, s21, s19
-; SI-NEXT: v_readlane_b32 s21, v43, 42
+; SI-NEXT: s_or_b32 s19, s20, s19
+; SI-NEXT: v_readlane_b32 s20, v47, 37
; SI-NEXT: s_and_b32 s22, s22, 0xff
; SI-NEXT: s_addk_i32 s19, 0x300
-; SI-NEXT: s_lshl_b32 s21, s21, 24
+; SI-NEXT: s_lshl_b32 s20, s20, 24
; SI-NEXT: s_lshl_b32 s22, s22, 16
; SI-NEXT: s_and_b32 s19, s19, 0xffff
-; SI-NEXT: s_or_b32 s21, s21, s22
-; SI-NEXT: s_or_b32 s19, s21, s19
-; SI-NEXT: v_readlane_b32 s21, v43, 52
-; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: v_readlane_b32 s22, v43, 48
-; SI-NEXT: v_readlane_b32 s43, v43, 41
-; SI-NEXT: s_and_b32 s21, s21, 0xff
+; SI-NEXT: s_or_b32 s20, s20, s22
+; SI-NEXT: s_or_b32 s19, s20, s19
+; SI-NEXT: v_readlane_b32 s20, v47, 47
+; SI-NEXT: s_add_i32 s20, s20, 3
+; SI-NEXT: v_readlane_b32 s22, v47, 45
+; SI-NEXT: v_readlane_b32 s26, v47, 40
+; SI-NEXT: s_and_b32 s20, s20, 0xff
; SI-NEXT: s_lshl_b32 s22, s22, 8
-; SI-NEXT: s_add_i32 s43, s43, 3
-; SI-NEXT: s_or_b32 s21, s22, s21
-; SI-NEXT: v_readlane_b32 s22, v43, 40
-; SI-NEXT: s_and_b32 s43, s43, 0xff
-; SI-NEXT: s_addk_i32 s21, 0x300
+; SI-NEXT: s_add_i32 s26, s26, 3
+; SI-NEXT: s_or_b32 s20, s22, s20
+; SI-NEXT: v_readlane_b32 s22, v47, 39
+; SI-NEXT: s_and_b32 s26, s26, 0xff
+; SI-NEXT: s_addk_i32 s20, 0x300
; SI-NEXT: s_lshl_b32 s22, s22, 24
-; SI-NEXT: s_lshl_b32 s43, s43, 16
-; SI-NEXT: s_and_b32 s21, s21, 0xffff
-; SI-NEXT: s_or_b32 s22, s22, s43
-; SI-NEXT: s_or_b32 s21, s22, s21
-; SI-NEXT: s_add_i32 s43, s21, 0x3000000
-; SI-NEXT: v_readlane_b32 s21, v43, 1
-; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: v_readlane_b32 s22, v43, 0
-; SI-NEXT: v_readlane_b32 s44, v43, 39
-; SI-NEXT: s_and_b32 s21, s21, 0xff
+; SI-NEXT: s_lshl_b32 s26, s26, 16
+; SI-NEXT: s_and_b32 s20, s20, 0xffff
+; SI-NEXT: s_or_b32 s22, s22, s26
+; SI-NEXT: s_or_b32 s20, s22, s20
+; SI-NEXT: s_add_i32 s26, s20, 0x3000000
+; SI-NEXT: v_readlane_b32 s20, v47, 1
+; SI-NEXT: s_add_i32 s20, s20, 3
+; SI-NEXT: v_readlane_b32 s22, v47, 0
+; SI-NEXT: v_readlane_b32 s28, v47, 48
+; SI-NEXT: s_and_b32 s20, s20, 0xff
; SI-NEXT: s_lshl_b32 s22, s22, 8
-; SI-NEXT: s_add_i32 s44, s44, 3
-; SI-NEXT: s_or_b32 s21, s22, s21
-; SI-NEXT: v_readlane_b32 s22, v43, 38
-; SI-NEXT: s_and_b32 s44, s44, 0xff
-; SI-NEXT: s_addk_i32 s21, 0x300
+; SI-NEXT: s_add_i32 s28, s28, 3
+; SI-NEXT: s_or_b32 s20, s22, s20
+; SI-NEXT: v_readlane_b32 s22, v47, 46
+; SI-NEXT: s_and_b32 s28, s28, 0xff
+; SI-NEXT: s_addk_i32 s20, 0x300
; SI-NEXT: s_lshl_b32 s22, s22, 24
-; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: s_and_b32 s21, s21, 0xffff
-; SI-NEXT: s_or_b32 s22, s22, s44
-; SI-NEXT: s_or_b32 s21, s22, s21
-; SI-NEXT: s_add_i32 s22, s21, 0x3000000
-; SI-NEXT: v_readlane_b32 s21, v43, 5
-; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: v_readlane_b32 s44, v43, 4
-; SI-NEXT: v_readlane_b32 s45, v43, 3
-; SI-NEXT: s_and_b32 s21, s21, 0xff
-; SI-NEXT: s_lshl_b32 s44, s44, 8
-; SI-NEXT: s_add_i32 s45, s45, 3
-; SI-NEXT: s_or_b32 s21, s44, s21
-; SI-NEXT: v_readlane_b32 s44, v43, 2
-; SI-NEXT: s_and_b32 s45, s45, 0xff
-; SI-NEXT: s_addk_i32 s21, 0x300
-; SI-NEXT: s_lshl_b32 s44, s44, 24
-; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_and_b32 s21, s21, 0xffff
-; SI-NEXT: s_or_b32 s44, s44, s45
-; SI-NEXT: s_or_b32 s21, s44, s21
-; SI-NEXT: s_add_i32 s44, s21, 0x3000000
-; SI-NEXT: v_readlane_b32 s21, v43, 37
-; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: v_readlane_b32 s45, v43, 8
-; SI-NEXT: v_readlane_b32 s46, v43, 7
-; SI-NEXT: s_and_b32 s21, s21, 0xff
-; SI-NEXT: s_lshl_b32 s45, s45, 8
+; SI-NEXT: s_lshl_b32 s28, s28, 16
+; SI-NEXT: s_and_b32 s20, s20, 0xffff
+; SI-NEXT: s_or_b32 s22, s22, s28
+; SI-NEXT: s_or_b32 s20, s22, s20
+; SI-NEXT: s_add_i32 s22, s20, 0x3000000
+; SI-NEXT: v_readlane_b32 s20, v47, 5
+; SI-NEXT: s_add_i32 s20, s20, 3
+; SI-NEXT: v_readlane_b32 s28, v47, 4
+; SI-NEXT: v_readlane_b32 s41, v47, 3
+; SI-NEXT: s_and_b32 s20, s20, 0xff
+; SI-NEXT: s_lshl_b32 s28, s28, 8
+; SI-NEXT: s_add_i32 s41, s41, 3
+; SI-NEXT: s_or_b32 s20, s28, s20
+; SI-NEXT: v_readlane_b32 s28, v47, 2
+; SI-NEXT: s_and_b32 s41, s41, 0xff
+; SI-NEXT: s_addk_i32 s20, 0x300
+; SI-NEXT: s_lshl_b32 s28, s28, 24
+; SI-NEXT: s_lshl_b32 s41, s41, 16
+; SI-NEXT: s_and_b32 s20, s20, 0xffff
+; SI-NEXT: s_or_b32 s28, s28, s41
+; SI-NEXT: s_or_b32 s20, s28, s20
+; SI-NEXT: s_add_i32 s28, s20, 0x3000000
+; SI-NEXT: v_readlane_b32 s20, v47, 9
+; SI-NEXT: s_add_i32 s20, s20, 3
+; SI-NEXT: v_readlane_b32 s41, v47, 8
+; SI-NEXT: v_readlane_b32 s46, v47, 7
+; SI-NEXT: s_and_b32 s20, s20, 0xff
+; SI-NEXT: s_lshl_b32 s41, s41, 8
; SI-NEXT: s_add_i32 s46, s46, 3
-; SI-NEXT: s_or_b32 s21, s45, s21
-; SI-NEXT: v_readlane_b32 s45, v43, 6
+; SI-NEXT: s_or_b32 s20, s41, s20
+; SI-NEXT: v_readlane_b32 s41, v47, 6
; SI-NEXT: s_and_b32 s46, s46, 0xff
-; SI-NEXT: s_addk_i32 s21, 0x300
-; SI-NEXT: s_lshl_b32 s45, s45, 24
+; SI-NEXT: s_addk_i32 s20, 0x300
+; SI-NEXT: s_lshl_b32 s41, s41, 24
; SI-NEXT: s_lshl_b32 s46, s46, 16
-; SI-NEXT: s_and_b32 s21, s21, 0xffff
-; SI-NEXT: s_or_b32 s45, s45, s46
-; SI-NEXT: s_or_b32 s21, s45, s21
-; SI-NEXT: v_readlane_b32 s45, v43, 36
-; SI-NEXT: s_add_i32 s45, s45, 3
-; SI-NEXT: v_readlane_b32 s46, v43, 35
-; SI-NEXT: v_readlane_b32 s47, v43, 33
-; SI-NEXT: s_and_b32 s45, s45, 0xff
+; SI-NEXT: s_and_b32 s20, s20, 0xffff
+; SI-NEXT: s_or_b32 s41, s41, s46
+; SI-NEXT: s_or_b32 s20, s41, s20
+; SI-NEXT: v_readlane_b32 s41, v47, 34
+; SI-NEXT: s_add_i32 s41, s41, 3
+; SI-NEXT: v_readlane_b32 s46, v47, 12
+; SI-NEXT: v_readlane_b32 s47, v47, 11
+; SI-NEXT: s_and_b32 s41, s41, 0xff
; SI-NEXT: s_lshl_b32 s46, s46, 8
; SI-NEXT: s_add_i32 s47, s47, 3
-; SI-NEXT: s_or_b32 s45, s46, s45
-; SI-NEXT: v_readlane_b32 s46, v43, 34
+; SI-NEXT: s_or_b32 s41, s46, s41
+; SI-NEXT: v_readlane_b32 s46, v47, 10
; SI-NEXT: s_and_b32 s47, s47, 0xff
-; SI-NEXT: s_addk_i32 s45, 0x300
+; SI-NEXT: s_addk_i32 s41, 0x300
; SI-NEXT: s_lshl_b32 s46, s46, 24
; SI-NEXT: s_lshl_b32 s47, s47, 16
-; SI-NEXT: s_and_b32 s45, s45, 0xffff
+; SI-NEXT: s_and_b32 s41, s41, 0xffff
; SI-NEXT: s_or_b32 s46, s46, s47
-; SI-NEXT: s_or_b32 s45, s46, s45
-; SI-NEXT: s_add_i32 s23, s23, 0x3000000
-; SI-NEXT: s_add_i32 s24, s24, 0x3000000
-; SI-NEXT: s_add_i32 s7, s7, 0x3000000
-; SI-NEXT: s_add_i32 s25, s25, 0x3000000
-; SI-NEXT: s_add_i32 s26, s26, 0x3000000
-; SI-NEXT: s_add_i32 s45, s45, 0x3000000
+; SI-NEXT: s_or_b32 s41, s46, s41
+; SI-NEXT: s_add_i32 s41, s41, 0x3000000
+; SI-NEXT: s_add_i32 s40, s40, 0x3000000
+; SI-NEXT: s_add_i32 s44, s44, 0x3000000
+; SI-NEXT: s_add_i32 s20, s20, 0x3000000
+; SI-NEXT: s_and_b32 s57, s41, 0xffff0000
+; SI-NEXT: s_lshl_b32 s56, s41, 16
+; SI-NEXT: s_and_b32 s41, s28, 0xffff0000
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
-; SI-NEXT: s_add_i32 s9, s9, 0x3000000
+; SI-NEXT: s_add_i32 s10, s10, 0x3000000
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
-; SI-NEXT: s_add_i32 s20, s20, 0x3000000
+; SI-NEXT: s_add_i32 s23, s23, 0x3000000
+; SI-NEXT: s_add_i32 s24, s24, 0x3000000
; SI-NEXT: s_add_i32 s27, s27, 0x3000000
-; SI-NEXT: s_add_i32 s28, s28, 0x3000000
+; SI-NEXT: s_add_i32 s29, s29, 0x3000000
+; SI-NEXT: s_add_i32 s42, s42, 0x3000000
+; SI-NEXT: s_add_i32 s43, s43, 0x3000000
+; SI-NEXT: s_add_i32 s6, s6, 0x3000000
+; SI-NEXT: s_add_i32 s7, s7, 0x3000000
+; SI-NEXT: s_add_i32 s11, s11, 0x3000000
+; SI-NEXT: s_add_i32 s14, s14, 0x3000000
; SI-NEXT: s_add_i32 s16, s16, 0x3000000
-; SI-NEXT: s_add_i32 s17, s17, 0x3000000
; SI-NEXT: s_add_i32 s19, s19, 0x3000000
-; SI-NEXT: s_add_i32 s21, s21, 0x3000000
-; SI-NEXT: s_and_b32 s58, s45, 0xffff0000
-; SI-NEXT: s_lshl_b32 s38, s45, 16
-; SI-NEXT: s_and_b32 s59, s44, 0xffff0000
-; SI-NEXT: s_lshl_b32 s45, s44, 16
-; SI-NEXT: s_and_b32 s51, s22, 0xffff0000
-; SI-NEXT: s_lshl_b32 s44, s22, 16
-; SI-NEXT: s_and_b32 s53, s40, 0xffff0000
-; SI-NEXT: s_lshl_b32 s55, s40, 16
-; SI-NEXT: s_and_b32 s88, s29, 0xffff0000
-; SI-NEXT: s_lshl_b32 s64, s29, 16
-; SI-NEXT: s_and_b32 s75, s26, 0xffff0000
-; SI-NEXT: s_lshl_b32 s98, s26, 16
-; SI-NEXT: s_and_b32 s26, s25, 0xffff0000
-; SI-NEXT: s_lshl_b32 s22, s25, 16
-; SI-NEXT: s_and_b32 s25, s7, 0xffff0000
-; SI-NEXT: s_and_b32 s29, s24, 0xffff0000
-; SI-NEXT: s_lshl_b32 s24, s24, 16
-; SI-NEXT: s_and_b32 s40, s6, 0xffff0000
-; SI-NEXT: s_and_b32 s46, s23, 0xffff0000
-; SI-NEXT: s_lshl_b32 s23, s23, 16
-; SI-NEXT: s_and_b32 s50, s21, 0xffff0000
-; SI-NEXT: s_lshl_b32 s21, s21, 16
-; SI-NEXT: s_and_b32 s73, s43, 0xffff0000
-; SI-NEXT: s_lshl_b32 s47, s43, 16
-; SI-NEXT: s_and_b32 s74, s19, 0xffff0000
+; SI-NEXT: s_and_b32 s60, s20, 0xffff0000
+; SI-NEXT: s_lshl_b32 s94, s20, 16
+; SI-NEXT: v_writelane_b32 v46, s41, 40
+; SI-NEXT: s_lshl_b32 s28, s28, 16
+; SI-NEXT: s_lshl_b32 s20, s44, 16
+; SI-NEXT: s_and_b32 s66, s40, 0xffff0000
+; SI-NEXT: s_lshl_b32 s40, s40, 16
+; SI-NEXT: v_writelane_b32 v46, s28, 41
+; SI-NEXT: s_and_b32 s28, s22, 0xffff0000
+; SI-NEXT: s_lshl_b32 s22, s22, 16
+; SI-NEXT: s_and_b32 s62, s26, 0xffff0000
+; SI-NEXT: s_lshl_b32 s26, s26, 16
+; SI-NEXT: s_and_b32 s63, s19, 0xffff0000
; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_and_b32 s76, s42, 0xffff0000
-; SI-NEXT: s_lshl_b32 s49, s42, 16
-; SI-NEXT: s_and_b32 s77, s17, 0xffff0000
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_and_b32 s91, s41, 0xffff0000
-; SI-NEXT: s_lshl_b32 s41, s41, 16
-; SI-NEXT: s_and_b32 s48, s16, 0xffff0000
+; SI-NEXT: s_and_b32 s72, s25, 0xffff0000
+; SI-NEXT: s_lshl_b32 s25, s25, 16
+; SI-NEXT: s_and_b32 s78, s16, 0xffff0000
; SI-NEXT: s_lshl_b32 s16, s16, 16
-; SI-NEXT: s_and_b32 s65, s18, 0xffff0000
+; SI-NEXT: s_and_b32 s48, s14, 0xffff0000
+; SI-NEXT: s_lshl_b32 s58, s14, 16
+; SI-NEXT: s_and_b32 s37, s17, 0xffff0000
+; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_and_b32 s14, s11, 0xffff0000
+; SI-NEXT: s_lshl_b32 s50, s11, 16
+; SI-NEXT: s_and_b32 s51, s18, 0xffff0000
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s60, s28, 0xffff0000
-; SI-NEXT: s_lshl_b32 s99, s28, 16
-; SI-NEXT: s_and_b32 s63, s27, 0xffff0000
-; SI-NEXT: s_lshl_b32 s28, s27, 16
+; SI-NEXT: s_and_b32 s39, s45, 0xffff0000
+; SI-NEXT: s_lshl_b32 s91, s45, 16
+; SI-NEXT: s_and_b32 s52, s7, 0xffff0000
; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_and_b32 s53, s44, 0xffff0000
+; SI-NEXT: s_and_b32 s55, s6, 0xffff0000
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_and_b32 s95, s20, 0xffff0000
-; SI-NEXT: s_lshl_b32 s97, s20, 16
-; SI-NEXT: s_and_b32 s54, s15, 0xffff0000
-; SI-NEXT: s_lshl_b32 s52, s15, 16
-; SI-NEXT: s_and_b32 s27, s14, 0xffff0000
-; SI-NEXT: s_lshl_b32 s96, s14, 16
-; SI-NEXT: s_and_b32 s78, s13, 0xffff0000
-; SI-NEXT: s_lshl_b32 s42, s13, 16
-; SI-NEXT: s_mov_b32 s13, s25
-; SI-NEXT: s_and_b32 s67, s12, 0xffff0000
-; SI-NEXT: s_lshl_b32 s87, s12, 16
-; SI-NEXT: s_mov_b32 s12, s40
-; SI-NEXT: s_and_b32 s68, s11, 0xffff0000
-; SI-NEXT: s_lshl_b32 s66, s11, 16
-; SI-NEXT: s_mov_b32 s11, s24
-; SI-NEXT: s_and_b32 s70, s10, 0xffff0000
+; SI-NEXT: s_and_b32 s64, s43, 0xffff0000
+; SI-NEXT: s_lshl_b32 s54, s43, 16
+; SI-NEXT: s_and_b32 s65, s42, 0xffff0000
+; SI-NEXT: s_lshl_b32 s99, s42, 16
+; SI-NEXT: s_and_b32 s68, s29, 0xffff0000
+; SI-NEXT: s_lshl_b32 s98, s29, 16
+; SI-NEXT: s_and_b32 s11, s27, 0xffff0000
+; SI-NEXT: s_lshl_b32 s27, s27, 16
+; SI-NEXT: s_and_b32 s43, s24, 0xffff0000
+; SI-NEXT: s_lshl_b32 s97, s24, 16
+; SI-NEXT: s_and_b32 s42, s23, 0xffff0000
+; SI-NEXT: s_lshl_b32 s44, s23, 16
+; SI-NEXT: s_and_b32 s45, s21, 0xffff0000
+; SI-NEXT: s_lshl_b32 s96, s21, 16
+; SI-NEXT: s_and_b32 s30, s15, 0xffff0000
+; SI-NEXT: s_lshl_b32 s15, s15, 16
+; SI-NEXT: s_and_b32 s67, s13, 0xffff0000
+; SI-NEXT: s_lshl_b32 s87, s13, 16
+; SI-NEXT: s_and_b32 s21, s12, 0xffff0000
+; SI-NEXT: s_lshl_b32 s13, s12, 16
+; SI-NEXT: s_and_b32 s12, s10, 0xffff0000
; SI-NEXT: s_lshl_b32 s86, s10, 16
-; SI-NEXT: s_mov_b32 s14, s23
+; SI-NEXT: s_mov_b32 s10, s20
; SI-NEXT: s_and_b32 s71, s9, 0xffff0000
-; SI-NEXT: s_lshl_b32 s69, s9, 16
-; SI-NEXT: s_mov_b32 s9, s22
+; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_and_b32 s81, s8, 0xffff0000
; SI-NEXT: s_lshl_b32 s85, s8, 16
-; SI-NEXT: s_mov_b32 s8, s29
-; SI-NEXT: s_mov_b32 s29, s46
+; SI-NEXT: s_mov_b32 s8, s40
; SI-NEXT: s_and_b32 s82, s5, 0xffff0000
; SI-NEXT: s_lshl_b32 s80, s5, 16
; SI-NEXT: s_and_b32 s83, s4, 0xffff0000
; SI-NEXT: s_lshl_b32 s84, s4, 16
; SI-NEXT: .LBB89_3: ; %end
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s58
+; SI-NEXT: v_mul_f32_e64 v0, 1.0, s57
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s38
+; SI-NEXT: v_mul_f32_e64 v0, 1.0, s56
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s50
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s59
+; SI-NEXT: v_readlane_b32 s4, v46, 40
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
+; SI-NEXT: v_readlane_b32 s4, v46, 41
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s45
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s51
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s28
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s44
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s22
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s73
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s62
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s47
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s26
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
-; SI-NEXT: v_mul_f32_e64 v5, 1.0, s74
+; SI-NEXT: v_mul_f32_e64 v5, 1.0, s63
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s19
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s76
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s72
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s49
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s25
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s77
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s78
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s17
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s16
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s91
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s48
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s41
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s58
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s48
+; SI-NEXT: v_mul_f32_e64 v9, 1.0, s37
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
-; SI-NEXT: v_mul_f32_e64 v9, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v9, 1.0, s17
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s53
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s14
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s55
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s50
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s65
+; SI-NEXT: v_mul_f32_e64 v11, 1.0, s51
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s18
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s88
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s39
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
-; SI-NEXT: v_mul_f32_e64 v12, 1.0, s64
+; SI-NEXT: v_mul_f32_e64 v12, 1.0, s91
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
-; SI-NEXT: v_mul_f32_e64 v13, 1.0, s60
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s52
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
-; SI-NEXT: v_mul_f32_e64 v13, 1.0, s99
+; SI-NEXT: v_mul_f32_e64 v13, 1.0, s7
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s63
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s53
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s28
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s10
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s75
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s55
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s98
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s6
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s64
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
-; SI-NEXT: v_mul_f32_e64 v16, 1.0, s9
+; SI-NEXT: v_mul_f32_e64 v16, 1.0, s54
; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16
-; SI-NEXT: v_mul_f32_e64 v17, 1.0, s13
+; SI-NEXT: v_mul_f32_e64 v17, 1.0, s65
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; SI-NEXT: v_mul_f32_e64 v17, 1.0, s7
+; SI-NEXT: v_mul_f32_e64 v17, 1.0, s99
; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s8
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s66
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v18
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s11
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s8
; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16
-; SI-NEXT: v_mul_f32_e64 v19, 1.0, s12
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s68
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; SI-NEXT: v_mul_f32_e64 v19, 1.0, s6
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s98
; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16
-; SI-NEXT: v_mul_f32_e64 v20, 1.0, s29
+; SI-NEXT: v_mul_f32_e64 v20, 1.0, s11
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v20
-; SI-NEXT: v_mul_f32_e64 v20, 1.0, s14
+; SI-NEXT: v_mul_f32_e64 v20, 1.0, s27
; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16
-; SI-NEXT: v_mul_f32_e64 v21, 1.0, s95
+; SI-NEXT: v_mul_f32_e64 v21, 1.0, s43
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v21
; SI-NEXT: v_mul_f32_e64 v21, 1.0, s97
; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16
-; SI-NEXT: v_mul_f32_e64 v22, 1.0, s54
+; SI-NEXT: v_mul_f32_e64 v22, 1.0, s42
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v22
-; SI-NEXT: v_mul_f32_e64 v22, 1.0, s52
+; SI-NEXT: v_mul_f32_e64 v22, 1.0, s44
; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v23, 1.0, s45
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; SI-NEXT: v_mul_f32_e64 v23, 1.0, s96
; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16
-; SI-NEXT: v_mul_f32_e64 v24, 1.0, s78
+; SI-NEXT: v_mul_f32_e64 v24, 1.0, s30
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v24
-; SI-NEXT: v_mul_f32_e64 v24, 1.0, s42
+; SI-NEXT: v_mul_f32_e64 v24, 1.0, s15
; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16
; SI-NEXT: v_mul_f32_e64 v25, 1.0, s67
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v25
; SI-NEXT: v_mul_f32_e64 v25, 1.0, s87
; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16
-; SI-NEXT: v_mul_f32_e64 v26, 1.0, s68
+; SI-NEXT: v_mul_f32_e64 v26, 1.0, s21
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v26
-; SI-NEXT: v_mul_f32_e64 v26, 1.0, s66
+; SI-NEXT: v_mul_f32_e64 v26, 1.0, s13
; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16
-; SI-NEXT: v_mul_f32_e64 v27, 1.0, s70
+; SI-NEXT: v_mul_f32_e64 v27, 1.0, s12
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v27
; SI-NEXT: v_mul_f32_e64 v27, 1.0, s86
; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16
; SI-NEXT: v_mul_f32_e64 v28, 1.0, s71
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v28
-; SI-NEXT: v_mul_f32_e64 v28, 1.0, s69
+; SI-NEXT: v_mul_f32_e64 v28, 1.0, s9
; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16
; SI-NEXT: v_mul_f32_e64 v29, 1.0, s81
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v29
@@ -146636,114 +146630,112 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_mul_f32_e64 v31, 1.0, s83
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v31
; SI-NEXT: v_mul_f32_e64 v31, 1.0, s84
-; SI-NEXT: v_readlane_b32 s30, v40, 34
+; SI-NEXT: v_readlane_b32 s30, v45, 34
; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16
-; SI-NEXT: v_readlane_b32 s31, v40, 35
-; SI-NEXT: v_readlane_b32 s99, v40, 33
-; SI-NEXT: v_readlane_b32 s98, v40, 32
-; SI-NEXT: v_readlane_b32 s97, v40, 31
-; SI-NEXT: v_readlane_b32 s96, v40, 30
-; SI-NEXT: v_readlane_b32 s87, v40, 29
-; SI-NEXT: v_readlane_b32 s86, v40, 28
-; SI-NEXT: v_readlane_b32 s85, v40, 27
-; SI-NEXT: v_readlane_b32 s84, v40, 26
-; SI-NEXT: v_readlane_b32 s83, v40, 25
-; SI-NEXT: v_readlane_b32 s82, v40, 24
-; SI-NEXT: v_readlane_b32 s81, v40, 23
-; SI-NEXT: v_readlane_b32 s80, v40, 22
-; SI-NEXT: v_readlane_b32 s71, v40, 21
-; SI-NEXT: v_readlane_b32 s70, v40, 20
-; SI-NEXT: v_readlane_b32 s69, v40, 19
-; SI-NEXT: v_readlane_b32 s68, v40, 18
-; SI-NEXT: v_readlane_b32 s67, v40, 17
-; SI-NEXT: v_readlane_b32 s66, v40, 16
-; SI-NEXT: v_readlane_b32 s65, v40, 15
-; SI-NEXT: v_readlane_b32 s64, v40, 14
-; SI-NEXT: v_readlane_b32 s55, v40, 13
-; SI-NEXT: v_readlane_b32 s54, v40, 12
-; SI-NEXT: v_readlane_b32 s53, v40, 11
-; SI-NEXT: v_readlane_b32 s52, v40, 10
-; SI-NEXT: v_readlane_b32 s51, v40, 9
-; SI-NEXT: v_readlane_b32 s50, v40, 8
-; SI-NEXT: v_readlane_b32 s49, v40, 7
-; SI-NEXT: v_readlane_b32 s48, v40, 6
-; SI-NEXT: v_readlane_b32 s39, v40, 5
-; SI-NEXT: v_readlane_b32 s38, v40, 4
-; SI-NEXT: v_readlane_b32 s37, v40, 3
-; SI-NEXT: v_readlane_b32 s36, v40, 2
-; SI-NEXT: v_readlane_b32 s35, v40, 1
-; SI-NEXT: v_readlane_b32 s34, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v45, 35
+; SI-NEXT: v_readlane_b32 s99, v45, 33
+; SI-NEXT: v_readlane_b32 s98, v45, 32
+; SI-NEXT: v_readlane_b32 s97, v45, 31
+; SI-NEXT: v_readlane_b32 s96, v45, 30
+; SI-NEXT: v_readlane_b32 s87, v45, 29
+; SI-NEXT: v_readlane_b32 s86, v45, 28
+; SI-NEXT: v_readlane_b32 s85, v45, 27
+; SI-NEXT: v_readlane_b32 s84, v45, 26
+; SI-NEXT: v_readlane_b32 s83, v45, 25
+; SI-NEXT: v_readlane_b32 s82, v45, 24
+; SI-NEXT: v_readlane_b32 s81, v45, 23
+; SI-NEXT: v_readlane_b32 s80, v45, 22
+; SI-NEXT: v_readlane_b32 s71, v45, 21
+; SI-NEXT: v_readlane_b32 s70, v45, 20
+; SI-NEXT: v_readlane_b32 s69, v45, 19
+; SI-NEXT: v_readlane_b32 s68, v45, 18
+; SI-NEXT: v_readlane_b32 s67, v45, 17
+; SI-NEXT: v_readlane_b32 s66, v45, 16
+; SI-NEXT: v_readlane_b32 s65, v45, 15
+; SI-NEXT: v_readlane_b32 s64, v45, 14
+; SI-NEXT: v_readlane_b32 s55, v45, 13
+; SI-NEXT: v_readlane_b32 s54, v45, 12
+; SI-NEXT: v_readlane_b32 s53, v45, 11
+; SI-NEXT: v_readlane_b32 s52, v45, 10
+; SI-NEXT: v_readlane_b32 s51, v45, 9
+; SI-NEXT: v_readlane_b32 s50, v45, 8
+; SI-NEXT: v_readlane_b32 s49, v45, 7
+; SI-NEXT: v_readlane_b32 s48, v45, 6
+; SI-NEXT: v_readlane_b32 s39, v45, 5
+; SI-NEXT: v_readlane_b32 s38, v45, 4
+; SI-NEXT: v_readlane_b32 s37, v45, 3
+; SI-NEXT: v_readlane_b32 s36, v45, 2
+; SI-NEXT: v_readlane_b32 s35, v45, 1
+; SI-NEXT: v_readlane_b32 s34, v45, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB89_4:
-; SI-NEXT: s_mov_b32 s39, s22
-; SI-NEXT: s_mov_b32 s57, s90
-; SI-NEXT: s_mov_b32 s30, s93
-; SI-NEXT: s_mov_b32 s90, s92
-; SI-NEXT: s_mov_b32 s15, s58
-; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: s_mov_b32 s49, s76
+; SI-NEXT: s_mov_b32 s73, s92
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr94
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr22
+; SI-NEXT: ; implicit-def: $sgpr28
+; SI-NEXT: ; implicit-def: $sgpr26
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr19
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr25
+; SI-NEXT: ; implicit-def: $sgpr72
+; SI-NEXT: ; implicit-def: $sgpr16
+; SI-NEXT: ; implicit-def: $sgpr78
; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr21
+; SI-NEXT: ; implicit-def: $sgpr48
+; SI-NEXT: ; implicit-def: $sgpr17
+; SI-NEXT: ; implicit-def: $sgpr37
; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; implicit-def: $sgpr45
-; SI-NEXT: ; implicit-def: $sgpr59
-; SI-NEXT: ; implicit-def: $sgpr44
+; SI-NEXT: ; implicit-def: $sgpr14
+; SI-NEXT: ; implicit-def: $sgpr18
; SI-NEXT: ; implicit-def: $sgpr51
-; SI-NEXT: ; implicit-def: $sgpr47
-; SI-NEXT: ; implicit-def: $sgpr73
-; SI-NEXT: ; implicit-def: $sgpr19
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr49
-; SI-NEXT: ; implicit-def: $sgpr76
-; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr77
-; SI-NEXT: ; implicit-def: $sgpr41
; SI-NEXT: ; implicit-def: $sgpr91
-; SI-NEXT: ; implicit-def: $sgpr16
-; SI-NEXT: ; implicit-def: $sgpr48
-; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr39
+; SI-NEXT: ; implicit-def: $sgpr7
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: ; implicit-def: $sgpr10
; SI-NEXT: ; implicit-def: $sgpr53
-; SI-NEXT: ; implicit-def: $sgpr18
-; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; implicit-def: $sgpr64
-; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr99
-; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr28
-; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr8
+; SI-NEXT: ; implicit-def: $sgpr66
; SI-NEXT: ; implicit-def: $sgpr98
-; SI-NEXT: ; implicit-def: $sgpr75
-; SI-NEXT: ; implicit-def: $sgpr9
-; SI-NEXT: ; implicit-def: $sgpr26
-; SI-NEXT: ; implicit-def: $sgpr7
-; SI-NEXT: ; implicit-def: $sgpr13
+; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: ; implicit-def: $sgpr27
; SI-NEXT: ; implicit-def: $sgpr11
-; SI-NEXT: ; implicit-def: $sgpr8
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr12
-; SI-NEXT: ; implicit-def: $sgpr14
-; SI-NEXT: ; implicit-def: $sgpr29
; SI-NEXT: ; implicit-def: $sgpr97
-; SI-NEXT: ; implicit-def: $sgpr95
-; SI-NEXT: ; implicit-def: $sgpr52
-; SI-NEXT: ; implicit-def: $sgpr54
-; SI-NEXT: ; implicit-def: $sgpr96
-; SI-NEXT: ; implicit-def: $sgpr27
+; SI-NEXT: ; implicit-def: $sgpr43
+; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr42
-; SI-NEXT: ; implicit-def: $sgpr78
+; SI-NEXT: ; implicit-def: $sgpr96
+; SI-NEXT: ; implicit-def: $sgpr45
+; SI-NEXT: ; implicit-def: $sgpr15
+; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: ; implicit-def: $sgpr87
; SI-NEXT: ; implicit-def: $sgpr67
-; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: ; implicit-def: $sgpr13
+; SI-NEXT: ; implicit-def: $sgpr21
; SI-NEXT: ; implicit-def: $sgpr86
-; SI-NEXT: ; implicit-def: $sgpr70
-; SI-NEXT: ; implicit-def: $sgpr69
+; SI-NEXT: ; implicit-def: $sgpr12
+; SI-NEXT: ; implicit-def: $sgpr9
; SI-NEXT: ; implicit-def: $sgpr71
; SI-NEXT: ; implicit-def: $sgpr85
; SI-NEXT: ; implicit-def: $sgpr81
@@ -160898,12 +160890,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_readfirstlane_b32 s6, v17
; GFX9-NEXT: v_readfirstlane_b32 s9, v16
; GFX9-NEXT: v_readfirstlane_b32 s8, v15
-; GFX9-NEXT: v_readfirstlane_b32 s13, v14
-; GFX9-NEXT: v_readfirstlane_b32 s12, v13
-; GFX9-NEXT: v_readfirstlane_b32 s11, v12
-; GFX9-NEXT: v_readfirstlane_b32 s10, v11
-; GFX9-NEXT: v_readfirstlane_b32 s15, v10
-; GFX9-NEXT: v_readfirstlane_b32 s14, v9
+; GFX9-NEXT: v_readfirstlane_b32 s11, v14
+; GFX9-NEXT: v_readfirstlane_b32 s10, v13
+; GFX9-NEXT: v_readfirstlane_b32 s15, v12
+; GFX9-NEXT: v_readfirstlane_b32 s14, v11
+; GFX9-NEXT: v_readfirstlane_b32 s13, v10
+; GFX9-NEXT: v_readfirstlane_b32 s12, v9
; GFX9-NEXT: v_readfirstlane_b32 s41, v8
; GFX9-NEXT: v_readfirstlane_b32 s40, v7
; GFX9-NEXT: v_readfirstlane_b32 s43, v6
@@ -160996,9 +160988,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_writelane_b32 v62, s46, 14
; GFX9-NEXT: s_lshr_b32 s46, s16, 8
; GFX9-NEXT: v_writelane_b32 v62, s46, 37
-; GFX9-NEXT: s_lshr_b32 s46, s15, 24
+; GFX9-NEXT: s_lshr_b32 s46, s13, 24
; GFX9-NEXT: v_writelane_b32 v62, s46, 40
-; GFX9-NEXT: s_lshr_b32 s46, s15, 8
+; GFX9-NEXT: s_lshr_b32 s46, s13, 8
; GFX9-NEXT: v_writelane_b32 v62, s46, 41
; GFX9-NEXT: s_lshr_b32 s46, s41, 24
; GFX9-NEXT: v_writelane_b32 v62, s46, 42
@@ -161025,19 +161017,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_lshr_b32 s96, s9, 8
; GFX9-NEXT: s_lshr_b32 s80, s8, 16
; GFX9-NEXT: s_lshr_b32 s48, s8, 8
-; GFX9-NEXT: s_lshr_b32 s85, s13, 24
-; GFX9-NEXT: s_lshr_b32 s66, s13, 16
-; GFX9-NEXT: s_lshr_b32 s39, s13, 8
-; GFX9-NEXT: s_lshr_b32 s71, s12, 16
-; GFX9-NEXT: s_lshr_b32 s98, s12, 8
-; GFX9-NEXT: s_lshr_b32 s82, s11, 24
-; GFX9-NEXT: s_lshr_b32 s65, s11, 16
-; GFX9-NEXT: s_lshr_b32 s84, s11, 8
-; GFX9-NEXT: s_lshr_b32 s70, s10, 16
-; GFX9-NEXT: s_lshr_b32 s87, s10, 8
-; GFX9-NEXT: s_lshr_b32 s64, s15, 16
-; GFX9-NEXT: s_lshr_b32 s69, s14, 16
-; GFX9-NEXT: s_lshr_b32 s38, s14, 8
+; GFX9-NEXT: s_lshr_b32 s85, s11, 24
+; GFX9-NEXT: s_lshr_b32 s66, s11, 16
+; GFX9-NEXT: s_lshr_b32 s39, s11, 8
+; GFX9-NEXT: s_lshr_b32 s71, s10, 16
+; GFX9-NEXT: s_lshr_b32 s98, s10, 8
+; GFX9-NEXT: s_lshr_b32 s82, s15, 24
+; GFX9-NEXT: s_lshr_b32 s65, s15, 16
+; GFX9-NEXT: s_lshr_b32 s84, s15, 8
+; GFX9-NEXT: s_lshr_b32 s70, s14, 16
+; GFX9-NEXT: s_lshr_b32 s87, s14, 8
+; GFX9-NEXT: s_lshr_b32 s64, s13, 16
+; GFX9-NEXT: s_lshr_b32 s69, s12, 16
+; GFX9-NEXT: s_lshr_b32 s38, s12, 8
; GFX9-NEXT: s_lshr_b32 s54, s41, 16
; GFX9-NEXT: s_lshr_b32 s55, s40, 16
; GFX9-NEXT: s_lshr_b32 s83, s40, 8
@@ -161056,9 +161048,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_lshr_b64 s[76:77], s[16:17], 24
; GFX9-NEXT: s_lshr_b64 s[78:79], s[6:7], 24
; GFX9-NEXT: s_lshr_b64 s[88:89], s[8:9], 24
-; GFX9-NEXT: s_lshr_b64 s[90:91], s[12:13], 24
-; GFX9-NEXT: s_lshr_b64 s[92:93], s[10:11], 24
-; GFX9-NEXT: s_lshr_b64 s[94:95], s[14:15], 24
+; GFX9-NEXT: s_lshr_b64 s[90:91], s[10:11], 24
+; GFX9-NEXT: s_lshr_b64 s[92:93], s[14:15], 24
+; GFX9-NEXT: s_lshr_b64 s[94:95], s[12:13], 24
; GFX9-NEXT: s_lshr_b64 s[30:31], s[40:41], 24
; GFX9-NEXT: s_lshr_b64 s[34:35], s[42:43], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[44:45], 24
@@ -161171,14 +161163,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX9-NEXT: s_and_b32 s41, s40, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v5
; GFX9-NEXT: v_add_f32_e32 v5, s41, v13
; GFX9-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX9-NEXT: v_add_u32_e32 v7, v7, v5
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_add_u32_e32 v7, 0x7fff, v7
; GFX9-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
@@ -161191,7 +161183,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_add_u32_e32 v7, 0x7fff, v7
; GFX9-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
-; GFX9-NEXT: s_and_b32 s40, s15, 0xffff0000
+; GFX9-NEXT: s_and_b32 s40, s13, 0xffff0000
; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc
; GFX9-NEXT: v_add_f32_e32 v7, s40, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -161205,9 +161197,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: s_lshl_b32 s15, s15, 16
+; GFX9-NEXT: s_lshl_b32 s13, s13, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s15, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s13, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
@@ -161215,21 +161207,21 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX9-NEXT: s_and_b32 s15, s14, 0xffff0000
+; GFX9-NEXT: s_and_b32 s13, s12, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v11, v10, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s15, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s13, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: s_lshl_b32 s14, s14, 16
-; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: s_lshl_b32 s12, s12, 16
+; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s14, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s12, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
@@ -161237,21 +161229,21 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX9-NEXT: s_and_b32 s14, s11, 0xffff0000
+; GFX9-NEXT: s_and_b32 s12, s15, 0xffff0000
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshl_or_b32 v10, v10, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s14, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s12, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: s_lshl_b32 s11, s11, 16
+; GFX9-NEXT: s_lshl_b32 s12, s15, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s11, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s12, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
@@ -161259,21 +161251,21 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX9-NEXT: s_and_b32 s11, s10, 0xffff0000
+; GFX9-NEXT: s_and_b32 s12, s14, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v17, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s11, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s12, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: s_lshl_b32 s10, s10, 16
+; GFX9-NEXT: s_lshl_b32 s12, s14, 16
; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s12, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
@@ -161281,21 +161273,21 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX9-NEXT: s_and_b32 s10, s13, 0xffff0000
+; GFX9-NEXT: s_and_b32 s12, s11, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v16, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s12, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: s_lshl_b32 s10, s13, 16
+; GFX9-NEXT: s_lshl_b32 s11, s11, 16
; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s11, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
@@ -161303,18 +161295,18 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX9-NEXT: s_and_b32 s10, s12, 0xffff0000
+; GFX9-NEXT: s_and_b32 s11, s10, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v19, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s11, v13
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: s_lshl_b32 s10, s12, 16
+; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
@@ -161325,7 +161317,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: s_and_b32 s10, s9, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v18, v12, 16, v7
@@ -161347,7 +161339,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: s_and_b32 s9, s8, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v23, v12, 16, v7
@@ -162033,30 +162025,30 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: v_mov_b32_e32 v13, s4
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s12
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s10
; GFX9-NEXT: v_readlane_b32 s4, v62, 0
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s13
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s11
; GFX9-NEXT: v_mov_b32_e32 v59, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 1
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s10
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s14
; GFX9-NEXT: v_mov_b32_e32 v58, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 2
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s11
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s15
; GFX9-NEXT: v_mov_b32_e32 v14, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 3
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s14
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s12
; GFX9-NEXT: v_mov_b32_e32 v56, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 4
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s15
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s13
; GFX9-NEXT: v_mov_b32_e32 v57, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 5
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 6
; GFX9-NEXT: v_mov_b32_e32 v12, s4
@@ -162157,15 +162149,15 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_mov_b32_e32 v1, s69
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s64
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s40
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s41
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s54
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s42
; GFX9-NEXT: v_readlane_b32 s4, v62, 33
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
@@ -162470,9 +162462,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:80
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -162480,7 +162472,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:84
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
@@ -162491,9 +162483,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:88
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v1, v1, v11, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -162501,7 +162493,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:92
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
@@ -162512,7 +162504,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:96
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -162522,7 +162514,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:100
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -162537,7 +162529,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
@@ -162556,7 +162548,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -171866,778 +171858,809 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_writelane_b32 v40, s34, 0
-; SI-NEXT: v_writelane_b32 v40, s35, 1
-; SI-NEXT: v_writelane_b32 v40, s36, 2
-; SI-NEXT: v_writelane_b32 v40, s37, 3
-; SI-NEXT: v_writelane_b32 v40, s38, 4
-; SI-NEXT: v_writelane_b32 v40, s39, 5
-; SI-NEXT: v_writelane_b32 v40, s48, 6
-; SI-NEXT: v_writelane_b32 v40, s49, 7
-; SI-NEXT: v_writelane_b32 v40, s50, 8
-; SI-NEXT: v_writelane_b32 v40, s51, 9
-; SI-NEXT: v_writelane_b32 v40, s52, 10
-; SI-NEXT: v_writelane_b32 v40, s53, 11
-; SI-NEXT: v_writelane_b32 v40, s54, 12
-; SI-NEXT: v_writelane_b32 v40, s55, 13
-; SI-NEXT: v_writelane_b32 v40, s64, 14
-; SI-NEXT: v_writelane_b32 v40, s65, 15
-; SI-NEXT: v_writelane_b32 v40, s66, 16
-; SI-NEXT: v_writelane_b32 v40, s67, 17
-; SI-NEXT: v_writelane_b32 v40, s68, 18
-; SI-NEXT: v_writelane_b32 v40, s69, 19
-; SI-NEXT: v_writelane_b32 v40, s70, 20
-; SI-NEXT: v_writelane_b32 v40, s71, 21
-; SI-NEXT: v_writelane_b32 v40, s80, 22
-; SI-NEXT: v_writelane_b32 v40, s81, 23
-; SI-NEXT: v_writelane_b32 v40, s82, 24
-; SI-NEXT: v_writelane_b32 v40, s83, 25
-; SI-NEXT: v_writelane_b32 v40, s84, 26
-; SI-NEXT: v_writelane_b32 v40, s85, 27
-; SI-NEXT: v_writelane_b32 v40, s86, 28
-; SI-NEXT: v_writelane_b32 v40, s87, 29
-; SI-NEXT: v_writelane_b32 v40, s96, 30
-; SI-NEXT: v_writelane_b32 v40, s97, 31
-; SI-NEXT: v_writelane_b32 v40, s98, 32
-; SI-NEXT: v_writelane_b32 v40, s99, 33
-; SI-NEXT: v_writelane_b32 v40, s30, 34
-; SI-NEXT: v_writelane_b32 v40, s31, 35
-; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_writelane_b32 v45, s34, 0
+; SI-NEXT: v_writelane_b32 v45, s35, 1
+; SI-NEXT: v_writelane_b32 v45, s36, 2
+; SI-NEXT: v_writelane_b32 v45, s37, 3
+; SI-NEXT: v_writelane_b32 v45, s38, 4
+; SI-NEXT: v_writelane_b32 v45, s39, 5
+; SI-NEXT: v_writelane_b32 v45, s48, 6
+; SI-NEXT: v_writelane_b32 v45, s49, 7
+; SI-NEXT: v_writelane_b32 v45, s50, 8
+; SI-NEXT: v_writelane_b32 v45, s51, 9
+; SI-NEXT: v_writelane_b32 v45, s52, 10
+; SI-NEXT: v_writelane_b32 v45, s53, 11
+; SI-NEXT: v_writelane_b32 v45, s54, 12
+; SI-NEXT: v_writelane_b32 v45, s55, 13
+; SI-NEXT: v_writelane_b32 v45, s64, 14
+; SI-NEXT: v_writelane_b32 v45, s65, 15
+; SI-NEXT: v_writelane_b32 v45, s66, 16
+; SI-NEXT: v_writelane_b32 v45, s67, 17
+; SI-NEXT: v_writelane_b32 v45, s68, 18
+; SI-NEXT: v_writelane_b32 v45, s69, 19
+; SI-NEXT: v_writelane_b32 v45, s70, 20
+; SI-NEXT: v_writelane_b32 v45, s71, 21
+; SI-NEXT: v_writelane_b32 v45, s80, 22
+; SI-NEXT: v_writelane_b32 v45, s81, 23
+; SI-NEXT: v_writelane_b32 v45, s82, 24
+; SI-NEXT: v_writelane_b32 v45, s83, 25
+; SI-NEXT: v_writelane_b32 v45, s84, 26
+; SI-NEXT: v_writelane_b32 v45, s85, 27
+; SI-NEXT: v_writelane_b32 v45, s86, 28
+; SI-NEXT: v_writelane_b32 v45, s87, 29
+; SI-NEXT: v_writelane_b32 v45, s96, 30
+; SI-NEXT: v_writelane_b32 v45, s97, 31
+; SI-NEXT: v_writelane_b32 v45, s98, 32
+; SI-NEXT: v_writelane_b32 v45, s99, 33
+; SI-NEXT: v_writelane_b32 v45, s30, 34
+; SI-NEXT: v_writelane_b32 v45, s31, 35
+; SI-NEXT: ; implicit-def: $vgpr47 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s4, v30
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v42, s29, 0
-; SI-NEXT: v_writelane_b32 v42, s28, 1
-; SI-NEXT: v_writelane_b32 v42, s27, 2
-; SI-NEXT: v_writelane_b32 v42, s26, 3
-; SI-NEXT: v_writelane_b32 v42, s25, 4
-; SI-NEXT: v_writelane_b32 v42, s24, 5
-; SI-NEXT: v_writelane_b32 v42, s23, 6
-; SI-NEXT: v_writelane_b32 v42, s22, 7
-; SI-NEXT: v_writelane_b32 v42, s21, 8
-; SI-NEXT: v_writelane_b32 v42, s20, 9
-; SI-NEXT: v_writelane_b32 v42, s19, 10
-; SI-NEXT: v_writelane_b32 v42, s18, 11
-; SI-NEXT: v_writelane_b32 v42, s17, 12
-; SI-NEXT: v_writelane_b32 v42, s16, 13
-; SI-NEXT: v_writelane_b32 v42, s4, 14
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_writelane_b32 v47, s29, 0
+; SI-NEXT: v_writelane_b32 v47, s28, 1
+; SI-NEXT: v_writelane_b32 v47, s27, 2
+; SI-NEXT: v_writelane_b32 v47, s26, 3
+; SI-NEXT: v_writelane_b32 v47, s25, 4
+; SI-NEXT: v_writelane_b32 v47, s24, 5
+; SI-NEXT: v_writelane_b32 v47, s23, 6
+; SI-NEXT: v_writelane_b32 v47, s22, 7
+; SI-NEXT: v_writelane_b32 v47, s21, 8
+; SI-NEXT: v_writelane_b32 v47, s20, 9
+; SI-NEXT: v_writelane_b32 v47, s19, 10
+; SI-NEXT: v_writelane_b32 v47, s18, 11
+; SI-NEXT: v_writelane_b32 v47, s17, 12
+; SI-NEXT: v_writelane_b32 v47, s16, 13
+; SI-NEXT: v_writelane_b32 v47, s4, 14
; SI-NEXT: v_readfirstlane_b32 s4, v29
-; SI-NEXT: v_writelane_b32 v42, s4, 15
+; SI-NEXT: v_writelane_b32 v47, s4, 15
; SI-NEXT: v_readfirstlane_b32 s4, v28
-; SI-NEXT: v_writelane_b32 v42, s4, 16
+; SI-NEXT: v_writelane_b32 v47, s4, 16
; SI-NEXT: v_readfirstlane_b32 s4, v27
-; SI-NEXT: v_writelane_b32 v42, s4, 17
+; SI-NEXT: v_writelane_b32 v47, s4, 17
; SI-NEXT: v_readfirstlane_b32 s4, v26
-; SI-NEXT: v_writelane_b32 v42, s4, 18
+; SI-NEXT: v_writelane_b32 v47, s4, 18
; SI-NEXT: v_readfirstlane_b32 s4, v25
-; SI-NEXT: v_writelane_b32 v42, s4, 19
+; SI-NEXT: v_writelane_b32 v47, s4, 19
; SI-NEXT: v_readfirstlane_b32 s4, v24
-; SI-NEXT: v_writelane_b32 v42, s4, 20
+; SI-NEXT: v_writelane_b32 v47, s4, 20
; SI-NEXT: v_readfirstlane_b32 s4, v23
-; SI-NEXT: v_writelane_b32 v42, s4, 21
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:332
+; SI-NEXT: v_writelane_b32 v47, s4, 21
; SI-NEXT: v_readfirstlane_b32 s4, v22
-; SI-NEXT: v_writelane_b32 v42, s4, 22
+; SI-NEXT: v_writelane_b32 v47, s4, 22
; SI-NEXT: v_readfirstlane_b32 s4, v21
-; SI-NEXT: v_writelane_b32 v42, s4, 23
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:324
+; SI-NEXT: v_writelane_b32 v47, s4, 23
; SI-NEXT: v_readfirstlane_b32 s4, v20
-; SI-NEXT: v_writelane_b32 v42, s4, 24
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:320
+; SI-NEXT: v_writelane_b32 v47, s4, 24
; SI-NEXT: v_readfirstlane_b32 s4, v19
-; SI-NEXT: v_writelane_b32 v42, s4, 25
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:316
+; SI-NEXT: v_writelane_b32 v47, s4, 25
+; SI-NEXT: v_readfirstlane_b32 s4, v18
+; SI-NEXT: v_writelane_b32 v47, s4, 26
; SI-NEXT: v_readfirstlane_b32 s4, v17
-; SI-NEXT: v_writelane_b32 v42, s4, 26
+; SI-NEXT: v_writelane_b32 v47, s4, 27
; SI-NEXT: v_readfirstlane_b32 s4, v16
-; SI-NEXT: v_readfirstlane_b32 s70, v18
-; SI-NEXT: v_writelane_b32 v42, s4, 27
+; SI-NEXT: v_writelane_b32 v47, s4, 28
; SI-NEXT: v_readfirstlane_b32 s4, v15
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:232
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:324
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:316
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:304
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:300
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:296
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:292
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:284
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:280
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:276
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:268
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:264
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:260
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:252
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:248
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:244
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:332
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:236
-; SI-NEXT: v_writelane_b32 v42, s4, 28
+; SI-NEXT: v_writelane_b32 v47, s4, 29
; SI-NEXT: v_readfirstlane_b32 s4, v14
-; SI-NEXT: v_writelane_b32 v42, s4, 29
+; SI-NEXT: v_writelane_b32 v47, s4, 30
; SI-NEXT: v_readfirstlane_b32 s4, v13
-; SI-NEXT: v_writelane_b32 v42, s4, 30
+; SI-NEXT: v_writelane_b32 v47, s4, 31
; SI-NEXT: v_readfirstlane_b32 s4, v12
-; SI-NEXT: v_readfirstlane_b32 s81, v11
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:204
-; SI-NEXT: v_writelane_b32 v42, s4, 31
+; SI-NEXT: v_writelane_b32 v47, s4, 32
+; SI-NEXT: v_readfirstlane_b32 s4, v11
+; SI-NEXT: v_writelane_b32 v47, s4, 33
+; SI-NEXT: v_readfirstlane_b32 s4, v10
+; SI-NEXT: v_writelane_b32 v47, s4, 34
; SI-NEXT: v_readfirstlane_b32 s4, v9
-; SI-NEXT: v_writelane_b32 v42, s4, 32
+; SI-NEXT: v_writelane_b32 v47, s4, 35
; SI-NEXT: v_readfirstlane_b32 s4, v8
-; SI-NEXT: v_readfirstlane_b32 s78, v10
-; SI-NEXT: v_writelane_b32 v42, s4, 33
+; SI-NEXT: v_writelane_b32 v47, s4, 36
; SI-NEXT: v_readfirstlane_b32 s4, v7
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:196
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:188
-; SI-NEXT: v_writelane_b32 v42, s4, 34
+; SI-NEXT: v_writelane_b32 v47, s4, 37
; SI-NEXT: v_readfirstlane_b32 s4, v6
-; SI-NEXT: v_writelane_b32 v42, s4, 35
+; SI-NEXT: v_writelane_b32 v47, s4, 38
; SI-NEXT: v_readfirstlane_b32 s4, v5
-; SI-NEXT: v_writelane_b32 v42, s4, 36
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:300
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:292
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:288
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:284
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:276
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:264
+; SI-NEXT: v_writelane_b32 v47, s4, 39
; SI-NEXT: v_readfirstlane_b32 s4, v4
-; SI-NEXT: v_writelane_b32 v42, s4, 37
+; SI-NEXT: v_writelane_b32 v47, s4, 40
+; SI-NEXT: v_readfirstlane_b32 s4, v3
+; SI-NEXT: v_writelane_b32 v47, s4, 41
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268
+; SI-NEXT: v_readfirstlane_b32 s69, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260
+; SI-NEXT: ; implicit-def: $vgpr46 : SGPR spill to VGPR lane
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s4, v1
-; SI-NEXT: v_readfirstlane_b32 s37, v2
-; SI-NEXT: v_writelane_b32 v42, s4, 38
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:248
+; SI-NEXT: v_writelane_b32 v47, s4, 42
; SI-NEXT: v_readfirstlane_b32 s4, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176
-; SI-NEXT: v_writelane_b32 v42, s4, 39
-; SI-NEXT: v_readfirstlane_b32 s35, v3
-; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:244
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240
+; SI-NEXT: v_readfirstlane_b32 s83, v21
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:236
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:232
+; SI-NEXT: v_readfirstlane_b32 s86, v22
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:228
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:224
+; SI-NEXT: v_readfirstlane_b32 s99, v20
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:220
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:216
+; SI-NEXT: v_readfirstlane_b32 s17, v19
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208
+; SI-NEXT: v_writelane_b32 v47, s4, 43
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s97, v19
-; SI-NEXT: v_readfirstlane_b32 s58, v20
-; SI-NEXT: v_readfirstlane_b32 s59, v21
-; SI-NEXT: v_readfirstlane_b32 s28, v22
-; SI-NEXT: v_readfirstlane_b32 s21, v23
-; SI-NEXT: v_readfirstlane_b32 s60, v24
-; SI-NEXT: v_readfirstlane_b32 s75, v25
-; SI-NEXT: v_readfirstlane_b32 s79, v26
-; SI-NEXT: v_readfirstlane_b32 s96, v27
-; SI-NEXT: v_readfirstlane_b32 s4, v28
-; SI-NEXT: v_writelane_b32 v42, s4, 40
-; SI-NEXT: v_readfirstlane_b32 s46, v29
-; SI-NEXT: v_readfirstlane_b32 s57, v31
-; SI-NEXT: v_readfirstlane_b32 s56, v32
-; SI-NEXT: v_readfirstlane_b32 s74, v33
-; SI-NEXT: v_readfirstlane_b32 s26, v34
-; SI-NEXT: v_readfirstlane_b32 s47, v30
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:168
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:156
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:148
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:136
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:124
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:116
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:112
-; SI-NEXT: v_readfirstlane_b32 s88, v35
-; SI-NEXT: v_readfirstlane_b32 s16, v36
-; SI-NEXT: v_readfirstlane_b32 s4, v39
-; SI-NEXT: v_writelane_b32 v42, s4, 41
-; SI-NEXT: v_readfirstlane_b32 s4, v48
-; SI-NEXT: v_writelane_b32 v42, s4, 42
-; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_readfirstlane_b32 s83, v17
-; SI-NEXT: v_readfirstlane_b32 s22, v16
-; SI-NEXT: v_readfirstlane_b32 s69, v15
+; SI-NEXT: v_readfirstlane_b32 s66, v14
+; SI-NEXT: v_readfirstlane_b32 s84, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192
+; SI-NEXT: v_readfirstlane_b32 s8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:188
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:184
+; SI-NEXT: v_readfirstlane_b32 s9, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:176
+; SI-NEXT: v_readfirstlane_b32 s16, v10
+; SI-NEXT: v_readfirstlane_b32 s46, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:136
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:168
+; SI-NEXT: v_readfirstlane_b32 s24, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:156
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:152
+; SI-NEXT: v_readfirstlane_b32 s29, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:144
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:200
+; SI-NEXT: v_readfirstlane_b32 s10, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:120
+; SI-NEXT: v_readfirstlane_b32 s13, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:112
+; SI-NEXT: v_readfirstlane_b32 s19, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:160
+; SI-NEXT: v_readfirstlane_b32 s47, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:128
+; SI-NEXT: v_readfirstlane_b32 s27, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80
-; SI-NEXT: v_readfirstlane_b32 s27, v37
-; SI-NEXT: v_readfirstlane_b32 s85, v38
-; SI-NEXT: v_writelane_b32 v42, s4, 43
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:104
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s4, v14
-; SI-NEXT: v_readfirstlane_b32 s44, v13
-; SI-NEXT: v_readfirstlane_b32 s40, v12
-; SI-NEXT: v_readfirstlane_b32 s42, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v49
-; SI-NEXT: v_readfirstlane_b32 s15, v50
-; SI-NEXT: v_writelane_b32 v42, s4, 44
-; SI-NEXT: v_readfirstlane_b32 s86, v10
-; SI-NEXT: v_readfirstlane_b32 s87, v9
-; SI-NEXT: v_readfirstlane_b32 s25, v8
-; SI-NEXT: v_readfirstlane_b32 s4, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:16
-; SI-NEXT: v_readfirstlane_b32 s23, v51
-; SI-NEXT: v_writelane_b32 v42, s4, 45
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s82, v1
-; SI-NEXT: v_readfirstlane_b32 s45, v0
-; SI-NEXT: v_readfirstlane_b32 s41, v2
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: v_readfirstlane_b32 s63, v3
-; SI-NEXT: v_readfirstlane_b32 s67, v4
-; SI-NEXT: v_readfirstlane_b32 s66, v5
-; SI-NEXT: v_readfirstlane_b32 s17, v6
-; SI-NEXT: v_readfirstlane_b32 s24, v19
-; SI-NEXT: v_readfirstlane_b32 s4, v20
-; SI-NEXT: v_writelane_b32 v42, s4, 46
-; SI-NEXT: v_readfirstlane_b32 s13, v22
-; SI-NEXT: v_readfirstlane_b32 s14, v23
-; SI-NEXT: v_readfirstlane_b32 s51, v24
+; SI-NEXT: v_readfirstlane_b32 s28, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:96
+; SI-NEXT: v_readfirstlane_b32 s54, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:88
+; SI-NEXT: v_readfirstlane_b32 s59, v17
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:72
+; SI-NEXT: v_readfirstlane_b32 s61, v18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:64
+; SI-NEXT: v_readfirstlane_b32 s44, v1
+; SI-NEXT: v_readfirstlane_b32 s52, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:40
+; SI-NEXT: v_readfirstlane_b32 s53, v24
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:32
+; SI-NEXT: v_readfirstlane_b32 s45, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24
+; SI-NEXT: v_readfirstlane_b32 s60, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:8
+; SI-NEXT: v_readfirstlane_b32 s62, v29
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:80
+; SI-NEXT: v_readfirstlane_b32 s14, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:56
+; SI-NEXT: v_readfirstlane_b32 s15, v23
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
+; SI-NEXT: v_readfirstlane_b32 s56, v25
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16
+; SI-NEXT: v_writelane_b32 v46, s54, 0
+; SI-NEXT: v_writelane_b32 v46, s53, 1
+; SI-NEXT: v_readfirstlane_b32 s40, v19
+; SI-NEXT: v_readfirstlane_b32 s50, v13
+; SI-NEXT: v_readfirstlane_b32 s64, v27
+; SI-NEXT: v_readfirstlane_b32 s85, v12
+; SI-NEXT: v_readfirstlane_b32 s58, v28
+; SI-NEXT: v_readfirstlane_b32 s57, v11
+; SI-NEXT: v_readfirstlane_b32 s11, v30
+; SI-NEXT: v_readfirstlane_b32 s7, v6
+; SI-NEXT: v_writelane_b32 v46, s7, 2
+; SI-NEXT: v_writelane_b32 v46, s64, 3
+; SI-NEXT: v_writelane_b32 v46, s44, 4
+; SI-NEXT: v_writelane_b32 v46, s85, 5
+; SI-NEXT: v_writelane_b32 v46, s8, 6
+; SI-NEXT: v_writelane_b32 v46, s45, 7
+; SI-NEXT: v_writelane_b32 v46, s46, 8
+; SI-NEXT: v_writelane_b32 v46, s47, 9
+; SI-NEXT: v_writelane_b32 v46, s56, 10
+; SI-NEXT: v_writelane_b32 v46, s9, 11
+; SI-NEXT: v_writelane_b32 v46, s57, 12
+; SI-NEXT: v_writelane_b32 v46, s58, 13
+; SI-NEXT: v_writelane_b32 v46, s10, 14
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s50, v25
-; SI-NEXT: v_readfirstlane_b32 s52, v26
-; SI-NEXT: v_readfirstlane_b32 s53, v27
-; SI-NEXT: v_readfirstlane_b32 s64, v28
-; SI-NEXT: v_readfirstlane_b32 s54, v29
-; SI-NEXT: v_readfirstlane_b32 s4, v21
-; SI-NEXT: v_writelane_b32 v42, s4, 47
-; SI-NEXT: v_readfirstlane_b32 s18, v30
-; SI-NEXT: v_readfirstlane_b32 s12, v15
-; SI-NEXT: v_readfirstlane_b32 s36, v16
-; SI-NEXT: v_readfirstlane_b32 s34, v17
-; SI-NEXT: v_readfirstlane_b32 s38, v18
-; SI-NEXT: v_readfirstlane_b32 s39, v31
-; SI-NEXT: v_readfirstlane_b32 s49, v32
+; SI-NEXT: v_readfirstlane_b32 s92, v3
+; SI-NEXT: v_writelane_b32 v46, s11, 15
+; SI-NEXT: v_readfirstlane_b32 s12, v10
+; SI-NEXT: v_readfirstlane_b32 s30, v37
+; SI-NEXT: v_writelane_b32 v46, s59, 16
+; SI-NEXT: v_readfirstlane_b32 s36, v7
+; SI-NEXT: v_writelane_b32 v46, s12, 17
; SI-NEXT: v_readfirstlane_b32 s48, v33
-; SI-NEXT: v_writelane_b32 v41, s48, 0
-; SI-NEXT: v_readfirstlane_b32 s10, v34
-; SI-NEXT: v_writelane_b32 v41, s49, 1
-; SI-NEXT: v_writelane_b32 v41, s10, 2
-; SI-NEXT: v_writelane_b32 v41, s50, 3
-; SI-NEXT: v_readfirstlane_b32 s11, v11
-; SI-NEXT: v_writelane_b32 v41, s51, 4
-; SI-NEXT: v_writelane_b32 v41, s11, 5
-; SI-NEXT: v_writelane_b32 v41, s52, 6
-; SI-NEXT: v_writelane_b32 v41, s53, 7
-; SI-NEXT: v_writelane_b32 v41, s54, 8
-; SI-NEXT: v_writelane_b32 v41, s64, 9
-; SI-NEXT: v_writelane_b32 v41, s66, 10
-; SI-NEXT: v_writelane_b32 v41, s67, 11
-; SI-NEXT: v_writelane_b32 v41, s83, 12
-; SI-NEXT: v_writelane_b32 v41, s86, 13
-; SI-NEXT: v_writelane_b32 v41, s12, 14
-; SI-NEXT: v_writelane_b32 v41, s87, 15
-; SI-NEXT: v_writelane_b32 v41, s13, 16
-; SI-NEXT: v_writelane_b32 v41, s14, 17
-; SI-NEXT: v_writelane_b32 v41, s85, 18
-; SI-NEXT: v_writelane_b32 v41, s15, 19
-; SI-NEXT: v_writelane_b32 v41, s44, 20
+; SI-NEXT: v_writelane_b32 v46, s60, 18
+; SI-NEXT: v_writelane_b32 v46, s61, 19
+; SI-NEXT: v_writelane_b32 v46, s13, 20
+; SI-NEXT: v_writelane_b32 v46, s62, 21
+; SI-NEXT: v_readfirstlane_b32 s6, v34
+; SI-NEXT: v_writelane_b32 v46, s14, 22
+; SI-NEXT: v_writelane_b32 v46, s15, 23
+; SI-NEXT: v_readfirstlane_b32 s41, v14
+; SI-NEXT: v_readfirstlane_b32 s51, v26
+; SI-NEXT: v_readfirstlane_b32 s87, v31
+; SI-NEXT: v_readfirstlane_b32 s23, v9
+; SI-NEXT: v_readfirstlane_b32 s25, v32
+; SI-NEXT: v_readfirstlane_b32 s26, v8
+; SI-NEXT: v_readfirstlane_b32 s4, v51
+; SI-NEXT: v_writelane_b32 v47, s4, 44
+; SI-NEXT: v_readfirstlane_b32 s4, v18
+; SI-NEXT: v_writelane_b32 v47, s4, 45
+; SI-NEXT: v_readfirstlane_b32 s4, v52
+; SI-NEXT: v_writelane_b32 v47, s4, 46
+; SI-NEXT: v_readfirstlane_b32 s4, v55
+; SI-NEXT: v_writelane_b32 v47, s4, 47
+; SI-NEXT: v_readfirstlane_b32 s4, v24
+; SI-NEXT: v_writelane_b32 v47, s4, 48
+; SI-NEXT: v_readfirstlane_b32 s4, v40
+; SI-NEXT: v_writelane_b32 v47, s4, 49
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_readfirstlane_b32 s4, v41
+; SI-NEXT: v_writelane_b32 v47, s4, 50
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_readfirstlane_b32 s4, v43
+; SI-NEXT: v_writelane_b32 v47, s4, 51
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_readfirstlane_b32 s4, v29
+; SI-NEXT: v_writelane_b32 v47, s4, 52
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_readfirstlane_b32 s4, v44
+; SI-NEXT: v_writelane_b32 v47, s4, 53
+; SI-NEXT: v_writelane_b32 v47, s92, 54
+; SI-NEXT: v_writelane_b32 v47, s30, 55
+; SI-NEXT: v_writelane_b32 v47, s36, 56
+; SI-NEXT: v_writelane_b32 v47, s48, 57
+; SI-NEXT: v_writelane_b32 v47, s66, 58
+; SI-NEXT: v_writelane_b32 v47, s52, 59
+; SI-NEXT: v_writelane_b32 v47, s84, 60
+; SI-NEXT: v_writelane_b32 v47, s6, 61
+; SI-NEXT: v_readfirstlane_b32 s67, v35
+; SI-NEXT: v_readfirstlane_b32 s94, v5
+; SI-NEXT: v_readfirstlane_b32 s65, v36
+; SI-NEXT: v_readfirstlane_b32 s22, v4
+; SI-NEXT: v_readfirstlane_b32 s18, v38
+; SI-NEXT: v_readfirstlane_b32 s20, v15
+; SI-NEXT: v_readfirstlane_b32 s35, v39
+; SI-NEXT: v_readfirstlane_b32 s31, v2
+; SI-NEXT: v_readfirstlane_b32 s78, v48
+; SI-NEXT: v_readfirstlane_b32 s98, v16
+; SI-NEXT: v_readfirstlane_b32 s97, v49
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_readfirstlane_b32 s55, v1
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_readfirstlane_b32 s81, v50
+; SI-NEXT: v_readfirstlane_b32 s71, v17
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_readfirstlane_b32 s19, v49
-; SI-NEXT: v_writelane_b32 v41, s82, 21
-; SI-NEXT: v_readfirstlane_b32 s20, v48
-; SI-NEXT: v_writelane_b32 v42, s19, 48
-; SI-NEXT: v_writelane_b32 v41, s23, 22
-; SI-NEXT: v_readfirstlane_b32 s76, v13
-; SI-NEXT: v_writelane_b32 v42, s20, 49
-; SI-NEXT: v_writelane_b32 v41, s45, 23
-; SI-NEXT: v_readfirstlane_b32 s77, v12
-; SI-NEXT: v_writelane_b32 v42, s76, 50
-; SI-NEXT: v_writelane_b32 v41, s46, 24
+; SI-NEXT: v_readfirstlane_b32 s96, v0
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_readfirstlane_b32 s6, v50
-; SI-NEXT: v_writelane_b32 v42, s77, 51
-; SI-NEXT: v_writelane_b32 v41, s47, 25
+; SI-NEXT: v_readfirstlane_b32 s79, v53
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_readfirstlane_b32 s7, v0
-; SI-NEXT: v_writelane_b32 v42, s6, 52
-; SI-NEXT: v_writelane_b32 v41, s40, 26
-; SI-NEXT: v_readfirstlane_b32 s43, v14
-; SI-NEXT: v_writelane_b32 v42, s7, 53
-; SI-NEXT: v_writelane_b32 v41, s41, 27
-; SI-NEXT: v_readfirstlane_b32 vcc_lo, v35
-; SI-NEXT: v_writelane_b32 v42, s43, 54
-; SI-NEXT: v_writelane_b32 v41, s42, 28
-; SI-NEXT: v_readfirstlane_b32 vcc_hi, v37
-; SI-NEXT: v_writelane_b32 v42, vcc_lo, 55
-; SI-NEXT: v_writelane_b32 v41, s56, 29
-; SI-NEXT: v_readfirstlane_b32 s30, v36
-; SI-NEXT: v_writelane_b32 v42, vcc_hi, 56
-; SI-NEXT: v_writelane_b32 v41, s57, 30
-; SI-NEXT: v_writelane_b32 v42, s30, 57
-; SI-NEXT: v_writelane_b32 v41, s63, 31
-; SI-NEXT: v_writelane_b32 v42, s34, 58
-; SI-NEXT: v_writelane_b32 v41, s74, 32
-; SI-NEXT: v_readfirstlane_b32 s8, v38
-; SI-NEXT: v_writelane_b32 v42, s36, 59
-; SI-NEXT: v_writelane_b32 v41, s26, 33
-; SI-NEXT: v_readfirstlane_b32 s9, v7
-; SI-NEXT: v_writelane_b32 v42, s8, 60
-; SI-NEXT: v_writelane_b32 v41, s75, 34
-; SI-NEXT: v_writelane_b32 v42, s9, 61
-; SI-NEXT: v_writelane_b32 v41, s79, 35
-; SI-NEXT: v_readfirstlane_b32 s80, v8
-; SI-NEXT: v_readfirstlane_b32 s98, v9
-; SI-NEXT: v_readfirstlane_b32 s55, v10
-; SI-NEXT: v_readfirstlane_b32 s99, v39
+; SI-NEXT: v_readfirstlane_b32 s90, v23
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_readfirstlane_b32 s65, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_readfirstlane_b32 s71, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s84, v51
-; SI-NEXT: v_writelane_b32 v42, s38, 62
-; SI-NEXT: v_writelane_b32 v41, s58, 36
-; SI-NEXT: v_writelane_b32 v42, s39, 63
-; SI-NEXT: v_writelane_b32 v41, s28, 37
+; SI-NEXT: v_readfirstlane_b32 s37, v54
+; SI-NEXT: v_readfirstlane_b32 s82, v21
+; SI-NEXT: v_readfirstlane_b32 s80, v22
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_readfirstlane_b32 s70, v25
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_readfirstlane_b32 s76, v42
+; SI-NEXT: v_readfirstlane_b32 s21, v20
+; SI-NEXT: v_writelane_b32 v47, s50, 62
+; SI-NEXT: v_writelane_b32 v46, s40, 24
+; SI-NEXT: v_writelane_b32 v47, s51, 63
+; SI-NEXT: v_writelane_b32 v46, s41, 25
; SI-NEXT: s_cbranch_scc0 .LBB93_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_readlane_b32 s4, v42, 13
-; SI-NEXT: v_readlane_b32 s5, v42, 12
+; SI-NEXT: v_readlane_b32 s4, v47, 13
+; SI-NEXT: v_readlane_b32 s5, v47, 12
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 38
-; SI-NEXT: v_readlane_b32 s4, v42, 5
-; SI-NEXT: v_readlane_b32 s5, v42, 4
+; SI-NEXT: v_writelane_b32 v46, s4, 26
+; SI-NEXT: v_readlane_b32 s4, v47, 5
+; SI-NEXT: v_readlane_b32 s5, v47, 4
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 40
-; SI-NEXT: s_and_b32 s4, s37, 0xff
-; SI-NEXT: s_lshl_b32 s5, s35, 8
+; SI-NEXT: v_readlane_b32 s5, v47, 41
+; SI-NEXT: v_writelane_b32 v46, s4, 28
+; SI-NEXT: s_and_b32 s4, s69, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 8
+; SI-NEXT: v_writelane_b32 v46, s69, 44
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 42
-; SI-NEXT: v_writelane_b32 v41, s27, 46
-; SI-NEXT: s_and_b32 s4, s78, 0xff
-; SI-NEXT: s_lshl_b32 s5, s81, 8
-; SI-NEXT: v_writelane_b32 v41, s96, 47
+; SI-NEXT: v_writelane_b32 v46, s4, 30
+; SI-NEXT: v_readlane_b32 s4, v47, 34
+; SI-NEXT: v_readlane_b32 s5, v47, 33
+; SI-NEXT: s_and_b32 s4, s4, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_readlane_b32 s5, v42, 25
-; SI-NEXT: v_writelane_b32 v41, s4, 44
-; SI-NEXT: s_and_b32 s4, s70, 0xff
+; SI-NEXT: v_writelane_b32 v46, s4, 32
+; SI-NEXT: v_readlane_b32 s4, v47, 26
+; SI-NEXT: v_readlane_b32 s5, v47, 25
+; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 48
-; SI-NEXT: v_readlane_b32 s4, v42, 18
-; SI-NEXT: v_readlane_b32 s5, v42, 17
+; SI-NEXT: v_writelane_b32 v46, s4, 34
+; SI-NEXT: v_readlane_b32 s4, v47, 18
+; SI-NEXT: v_readlane_b32 s5, v47, 17
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 49
-; SI-NEXT: s_and_b32 s4, s7, 0xff
-; SI-NEXT: s_lshl_b32 s5, s6, 8
+; SI-NEXT: v_writelane_b32 v46, s4, 36
+; SI-NEXT: s_and_b32 s4, s21, 0xff
+; SI-NEXT: s_lshl_b32 s5, s76, 8
+; SI-NEXT: v_writelane_b32 v46, s24, 45
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 50
-; SI-NEXT: s_and_b32 s4, s9, 0xff
-; SI-NEXT: s_lshl_b32 s5, s8, 8
+; SI-NEXT: v_writelane_b32 v46, s4, 38
+; SI-NEXT: s_and_b32 s4, s82, 0xff
+; SI-NEXT: s_lshl_b32 s5, s37, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 51
-; SI-NEXT: s_and_b32 s4, s11, 0xff
-; SI-NEXT: s_lshl_b32 s5, s10, 8
+; SI-NEXT: v_writelane_b32 v46, s4, 40
+; SI-NEXT: s_and_b32 s4, s71, 0xff
+; SI-NEXT: s_lshl_b32 s5, s81, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 52
-; SI-NEXT: s_and_b32 s4, s12, 0xff
+; SI-NEXT: v_writelane_b32 v46, s4, 42
+; SI-NEXT: s_and_b32 s4, s20, 0xff
; SI-NEXT: s_lshl_b32 s5, s18, 8
-; SI-NEXT: s_or_b32 s61, s4, s5
-; SI-NEXT: s_and_b32 s4, s14, 0xff
-; SI-NEXT: s_lshl_b32 s5, s13, 8
-; SI-NEXT: s_or_b32 s62, s4, s5
-; SI-NEXT: s_and_b32 s4, s63, 0xff
-; SI-NEXT: s_lshl_b32 s5, s41, 8
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_writelane_b32 v46, s4, 46
+; SI-NEXT: s_and_b32 s4, s7, 0xff
+; SI-NEXT: s_lshl_b32 s5, s6, 8
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_writelane_b32 v46, s4, 47
+; SI-NEXT: s_and_b32 s4, s12, 0xff
+; SI-NEXT: s_lshl_b32 s5, s11, 8
; SI-NEXT: s_or_b32 s63, s4, s5
-; SI-NEXT: s_and_b32 s4, s42, 0xff
+; SI-NEXT: s_and_b32 s4, s41, 0xff
; SI-NEXT: s_lshl_b32 s5, s40, 8
; SI-NEXT: s_or_b32 s72, s4, s5
-; SI-NEXT: s_and_b32 s4, s23, 0xff
-; SI-NEXT: s_lshl_b32 s5, s15, 8
+; SI-NEXT: s_and_b32 s4, s15, 0xff
+; SI-NEXT: s_lshl_b32 s5, s14, 8
; SI-NEXT: s_or_b32 s73, s4, s5
-; SI-NEXT: s_and_b32 s4, s26, 0xff
-; SI-NEXT: s_lshl_b32 s5, s74, 8
+; SI-NEXT: s_and_b32 s4, s13, 0xff
+; SI-NEXT: s_lshl_b32 s5, s10, 8
; SI-NEXT: s_or_b32 s74, s4, s5
-; SI-NEXT: s_and_b32 s4, s79, 0xff
-; SI-NEXT: s_lshl_b32 s5, s75, 8
+; SI-NEXT: s_and_b32 s4, s9, 0xff
+; SI-NEXT: s_lshl_b32 s5, s8, 8
; SI-NEXT: s_or_b32 s75, s4, s5
-; SI-NEXT: v_readlane_b32 s4, v42, 9
-; SI-NEXT: v_readlane_b32 s5, v42, 8
+; SI-NEXT: v_readlane_b32 s4, v47, 9
+; SI-NEXT: v_readlane_b32 s5, v47, 8
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s5, s4, s5
-; SI-NEXT: v_readlane_b32 s4, v42, 7
+; SI-NEXT: v_readlane_b32 s4, v47, 7
; SI-NEXT: s_and_b32 s4, s4, 0xff
-; SI-NEXT: v_readlane_b32 s6, v42, 6
+; SI-NEXT: v_readlane_b32 s6, v47, 6
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s6, s6, 24
-; SI-NEXT: s_or_b32 s79, s6, s4
-; SI-NEXT: v_readlane_b32 s4, v42, 11
+; SI-NEXT: s_or_b32 s68, s6, s4
+; SI-NEXT: v_readlane_b32 s4, v47, 11
; SI-NEXT: s_and_b32 s4, s4, 0xff
-; SI-NEXT: v_readlane_b32 s6, v42, 10
+; SI-NEXT: v_readlane_b32 s6, v47, 10
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s6, s6, 24
; SI-NEXT: s_or_b32 s4, s6, s4
-; SI-NEXT: v_readlane_b32 s6, v42, 1
-; SI-NEXT: v_readlane_b32 s7, v42, 0
+; SI-NEXT: v_readlane_b32 s6, v47, 1
+; SI-NEXT: v_readlane_b32 s7, v47, 0
; SI-NEXT: s_and_b32 s6, s6, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_or_b32 s7, s6, s7
-; SI-NEXT: v_readlane_b32 s6, v42, 39
+; SI-NEXT: v_readlane_b32 s6, v47, 43
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s8, v42, 38
+; SI-NEXT: v_readlane_b32 s8, v47, 42
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s8, s8, 24
-; SI-NEXT: s_or_b32 s89, s8, s6
-; SI-NEXT: v_readlane_b32 s6, v42, 3
+; SI-NEXT: s_or_b32 s91, s8, s6
+; SI-NEXT: v_readlane_b32 s6, v47, 3
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s8, v42, 2
+; SI-NEXT: v_readlane_b32 s8, v47, 2
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s8, s8, 24
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: v_readlane_b32 s8, v42, 35
-; SI-NEXT: v_readlane_b32 s9, v42, 34
+; SI-NEXT: v_readlane_b32 s8, v47, 38
+; SI-NEXT: v_readlane_b32 s9, v47, 37
; SI-NEXT: s_and_b32 s8, s8, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 8
; SI-NEXT: s_or_b32 s9, s8, s9
-; SI-NEXT: v_readlane_b32 s8, v42, 33
+; SI-NEXT: v_readlane_b32 s8, v47, 36
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s10, v42, 32
+; SI-NEXT: v_readlane_b32 s10, v47, 35
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_lshl_b32 s10, s10, 24
-; SI-NEXT: s_or_b32 s23, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v42, 37
+; SI-NEXT: s_or_b32 s88, s10, s8
+; SI-NEXT: v_readlane_b32 s8, v47, 40
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s10, v42, 36
+; SI-NEXT: v_readlane_b32 s10, v47, 39
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_lshl_b32 s10, s10, 24
; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v42, 29
-; SI-NEXT: v_readlane_b32 s11, v42, 28
+; SI-NEXT: v_readlane_b32 s10, v47, 30
+; SI-NEXT: v_readlane_b32 s11, v47, 29
; SI-NEXT: s_and_b32 s10, s10, 0xff
; SI-NEXT: s_lshl_b32 s11, s11, 8
; SI-NEXT: s_or_b32 s11, s10, s11
-; SI-NEXT: v_readlane_b32 s10, v42, 27
+; SI-NEXT: v_readlane_b32 s10, v47, 28
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s12, v42, 26
+; SI-NEXT: v_readlane_b32 s12, v47, 27
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_lshl_b32 s12, s12, 24
-; SI-NEXT: s_or_b32 s93, s12, s10
-; SI-NEXT: v_readlane_b32 s10, v42, 31
+; SI-NEXT: s_or_b32 s95, s12, s10
+; SI-NEXT: v_readlane_b32 s10, v47, 32
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s12, v42, 30
+; SI-NEXT: v_readlane_b32 s12, v47, 31
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_lshl_b32 s12, s12, 24
; SI-NEXT: s_or_b32 s10, s12, s10
-; SI-NEXT: v_readlane_b32 s12, v42, 22
-; SI-NEXT: v_readlane_b32 s13, v42, 21
+; SI-NEXT: v_readlane_b32 s12, v47, 22
+; SI-NEXT: v_readlane_b32 s13, v47, 21
; SI-NEXT: s_and_b32 s12, s12, 0xff
; SI-NEXT: s_lshl_b32 s13, s13, 8
; SI-NEXT: s_or_b32 s13, s12, s13
-; SI-NEXT: v_readlane_b32 s12, v42, 20
+; SI-NEXT: v_readlane_b32 s12, v47, 20
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s14, v42, 19
+; SI-NEXT: v_readlane_b32 s14, v47, 19
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_lshl_b32 s14, s14, 24
-; SI-NEXT: s_or_b32 s95, s14, s12
-; SI-NEXT: v_readlane_b32 s12, v42, 24
+; SI-NEXT: s_or_b32 s89, s14, s12
+; SI-NEXT: v_readlane_b32 s12, v47, 24
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s14, v42, 23
+; SI-NEXT: v_readlane_b32 s14, v47, 23
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_lshl_b32 s14, s14, 24
; SI-NEXT: s_or_b32 s12, s14, s12
-; SI-NEXT: v_readlane_b32 s14, v42, 14
+; SI-NEXT: v_readlane_b32 s14, v47, 14
+; SI-NEXT: v_readlane_b32 s15, v47, 53
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: s_lshl_b32 s15, s84, 8
+; SI-NEXT: s_lshl_b32 s15, s15, 8
+; SI-NEXT: v_writelane_b32 v46, s71, 48
; SI-NEXT: s_or_b32 s15, s14, s15
-; SI-NEXT: s_and_b32 s14, s71, 0xff
-; SI-NEXT: v_writelane_b32 v41, s18, 53
+; SI-NEXT: v_readlane_b32 s14, v47, 52
+; SI-NEXT: s_and_b32 s14, s14, 0xff
+; SI-NEXT: v_writelane_b32 v46, s16, 49
+; SI-NEXT: v_readlane_b32 s16, v47, 51
; SI-NEXT: s_lshl_b32 s14, s14, 16
-; SI-NEXT: s_mov_b32 s68, s17
-; SI-NEXT: s_lshl_b32 s17, s65, 24
-; SI-NEXT: v_writelane_b32 v41, s88, 54
-; SI-NEXT: s_or_b32 s91, s17, s14
-; SI-NEXT: v_readlane_b32 s14, v42, 16
+; SI-NEXT: v_writelane_b32 v46, s18, 50
+; SI-NEXT: s_lshl_b32 s18, s16, 24
+; SI-NEXT: s_or_b32 s93, s18, s14
+; SI-NEXT: v_readlane_b32 s14, v47, 16
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_writelane_b32 v41, s69, 55
-; SI-NEXT: s_mov_b32 s69, s25
-; SI-NEXT: s_mov_b32 s25, s22
-; SI-NEXT: s_mov_b32 s22, s24
-; SI-NEXT: s_mov_b32 s24, s16
-; SI-NEXT: v_readlane_b32 s16, v42, 15
+; SI-NEXT: v_readlane_b32 s16, v47, 15
; SI-NEXT: s_lshl_b32 s14, s14, 16
-; SI-NEXT: s_lshl_b32 s17, s16, 24
-; SI-NEXT: s_or_b32 s14, s17, s14
-; SI-NEXT: s_and_b32 s17, s99, 0xff
-; SI-NEXT: s_lshl_b32 s40, s55, 8
-; SI-NEXT: s_or_b32 s41, s17, s40
-; SI-NEXT: s_and_b32 s17, s98, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s40, s80, 24
-; SI-NEXT: s_or_b32 s88, s40, s17
-; SI-NEXT: s_and_b32 s40, s19, 0xff
+; SI-NEXT: s_lshl_b32 s18, s16, 24
+; SI-NEXT: v_readlane_b32 s16, v47, 49
+; SI-NEXT: s_or_b32 s14, s18, s14
+; SI-NEXT: s_and_b32 s18, s80, 0xff
+; SI-NEXT: s_lshl_b32 s40, s16, 8
+; SI-NEXT: v_readlane_b32 s16, v47, 48
+; SI-NEXT: s_or_b32 s41, s18, s40
+; SI-NEXT: s_and_b32 s18, s16, 0xff
+; SI-NEXT: v_readlane_b32 s16, v47, 47
+; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_lshl_b32 s40, s16, 24
+; SI-NEXT: s_mov_b32 s24, s21
+; SI-NEXT: s_or_b32 s21, s40, s18
+; SI-NEXT: s_and_b32 s40, s70, 0xff
+; SI-NEXT: v_readlane_b32 s18, v47, 50
; SI-NEXT: s_lshl_b32 s40, s40, 16
-; SI-NEXT: s_lshl_b32 s42, s20, 24
+; SI-NEXT: s_lshl_b32 s42, s18, 24
+; SI-NEXT: v_readlane_b32 s18, v47, 46
; SI-NEXT: s_or_b32 s40, s42, s40
-; SI-NEXT: s_and_b32 s42, vcc_lo, 0xff
-; SI-NEXT: s_lshl_b32 s43, s43, 8
+; SI-NEXT: s_and_b32 s42, s96, 0xff
+; SI-NEXT: s_lshl_b32 s43, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v47, 45
; SI-NEXT: s_or_b32 s43, s42, s43
-; SI-NEXT: s_and_b32 s42, s76, 0xff
+; SI-NEXT: s_and_b32 s42, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v47, 44
+; SI-NEXT: s_mov_b32 s34, s76
; SI-NEXT: s_lshl_b32 s42, s42, 16
-; SI-NEXT: s_lshl_b32 s76, s77, 24
-; SI-NEXT: s_or_b32 s19, s76, s42
-; SI-NEXT: s_and_b32 s42, vcc_hi, 0xff
+; SI-NEXT: s_lshl_b32 s76, s18, 24
+; SI-NEXT: s_or_b32 s69, s76, s42
+; SI-NEXT: s_and_b32 s42, s90, 0xff
; SI-NEXT: s_lshl_b32 s42, s42, 16
-; SI-NEXT: s_lshl_b32 s76, s30, 24
+; SI-NEXT: s_lshl_b32 s76, s79, 24
; SI-NEXT: s_or_b32 s42, s76, s42
-; SI-NEXT: s_and_b32 s76, s39, 0xff
-; SI-NEXT: s_lshl_b32 s77, s38, 8
+; SI-NEXT: s_and_b32 s76, s98, 0xff
+; SI-NEXT: s_lshl_b32 s77, s78, 8
+; SI-NEXT: v_writelane_b32 v46, s20, 51
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s34, 0xff
-; SI-NEXT: s_mov_b32 s27, s78
+; SI-NEXT: s_and_b32 s77, s31, 0xff
+; SI-NEXT: v_writelane_b32 v46, s78, 52
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s36, 24
-; SI-NEXT: s_mov_b32 s29, s70
+; SI-NEXT: s_lshl_b32 s78, s35, 24
+; SI-NEXT: s_mov_b32 s16, s70
; SI-NEXT: s_or_b32 s70, s78, s77
-; SI-NEXT: s_and_b32 s77, s48, 0xff
+; SI-NEXT: s_and_b32 s77, s55, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s49, 24
+; SI-NEXT: s_lshl_b32 s78, s97, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
; SI-NEXT: s_or_b32 vcc_lo, s78, s77
; SI-NEXT: s_or_b32 vcc_hi, s76, s70
-; SI-NEXT: s_and_b32 s76, s53, 0xff
-; SI-NEXT: s_lshl_b32 s77, s52, 8
+; SI-NEXT: s_and_b32 s76, s22, 0xff
+; SI-NEXT: s_lshl_b32 s77, s65, 8
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s50, 0xff
+; SI-NEXT: s_and_b32 s77, s94, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s51, 24
-; SI-NEXT: v_writelane_b32 v41, s65, 56
-; SI-NEXT: v_writelane_b32 v41, s71, 57
+; SI-NEXT: s_lshl_b32 s78, s67, 24
; SI-NEXT: s_or_b32 s71, s78, s77
-; SI-NEXT: s_and_b32 s77, s54, 0xff
-; SI-NEXT: v_writelane_b32 v41, s29, 58
+; SI-NEXT: s_and_b32 s77, s92, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s64, 24
+; SI-NEXT: s_lshl_b32 s78, s30, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s27, 59
; SI-NEXT: s_or_b32 s38, s78, s77
; SI-NEXT: s_or_b32 s39, s76, s71
-; SI-NEXT: s_and_b32 s76, s22, 0xff
-; SI-NEXT: s_lshl_b32 s77, s68, 8
+; SI-NEXT: s_and_b32 s76, s26, 0xff
+; SI-NEXT: s_lshl_b32 s77, s25, 8
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s66, 0xff
-; SI-NEXT: v_writelane_b32 v41, s99, 60
+; SI-NEXT: s_and_b32 s77, s23, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s67, 24
-; SI-NEXT: v_writelane_b32 v41, s55, 61
-; SI-NEXT: v_readlane_b32 s16, v42, 47
-; SI-NEXT: v_writelane_b32 v41, s80, 62
+; SI-NEXT: s_lshl_b32 s78, s87, 24
+; SI-NEXT: v_writelane_b32 v46, s80, 53
; SI-NEXT: s_or_b32 s80, s78, s77
-; SI-NEXT: s_and_b32 s77, s16, 0xff
-; SI-NEXT: v_readlane_b32 s16, v42, 46
+; SI-NEXT: s_and_b32 s77, s36, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_lshl_b32 s78, s48, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_readlane_b32 s16, v42, 45
; SI-NEXT: s_or_b32 s48, s78, s77
; SI-NEXT: s_or_b32 s49, s76, s80
-; SI-NEXT: s_and_b32 s76, s16, 0xff
-; SI-NEXT: s_lshl_b32 s77, s69, 8
+; SI-NEXT: s_and_b32 s76, s85, 0xff
+; SI-NEXT: s_lshl_b32 s77, s64, 8
+; SI-NEXT: v_writelane_b32 v46, s98, 54
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s87, 0xff
+; SI-NEXT: s_and_b32 s77, s50, 0xff
+; SI-NEXT: v_writelane_b32 v46, s24, 55
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s86, 24
-; SI-NEXT: s_mov_b32 s92, s81
-; SI-NEXT: v_writelane_b32 v41, s98, 63
+; SI-NEXT: s_lshl_b32 s78, s51, 24
+; SI-NEXT: v_writelane_b32 v46, s34, 56
+; SI-NEXT: v_writelane_b32 v46, s81, 57
; SI-NEXT: s_or_b32 s81, s78, s77
-; SI-NEXT: s_and_b32 s77, s45, 0xff
+; SI-NEXT: s_and_b32 s77, s57, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s82, 24
+; SI-NEXT: s_lshl_b32 s78, s58, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_readlane_b32 s16, v41, 55
; SI-NEXT: s_or_b32 s50, s78, s77
; SI-NEXT: s_or_b32 s51, s76, s81
-; SI-NEXT: s_and_b32 s76, s16, 0xff
-; SI-NEXT: s_lshl_b32 s77, s25, 8
+; SI-NEXT: s_and_b32 s76, s56, 0xff
+; SI-NEXT: s_lshl_b32 s77, s45, 8
+; SI-NEXT: v_writelane_b32 v46, s22, 58
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s83, 0xff
-; SI-NEXT: v_readlane_b32 s16, v42, 43
+; SI-NEXT: s_and_b32 s77, s53, 0xff
+; SI-NEXT: v_writelane_b32 v46, s65, 59
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_lshl_b32 s78, s52, 24
+; SI-NEXT: v_writelane_b32 v46, s67, 60
+; SI-NEXT: v_writelane_b32 v46, s94, 61
+; SI-NEXT: s_mov_b32 s94, s82
; SI-NEXT: s_or_b32 s82, s78, s77
-; SI-NEXT: s_and_b32 s77, s44, 0xff
-; SI-NEXT: v_readlane_b32 s16, v42, 44
+; SI-NEXT: s_and_b32 s77, s62, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_lshl_b32 s78, s60, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_readlane_b32 s16, v41, 46
; SI-NEXT: s_or_b32 s52, s78, s77
; SI-NEXT: s_or_b32 s53, s76, s82
-; SI-NEXT: s_and_b32 s76, s85, 0xff
-; SI-NEXT: s_lshl_b32 s77, s16, 8
+; SI-NEXT: s_and_b32 s76, s44, 0xff
+; SI-NEXT: s_lshl_b32 s77, s54, 8
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s24, 0xff
-; SI-NEXT: v_readlane_b32 s16, v41, 54
+; SI-NEXT: s_and_b32 s77, s28, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
-; SI-NEXT: v_readlane_b32 s16, v42, 42
-; SI-NEXT: s_mov_b32 s18, s84
-; SI-NEXT: s_or_b32 s84, s78, s77
-; SI-NEXT: s_and_b32 s77, s16, 0xff
-; SI-NEXT: v_readlane_b32 s16, v42, 41
+; SI-NEXT: s_lshl_b32 s78, s27, 24
+; SI-NEXT: v_writelane_b32 v46, s97, 62
+; SI-NEXT: s_mov_b32 s92, s28
+; SI-NEXT: s_mov_b32 s28, s27
+; SI-NEXT: s_mov_b32 s27, s26
+; SI-NEXT: s_mov_b32 s26, s25
+; SI-NEXT: s_mov_b32 s25, s87
+; SI-NEXT: s_or_b32 s87, s78, s77
+; SI-NEXT: s_and_b32 s77, s61, 0xff
+; SI-NEXT: s_mov_b32 s24, s23
+; SI-NEXT: s_mov_b32 s23, s16
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_lshl_b32 s78, s59, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
+; SI-NEXT: v_readlane_b32 s16, v46, 45
+; SI-NEXT: s_mov_b32 s85, s55
; SI-NEXT: s_or_b32 s54, s78, s77
-; SI-NEXT: s_or_b32 s55, s76, s84
-; SI-NEXT: s_and_b32 s76, s47, 0xff
-; SI-NEXT: s_lshl_b32 s77, s46, 8
-; SI-NEXT: v_readlane_b32 s16, v42, 40
+; SI-NEXT: s_or_b32 s55, s76, s87
+; SI-NEXT: s_and_b32 s76, s29, 0xff
+; SI-NEXT: s_lshl_b32 s77, s16, 8
+; SI-NEXT: v_readlane_b32 s18, v46, 26
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s16, 0xff
-; SI-NEXT: v_readlane_b32 s16, v41, 47
-; SI-NEXT: s_lshl_b32 s78, s16, 24
-; SI-NEXT: s_mov_b32 s16, s18
-; SI-NEXT: v_readlane_b32 s18, v41, 38
-; SI-NEXT: s_lshl_b32 s77, s77, 16
+; SI-NEXT: s_and_b32 s77, s19, 0xff
+; SI-NEXT: v_readlane_b32 s16, v46, 49
; SI-NEXT: s_and_b32 s44, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 40
-; SI-NEXT: s_or_b32 s85, s78, s77
-; SI-NEXT: s_and_b32 s77, s56, 0xff
-; SI-NEXT: s_and_b32 s45, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 42
+; SI-NEXT: v_readlane_b32 s18, v46, 28
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s57, 24
-; SI-NEXT: s_and_b32 s76, s76, 0xffff
+; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_and_b32 s45, s18, 0xffff
+; SI-NEXT: v_readlane_b32 s18, v46, 30
+; SI-NEXT: s_mov_b32 s20, s19
+; SI-NEXT: s_mov_b32 s19, s37
+; SI-NEXT: s_mov_b32 s37, s35
+; SI-NEXT: s_mov_b32 s35, s31
+; SI-NEXT: s_mov_b32 s31, s79
+; SI-NEXT: s_mov_b32 s79, s90
+; SI-NEXT: s_mov_b32 s90, s96
+; SI-NEXT: s_or_b32 s96, s78, s77
+; SI-NEXT: s_lshl_b32 s78, s46, 24
; SI-NEXT: s_and_b32 s46, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 44
-; SI-NEXT: s_or_b32 s64, s78, s77
-; SI-NEXT: s_or_b32 s65, s76, s85
-; SI-NEXT: s_and_b32 s76, s28, 0xff
-; SI-NEXT: s_lshl_b32 s77, s59, 8
+; SI-NEXT: v_readlane_b32 s18, v46, 32
+; SI-NEXT: s_and_b32 s77, s47, 0xff
; SI-NEXT: s_and_b32 s47, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 48
-; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s58, 0xff
-; SI-NEXT: s_and_b32 s56, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 49
-; SI-NEXT: s_or_b32 s7, s7, s89
-; SI-NEXT: s_or_b32 s15, s15, s91
+; SI-NEXT: v_readlane_b32 s18, v46, 34
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s97, 24
+; SI-NEXT: s_and_b32 s76, s76, 0xffff
+; SI-NEXT: s_and_b32 s56, s18, 0xffff
+; SI-NEXT: v_readlane_b32 s18, v46, 36
+; SI-NEXT: s_or_b32 s64, s78, s77
+; SI-NEXT: s_or_b32 s65, s76, s96
+; SI-NEXT: s_and_b32 s76, s17, 0xff
+; SI-NEXT: s_lshl_b32 s77, s99, 8
; SI-NEXT: s_and_b32 s57, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 50
-; SI-NEXT: s_and_b32 s41, s41, 0xffff
-; SI-NEXT: s_mov_b32 s31, s97
-; SI-NEXT: s_or_b32 s96, s78, s77
-; SI-NEXT: s_mov_b32 s90, s21
-; SI-NEXT: s_lshl_b32 s78, s21, 24
+; SI-NEXT: v_readlane_b32 s18, v46, 38
+; SI-NEXT: s_or_b32 s76, s76, s77
+; SI-NEXT: s_and_b32 s77, s86, 0xff
; SI-NEXT: s_and_b32 s30, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 51
-; SI-NEXT: s_and_b32 s87, s72, 0xffff
-; SI-NEXT: s_and_b32 s97, s73, 0xffff
-; SI-NEXT: s_or_b32 s72, s45, s6
-; SI-NEXT: s_mov_b32 s73, s7
-; SI-NEXT: s_lshr_b64 s[20:21], s[6:7], 16
-; SI-NEXT: s_lshr_b64 s[6:7], s[14:15], 16
-; SI-NEXT: s_or_b32 s41, s41, s88
+; SI-NEXT: v_readlane_b32 s18, v46, 40
+; SI-NEXT: s_lshl_b32 s77, s77, 16
+; SI-NEXT: s_lshl_b32 s78, s83, 24
; SI-NEXT: s_and_b32 s34, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 52
-; SI-NEXT: v_writelane_b32 v41, s6, 38
-; SI-NEXT: s_and_b32 s43, s43, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s7, 39
-; SI-NEXT: s_lshr_b64 s[6:7], s[40:41], 16
-; SI-NEXT: s_or_b32 s43, s43, s19
-; SI-NEXT: v_writelane_b32 v41, s6, 40
-; SI-NEXT: v_writelane_b32 v41, s7, 41
-; SI-NEXT: s_lshr_b64 s[6:7], s[42:43], 16
+; SI-NEXT: v_readlane_b32 s18, v46, 42
; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_and_b32 s13, s13, 0xffff
-; SI-NEXT: s_and_b32 s77, s60, 0xff
-; SI-NEXT: v_writelane_b32 v41, s6, 42
-; SI-NEXT: s_or_b32 s5, s5, s79
-; SI-NEXT: s_and_b32 s9, s9, 0xffff
-; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: s_or_b32 s13, s13, s95
+; SI-NEXT: s_mov_b32 s16, s83
+; SI-NEXT: s_or_b32 s83, s78, s77
+; SI-NEXT: s_and_b32 s77, s84, 0xff
+; SI-NEXT: s_and_b32 s36, s18, 0xffff
+; SI-NEXT: v_readlane_b32 s18, v46, 46
+; SI-NEXT: s_or_b32 s5, s5, s68
; SI-NEXT: s_lshl_b32 s77, s77, 16
+; SI-NEXT: s_lshl_b32 s78, s66, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s7, 43
-; SI-NEXT: s_lshr_b64 s[6:7], vcc, 16
-; SI-NEXT: s_or_b32 s9, s9, s23
-; SI-NEXT: s_or_b32 s11, s11, s93
+; SI-NEXT: s_and_b32 s84, s18, 0xffff
+; SI-NEXT: v_readlane_b32 s18, v46, 47
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s66, s78, s77
-; SI-NEXT: s_or_b32 s67, s76, s96
-; SI-NEXT: s_and_b32 s36, s18, 0xffff
-; SI-NEXT: s_and_b32 s83, s61, 0xffff
-; SI-NEXT: s_and_b32 s86, s62, 0xffff
-; SI-NEXT: s_and_b32 s98, s63, 0xffff
+; SI-NEXT: s_or_b32 s67, s76, s83
+; SI-NEXT: s_mov_b32 s78, s86
+; SI-NEXT: s_and_b32 s86, s18, 0xffff
+; SI-NEXT: s_mov_b32 s76, s99
; SI-NEXT: s_and_b32 s99, s74, 0xffff
; SI-NEXT: s_and_b32 s18, s75, 0xffff
; SI-NEXT: s_or_b32 s74, s44, s4
; SI-NEXT: s_mov_b32 s75, s5
-; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 16
+; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; SI-NEXT: s_or_b32 s7, s7, s91
+; SI-NEXT: v_writelane_b32 v46, s4, 26
+; SI-NEXT: s_and_b32 s9, s9, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 27
+; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
+; SI-NEXT: s_or_b32 s9, s9, s88
+; SI-NEXT: v_writelane_b32 v46, s4, 28
+; SI-NEXT: s_and_b32 s11, s11, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 29
+; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 16
+; SI-NEXT: s_or_b32 s11, s11, s95
+; SI-NEXT: v_writelane_b32 v46, s4, 30
+; SI-NEXT: s_and_b32 s13, s13, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 31
+; SI-NEXT: s_lshr_b64 s[4:5], s[10:11], 16
+; SI-NEXT: s_or_b32 s13, s13, s89
+; SI-NEXT: v_writelane_b32 v46, s4, 32
+; SI-NEXT: s_and_b32 s15, s15, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 33
; SI-NEXT: s_lshr_b64 s[4:5], s[12:13], 16
-; SI-NEXT: v_writelane_b32 v41, s6, 44
-; SI-NEXT: s_mov_b32 s17, s92
-; SI-NEXT: s_mov_b32 s92, s59
-; SI-NEXT: s_mov_b32 s94, s60
+; SI-NEXT: s_or_b32 s15, s15, s93
+; SI-NEXT: v_writelane_b32 v46, s4, 34
+; SI-NEXT: s_and_b32 s41, s41, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 35
+; SI-NEXT: s_lshr_b64 s[4:5], s[14:15], 16
+; SI-NEXT: s_or_b32 s41, s41, s21
+; SI-NEXT: v_writelane_b32 v46, s4, 36
+; SI-NEXT: s_and_b32 s43, s43, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 37
+; SI-NEXT: s_lshr_b64 s[4:5], s[40:41], 16
+; SI-NEXT: s_or_b32 s43, s43, s69
+; SI-NEXT: v_writelane_b32 v46, s4, 38
+; SI-NEXT: v_writelane_b32 v46, s5, 39
+; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v46, s4, 40
+; SI-NEXT: v_writelane_b32 v46, s5, 41
+; SI-NEXT: s_lshr_b64 s[4:5], vcc, 16
+; SI-NEXT: s_and_b32 s97, s63, 0xffff
+; SI-NEXT: s_and_b32 s98, s72, 0xffff
+; SI-NEXT: s_and_b32 s22, s73, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s4, 42
+; SI-NEXT: s_or_b32 s72, s45, s6
+; SI-NEXT: s_mov_b32 s73, s7
; SI-NEXT: s_or_b32 s62, s46, s8
; SI-NEXT: s_mov_b32 s63, s9
-; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 16
; SI-NEXT: s_or_b32 s60, s47, s10
; SI-NEXT: s_mov_b32 s61, s11
-; SI-NEXT: s_lshr_b64 s[28:29], s[10:11], 16
; SI-NEXT: s_or_b32 s58, s56, s12
; SI-NEXT: s_mov_b32 s59, s13
; SI-NEXT: s_or_b32 s56, s57, s14
; SI-NEXT: s_mov_b32 s57, s15
; SI-NEXT: s_or_b32 s46, s30, s40
; SI-NEXT: s_mov_b32 s47, s41
-; SI-NEXT: v_writelane_b32 v41, s7, 45
-; SI-NEXT: s_or_b32 s40, s83, s38
+; SI-NEXT: v_writelane_b32 v46, s5, 43
+; SI-NEXT: s_or_b32 s40, s84, s38
; SI-NEXT: s_mov_b32 s41, s39
; SI-NEXT: s_lshr_b64 s[38:39], s[38:39], 16
; SI-NEXT: s_or_b32 s14, s86, s48
; SI-NEXT: s_mov_b32 s15, s49
; SI-NEXT: s_lshr_b64 s[48:49], s[48:49], 16
-; SI-NEXT: s_or_b32 s12, s98, s50
+; SI-NEXT: s_or_b32 s12, s97, s50
; SI-NEXT: s_mov_b32 s13, s51
; SI-NEXT: s_lshr_b64 s[50:51], s[50:51], 16
-; SI-NEXT: s_or_b32 s10, s87, s52
-; SI-NEXT: s_mov_b32 s86, s4
+; SI-NEXT: s_or_b32 s10, s98, s52
; SI-NEXT: s_mov_b32 s11, s53
; SI-NEXT: s_lshr_b64 s[52:53], s[52:53], 16
-; SI-NEXT: s_or_b32 s8, s97, s54
+; SI-NEXT: s_or_b32 s8, s22, s54
; SI-NEXT: s_mov_b32 s9, s55
; SI-NEXT: s_lshr_b64 s[54:55], s[54:55], 16
; SI-NEXT: s_or_b32 s6, s99, s64
@@ -172650,141 +172673,155 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_mov_b32 s45, s43
; SI-NEXT: s_or_b32 s42, s36, vcc_lo
; SI-NEXT: s_mov_b32 s43, vcc_hi
-; SI-NEXT: s_lshr_b32 s77, s79, 16
-; SI-NEXT: s_lshr_b32 s67, s89, 16
-; SI-NEXT: s_lshr_b32 s23, s23, 16
-; SI-NEXT: s_lshr_b32 s79, s93, 16
-; SI-NEXT: s_lshr_b32 s89, s95, 16
-; SI-NEXT: s_lshr_b32 s91, s91, 16
-; SI-NEXT: s_lshr_b32 s93, s88, 16
-; SI-NEXT: s_lshr_b32 s95, s19, 16
+; SI-NEXT: s_mov_b32 s86, s78
+; SI-NEXT: s_mov_b32 s99, s76
+; SI-NEXT: v_readlane_b32 s18, v46, 50
+; SI-NEXT: s_lshr_b32 s77, s68, 16
+; SI-NEXT: s_lshr_b32 s68, s91, 16
+; SI-NEXT: s_lshr_b32 s88, s88, 16
+; SI-NEXT: s_lshr_b32 s84, s95, 16
+; SI-NEXT: s_lshr_b32 s89, s89, 16
+; SI-NEXT: s_lshr_b32 s91, s93, 16
+; SI-NEXT: s_lshr_b32 s93, s21, 16
+; SI-NEXT: s_lshr_b32 s95, s69, 16
; SI-NEXT: s_lshr_b32 s30, s70, 16
; SI-NEXT: s_lshr_b32 s34, s71, 16
-; SI-NEXT: v_readlane_b32 s78, v41, 59
-; SI-NEXT: v_readlane_b32 s70, v41, 58
-; SI-NEXT: v_readlane_b32 s71, v41, 57
-; SI-NEXT: v_readlane_b32 s65, v41, 56
; SI-NEXT: s_lshr_b32 s36, s80, 16
-; SI-NEXT: v_readlane_b32 s98, v41, 63
-; SI-NEXT: v_readlane_b32 s80, v41, 62
-; SI-NEXT: v_readlane_b32 s55, v41, 61
-; SI-NEXT: v_readlane_b32 s99, v41, 60
+; SI-NEXT: v_readlane_b32 s69, v46, 44
+; SI-NEXT: v_readlane_b32 s80, v46, 53
; SI-NEXT: s_lshr_b32 s39, s81, 16
-; SI-NEXT: v_readlane_b32 s27, v41, 46
+; SI-NEXT: v_readlane_b32 s81, v46, 57
+; SI-NEXT: v_readlane_b32 s76, v46, 56
+; SI-NEXT: v_readlane_b32 s21, v46, 55
+; SI-NEXT: v_readlane_b32 s98, v46, 54
; SI-NEXT: s_lshr_b32 s49, s82, 16
-; SI-NEXT: s_lshr_b32 s51, s84, 16
-; SI-NEXT: v_readlane_b32 s18, v41, 53
-; SI-NEXT: s_lshr_b32 s53, s85, 16
-; SI-NEXT: s_mov_b32 s81, s17
-; SI-NEXT: s_mov_b32 s17, s68
-; SI-NEXT: v_readlane_b32 s88, v41, 54
-; SI-NEXT: s_lshr_b32 s68, s96, 16
-; SI-NEXT: v_readlane_b32 s96, v41, 47
-; SI-NEXT: s_mov_b32 s84, s16
-; SI-NEXT: s_mov_b32 s16, s24
-; SI-NEXT: s_mov_b32 s24, s22
-; SI-NEXT: s_mov_b32 s22, s25
-; SI-NEXT: s_mov_b32 s25, s69
-; SI-NEXT: v_readlane_b32 s69, v41, 55
+; SI-NEXT: s_mov_b32 s82, s94
+; SI-NEXT: v_readlane_b32 s71, v46, 48
+; SI-NEXT: v_readlane_b32 s78, v46, 52
+; SI-NEXT: s_mov_b32 s55, s85
+; SI-NEXT: v_readlane_b32 s97, v46, 62
+; SI-NEXT: v_readlane_b32 s94, v46, 61
+; SI-NEXT: v_readlane_b32 s67, v46, 60
+; SI-NEXT: v_readlane_b32 s65, v46, 59
+; SI-NEXT: v_readlane_b32 s22, v46, 58
+; SI-NEXT: s_lshr_b32 s51, s87, 16
+; SI-NEXT: s_mov_b32 s70, s23
+; SI-NEXT: s_mov_b32 s23, s24
+; SI-NEXT: v_readlane_b32 s24, v46, 45
+; SI-NEXT: s_mov_b32 s87, s25
+; SI-NEXT: s_mov_b32 s25, s26
+; SI-NEXT: s_mov_b32 s26, s27
+; SI-NEXT: s_mov_b32 s27, s28
+; SI-NEXT: s_mov_b32 s28, s92
+; SI-NEXT: s_lshr_b32 s53, s96, 16
+; SI-NEXT: s_mov_b32 s96, s90
+; SI-NEXT: s_mov_b32 s90, s79
+; SI-NEXT: s_mov_b32 s79, s31
+; SI-NEXT: s_mov_b32 s31, s35
+; SI-NEXT: s_mov_b32 s35, s37
+; SI-NEXT: s_mov_b32 s37, s19
+; SI-NEXT: s_mov_b32 s19, s20
+; SI-NEXT: v_readlane_b32 s20, v46, 51
+; SI-NEXT: s_lshr_b32 s92, s83, 16
+; SI-NEXT: s_mov_b32 s83, s16
+; SI-NEXT: v_readlane_b32 s16, v46, 49
; SI-NEXT: s_cbranch_execnz .LBB93_3
; SI-NEXT: .LBB93_2: ; %cmp.true
-; SI-NEXT: v_readlane_b32 s4, v41, 35
-; SI-NEXT: s_add_i32 s19, s4, 3
-; SI-NEXT: v_readlane_b32 s5, v41, 34
-; SI-NEXT: s_and_b32 s4, s19, 0xff
+; SI-NEXT: v_readlane_b32 s4, v46, 11
+; SI-NEXT: s_add_i32 s85, s4, 3
+; SI-NEXT: v_readlane_b32 s5, v46, 6
+; SI-NEXT: v_readlane_b32 s6, v47, 60
+; SI-NEXT: s_and_b32 s4, s85, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
-; SI-NEXT: s_add_i32 s20, s94, 3
+; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: s_and_b32 s6, s20, 0xff
-; SI-NEXT: s_lshl_b32 s5, s90, 24
+; SI-NEXT: v_readlane_b32 s5, v47, 58
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 24
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_addk_i32 s4, 0x300
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_readlane_b32 s5, v41, 37
-; SI-NEXT: s_add_i32 s23, s5, 3
-; SI-NEXT: v_readlane_b32 s7, v41, 36
-; SI-NEXT: s_and_b32 s5, s23, 0xff
-; SI-NEXT: s_lshl_b32 s6, s92, 8
-; SI-NEXT: s_add_i32 s7, s7, 3
+; SI-NEXT: s_add_i32 s5, s17, 3
+; SI-NEXT: s_and_b32 s5, s5, 0xff
+; SI-NEXT: s_lshl_b32 s6, s99, 8
+; SI-NEXT: s_add_i32 s7, s86, 3
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: s_lshl_b32 s6, s31, 24
+; SI-NEXT: s_lshl_b32 s6, s83, 24
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_addk_i32 s5, 0x300
; SI-NEXT: s_or_b32 s6, s6, s7
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_readlane_b32 s6, v41, 33
-; SI-NEXT: s_add_i32 s68, s6, 3
-; SI-NEXT: v_readlane_b32 s7, v41, 32
-; SI-NEXT: v_readlane_b32 s8, v41, 29
-; SI-NEXT: s_and_b32 s6, s68, 0xff
+; SI-NEXT: v_readlane_b32 s6, v46, 20
+; SI-NEXT: s_add_i32 s6, s6, 3
+; SI-NEXT: v_readlane_b32 s7, v46, 14
+; SI-NEXT: v_readlane_b32 s8, v46, 9
+; SI-NEXT: s_and_b32 s6, s6, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 8
-; SI-NEXT: s_add_i32 s87, s8, 3
+; SI-NEXT: s_add_i32 s83, s8, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: v_readlane_b32 s7, v41, 30
-; SI-NEXT: s_and_b32 s8, s87, 0xff
+; SI-NEXT: v_readlane_b32 s7, v46, 8
+; SI-NEXT: s_and_b32 s8, s83, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_addk_i32 s6, 0x300
; SI-NEXT: s_or_b32 s7, s7, s8
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: v_readlane_b32 s7, v41, 25
-; SI-NEXT: s_add_i32 s83, s7, 3
-; SI-NEXT: v_readlane_b32 s8, v41, 24
-; SI-NEXT: v_readlane_b32 s9, v42, 40
-; SI-NEXT: s_and_b32 s7, s83, 0xff
-; SI-NEXT: s_lshl_b32 s8, s8, 8
-; SI-NEXT: s_add_i32 s9, s9, 3
+; SI-NEXT: s_add_i32 s7, s29, 3
+; SI-NEXT: s_and_b32 s7, s7, 0xff
+; SI-NEXT: s_lshl_b32 s8, s24, 8
+; SI-NEXT: s_add_i32 s9, s19, 3
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: s_and_b32 s9, s9, 0xff
-; SI-NEXT: s_lshl_b32 s8, s96, 24
+; SI-NEXT: s_lshl_b32 s8, s16, 24
; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_addk_i32 s7, 0x300
; SI-NEXT: s_or_b32 s8, s8, s9
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: v_readlane_b32 s8, v41, 22
+; SI-NEXT: v_readlane_b32 s8, v46, 23
; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: v_readlane_b32 s9, v41, 19
-; SI-NEXT: v_readlane_b32 s10, v42, 42
+; SI-NEXT: v_readlane_b32 s9, v46, 22
+; SI-NEXT: v_readlane_b32 s10, v46, 19
; SI-NEXT: s_and_b32 s8, s8, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 8
-; SI-NEXT: s_add_i32 s10, s10, 3
+; SI-NEXT: s_add_i32 s68, s10, 3
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: v_readlane_b32 s9, v42, 41
-; SI-NEXT: s_and_b32 s10, s10, 0xff
+; SI-NEXT: v_readlane_b32 s9, v46, 16
+; SI-NEXT: s_and_b32 s10, s68, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 24
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_addk_i32 s8, 0x300
; SI-NEXT: s_or_b32 s9, s9, s10
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: v_readlane_b32 s9, v41, 18
+; SI-NEXT: v_readlane_b32 s9, v46, 4
; SI-NEXT: s_add_i32 s9, s9, 3
+; SI-NEXT: v_readlane_b32 s10, v46, 0
; SI-NEXT: s_and_b32 s9, s9, 0xff
-; SI-NEXT: s_lshl_b32 s10, s27, 8
-; SI-NEXT: s_add_i32 s11, s16, 3
+; SI-NEXT: s_lshl_b32 s10, s10, 8
+; SI-NEXT: s_add_i32 s11, s28, 3
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: s_lshl_b32 s10, s88, 24
+; SI-NEXT: s_lshl_b32 s10, s27, 24
; SI-NEXT: s_lshl_b32 s11, s11, 16
; SI-NEXT: s_addk_i32 s9, 0x300
; SI-NEXT: s_or_b32 s10, s10, s11
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_or_b32 s9, s10, s9
-; SI-NEXT: v_readlane_b32 s10, v41, 28
-; SI-NEXT: s_add_i32 s86, s10, 3
-; SI-NEXT: v_readlane_b32 s11, v41, 26
-; SI-NEXT: v_readlane_b32 s12, v41, 20
-; SI-NEXT: s_and_b32 s10, s86, 0xff
+; SI-NEXT: v_readlane_b32 s10, v46, 25
+; SI-NEXT: s_add_i32 s17, s10, 3
+; SI-NEXT: v_readlane_b32 s11, v46, 24
+; SI-NEXT: v_readlane_b32 s12, v46, 21
+; SI-NEXT: s_and_b32 s10, s17, 0xff
; SI-NEXT: s_lshl_b32 s11, s11, 8
; SI-NEXT: s_add_i32 s12, s12, 3
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: v_readlane_b32 s11, v42, 44
+; SI-NEXT: v_readlane_b32 s11, v46, 18
; SI-NEXT: s_and_b32 s12, s12, 0xff
; SI-NEXT: s_lshl_b32 s11, s11, 24
; SI-NEXT: s_lshl_b32 s12, s12, 16
@@ -172792,13 +172829,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s11, s11, s12
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: s_add_i32 s11, s69, 3
-; SI-NEXT: v_readlane_b32 s13, v41, 12
-; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: s_lshl_b32 s12, s22, 8
+; SI-NEXT: v_readlane_b32 s11, v46, 10
+; SI-NEXT: s_add_i32 s84, s11, 3
+; SI-NEXT: v_readlane_b32 s12, v46, 7
+; SI-NEXT: v_readlane_b32 s13, v46, 1
+; SI-NEXT: s_and_b32 s11, s84, 0xff
+; SI-NEXT: s_lshl_b32 s12, s12, 8
; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: v_readlane_b32 s12, v42, 43
+; SI-NEXT: v_readlane_b32 s12, v47, 59
; SI-NEXT: s_and_b32 s13, s13, 0xff
; SI-NEXT: s_lshl_b32 s12, s12, 24
; SI-NEXT: s_lshl_b32 s13, s13, 16
@@ -172806,30 +172845,31 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s12, s12, s13
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: v_readlane_b32 s12, v41, 31
-; SI-NEXT: s_add_i32 s97, s12, 3
-; SI-NEXT: v_readlane_b32 s13, v41, 27
-; SI-NEXT: v_readlane_b32 s14, v41, 23
-; SI-NEXT: s_and_b32 s12, s97, 0xff
+; SI-NEXT: v_readlane_b32 s12, v46, 17
+; SI-NEXT: s_add_i32 s99, s12, 3
+; SI-NEXT: v_readlane_b32 s13, v46, 15
+; SI-NEXT: v_readlane_b32 s14, v46, 12
+; SI-NEXT: s_and_b32 s12, s99, 0xff
; SI-NEXT: s_lshl_b32 s13, s13, 8
-; SI-NEXT: s_add_i32 s14, s14, 3
+; SI-NEXT: s_add_i32 s86, s14, 3
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: v_readlane_b32 s13, v41, 21
-; SI-NEXT: s_and_b32 s14, s14, 0xff
+; SI-NEXT: v_readlane_b32 s13, v46, 13
+; SI-NEXT: s_and_b32 s14, s86, 0xff
; SI-NEXT: s_lshl_b32 s13, s13, 24
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_addk_i32 s12, 0x300
; SI-NEXT: s_or_b32 s13, s13, s14
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: v_readlane_b32 s13, v42, 45
+; SI-NEXT: v_readlane_b32 s13, v46, 5
; SI-NEXT: s_add_i32 s13, s13, 3
-; SI-NEXT: v_readlane_b32 s15, v41, 15
+; SI-NEXT: v_readlane_b32 s14, v46, 3
+; SI-NEXT: v_readlane_b32 s15, v47, 62
; SI-NEXT: s_and_b32 s13, s13, 0xff
-; SI-NEXT: s_lshl_b32 s14, s25, 8
+; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_add_i32 s15, s15, 3
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: v_readlane_b32 s14, v41, 13
+; SI-NEXT: v_readlane_b32 s14, v47, 63
; SI-NEXT: s_and_b32 s15, s15, 0xff
; SI-NEXT: s_lshl_b32 s14, s14, 24
; SI-NEXT: s_lshl_b32 s15, s15, 16
@@ -172837,15 +172877,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s14, s14, s15
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: v_readlane_b32 s14, v41, 17
+; SI-NEXT: v_readlane_b32 s14, v46, 2
; SI-NEXT: s_add_i32 s14, s14, 3
-; SI-NEXT: v_readlane_b32 s15, v41, 16
-; SI-NEXT: v_readlane_b32 s16, v42, 47
+; SI-NEXT: v_readlane_b32 s15, v47, 61
+; SI-NEXT: v_readlane_b32 s16, v47, 56
; SI-NEXT: s_and_b32 s14, s14, 0xff
; SI-NEXT: s_lshl_b32 s15, s15, 8
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: v_readlane_b32 s15, v42, 46
+; SI-NEXT: v_readlane_b32 s15, v47, 57
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s15, s15, 24
; SI-NEXT: s_lshl_b32 s16, s16, 16
@@ -172853,113 +172893,93 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s15, s15, s16
; SI-NEXT: s_and_b32 s14, s14, 0xffff
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: s_add_i32 s15, s24, 3
-; SI-NEXT: s_lshl_b32 s16, s17, 8
-; SI-NEXT: v_readlane_b32 s17, v41, 10
+; SI-NEXT: s_add_i32 s15, s26, 3
; SI-NEXT: s_and_b32 s15, s15, 0xff
-; SI-NEXT: s_add_i32 s17, s17, 3
+; SI-NEXT: s_lshl_b32 s16, s25, 8
+; SI-NEXT: s_add_i32 s17, s23, 3
; SI-NEXT: s_or_b32 s15, s16, s15
-; SI-NEXT: v_readlane_b32 s16, v41, 11
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: s_lshl_b32 s16, s16, 24
+; SI-NEXT: s_lshl_b32 s16, s87, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_addk_i32 s15, 0x300
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s15, s15, 0xffff
; SI-NEXT: s_or_b32 s15, s16, s15
-; SI-NEXT: v_readlane_b32 s16, v41, 14
-; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: s_add_i32 s16, s20, 3
; SI-NEXT: s_lshl_b32 s17, s18, 8
-; SI-NEXT: v_readlane_b32 s18, v41, 8
+; SI-NEXT: v_readlane_b32 s18, v47, 54
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v41, 9
+; SI-NEXT: v_readlane_b32 s17, v47, 55
; SI-NEXT: s_and_b32 s18, s18, 0xff
+; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v41, 7
-; SI-NEXT: s_add_i32 s17, s17, 3
-; SI-NEXT: v_readlane_b32 s18, v41, 6
-; SI-NEXT: v_readlane_b32 s19, v41, 3
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: s_lshl_b32 s18, s18, 8
-; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: v_readlane_b32 s18, v41, 4
-; SI-NEXT: s_and_b32 s19, s19, 0xff
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_addk_i32 s17, 0x300
-; SI-NEXT: s_or_b32 s18, s18, s19
-; SI-NEXT: s_and_b32 s17, s17, 0xffff
-; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_add_i32 s40, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v41, 5
-; SI-NEXT: s_add_i32 s41, s17, 0x3000000
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v41, 2
-; SI-NEXT: v_readlane_b32 s18, v41, 0
+; SI-NEXT: s_add_i32 s16, s22, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_lshl_b32 s17, s65, 8
+; SI-NEXT: s_add_i32 s18, s94, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v41, 1
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
+; SI-NEXT: s_lshl_b32 s17, s67, 24
+; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s17, s18
+; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s41, s16, 0x3000000
+; SI-NEXT: s_add_i32 s16, s71, 3
+; SI-NEXT: s_and_b32 s16, s16, 0xff
+; SI-NEXT: s_lshl_b32 s17, s81, 8
+; SI-NEXT: s_add_i32 s18, s55, 3
+; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_and_b32 s18, s18, 0xff
+; SI-NEXT: s_addk_i32 s16, 0x300
+; SI-NEXT: s_lshl_b32 s17, s97, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s42, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 63
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 62
-; SI-NEXT: v_readlane_b32 s18, v42, 58
+; SI-NEXT: s_add_i32 s16, s98, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_lshl_b32 s17, s78, 8
+; SI-NEXT: s_add_i32 s18, s31, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 59
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
+; SI-NEXT: s_lshl_b32 s17, s35, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s43, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 61
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 60
-; SI-NEXT: v_readlane_b32 s18, v42, 56
+; SI-NEXT: s_add_i32 s16, s82, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_lshl_b32 s17, s37, 8
+; SI-NEXT: s_add_i32 s18, s90, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 57
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
+; SI-NEXT: s_lshl_b32 s17, s79, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s44, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 55
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 54
-; SI-NEXT: v_readlane_b32 s18, v42, 50
+; SI-NEXT: s_add_i32 s16, s96, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 46
+; SI-NEXT: v_readlane_b32 s18, v47, 45
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 51
+; SI-NEXT: v_readlane_b32 s17, v47, 44
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -172968,15 +172988,12 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s45, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 53
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 52
-; SI-NEXT: v_readlane_b32 s18, v42, 48
+; SI-NEXT: s_add_i32 s16, s21, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_lshl_b32 s17, s76, 8
+; SI-NEXT: s_add_i32 s18, s70, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 49
+; SI-NEXT: v_readlane_b32 s17, v47, 50
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -172985,28 +173002,31 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s46, s16, 0x3000000
-; SI-NEXT: s_add_i32 s16, s99, 3
+; SI-NEXT: s_add_i32 s16, s80, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 49
+; SI-NEXT: v_readlane_b32 s18, v47, 48
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s55, 8
-; SI-NEXT: s_add_i32 s18, s98, 3
+; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: v_readlane_b32 s17, v47, 47
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s80, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s47, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 18
+; SI-NEXT: v_readlane_b32 s16, v47, 18
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 17
-; SI-NEXT: v_readlane_b32 s18, v42, 16
+; SI-NEXT: v_readlane_b32 s17, v47, 17
+; SI-NEXT: v_readlane_b32 s18, v47, 16
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 15
+; SI-NEXT: v_readlane_b32 s17, v47, 15
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173015,28 +173035,32 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s56, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 14
+; SI-NEXT: v_readlane_b32 s16, v47, 14
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 53
+; SI-NEXT: v_readlane_b32 s18, v47, 52
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s84, 8
-; SI-NEXT: s_add_i32 s18, s71, 3
+; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: v_readlane_b32 s17, v47, 51
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s65, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s57, s16, 0x3000000
-; SI-NEXT: s_add_i32 s16, s70, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 25
-; SI-NEXT: v_readlane_b32 s18, v42, 24
+; SI-NEXT: v_readlane_b32 s16, v47, 26
+; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 25
+; SI-NEXT: v_readlane_b32 s18, v47, 24
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 23
+; SI-NEXT: v_readlane_b32 s17, v47, 23
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173045,15 +173069,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s58, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 22
+; SI-NEXT: v_readlane_b32 s16, v47, 22
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 21
-; SI-NEXT: v_readlane_b32 s18, v42, 20
+; SI-NEXT: v_readlane_b32 s17, v47, 21
+; SI-NEXT: v_readlane_b32 s18, v47, 20
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 19
+; SI-NEXT: v_readlane_b32 s17, v47, 19
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173062,13 +173086,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s59, s16, 0x3000000
-; SI-NEXT: s_add_i32 s16, s78, 3
-; SI-NEXT: v_readlane_b32 s18, v42, 31
+; SI-NEXT: v_readlane_b32 s16, v47, 34
+; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 33
+; SI-NEXT: v_readlane_b32 s18, v47, 32
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s81, 8
+; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 30
+; SI-NEXT: v_readlane_b32 s17, v47, 31
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173077,15 +173103,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s60, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 29
+; SI-NEXT: v_readlane_b32 s16, v47, 30
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 28
-; SI-NEXT: v_readlane_b32 s18, v42, 27
+; SI-NEXT: v_readlane_b32 s17, v47, 29
+; SI-NEXT: v_readlane_b32 s18, v47, 28
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 26
+; SI-NEXT: v_readlane_b32 s17, v47, 27
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173094,13 +173120,14 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s61, s16, 0x3000000
-; SI-NEXT: s_add_i32 s16, s37, 3
-; SI-NEXT: v_readlane_b32 s18, v42, 37
+; SI-NEXT: s_add_i32 s16, s69, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 41
+; SI-NEXT: v_readlane_b32 s18, v47, 40
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s35, 8
+; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 36
+; SI-NEXT: v_readlane_b32 s17, v47, 39
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173109,15 +173136,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s62, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 35
+; SI-NEXT: v_readlane_b32 s16, v47, 38
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 34
-; SI-NEXT: v_readlane_b32 s18, v42, 33
+; SI-NEXT: v_readlane_b32 s17, v47, 37
+; SI-NEXT: v_readlane_b32 s18, v47, 36
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 32
+; SI-NEXT: v_readlane_b32 s17, v47, 35
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173126,15 +173153,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s63, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 5
+; SI-NEXT: v_readlane_b32 s16, v47, 5
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 4
-; SI-NEXT: v_readlane_b32 s18, v42, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 4
+; SI-NEXT: v_readlane_b32 s18, v47, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 2
+; SI-NEXT: v_readlane_b32 s17, v47, 2
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173143,15 +173170,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s72, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 1
+; SI-NEXT: v_readlane_b32 s16, v47, 1
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 0
-; SI-NEXT: v_readlane_b32 s18, v42, 39
+; SI-NEXT: v_readlane_b32 s17, v47, 0
+; SI-NEXT: v_readlane_b32 s18, v47, 43
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 38
+; SI-NEXT: v_readlane_b32 s17, v47, 42
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173160,15 +173187,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s73, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 13
+; SI-NEXT: v_readlane_b32 s16, v47, 13
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 12
-; SI-NEXT: v_readlane_b32 s18, v42, 11
+; SI-NEXT: v_readlane_b32 s17, v47, 12
+; SI-NEXT: v_readlane_b32 s18, v47, 11
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 10
+; SI-NEXT: v_readlane_b32 s17, v47, 10
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173177,15 +173204,15 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s74, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 9
+; SI-NEXT: v_readlane_b32 s16, v47, 9
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 8
-; SI-NEXT: v_readlane_b32 s18, v42, 7
+; SI-NEXT: v_readlane_b32 s17, v47, 8
+; SI-NEXT: v_readlane_b32 s18, v47, 7
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 6
+; SI-NEXT: v_readlane_b32 s17, v47, 6
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -173194,45 +173221,55 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s75, s16, 0x3000000
+; SI-NEXT: s_lshr_b64 s[16:17], s[74:75], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 26
+; SI-NEXT: v_writelane_b32 v46, s17, 27
+; SI-NEXT: s_lshr_b64 s[16:17], s[72:73], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 28
+; SI-NEXT: v_writelane_b32 v46, s17, 29
+; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 30
+; SI-NEXT: v_writelane_b32 v46, s17, 31
+; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 32
+; SI-NEXT: v_writelane_b32 v46, s17, 33
+; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 34
+; SI-NEXT: v_writelane_b32 v46, s17, 35
; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
-; SI-NEXT: v_writelane_b32 v41, s16, 38
-; SI-NEXT: v_writelane_b32 v41, s17, 39
+; SI-NEXT: v_writelane_b32 v46, s16, 36
+; SI-NEXT: v_writelane_b32 v46, s17, 37
; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
-; SI-NEXT: v_writelane_b32 v41, s16, 40
-; SI-NEXT: v_writelane_b32 v41, s17, 41
+; SI-NEXT: v_writelane_b32 v46, s16, 38
+; SI-NEXT: v_writelane_b32 v46, s17, 39
; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
-; SI-NEXT: s_add_i32 s4, s4, 0x3000000
-; SI-NEXT: s_add_i32 s5, s5, 0x3000000
; SI-NEXT: s_add_i32 s10, s10, 0x3000000
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
; SI-NEXT: s_add_i32 s13, s13, 0x3000000
; SI-NEXT: s_add_i32 s14, s14, 0x3000000
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
-; SI-NEXT: v_writelane_b32 v41, s16, 42
+; SI-NEXT: v_writelane_b32 v46, s16, 40
+; SI-NEXT: s_add_i32 s4, s4, 0x3000000
+; SI-NEXT: s_add_i32 s5, s5, 0x3000000
; SI-NEXT: s_add_i32 s6, s6, 0x3000000
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
; SI-NEXT: s_add_i32 s8, s8, 0x3000000
; SI-NEXT: s_add_i32 s9, s9, 0x3000000
-; SI-NEXT: s_lshr_b64 s[76:77], s[74:75], 16
-; SI-NEXT: v_writelane_b32 v41, s17, 43
+; SI-NEXT: v_writelane_b32 v46, s17, 41
; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
; SI-NEXT: s_lshr_b64 s[38:39], s[40:41], 16
; SI-NEXT: s_lshr_b64 s[48:49], s[14:15], 16
; SI-NEXT: s_lshr_b64 s[50:51], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[52:53], s[10:11], 16
-; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[20:21], s[72:73], 16
-; SI-NEXT: s_lshr_b64 s[26:27], s[62:63], 16
-; SI-NEXT: s_lshr_b64 s[28:29], s[60:61], 16
-; SI-NEXT: s_lshr_b64 s[86:87], s[58:59], 16
-; SI-NEXT: v_writelane_b32 v41, s16, 44
+; SI-NEXT: v_writelane_b32 v46, s16, 42
; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[64:65], s[6:7], 16
+; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 16
; SI-NEXT: s_lshr_b32 s77, s75, 16
-; SI-NEXT: s_lshr_b32 s67, s73, 16
-; SI-NEXT: s_lshr_b32 s23, s63, 16
-; SI-NEXT: s_lshr_b32 s79, s61, 16
+; SI-NEXT: s_lshr_b32 s68, s73, 16
+; SI-NEXT: s_lshr_b32 s88, s63, 16
+; SI-NEXT: s_lshr_b32 s84, s61, 16
; SI-NEXT: s_lshr_b32 s89, s59, 16
; SI-NEXT: s_lshr_b32 s91, s57, 16
; SI-NEXT: s_lshr_b32 s93, s47, 16
@@ -173244,63 +173281,78 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_lshr_b32 s49, s11, 16
; SI-NEXT: s_lshr_b32 s51, s9, 16
; SI-NEXT: s_lshr_b32 s53, s7, 16
-; SI-NEXT: s_lshr_b32 s68, s5, 16
-; SI-NEXT: v_writelane_b32 v41, s17, 45
+; SI-NEXT: s_lshr_b32 s92, s5, 16
+; SI-NEXT: v_writelane_b32 v46, s17, 43
; SI-NEXT: .LBB93_3: ; %end
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: v_readlane_b32 s18, v46, 26
; SI-NEXT: s_and_b32 s17, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s18, s76, 16
+; SI-NEXT: v_readlane_b32 s19, v46, 27
+; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s75, 0xffff
; SI-NEXT: s_lshl_b32 s19, s77, 16
+; SI-NEXT: v_readlane_b32 s20, v46, 28
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s72, 0xffff
+; SI-NEXT: v_readlane_b32 s21, v46, 29
; SI-NEXT: s_lshl_b32 s20, s20, 16
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_and_b32 s20, s73, 0xffff
-; SI-NEXT: s_lshl_b32 s21, s67, 16
+; SI-NEXT: s_lshl_b32 s21, s68, 16
+; SI-NEXT: v_readlane_b32 s22, v46, 30
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s62, 0xffff
-; SI-NEXT: s_lshl_b32 s22, s26, 16
+; SI-NEXT: v_readlane_b32 s23, v46, 31
+; SI-NEXT: s_lshl_b32 s22, s22, 16
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s63, 0xffff
-; SI-NEXT: s_lshl_b32 s23, s23, 16
+; SI-NEXT: s_lshl_b32 s23, s88, 16
+; SI-NEXT: v_readlane_b32 s24, v46, 32
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s60, 0xffff
-; SI-NEXT: s_lshl_b32 s24, s28, 16
+; SI-NEXT: v_readlane_b32 s25, v46, 33
+; SI-NEXT: s_lshl_b32 s24, s24, 16
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s24, s61, 0xffff
-; SI-NEXT: s_lshl_b32 s25, s79, 16
+; SI-NEXT: s_lshl_b32 s25, s84, 16
+; SI-NEXT: v_readlane_b32 s26, v46, 34
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s58, 0xffff
-; SI-NEXT: s_lshl_b32 s26, s86, 16
+; SI-NEXT: v_readlane_b32 s27, v46, 35
+; SI-NEXT: s_lshl_b32 s26, s26, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s59, 0xffff
; SI-NEXT: s_lshl_b32 s27, s89, 16
-; SI-NEXT: v_readlane_b32 s28, v41, 38
+; SI-NEXT: v_readlane_b32 s28, v46, 36
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s56, 0xffff
-; SI-NEXT: v_readlane_b32 s29, v41, 39
+; SI-NEXT: v_readlane_b32 s29, v46, 37
; SI-NEXT: s_lshl_b32 s28, s28, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s57, 0xffff
; SI-NEXT: s_lshl_b32 s29, s91, 16
-; SI-NEXT: v_readlane_b32 s56, v41, 40
+; SI-NEXT: v_readlane_b32 s56, v46, 38
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s29, s46, 0xffff
-; SI-NEXT: v_readlane_b32 s57, v41, 41
+; SI-NEXT: v_readlane_b32 s57, v46, 39
; SI-NEXT: s_lshl_b32 s46, s56, 16
; SI-NEXT: s_or_b32 s29, s29, s46
; SI-NEXT: s_and_b32 s46, s47, 0xffff
; SI-NEXT: s_lshl_b32 s47, s93, 16
-; SI-NEXT: v_readlane_b32 s56, v41, 42
+; SI-NEXT: v_readlane_b32 s56, v46, 40
; SI-NEXT: s_or_b32 s46, s46, s47
; SI-NEXT: s_and_b32 s44, s44, 0xffff
-; SI-NEXT: v_readlane_b32 s57, v41, 43
+; SI-NEXT: v_readlane_b32 s57, v46, 41
; SI-NEXT: s_lshl_b32 s47, s56, 16
; SI-NEXT: s_or_b32 s44, s44, s47
; SI-NEXT: s_and_b32 s45, s45, 0xffff
; SI-NEXT: s_lshl_b32 s47, s95, 16
-; SI-NEXT: v_readlane_b32 s56, v41, 44
+; SI-NEXT: v_readlane_b32 s56, v46, 42
; SI-NEXT: s_or_b32 s45, s45, s47
; SI-NEXT: s_and_b32 s42, s42, 0xffff
; SI-NEXT: s_lshl_b32 s47, s56, 16
@@ -173347,11 +173399,11 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s47, s66, 16
; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_lshl_b32 s16, s68, 16
+; SI-NEXT: s_lshl_b32 s16, s92, 16
; SI-NEXT: s_or_b32 s4, s4, s47
; SI-NEXT: s_or_b32 s5, s5, s16
-; SI-NEXT: v_readlane_b32 s30, v40, 34
-; SI-NEXT: v_readlane_b32 s57, v41, 45
+; SI-NEXT: v_readlane_b32 s30, v45, 34
+; SI-NEXT: v_readlane_b32 s57, v46, 43
; SI-NEXT: v_mov_b32_e32 v0, s17
; SI-NEXT: v_mov_b32_e32 v1, s18
; SI-NEXT: v_mov_b32_e32 v2, s19
@@ -173384,78 +173436,62 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: v_mov_b32_e32 v29, s7
; SI-NEXT: v_mov_b32_e32 v30, s4
; SI-NEXT: v_mov_b32_e32 v31, s5
-; SI-NEXT: v_readlane_b32 s31, v40, 35
-; SI-NEXT: v_readlane_b32 s99, v40, 33
-; SI-NEXT: v_readlane_b32 s98, v40, 32
-; SI-NEXT: v_readlane_b32 s97, v40, 31
-; SI-NEXT: v_readlane_b32 s96, v40, 30
-; SI-NEXT: v_readlane_b32 s87, v40, 29
-; SI-NEXT: v_readlane_b32 s86, v40, 28
-; SI-NEXT: v_readlane_b32 s85, v40, 27
-; SI-NEXT: v_readlane_b32 s84, v40, 26
-; SI-NEXT: v_readlane_b32 s83, v40, 25
-; SI-NEXT: v_readlane_b32 s82, v40, 24
-; SI-NEXT: v_readlane_b32 s81, v40, 23
-; SI-NEXT: v_readlane_b32 s80, v40, 22
-; SI-NEXT: v_readlane_b32 s71, v40, 21
-; SI-NEXT: v_readlane_b32 s70, v40, 20
-; SI-NEXT: v_readlane_b32 s69, v40, 19
-; SI-NEXT: v_readlane_b32 s68, v40, 18
-; SI-NEXT: v_readlane_b32 s67, v40, 17
-; SI-NEXT: v_readlane_b32 s66, v40, 16
-; SI-NEXT: v_readlane_b32 s65, v40, 15
-; SI-NEXT: v_readlane_b32 s64, v40, 14
-; SI-NEXT: v_readlane_b32 s55, v40, 13
-; SI-NEXT: v_readlane_b32 s54, v40, 12
-; SI-NEXT: v_readlane_b32 s53, v40, 11
-; SI-NEXT: v_readlane_b32 s52, v40, 10
-; SI-NEXT: v_readlane_b32 s51, v40, 9
-; SI-NEXT: v_readlane_b32 s50, v40, 8
-; SI-NEXT: v_readlane_b32 s49, v40, 7
-; SI-NEXT: v_readlane_b32 s48, v40, 6
-; SI-NEXT: v_readlane_b32 s39, v40, 5
-; SI-NEXT: v_readlane_b32 s38, v40, 4
-; SI-NEXT: v_readlane_b32 s37, v40, 3
-; SI-NEXT: v_readlane_b32 s36, v40, 2
-; SI-NEXT: v_readlane_b32 s35, v40, 1
-; SI-NEXT: v_readlane_b32 s34, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v45, 35
+; SI-NEXT: v_readlane_b32 s99, v45, 33
+; SI-NEXT: v_readlane_b32 s98, v45, 32
+; SI-NEXT: v_readlane_b32 s97, v45, 31
+; SI-NEXT: v_readlane_b32 s96, v45, 30
+; SI-NEXT: v_readlane_b32 s87, v45, 29
+; SI-NEXT: v_readlane_b32 s86, v45, 28
+; SI-NEXT: v_readlane_b32 s85, v45, 27
+; SI-NEXT: v_readlane_b32 s84, v45, 26
+; SI-NEXT: v_readlane_b32 s83, v45, 25
+; SI-NEXT: v_readlane_b32 s82, v45, 24
+; SI-NEXT: v_readlane_b32 s81, v45, 23
+; SI-NEXT: v_readlane_b32 s80, v45, 22
+; SI-NEXT: v_readlane_b32 s71, v45, 21
+; SI-NEXT: v_readlane_b32 s70, v45, 20
+; SI-NEXT: v_readlane_b32 s69, v45, 19
+; SI-NEXT: v_readlane_b32 s68, v45, 18
+; SI-NEXT: v_readlane_b32 s67, v45, 17
+; SI-NEXT: v_readlane_b32 s66, v45, 16
+; SI-NEXT: v_readlane_b32 s65, v45, 15
+; SI-NEXT: v_readlane_b32 s64, v45, 14
+; SI-NEXT: v_readlane_b32 s55, v45, 13
+; SI-NEXT: v_readlane_b32 s54, v45, 12
+; SI-NEXT: v_readlane_b32 s53, v45, 11
+; SI-NEXT: v_readlane_b32 s52, v45, 10
+; SI-NEXT: v_readlane_b32 s51, v45, 9
+; SI-NEXT: v_readlane_b32 s50, v45, 8
+; SI-NEXT: v_readlane_b32 s49, v45, 7
+; SI-NEXT: v_readlane_b32 s48, v45, 6
+; SI-NEXT: v_readlane_b32 s39, v45, 5
+; SI-NEXT: v_readlane_b32 s38, v45, 4
+; SI-NEXT: v_readlane_b32 s37, v45, 3
+; SI-NEXT: v_readlane_b32 s36, v45, 2
+; SI-NEXT: v_readlane_b32 s35, v45, 1
+; SI-NEXT: v_readlane_b32 s34, v45, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB93_4:
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_mov_b32 s90, s21
-; SI-NEXT: v_writelane_b32 v41, s4, 38
-; SI-NEXT: v_writelane_b32 v41, s5, 39
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_mov_b32 s94, s60
-; SI-NEXT: v_writelane_b32 v41, s4, 40
-; SI-NEXT: v_writelane_b32 v41, s5, 41
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_mov_b32 s92, s59
-; SI-NEXT: v_writelane_b32 v41, s4, 42
-; SI-NEXT: v_writelane_b32 v41, s5, 43
+; SI-NEXT: v_writelane_b32 v46, s4, 26
+; SI-NEXT: v_writelane_b32 v46, s5, 27
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_mov_b32 s31, s97
-; SI-NEXT: v_writelane_b32 v41, s4, 44
; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr77
; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr20
-; SI-NEXT: ; implicit-def: $sgpr67
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $sgpr26
-; SI-NEXT: ; implicit-def: $sgpr23
+; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr28
-; SI-NEXT: ; implicit-def: $sgpr79
+; SI-NEXT: ; implicit-def: $sgpr84
; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr86
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr91
@@ -173464,7 +173500,6 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr42
-; SI-NEXT: v_writelane_b32 v41, s5, 45
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr38
@@ -173484,9 +173519,32 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr64
; SI-NEXT: ; implicit-def: $sgpr53
-; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: v_writelane_b32 v46, s4, 28
+; SI-NEXT: v_writelane_b32 v46, s5, 29
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 30
+; SI-NEXT: v_writelane_b32 v46, s5, 31
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 32
+; SI-NEXT: v_writelane_b32 v46, s5, 33
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 34
+; SI-NEXT: v_writelane_b32 v46, s5, 35
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 36
+; SI-NEXT: v_writelane_b32 v46, s5, 37
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 38
+; SI-NEXT: v_writelane_b32 v46, s5, 39
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 40
+; SI-NEXT: v_writelane_b32 v46, s5, 41
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 42
+; SI-NEXT: v_writelane_b32 v46, s5, 43
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_branch .LBB93_2
;
; VI-LABEL: bitcast_v128i8_to_v64f16_scalar:
@@ -183140,10 +183198,10 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_lshr_b32 s44, s43, 16
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v53, s44, v7
+; VI-NEXT: v_add_f16_e32 v59, s44, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v22, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v53
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
; VI-NEXT: v_add_f16_e32 v2, s43, v7
; VI-NEXT: s_lshr_b32 s43, s42, 16
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
@@ -183153,10 +183211,10 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_lshr_b32 s42, s41, 16
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v50, s42, v7
+; VI-NEXT: v_add_f16_e32 v56, s42, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v24, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v50
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v56
; VI-NEXT: v_add_f16_e32 v2, s41, v7
; VI-NEXT: s_lshr_b32 s41, s40, 16
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
@@ -183167,7 +183225,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v61, s40, v7
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v26, v2, v1
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
; VI-NEXT: v_add_f16_e32 v2, s15, v7
@@ -183179,10 +183237,10 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_lshr_b32 s14, s13, 16
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v51, s14, v7
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_e32 v57, s14, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v28, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v57
; VI-NEXT: v_add_f16_e32 v2, s13, v7
; VI-NEXT: s_lshr_b32 s13, s12, 16
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
@@ -183193,7 +183251,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v41, s12, v7
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v5, v2, v1
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v41
; VI-NEXT: v_add_f16_e32 v2, s11, v7
@@ -183206,7 +183264,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v37, s10, v7
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v30, v2, v1
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v37
; VI-NEXT: v_add_f16_e32 v2, s9, v7
@@ -183218,13 +183276,13 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_lshr_b32 s8, s7, 16
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v52, s8, v7
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_e32 v58, s8, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v3, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v52
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v58
; VI-NEXT: v_add_f16_e32 v2, s7, v7
; VI-NEXT: s_lshr_b32 s7, s6, 16
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v2, v2, v1
; VI-NEXT: v_add_f16_e32 v1, s7, v7
; VI-NEXT: v_add_f16_e32 v8, s6, v7
@@ -183257,13 +183315,13 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_add_f16_e32 v9, s18, v7
; VI-NEXT: s_lshr_b32 s7, s20, 16
; VI-NEXT: v_add_f16_e32 v39, s6, v7
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v20, v9, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
; VI-NEXT: v_add_f16_e32 v9, s21, v7
; VI-NEXT: v_add_f16_e32 v38, s7, v7
; VI-NEXT: s_lshr_b32 s6, s23, 16
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v35, v9, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
; VI-NEXT: v_add_f16_e32 v9, s20, v7
@@ -183279,11 +183337,11 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v19, v9, v8
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v48
; VI-NEXT: v_add_f16_e32 v9, s22, v7
-; VI-NEXT: v_add_f16_e32 v45, s6, v7
+; VI-NEXT: v_add_f16_e32 v51, s6, v7
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v18, v9, v8
; VI-NEXT: s_lshr_b32 s7, s24, 16
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v51
; VI-NEXT: v_add_f16_e32 v9, s25, v7
; VI-NEXT: v_or_b32_e32 v16, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s7, v7
@@ -183292,11 +183350,11 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_add_f16_e32 v9, s24, v7
-; VI-NEXT: v_add_f16_e32 v47, s6, v7
+; VI-NEXT: v_add_f16_e32 v53, s6, v7
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v15, v9, v8
; VI-NEXT: s_lshr_b32 s7, s26, 16
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v47
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v53
; VI-NEXT: v_add_f16_e32 v9, s27, v7
; VI-NEXT: v_or_b32_e32 v13, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s7, v7
@@ -183304,11 +183362,11 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_add_f16_e32 v54, s26, v7
-; VI-NEXT: v_add_f16_e32 v57, s6, v7
+; VI-NEXT: v_add_f16_e32 v45, s6, v7
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v12, v54, v8
; VI-NEXT: s_lshr_b32 s7, s28, 16
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v57
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
; VI-NEXT: v_add_f16_e32 v9, s29, v7
; VI-NEXT: v_or_b32_e32 v10, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s7, v7
@@ -183318,13 +183376,13 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_add_f16_e32 v9, s28, v7
; VI-NEXT: s_lshr_b32 s7, s4, 16
-; VI-NEXT: v_add_f16_e32 v59, s6, v7
+; VI-NEXT: v_add_f16_e32 v47, s6, v7
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v9, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s5, v7
; VI-NEXT: v_add_f16_e32 v14, s7, v7
; VI-NEXT: v_add_f16_e32 v17, s4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v47
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; VI-NEXT: v_or_b32_e32 v8, v8, v7
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v14
@@ -183357,7 +183415,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[18:19]
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v35
-; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v34
+; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v34
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[34:35]
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v1
@@ -183365,7 +183423,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v25
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v24
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[24:25]
-; VI-NEXT: v_bfe_u32 v25, v52, 8, 8
+; VI-NEXT: v_bfe_u32 v25, v58, 8, 8
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
@@ -183377,22 +183435,22 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v3
; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[3:4]
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v25, v51, 8, 8
+; VI-NEXT: v_bfe_u32 v25, v57, 8, 8
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v31
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[30:31]
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; VI-NEXT: v_bfe_u32 v25, v61, 8, 8
-; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v20
+; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v20
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[20:21]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v30
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v5
; VI-NEXT: v_lshrrev_b64 v[4:5], 24, v[5:6]
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v25, v50, 8, 8
+; VI-NEXT: v_bfe_u32 v25, v56, 8, 8
; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v21
-; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v32
+; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v32
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[32:33]
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
@@ -183402,25 +183460,25 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v27
; VI-NEXT: v_lshrrev_b64 v[8:9], 24, v[26:27]
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; VI-NEXT: v_bfe_u32 v25, v53, 8, 8
+; VI-NEXT: v_bfe_u32 v25, v59, 8, 8
; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; VI-NEXT: v_bfe_u32 v27, v36, 8, 8
-; VI-NEXT: v_mov_b32_e32 v36, v53
-; VI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; VI-NEXT: v_mov_b32_e32 v36, v59
+; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[12:13]
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[22:23]
-; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v33
+; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v33
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v28
; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v26
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v23
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
; VI-NEXT: v_mov_b32_e32 v23, v11
-; VI-NEXT: v_bfe_u32 v11, v59, 8, 8
-; VI-NEXT: v_bfe_u32 v26, v57, 8, 8
-; VI-NEXT: v_bfe_u32 v28, v47, 8, 8
-; VI-NEXT: v_bfe_u32 v9, v45, 8, 8
+; VI-NEXT: v_bfe_u32 v11, v47, 8, 8
+; VI-NEXT: v_bfe_u32 v26, v45, 8, 8
+; VI-NEXT: v_bfe_u32 v28, v53, 8, 8
+; VI-NEXT: v_bfe_u32 v9, v51, 8, 8
; VI-NEXT: v_bfe_u32 v12, v49, 8, 8
; VI-NEXT: v_bfe_u32 v15, v39, 8, 8
; VI-NEXT: v_bfe_u32 v22, v60, 8, 8
@@ -183592,44 +183650,44 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_mov_b32_e32 v1, s43
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s40
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s41
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s14
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s15
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s12
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_mov_b32_e32 v2, s46
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s11
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s8
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s9
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s7
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s16
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s18
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s19
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s20
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s22
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s23
@@ -183675,17 +183733,17 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: v_readlane_b32 s6, v62, 9
-; VI-NEXT: v_mov_b32_e32 v45, s6
+; VI-NEXT: v_mov_b32_e32 v51, s6
; VI-NEXT: v_readlane_b32 s6, v62, 10
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: v_readlane_b32 s6, v62, 11
-; VI-NEXT: v_mov_b32_e32 v47, s6
+; VI-NEXT: v_mov_b32_e32 v53, s6
; VI-NEXT: v_readlane_b32 s6, v62, 12
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: v_readlane_b32 s6, v62, 13
-; VI-NEXT: v_mov_b32_e32 v57, s6
+; VI-NEXT: v_mov_b32_e32 v45, s6
; VI-NEXT: v_readlane_b32 s6, v62, 14
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s6
@@ -183757,17 +183815,17 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_readlane_b32 s4, v62, 36
-; VI-NEXT: v_mov_b32_e32 v44, s4
+; VI-NEXT: v_mov_b32_e32 v50, s4
; VI-NEXT: v_readlane_b32 s4, v62, 37
; VI-NEXT: v_mov_b32_e32 v43, s4
; VI-NEXT: v_readlane_b32 s4, v62, 38
-; VI-NEXT: v_mov_b32_e32 v46, s4
+; VI-NEXT: v_mov_b32_e32 v52, s4
; VI-NEXT: v_readlane_b32 s4, v62, 39
; VI-NEXT: v_mov_b32_e32 v40, s4
; VI-NEXT: v_readlane_b32 s4, v62, 40
-; VI-NEXT: v_mov_b32_e32 v58, s4
+; VI-NEXT: v_mov_b32_e32 v46, s4
; VI-NEXT: v_readlane_b32 s4, v62, 41
-; VI-NEXT: v_mov_b32_e32 v56, s4
+; VI-NEXT: v_mov_b32_e32 v44, s4
; VI-NEXT: v_readlane_b32 s4, v62, 42
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s4
@@ -183812,15 +183870,15 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v54, s26
-; VI-NEXT: v_mov_b32_e32 v53, s71
+; VI-NEXT: v_mov_b32_e32 v59, s71
; VI-NEXT: v_mov_b32_e32 v36, s68
-; VI-NEXT: v_mov_b32_e32 v50, s66
+; VI-NEXT: v_mov_b32_e32 v56, s66
; VI-NEXT: v_mov_b32_e32 v61, s64
-; VI-NEXT: v_mov_b32_e32 v51, s54
+; VI-NEXT: v_mov_b32_e32 v57, s54
; VI-NEXT: v_mov_b32_e32 v41, s86
; VI-NEXT: v_mov_b32_e32 v37, s84
-; VI-NEXT: v_mov_b32_e32 v52, s52
-; VI-NEXT: v_mov_b32_e32 v59, s6
+; VI-NEXT: v_mov_b32_e32 v58, s52
+; VI-NEXT: v_mov_b32_e32 v47, s6
; VI-NEXT: v_mov_b32_e32 v25, s50
; VI-NEXT: v_mov_b32_e32 v27, s51
; VI-NEXT: v_mov_b32_e32 v21, s4
@@ -183853,7 +183911,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v12, v49, v12, s4
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_perm_b32 v9, v45, v9, s4
+; VI-NEXT: v_perm_b32 v9, v51, v9, s4
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_readlane_b32 s30, v63, 30
; VI-NEXT: v_readlane_b32 s31, v63, 31
@@ -183888,18 +183946,18 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_readlane_b32 s35, v63, 1
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v58, v23, v58, s4
-; VI-NEXT: v_or_b32_e32 v20, v58, v20
+; VI-NEXT: v_perm_b32 v46, v23, v46, s4
+; VI-NEXT: v_or_b32_e32 v20, v46, v20
; VI-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v20, v20, v56, s4
+; VI-NEXT: v_perm_b32 v20, v20, v44, s4
; VI-NEXT: v_or_b32_e32 v20, v20, v30
; VI-NEXT: v_add_u32_e32 v30, vcc, 4, v0
; VI-NEXT: buffer_store_dword v20, v30, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v20, v20, v46, s4
+; VI-NEXT: v_perm_b32 v20, v20, v52, s4
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_add_u32_e32 v20, vcc, 8, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
@@ -183913,11 +183971,11 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v19, v19, v44, s4
+; VI-NEXT: v_perm_b32 v19, v19, v50, s4
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_add_u32_e32 v19, vcc, 16, v0
; VI-NEXT: buffer_store_dword v18, v19, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v18, v43, s4
; VI-NEXT: v_or_b32_e32 v15, v18, v15
@@ -183968,7 +184026,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v9, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v12, v47, v28, s4
+; VI-NEXT: v_perm_b32 v12, v53, v28, s4
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v9, v10, s4
@@ -183988,7 +184046,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v10, v57, v26, s4
+; VI-NEXT: v_perm_b32 v10, v45, v26, s4
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v7, v9, s4
@@ -184012,13 +184070,13 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v7, v9, s4
-; VI-NEXT: v_perm_b32 v9, v59, v11, s4
+; VI-NEXT: v_perm_b32 v9, v47, v11, s4
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_u32_e32 v9, vcc, 60, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v7, v53, v14, s4
+; VI-NEXT: v_perm_b32 v7, v59, v14, s4
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v9, v1, s4
@@ -184053,7 +184111,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v1, v1, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v6, s4
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
@@ -184068,12 +184126,12 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v29, s4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v6, v50, v6, s4
+; VI-NEXT: v_perm_b32 v6, v56, v6, s4
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_or_b32_e32 v1, v1, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v33, s4
@@ -184093,7 +184151,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
@@ -184109,12 +184167,12 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v4, s4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v4, v51, v4, s4
+; VI-NEXT: v_perm_b32 v4, v57, v4, s4
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v4, s4
@@ -184136,7 +184194,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v3, s4
@@ -184171,14 +184229,14 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v2, v52, v2, s4
+; VI-NEXT: v_perm_b32 v2, v58, v2, s4
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -192649,778 +192707,809 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_writelane_b32 v40, s34, 0
-; SI-NEXT: v_writelane_b32 v40, s35, 1
-; SI-NEXT: v_writelane_b32 v40, s36, 2
-; SI-NEXT: v_writelane_b32 v40, s37, 3
-; SI-NEXT: v_writelane_b32 v40, s38, 4
-; SI-NEXT: v_writelane_b32 v40, s39, 5
-; SI-NEXT: v_writelane_b32 v40, s48, 6
-; SI-NEXT: v_writelane_b32 v40, s49, 7
-; SI-NEXT: v_writelane_b32 v40, s50, 8
-; SI-NEXT: v_writelane_b32 v40, s51, 9
-; SI-NEXT: v_writelane_b32 v40, s52, 10
-; SI-NEXT: v_writelane_b32 v40, s53, 11
-; SI-NEXT: v_writelane_b32 v40, s54, 12
-; SI-NEXT: v_writelane_b32 v40, s55, 13
-; SI-NEXT: v_writelane_b32 v40, s64, 14
-; SI-NEXT: v_writelane_b32 v40, s65, 15
-; SI-NEXT: v_writelane_b32 v40, s66, 16
-; SI-NEXT: v_writelane_b32 v40, s67, 17
-; SI-NEXT: v_writelane_b32 v40, s68, 18
-; SI-NEXT: v_writelane_b32 v40, s69, 19
-; SI-NEXT: v_writelane_b32 v40, s70, 20
-; SI-NEXT: v_writelane_b32 v40, s71, 21
-; SI-NEXT: v_writelane_b32 v40, s80, 22
-; SI-NEXT: v_writelane_b32 v40, s81, 23
-; SI-NEXT: v_writelane_b32 v40, s82, 24
-; SI-NEXT: v_writelane_b32 v40, s83, 25
-; SI-NEXT: v_writelane_b32 v40, s84, 26
-; SI-NEXT: v_writelane_b32 v40, s85, 27
-; SI-NEXT: v_writelane_b32 v40, s86, 28
-; SI-NEXT: v_writelane_b32 v40, s87, 29
-; SI-NEXT: v_writelane_b32 v40, s96, 30
-; SI-NEXT: v_writelane_b32 v40, s97, 31
-; SI-NEXT: v_writelane_b32 v40, s98, 32
-; SI-NEXT: v_writelane_b32 v40, s99, 33
-; SI-NEXT: v_writelane_b32 v40, s30, 34
-; SI-NEXT: v_writelane_b32 v40, s31, 35
-; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; SI-NEXT: v_writelane_b32 v45, s34, 0
+; SI-NEXT: v_writelane_b32 v45, s35, 1
+; SI-NEXT: v_writelane_b32 v45, s36, 2
+; SI-NEXT: v_writelane_b32 v45, s37, 3
+; SI-NEXT: v_writelane_b32 v45, s38, 4
+; SI-NEXT: v_writelane_b32 v45, s39, 5
+; SI-NEXT: v_writelane_b32 v45, s48, 6
+; SI-NEXT: v_writelane_b32 v45, s49, 7
+; SI-NEXT: v_writelane_b32 v45, s50, 8
+; SI-NEXT: v_writelane_b32 v45, s51, 9
+; SI-NEXT: v_writelane_b32 v45, s52, 10
+; SI-NEXT: v_writelane_b32 v45, s53, 11
+; SI-NEXT: v_writelane_b32 v45, s54, 12
+; SI-NEXT: v_writelane_b32 v45, s55, 13
+; SI-NEXT: v_writelane_b32 v45, s64, 14
+; SI-NEXT: v_writelane_b32 v45, s65, 15
+; SI-NEXT: v_writelane_b32 v45, s66, 16
+; SI-NEXT: v_writelane_b32 v45, s67, 17
+; SI-NEXT: v_writelane_b32 v45, s68, 18
+; SI-NEXT: v_writelane_b32 v45, s69, 19
+; SI-NEXT: v_writelane_b32 v45, s70, 20
+; SI-NEXT: v_writelane_b32 v45, s71, 21
+; SI-NEXT: v_writelane_b32 v45, s80, 22
+; SI-NEXT: v_writelane_b32 v45, s81, 23
+; SI-NEXT: v_writelane_b32 v45, s82, 24
+; SI-NEXT: v_writelane_b32 v45, s83, 25
+; SI-NEXT: v_writelane_b32 v45, s84, 26
+; SI-NEXT: v_writelane_b32 v45, s85, 27
+; SI-NEXT: v_writelane_b32 v45, s86, 28
+; SI-NEXT: v_writelane_b32 v45, s87, 29
+; SI-NEXT: v_writelane_b32 v45, s96, 30
+; SI-NEXT: v_writelane_b32 v45, s97, 31
+; SI-NEXT: v_writelane_b32 v45, s98, 32
+; SI-NEXT: v_writelane_b32 v45, s99, 33
+; SI-NEXT: v_writelane_b32 v45, s30, 34
+; SI-NEXT: v_writelane_b32 v45, s31, 35
+; SI-NEXT: ; implicit-def: $vgpr47 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s4, v30
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v42, s29, 0
-; SI-NEXT: v_writelane_b32 v42, s28, 1
-; SI-NEXT: v_writelane_b32 v42, s27, 2
-; SI-NEXT: v_writelane_b32 v42, s26, 3
-; SI-NEXT: v_writelane_b32 v42, s25, 4
-; SI-NEXT: v_writelane_b32 v42, s24, 5
-; SI-NEXT: v_writelane_b32 v42, s23, 6
-; SI-NEXT: v_writelane_b32 v42, s22, 7
-; SI-NEXT: v_writelane_b32 v42, s21, 8
-; SI-NEXT: v_writelane_b32 v42, s20, 9
-; SI-NEXT: v_writelane_b32 v42, s19, 10
-; SI-NEXT: v_writelane_b32 v42, s18, 11
-; SI-NEXT: v_writelane_b32 v42, s17, 12
-; SI-NEXT: v_writelane_b32 v42, s16, 13
-; SI-NEXT: v_writelane_b32 v42, s4, 14
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_writelane_b32 v47, s29, 0
+; SI-NEXT: v_writelane_b32 v47, s28, 1
+; SI-NEXT: v_writelane_b32 v47, s27, 2
+; SI-NEXT: v_writelane_b32 v47, s26, 3
+; SI-NEXT: v_writelane_b32 v47, s25, 4
+; SI-NEXT: v_writelane_b32 v47, s24, 5
+; SI-NEXT: v_writelane_b32 v47, s23, 6
+; SI-NEXT: v_writelane_b32 v47, s22, 7
+; SI-NEXT: v_writelane_b32 v47, s21, 8
+; SI-NEXT: v_writelane_b32 v47, s20, 9
+; SI-NEXT: v_writelane_b32 v47, s19, 10
+; SI-NEXT: v_writelane_b32 v47, s18, 11
+; SI-NEXT: v_writelane_b32 v47, s17, 12
+; SI-NEXT: v_writelane_b32 v47, s16, 13
+; SI-NEXT: v_writelane_b32 v47, s4, 14
; SI-NEXT: v_readfirstlane_b32 s4, v29
-; SI-NEXT: v_writelane_b32 v42, s4, 15
+; SI-NEXT: v_writelane_b32 v47, s4, 15
; SI-NEXT: v_readfirstlane_b32 s4, v28
-; SI-NEXT: v_writelane_b32 v42, s4, 16
+; SI-NEXT: v_writelane_b32 v47, s4, 16
; SI-NEXT: v_readfirstlane_b32 s4, v27
-; SI-NEXT: v_writelane_b32 v42, s4, 17
+; SI-NEXT: v_writelane_b32 v47, s4, 17
; SI-NEXT: v_readfirstlane_b32 s4, v26
-; SI-NEXT: v_writelane_b32 v42, s4, 18
+; SI-NEXT: v_writelane_b32 v47, s4, 18
; SI-NEXT: v_readfirstlane_b32 s4, v25
-; SI-NEXT: v_writelane_b32 v42, s4, 19
+; SI-NEXT: v_writelane_b32 v47, s4, 19
; SI-NEXT: v_readfirstlane_b32 s4, v24
-; SI-NEXT: v_writelane_b32 v42, s4, 20
+; SI-NEXT: v_writelane_b32 v47, s4, 20
; SI-NEXT: v_readfirstlane_b32 s4, v23
-; SI-NEXT: v_writelane_b32 v42, s4, 21
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:332
+; SI-NEXT: v_writelane_b32 v47, s4, 21
; SI-NEXT: v_readfirstlane_b32 s4, v22
-; SI-NEXT: v_writelane_b32 v42, s4, 22
+; SI-NEXT: v_writelane_b32 v47, s4, 22
; SI-NEXT: v_readfirstlane_b32 s4, v21
-; SI-NEXT: v_writelane_b32 v42, s4, 23
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:324
+; SI-NEXT: v_writelane_b32 v47, s4, 23
; SI-NEXT: v_readfirstlane_b32 s4, v20
-; SI-NEXT: v_writelane_b32 v42, s4, 24
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:320
+; SI-NEXT: v_writelane_b32 v47, s4, 24
; SI-NEXT: v_readfirstlane_b32 s4, v19
-; SI-NEXT: v_writelane_b32 v42, s4, 25
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:316
+; SI-NEXT: v_writelane_b32 v47, s4, 25
+; SI-NEXT: v_readfirstlane_b32 s4, v18
+; SI-NEXT: v_writelane_b32 v47, s4, 26
; SI-NEXT: v_readfirstlane_b32 s4, v17
-; SI-NEXT: v_writelane_b32 v42, s4, 26
+; SI-NEXT: v_writelane_b32 v47, s4, 27
; SI-NEXT: v_readfirstlane_b32 s4, v16
-; SI-NEXT: v_readfirstlane_b32 s70, v18
-; SI-NEXT: v_writelane_b32 v42, s4, 27
+; SI-NEXT: v_writelane_b32 v47, s4, 28
; SI-NEXT: v_readfirstlane_b32 s4, v15
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:232
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:324
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:316
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:304
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:300
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:296
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:292
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:284
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:280
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:276
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:268
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:264
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:260
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:252
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:248
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:244
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:332
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:236
-; SI-NEXT: v_writelane_b32 v42, s4, 28
+; SI-NEXT: v_writelane_b32 v47, s4, 29
; SI-NEXT: v_readfirstlane_b32 s4, v14
-; SI-NEXT: v_writelane_b32 v42, s4, 29
+; SI-NEXT: v_writelane_b32 v47, s4, 30
; SI-NEXT: v_readfirstlane_b32 s4, v13
-; SI-NEXT: v_writelane_b32 v42, s4, 30
+; SI-NEXT: v_writelane_b32 v47, s4, 31
; SI-NEXT: v_readfirstlane_b32 s4, v12
-; SI-NEXT: v_readfirstlane_b32 s81, v11
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:204
-; SI-NEXT: v_writelane_b32 v42, s4, 31
+; SI-NEXT: v_writelane_b32 v47, s4, 32
+; SI-NEXT: v_readfirstlane_b32 s4, v11
+; SI-NEXT: v_writelane_b32 v47, s4, 33
+; SI-NEXT: v_readfirstlane_b32 s4, v10
+; SI-NEXT: v_writelane_b32 v47, s4, 34
; SI-NEXT: v_readfirstlane_b32 s4, v9
-; SI-NEXT: v_writelane_b32 v42, s4, 32
+; SI-NEXT: v_writelane_b32 v47, s4, 35
; SI-NEXT: v_readfirstlane_b32 s4, v8
-; SI-NEXT: v_readfirstlane_b32 s78, v10
-; SI-NEXT: v_writelane_b32 v42, s4, 33
+; SI-NEXT: v_writelane_b32 v47, s4, 36
; SI-NEXT: v_readfirstlane_b32 s4, v7
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:196
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:188
-; SI-NEXT: v_writelane_b32 v42, s4, 34
+; SI-NEXT: v_writelane_b32 v47, s4, 37
; SI-NEXT: v_readfirstlane_b32 s4, v6
-; SI-NEXT: v_writelane_b32 v42, s4, 35
+; SI-NEXT: v_writelane_b32 v47, s4, 38
; SI-NEXT: v_readfirstlane_b32 s4, v5
-; SI-NEXT: v_writelane_b32 v42, s4, 36
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:300
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:292
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:288
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:284
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:276
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:264
+; SI-NEXT: v_writelane_b32 v47, s4, 39
; SI-NEXT: v_readfirstlane_b32 s4, v4
-; SI-NEXT: v_writelane_b32 v42, s4, 37
+; SI-NEXT: v_writelane_b32 v47, s4, 40
+; SI-NEXT: v_readfirstlane_b32 s4, v3
+; SI-NEXT: v_writelane_b32 v47, s4, 41
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268
+; SI-NEXT: v_readfirstlane_b32 s69, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260
+; SI-NEXT: ; implicit-def: $vgpr46 : SGPR spill to VGPR lane
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s4, v1
-; SI-NEXT: v_readfirstlane_b32 s37, v2
-; SI-NEXT: v_writelane_b32 v42, s4, 38
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:248
+; SI-NEXT: v_writelane_b32 v47, s4, 42
; SI-NEXT: v_readfirstlane_b32 s4, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176
-; SI-NEXT: v_writelane_b32 v42, s4, 39
-; SI-NEXT: v_readfirstlane_b32 s35, v3
-; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:244
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240
+; SI-NEXT: v_readfirstlane_b32 s83, v21
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:236
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:232
+; SI-NEXT: v_readfirstlane_b32 s86, v22
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:228
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:224
+; SI-NEXT: v_readfirstlane_b32 s99, v20
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:220
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:216
+; SI-NEXT: v_readfirstlane_b32 s17, v19
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208
+; SI-NEXT: v_writelane_b32 v47, s4, 43
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s97, v19
-; SI-NEXT: v_readfirstlane_b32 s58, v20
-; SI-NEXT: v_readfirstlane_b32 s59, v21
-; SI-NEXT: v_readfirstlane_b32 s28, v22
-; SI-NEXT: v_readfirstlane_b32 s21, v23
-; SI-NEXT: v_readfirstlane_b32 s60, v24
-; SI-NEXT: v_readfirstlane_b32 s75, v25
-; SI-NEXT: v_readfirstlane_b32 s79, v26
-; SI-NEXT: v_readfirstlane_b32 s96, v27
-; SI-NEXT: v_readfirstlane_b32 s4, v28
-; SI-NEXT: v_writelane_b32 v42, s4, 40
-; SI-NEXT: v_readfirstlane_b32 s46, v29
-; SI-NEXT: v_readfirstlane_b32 s57, v31
-; SI-NEXT: v_readfirstlane_b32 s56, v32
-; SI-NEXT: v_readfirstlane_b32 s74, v33
-; SI-NEXT: v_readfirstlane_b32 s26, v34
-; SI-NEXT: v_readfirstlane_b32 s47, v30
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:168
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:160
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:156
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:152
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:148
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:144
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:136
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:132
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:124
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:116
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:112
-; SI-NEXT: v_readfirstlane_b32 s88, v35
-; SI-NEXT: v_readfirstlane_b32 s16, v36
-; SI-NEXT: v_readfirstlane_b32 s4, v39
-; SI-NEXT: v_writelane_b32 v42, s4, 41
-; SI-NEXT: v_readfirstlane_b32 s4, v48
-; SI-NEXT: v_writelane_b32 v42, s4, 42
-; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_readfirstlane_b32 s83, v17
-; SI-NEXT: v_readfirstlane_b32 s22, v16
-; SI-NEXT: v_readfirstlane_b32 s69, v15
+; SI-NEXT: v_readfirstlane_b32 s66, v14
+; SI-NEXT: v_readfirstlane_b32 s84, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192
+; SI-NEXT: v_readfirstlane_b32 s8, v12
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:188
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:184
+; SI-NEXT: v_readfirstlane_b32 s9, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:176
+; SI-NEXT: v_readfirstlane_b32 s16, v10
+; SI-NEXT: v_readfirstlane_b32 s46, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:136
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:168
+; SI-NEXT: v_readfirstlane_b32 s24, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:156
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:152
+; SI-NEXT: v_readfirstlane_b32 s29, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:144
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:200
+; SI-NEXT: v_readfirstlane_b32 s10, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:120
+; SI-NEXT: v_readfirstlane_b32 s13, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:112
+; SI-NEXT: v_readfirstlane_b32 s19, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:160
+; SI-NEXT: v_readfirstlane_b32 s47, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:128
+; SI-NEXT: v_readfirstlane_b32 s27, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:100
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80
-; SI-NEXT: v_readfirstlane_b32 s27, v37
-; SI-NEXT: v_readfirstlane_b32 s85, v38
-; SI-NEXT: v_writelane_b32 v42, s4, 43
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:104
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s4, v14
-; SI-NEXT: v_readfirstlane_b32 s44, v13
-; SI-NEXT: v_readfirstlane_b32 s40, v12
-; SI-NEXT: v_readfirstlane_b32 s42, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v49
-; SI-NEXT: v_readfirstlane_b32 s15, v50
-; SI-NEXT: v_writelane_b32 v42, s4, 44
-; SI-NEXT: v_readfirstlane_b32 s86, v10
-; SI-NEXT: v_readfirstlane_b32 s87, v9
-; SI-NEXT: v_readfirstlane_b32 s25, v8
-; SI-NEXT: v_readfirstlane_b32 s4, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:16
-; SI-NEXT: v_readfirstlane_b32 s23, v51
-; SI-NEXT: v_writelane_b32 v42, s4, 45
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s82, v1
-; SI-NEXT: v_readfirstlane_b32 s45, v0
-; SI-NEXT: v_readfirstlane_b32 s41, v2
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: v_readfirstlane_b32 s63, v3
-; SI-NEXT: v_readfirstlane_b32 s67, v4
-; SI-NEXT: v_readfirstlane_b32 s66, v5
-; SI-NEXT: v_readfirstlane_b32 s17, v6
-; SI-NEXT: v_readfirstlane_b32 s24, v19
-; SI-NEXT: v_readfirstlane_b32 s4, v20
-; SI-NEXT: v_writelane_b32 v42, s4, 46
-; SI-NEXT: v_readfirstlane_b32 s13, v22
-; SI-NEXT: v_readfirstlane_b32 s14, v23
-; SI-NEXT: v_readfirstlane_b32 s51, v24
+; SI-NEXT: v_readfirstlane_b32 s28, v2
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:96
+; SI-NEXT: v_readfirstlane_b32 s54, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:88
+; SI-NEXT: v_readfirstlane_b32 s59, v17
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:72
+; SI-NEXT: v_readfirstlane_b32 s61, v18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:64
+; SI-NEXT: v_readfirstlane_b32 s44, v1
+; SI-NEXT: v_readfirstlane_b32 s52, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:40
+; SI-NEXT: v_readfirstlane_b32 s53, v24
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:32
+; SI-NEXT: v_readfirstlane_b32 s45, v22
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24
+; SI-NEXT: v_readfirstlane_b32 s60, v20
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:8
+; SI-NEXT: v_readfirstlane_b32 s62, v29
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:80
+; SI-NEXT: v_readfirstlane_b32 s14, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:56
+; SI-NEXT: v_readfirstlane_b32 s15, v23
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
+; SI-NEXT: v_readfirstlane_b32 s56, v25
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16
+; SI-NEXT: v_writelane_b32 v46, s54, 0
+; SI-NEXT: v_writelane_b32 v46, s53, 1
+; SI-NEXT: v_readfirstlane_b32 s40, v19
+; SI-NEXT: v_readfirstlane_b32 s50, v13
+; SI-NEXT: v_readfirstlane_b32 s64, v27
+; SI-NEXT: v_readfirstlane_b32 s85, v12
+; SI-NEXT: v_readfirstlane_b32 s58, v28
+; SI-NEXT: v_readfirstlane_b32 s57, v11
+; SI-NEXT: v_readfirstlane_b32 s11, v30
+; SI-NEXT: v_readfirstlane_b32 s7, v6
+; SI-NEXT: v_writelane_b32 v46, s7, 2
+; SI-NEXT: v_writelane_b32 v46, s64, 3
+; SI-NEXT: v_writelane_b32 v46, s44, 4
+; SI-NEXT: v_writelane_b32 v46, s85, 5
+; SI-NEXT: v_writelane_b32 v46, s8, 6
+; SI-NEXT: v_writelane_b32 v46, s45, 7
+; SI-NEXT: v_writelane_b32 v46, s46, 8
+; SI-NEXT: v_writelane_b32 v46, s47, 9
+; SI-NEXT: v_writelane_b32 v46, s56, 10
+; SI-NEXT: v_writelane_b32 v46, s9, 11
+; SI-NEXT: v_writelane_b32 v46, s57, 12
+; SI-NEXT: v_writelane_b32 v46, s58, 13
+; SI-NEXT: v_writelane_b32 v46, s10, 14
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s50, v25
-; SI-NEXT: v_readfirstlane_b32 s52, v26
-; SI-NEXT: v_readfirstlane_b32 s53, v27
-; SI-NEXT: v_readfirstlane_b32 s64, v28
-; SI-NEXT: v_readfirstlane_b32 s54, v29
-; SI-NEXT: v_readfirstlane_b32 s4, v21
-; SI-NEXT: v_writelane_b32 v42, s4, 47
-; SI-NEXT: v_readfirstlane_b32 s18, v30
-; SI-NEXT: v_readfirstlane_b32 s12, v15
-; SI-NEXT: v_readfirstlane_b32 s36, v16
-; SI-NEXT: v_readfirstlane_b32 s34, v17
-; SI-NEXT: v_readfirstlane_b32 s38, v18
-; SI-NEXT: v_readfirstlane_b32 s39, v31
-; SI-NEXT: v_readfirstlane_b32 s49, v32
+; SI-NEXT: v_readfirstlane_b32 s92, v3
+; SI-NEXT: v_writelane_b32 v46, s11, 15
+; SI-NEXT: v_readfirstlane_b32 s12, v10
+; SI-NEXT: v_readfirstlane_b32 s30, v37
+; SI-NEXT: v_writelane_b32 v46, s59, 16
+; SI-NEXT: v_readfirstlane_b32 s36, v7
+; SI-NEXT: v_writelane_b32 v46, s12, 17
; SI-NEXT: v_readfirstlane_b32 s48, v33
-; SI-NEXT: v_writelane_b32 v41, s48, 0
-; SI-NEXT: v_readfirstlane_b32 s10, v34
-; SI-NEXT: v_writelane_b32 v41, s49, 1
-; SI-NEXT: v_writelane_b32 v41, s10, 2
-; SI-NEXT: v_writelane_b32 v41, s50, 3
-; SI-NEXT: v_readfirstlane_b32 s11, v11
-; SI-NEXT: v_writelane_b32 v41, s51, 4
-; SI-NEXT: v_writelane_b32 v41, s11, 5
-; SI-NEXT: v_writelane_b32 v41, s52, 6
-; SI-NEXT: v_writelane_b32 v41, s53, 7
-; SI-NEXT: v_writelane_b32 v41, s54, 8
-; SI-NEXT: v_writelane_b32 v41, s64, 9
-; SI-NEXT: v_writelane_b32 v41, s66, 10
-; SI-NEXT: v_writelane_b32 v41, s67, 11
-; SI-NEXT: v_writelane_b32 v41, s83, 12
-; SI-NEXT: v_writelane_b32 v41, s86, 13
-; SI-NEXT: v_writelane_b32 v41, s12, 14
-; SI-NEXT: v_writelane_b32 v41, s87, 15
-; SI-NEXT: v_writelane_b32 v41, s13, 16
-; SI-NEXT: v_writelane_b32 v41, s14, 17
-; SI-NEXT: v_writelane_b32 v41, s85, 18
-; SI-NEXT: v_writelane_b32 v41, s15, 19
-; SI-NEXT: v_writelane_b32 v41, s44, 20
+; SI-NEXT: v_writelane_b32 v46, s60, 18
+; SI-NEXT: v_writelane_b32 v46, s61, 19
+; SI-NEXT: v_writelane_b32 v46, s13, 20
+; SI-NEXT: v_writelane_b32 v46, s62, 21
+; SI-NEXT: v_readfirstlane_b32 s6, v34
+; SI-NEXT: v_writelane_b32 v46, s14, 22
+; SI-NEXT: v_writelane_b32 v46, s15, 23
+; SI-NEXT: v_readfirstlane_b32 s41, v14
+; SI-NEXT: v_readfirstlane_b32 s51, v26
+; SI-NEXT: v_readfirstlane_b32 s87, v31
+; SI-NEXT: v_readfirstlane_b32 s23, v9
+; SI-NEXT: v_readfirstlane_b32 s25, v32
+; SI-NEXT: v_readfirstlane_b32 s26, v8
+; SI-NEXT: v_readfirstlane_b32 s4, v51
+; SI-NEXT: v_writelane_b32 v47, s4, 44
+; SI-NEXT: v_readfirstlane_b32 s4, v18
+; SI-NEXT: v_writelane_b32 v47, s4, 45
+; SI-NEXT: v_readfirstlane_b32 s4, v52
+; SI-NEXT: v_writelane_b32 v47, s4, 46
+; SI-NEXT: v_readfirstlane_b32 s4, v55
+; SI-NEXT: v_writelane_b32 v47, s4, 47
+; SI-NEXT: v_readfirstlane_b32 s4, v24
+; SI-NEXT: v_writelane_b32 v47, s4, 48
+; SI-NEXT: v_readfirstlane_b32 s4, v40
+; SI-NEXT: v_writelane_b32 v47, s4, 49
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_readfirstlane_b32 s4, v41
+; SI-NEXT: v_writelane_b32 v47, s4, 50
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_readfirstlane_b32 s4, v43
+; SI-NEXT: v_writelane_b32 v47, s4, 51
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_readfirstlane_b32 s4, v29
+; SI-NEXT: v_writelane_b32 v47, s4, 52
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_readfirstlane_b32 s4, v44
+; SI-NEXT: v_writelane_b32 v47, s4, 53
+; SI-NEXT: v_writelane_b32 v47, s92, 54
+; SI-NEXT: v_writelane_b32 v47, s30, 55
+; SI-NEXT: v_writelane_b32 v47, s36, 56
+; SI-NEXT: v_writelane_b32 v47, s48, 57
+; SI-NEXT: v_writelane_b32 v47, s66, 58
+; SI-NEXT: v_writelane_b32 v47, s52, 59
+; SI-NEXT: v_writelane_b32 v47, s84, 60
+; SI-NEXT: v_writelane_b32 v47, s6, 61
+; SI-NEXT: v_readfirstlane_b32 s67, v35
+; SI-NEXT: v_readfirstlane_b32 s94, v5
+; SI-NEXT: v_readfirstlane_b32 s65, v36
+; SI-NEXT: v_readfirstlane_b32 s22, v4
+; SI-NEXT: v_readfirstlane_b32 s18, v38
+; SI-NEXT: v_readfirstlane_b32 s20, v15
+; SI-NEXT: v_readfirstlane_b32 s35, v39
+; SI-NEXT: v_readfirstlane_b32 s31, v2
+; SI-NEXT: v_readfirstlane_b32 s78, v48
+; SI-NEXT: v_readfirstlane_b32 s98, v16
+; SI-NEXT: v_readfirstlane_b32 s97, v49
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_readfirstlane_b32 s55, v1
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_readfirstlane_b32 s81, v50
+; SI-NEXT: v_readfirstlane_b32 s71, v17
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_readfirstlane_b32 s19, v49
-; SI-NEXT: v_writelane_b32 v41, s82, 21
-; SI-NEXT: v_readfirstlane_b32 s20, v48
-; SI-NEXT: v_writelane_b32 v42, s19, 48
-; SI-NEXT: v_writelane_b32 v41, s23, 22
-; SI-NEXT: v_readfirstlane_b32 s76, v13
-; SI-NEXT: v_writelane_b32 v42, s20, 49
-; SI-NEXT: v_writelane_b32 v41, s45, 23
-; SI-NEXT: v_readfirstlane_b32 s77, v12
-; SI-NEXT: v_writelane_b32 v42, s76, 50
-; SI-NEXT: v_writelane_b32 v41, s46, 24
+; SI-NEXT: v_readfirstlane_b32 s96, v0
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_readfirstlane_b32 s6, v50
-; SI-NEXT: v_writelane_b32 v42, s77, 51
-; SI-NEXT: v_writelane_b32 v41, s47, 25
+; SI-NEXT: v_readfirstlane_b32 s79, v53
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_readfirstlane_b32 s7, v0
-; SI-NEXT: v_writelane_b32 v42, s6, 52
-; SI-NEXT: v_writelane_b32 v41, s40, 26
-; SI-NEXT: v_readfirstlane_b32 s43, v14
-; SI-NEXT: v_writelane_b32 v42, s7, 53
-; SI-NEXT: v_writelane_b32 v41, s41, 27
-; SI-NEXT: v_readfirstlane_b32 vcc_lo, v35
-; SI-NEXT: v_writelane_b32 v42, s43, 54
-; SI-NEXT: v_writelane_b32 v41, s42, 28
-; SI-NEXT: v_readfirstlane_b32 vcc_hi, v37
-; SI-NEXT: v_writelane_b32 v42, vcc_lo, 55
-; SI-NEXT: v_writelane_b32 v41, s56, 29
-; SI-NEXT: v_readfirstlane_b32 s30, v36
-; SI-NEXT: v_writelane_b32 v42, vcc_hi, 56
-; SI-NEXT: v_writelane_b32 v41, s57, 30
-; SI-NEXT: v_writelane_b32 v42, s30, 57
-; SI-NEXT: v_writelane_b32 v41, s63, 31
-; SI-NEXT: v_writelane_b32 v42, s34, 58
-; SI-NEXT: v_writelane_b32 v41, s74, 32
-; SI-NEXT: v_readfirstlane_b32 s8, v38
-; SI-NEXT: v_writelane_b32 v42, s36, 59
-; SI-NEXT: v_writelane_b32 v41, s26, 33
-; SI-NEXT: v_readfirstlane_b32 s9, v7
-; SI-NEXT: v_writelane_b32 v42, s8, 60
-; SI-NEXT: v_writelane_b32 v41, s75, 34
-; SI-NEXT: v_writelane_b32 v42, s9, 61
-; SI-NEXT: v_writelane_b32 v41, s79, 35
-; SI-NEXT: v_readfirstlane_b32 s80, v8
-; SI-NEXT: v_readfirstlane_b32 s98, v9
-; SI-NEXT: v_readfirstlane_b32 s55, v10
-; SI-NEXT: v_readfirstlane_b32 s99, v39
+; SI-NEXT: v_readfirstlane_b32 s90, v23
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_readfirstlane_b32 s65, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_readfirstlane_b32 s71, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s84, v51
-; SI-NEXT: v_writelane_b32 v42, s38, 62
-; SI-NEXT: v_writelane_b32 v41, s58, 36
-; SI-NEXT: v_writelane_b32 v42, s39, 63
-; SI-NEXT: v_writelane_b32 v41, s28, 37
+; SI-NEXT: v_readfirstlane_b32 s37, v54
+; SI-NEXT: v_readfirstlane_b32 s82, v21
+; SI-NEXT: v_readfirstlane_b32 s80, v22
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_readfirstlane_b32 s70, v25
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_readfirstlane_b32 s76, v42
+; SI-NEXT: v_readfirstlane_b32 s21, v20
+; SI-NEXT: v_writelane_b32 v47, s50, 62
+; SI-NEXT: v_writelane_b32 v46, s40, 24
+; SI-NEXT: v_writelane_b32 v47, s51, 63
+; SI-NEXT: v_writelane_b32 v46, s41, 25
; SI-NEXT: s_cbranch_scc0 .LBB97_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_readlane_b32 s4, v42, 13
-; SI-NEXT: v_readlane_b32 s5, v42, 12
+; SI-NEXT: v_readlane_b32 s4, v47, 13
+; SI-NEXT: v_readlane_b32 s5, v47, 12
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 38
-; SI-NEXT: v_readlane_b32 s4, v42, 5
-; SI-NEXT: v_readlane_b32 s5, v42, 4
+; SI-NEXT: v_writelane_b32 v46, s4, 26
+; SI-NEXT: v_readlane_b32 s4, v47, 5
+; SI-NEXT: v_readlane_b32 s5, v47, 4
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 40
-; SI-NEXT: s_and_b32 s4, s37, 0xff
-; SI-NEXT: s_lshl_b32 s5, s35, 8
+; SI-NEXT: v_readlane_b32 s5, v47, 41
+; SI-NEXT: v_writelane_b32 v46, s4, 28
+; SI-NEXT: s_and_b32 s4, s69, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 8
+; SI-NEXT: v_writelane_b32 v46, s69, 44
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 42
-; SI-NEXT: v_writelane_b32 v41, s27, 46
-; SI-NEXT: s_and_b32 s4, s78, 0xff
-; SI-NEXT: s_lshl_b32 s5, s81, 8
-; SI-NEXT: v_writelane_b32 v41, s96, 47
+; SI-NEXT: v_writelane_b32 v46, s4, 30
+; SI-NEXT: v_readlane_b32 s4, v47, 34
+; SI-NEXT: v_readlane_b32 s5, v47, 33
+; SI-NEXT: s_and_b32 s4, s4, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_readlane_b32 s5, v42, 25
-; SI-NEXT: v_writelane_b32 v41, s4, 44
-; SI-NEXT: s_and_b32 s4, s70, 0xff
+; SI-NEXT: v_writelane_b32 v46, s4, 32
+; SI-NEXT: v_readlane_b32 s4, v47, 26
+; SI-NEXT: v_readlane_b32 s5, v47, 25
+; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 48
-; SI-NEXT: v_readlane_b32 s4, v42, 18
-; SI-NEXT: v_readlane_b32 s5, v42, 17
+; SI-NEXT: v_writelane_b32 v46, s4, 34
+; SI-NEXT: v_readlane_b32 s4, v47, 18
+; SI-NEXT: v_readlane_b32 s5, v47, 17
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 49
-; SI-NEXT: s_and_b32 s4, s7, 0xff
-; SI-NEXT: s_lshl_b32 s5, s6, 8
+; SI-NEXT: v_writelane_b32 v46, s4, 36
+; SI-NEXT: s_and_b32 s4, s21, 0xff
+; SI-NEXT: s_lshl_b32 s5, s76, 8
+; SI-NEXT: v_writelane_b32 v46, s24, 45
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 50
-; SI-NEXT: s_and_b32 s4, s9, 0xff
-; SI-NEXT: s_lshl_b32 s5, s8, 8
+; SI-NEXT: v_writelane_b32 v46, s4, 38
+; SI-NEXT: s_and_b32 s4, s82, 0xff
+; SI-NEXT: s_lshl_b32 s5, s37, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 51
-; SI-NEXT: s_and_b32 s4, s11, 0xff
-; SI-NEXT: s_lshl_b32 s5, s10, 8
+; SI-NEXT: v_writelane_b32 v46, s4, 40
+; SI-NEXT: s_and_b32 s4, s71, 0xff
+; SI-NEXT: s_lshl_b32 s5, s81, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: v_writelane_b32 v41, s4, 52
-; SI-NEXT: s_and_b32 s4, s12, 0xff
+; SI-NEXT: v_writelane_b32 v46, s4, 42
+; SI-NEXT: s_and_b32 s4, s20, 0xff
; SI-NEXT: s_lshl_b32 s5, s18, 8
-; SI-NEXT: s_or_b32 s61, s4, s5
-; SI-NEXT: s_and_b32 s4, s14, 0xff
-; SI-NEXT: s_lshl_b32 s5, s13, 8
-; SI-NEXT: s_or_b32 s62, s4, s5
-; SI-NEXT: s_and_b32 s4, s63, 0xff
-; SI-NEXT: s_lshl_b32 s5, s41, 8
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_writelane_b32 v46, s4, 46
+; SI-NEXT: s_and_b32 s4, s7, 0xff
+; SI-NEXT: s_lshl_b32 s5, s6, 8
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_writelane_b32 v46, s4, 47
+; SI-NEXT: s_and_b32 s4, s12, 0xff
+; SI-NEXT: s_lshl_b32 s5, s11, 8
; SI-NEXT: s_or_b32 s63, s4, s5
-; SI-NEXT: s_and_b32 s4, s42, 0xff
+; SI-NEXT: s_and_b32 s4, s41, 0xff
; SI-NEXT: s_lshl_b32 s5, s40, 8
; SI-NEXT: s_or_b32 s72, s4, s5
-; SI-NEXT: s_and_b32 s4, s23, 0xff
-; SI-NEXT: s_lshl_b32 s5, s15, 8
+; SI-NEXT: s_and_b32 s4, s15, 0xff
+; SI-NEXT: s_lshl_b32 s5, s14, 8
; SI-NEXT: s_or_b32 s73, s4, s5
-; SI-NEXT: s_and_b32 s4, s26, 0xff
-; SI-NEXT: s_lshl_b32 s5, s74, 8
+; SI-NEXT: s_and_b32 s4, s13, 0xff
+; SI-NEXT: s_lshl_b32 s5, s10, 8
; SI-NEXT: s_or_b32 s74, s4, s5
-; SI-NEXT: s_and_b32 s4, s79, 0xff
-; SI-NEXT: s_lshl_b32 s5, s75, 8
+; SI-NEXT: s_and_b32 s4, s9, 0xff
+; SI-NEXT: s_lshl_b32 s5, s8, 8
; SI-NEXT: s_or_b32 s75, s4, s5
-; SI-NEXT: v_readlane_b32 s4, v42, 9
-; SI-NEXT: v_readlane_b32 s5, v42, 8
+; SI-NEXT: v_readlane_b32 s4, v47, 9
+; SI-NEXT: v_readlane_b32 s5, v47, 8
; SI-NEXT: s_and_b32 s4, s4, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
; SI-NEXT: s_or_b32 s5, s4, s5
-; SI-NEXT: v_readlane_b32 s4, v42, 7
+; SI-NEXT: v_readlane_b32 s4, v47, 7
; SI-NEXT: s_and_b32 s4, s4, 0xff
-; SI-NEXT: v_readlane_b32 s6, v42, 6
+; SI-NEXT: v_readlane_b32 s6, v47, 6
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s6, s6, 24
-; SI-NEXT: s_or_b32 s79, s6, s4
-; SI-NEXT: v_readlane_b32 s4, v42, 11
+; SI-NEXT: s_or_b32 s68, s6, s4
+; SI-NEXT: v_readlane_b32 s4, v47, 11
; SI-NEXT: s_and_b32 s4, s4, 0xff
-; SI-NEXT: v_readlane_b32 s6, v42, 10
+; SI-NEXT: v_readlane_b32 s6, v47, 10
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s6, s6, 24
; SI-NEXT: s_or_b32 s4, s6, s4
-; SI-NEXT: v_readlane_b32 s6, v42, 1
-; SI-NEXT: v_readlane_b32 s7, v42, 0
+; SI-NEXT: v_readlane_b32 s6, v47, 1
+; SI-NEXT: v_readlane_b32 s7, v47, 0
; SI-NEXT: s_and_b32 s6, s6, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_or_b32 s7, s6, s7
-; SI-NEXT: v_readlane_b32 s6, v42, 39
+; SI-NEXT: v_readlane_b32 s6, v47, 43
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s8, v42, 38
+; SI-NEXT: v_readlane_b32 s8, v47, 42
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s8, s8, 24
-; SI-NEXT: s_or_b32 s89, s8, s6
-; SI-NEXT: v_readlane_b32 s6, v42, 3
+; SI-NEXT: s_or_b32 s91, s8, s6
+; SI-NEXT: v_readlane_b32 s6, v47, 3
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s8, v42, 2
+; SI-NEXT: v_readlane_b32 s8, v47, 2
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s8, s8, 24
; SI-NEXT: s_or_b32 s6, s8, s6
-; SI-NEXT: v_readlane_b32 s8, v42, 35
-; SI-NEXT: v_readlane_b32 s9, v42, 34
+; SI-NEXT: v_readlane_b32 s8, v47, 38
+; SI-NEXT: v_readlane_b32 s9, v47, 37
; SI-NEXT: s_and_b32 s8, s8, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 8
; SI-NEXT: s_or_b32 s9, s8, s9
-; SI-NEXT: v_readlane_b32 s8, v42, 33
+; SI-NEXT: v_readlane_b32 s8, v47, 36
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s10, v42, 32
+; SI-NEXT: v_readlane_b32 s10, v47, 35
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_lshl_b32 s10, s10, 24
-; SI-NEXT: s_or_b32 s23, s10, s8
-; SI-NEXT: v_readlane_b32 s8, v42, 37
+; SI-NEXT: s_or_b32 s88, s10, s8
+; SI-NEXT: v_readlane_b32 s8, v47, 40
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s10, v42, 36
+; SI-NEXT: v_readlane_b32 s10, v47, 39
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_lshl_b32 s10, s10, 24
; SI-NEXT: s_or_b32 s8, s10, s8
-; SI-NEXT: v_readlane_b32 s10, v42, 29
-; SI-NEXT: v_readlane_b32 s11, v42, 28
+; SI-NEXT: v_readlane_b32 s10, v47, 30
+; SI-NEXT: v_readlane_b32 s11, v47, 29
; SI-NEXT: s_and_b32 s10, s10, 0xff
; SI-NEXT: s_lshl_b32 s11, s11, 8
; SI-NEXT: s_or_b32 s11, s10, s11
-; SI-NEXT: v_readlane_b32 s10, v42, 27
+; SI-NEXT: v_readlane_b32 s10, v47, 28
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s12, v42, 26
+; SI-NEXT: v_readlane_b32 s12, v47, 27
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_lshl_b32 s12, s12, 24
-; SI-NEXT: s_or_b32 s93, s12, s10
-; SI-NEXT: v_readlane_b32 s10, v42, 31
+; SI-NEXT: s_or_b32 s95, s12, s10
+; SI-NEXT: v_readlane_b32 s10, v47, 32
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s12, v42, 30
+; SI-NEXT: v_readlane_b32 s12, v47, 31
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_lshl_b32 s12, s12, 24
; SI-NEXT: s_or_b32 s10, s12, s10
-; SI-NEXT: v_readlane_b32 s12, v42, 22
-; SI-NEXT: v_readlane_b32 s13, v42, 21
+; SI-NEXT: v_readlane_b32 s12, v47, 22
+; SI-NEXT: v_readlane_b32 s13, v47, 21
; SI-NEXT: s_and_b32 s12, s12, 0xff
; SI-NEXT: s_lshl_b32 s13, s13, 8
; SI-NEXT: s_or_b32 s13, s12, s13
-; SI-NEXT: v_readlane_b32 s12, v42, 20
+; SI-NEXT: v_readlane_b32 s12, v47, 20
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s14, v42, 19
+; SI-NEXT: v_readlane_b32 s14, v47, 19
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_lshl_b32 s14, s14, 24
-; SI-NEXT: s_or_b32 s95, s14, s12
-; SI-NEXT: v_readlane_b32 s12, v42, 24
+; SI-NEXT: s_or_b32 s89, s14, s12
+; SI-NEXT: v_readlane_b32 s12, v47, 24
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s14, v42, 23
+; SI-NEXT: v_readlane_b32 s14, v47, 23
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_lshl_b32 s14, s14, 24
; SI-NEXT: s_or_b32 s12, s14, s12
-; SI-NEXT: v_readlane_b32 s14, v42, 14
+; SI-NEXT: v_readlane_b32 s14, v47, 14
+; SI-NEXT: v_readlane_b32 s15, v47, 53
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: s_lshl_b32 s15, s84, 8
+; SI-NEXT: s_lshl_b32 s15, s15, 8
+; SI-NEXT: v_writelane_b32 v46, s71, 48
; SI-NEXT: s_or_b32 s15, s14, s15
-; SI-NEXT: s_and_b32 s14, s71, 0xff
-; SI-NEXT: v_writelane_b32 v41, s18, 53
+; SI-NEXT: v_readlane_b32 s14, v47, 52
+; SI-NEXT: s_and_b32 s14, s14, 0xff
+; SI-NEXT: v_writelane_b32 v46, s16, 49
+; SI-NEXT: v_readlane_b32 s16, v47, 51
; SI-NEXT: s_lshl_b32 s14, s14, 16
-; SI-NEXT: s_mov_b32 s68, s17
-; SI-NEXT: s_lshl_b32 s17, s65, 24
-; SI-NEXT: v_writelane_b32 v41, s88, 54
-; SI-NEXT: s_or_b32 s91, s17, s14
-; SI-NEXT: v_readlane_b32 s14, v42, 16
+; SI-NEXT: v_writelane_b32 v46, s18, 50
+; SI-NEXT: s_lshl_b32 s18, s16, 24
+; SI-NEXT: s_or_b32 s93, s18, s14
+; SI-NEXT: v_readlane_b32 s14, v47, 16
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_writelane_b32 v41, s69, 55
-; SI-NEXT: s_mov_b32 s69, s25
-; SI-NEXT: s_mov_b32 s25, s22
-; SI-NEXT: s_mov_b32 s22, s24
-; SI-NEXT: s_mov_b32 s24, s16
-; SI-NEXT: v_readlane_b32 s16, v42, 15
+; SI-NEXT: v_readlane_b32 s16, v47, 15
; SI-NEXT: s_lshl_b32 s14, s14, 16
-; SI-NEXT: s_lshl_b32 s17, s16, 24
-; SI-NEXT: s_or_b32 s14, s17, s14
-; SI-NEXT: s_and_b32 s17, s99, 0xff
-; SI-NEXT: s_lshl_b32 s40, s55, 8
-; SI-NEXT: s_or_b32 s41, s17, s40
-; SI-NEXT: s_and_b32 s17, s98, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s40, s80, 24
-; SI-NEXT: s_or_b32 s88, s40, s17
-; SI-NEXT: s_and_b32 s40, s19, 0xff
+; SI-NEXT: s_lshl_b32 s18, s16, 24
+; SI-NEXT: v_readlane_b32 s16, v47, 49
+; SI-NEXT: s_or_b32 s14, s18, s14
+; SI-NEXT: s_and_b32 s18, s80, 0xff
+; SI-NEXT: s_lshl_b32 s40, s16, 8
+; SI-NEXT: v_readlane_b32 s16, v47, 48
+; SI-NEXT: s_or_b32 s41, s18, s40
+; SI-NEXT: s_and_b32 s18, s16, 0xff
+; SI-NEXT: v_readlane_b32 s16, v47, 47
+; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_lshl_b32 s40, s16, 24
+; SI-NEXT: s_mov_b32 s24, s21
+; SI-NEXT: s_or_b32 s21, s40, s18
+; SI-NEXT: s_and_b32 s40, s70, 0xff
+; SI-NEXT: v_readlane_b32 s18, v47, 50
; SI-NEXT: s_lshl_b32 s40, s40, 16
-; SI-NEXT: s_lshl_b32 s42, s20, 24
+; SI-NEXT: s_lshl_b32 s42, s18, 24
+; SI-NEXT: v_readlane_b32 s18, v47, 46
; SI-NEXT: s_or_b32 s40, s42, s40
-; SI-NEXT: s_and_b32 s42, vcc_lo, 0xff
-; SI-NEXT: s_lshl_b32 s43, s43, 8
+; SI-NEXT: s_and_b32 s42, s96, 0xff
+; SI-NEXT: s_lshl_b32 s43, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v47, 45
; SI-NEXT: s_or_b32 s43, s42, s43
-; SI-NEXT: s_and_b32 s42, s76, 0xff
+; SI-NEXT: s_and_b32 s42, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v47, 44
+; SI-NEXT: s_mov_b32 s34, s76
; SI-NEXT: s_lshl_b32 s42, s42, 16
-; SI-NEXT: s_lshl_b32 s76, s77, 24
-; SI-NEXT: s_or_b32 s19, s76, s42
-; SI-NEXT: s_and_b32 s42, vcc_hi, 0xff
+; SI-NEXT: s_lshl_b32 s76, s18, 24
+; SI-NEXT: s_or_b32 s69, s76, s42
+; SI-NEXT: s_and_b32 s42, s90, 0xff
; SI-NEXT: s_lshl_b32 s42, s42, 16
-; SI-NEXT: s_lshl_b32 s76, s30, 24
+; SI-NEXT: s_lshl_b32 s76, s79, 24
; SI-NEXT: s_or_b32 s42, s76, s42
-; SI-NEXT: s_and_b32 s76, s39, 0xff
-; SI-NEXT: s_lshl_b32 s77, s38, 8
+; SI-NEXT: s_and_b32 s76, s98, 0xff
+; SI-NEXT: s_lshl_b32 s77, s78, 8
+; SI-NEXT: v_writelane_b32 v46, s20, 51
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s34, 0xff
-; SI-NEXT: s_mov_b32 s27, s78
+; SI-NEXT: s_and_b32 s77, s31, 0xff
+; SI-NEXT: v_writelane_b32 v46, s78, 52
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s36, 24
-; SI-NEXT: s_mov_b32 s29, s70
+; SI-NEXT: s_lshl_b32 s78, s35, 24
+; SI-NEXT: s_mov_b32 s16, s70
; SI-NEXT: s_or_b32 s70, s78, s77
-; SI-NEXT: s_and_b32 s77, s48, 0xff
+; SI-NEXT: s_and_b32 s77, s55, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s49, 24
+; SI-NEXT: s_lshl_b32 s78, s97, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
; SI-NEXT: s_or_b32 vcc_lo, s78, s77
; SI-NEXT: s_or_b32 vcc_hi, s76, s70
-; SI-NEXT: s_and_b32 s76, s53, 0xff
-; SI-NEXT: s_lshl_b32 s77, s52, 8
+; SI-NEXT: s_and_b32 s76, s22, 0xff
+; SI-NEXT: s_lshl_b32 s77, s65, 8
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s50, 0xff
+; SI-NEXT: s_and_b32 s77, s94, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s51, 24
-; SI-NEXT: v_writelane_b32 v41, s65, 56
-; SI-NEXT: v_writelane_b32 v41, s71, 57
+; SI-NEXT: s_lshl_b32 s78, s67, 24
; SI-NEXT: s_or_b32 s71, s78, s77
-; SI-NEXT: s_and_b32 s77, s54, 0xff
-; SI-NEXT: v_writelane_b32 v41, s29, 58
+; SI-NEXT: s_and_b32 s77, s92, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s64, 24
+; SI-NEXT: s_lshl_b32 s78, s30, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s27, 59
; SI-NEXT: s_or_b32 s38, s78, s77
; SI-NEXT: s_or_b32 s39, s76, s71
-; SI-NEXT: s_and_b32 s76, s22, 0xff
-; SI-NEXT: s_lshl_b32 s77, s68, 8
+; SI-NEXT: s_and_b32 s76, s26, 0xff
+; SI-NEXT: s_lshl_b32 s77, s25, 8
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s66, 0xff
-; SI-NEXT: v_writelane_b32 v41, s99, 60
+; SI-NEXT: s_and_b32 s77, s23, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s67, 24
-; SI-NEXT: v_writelane_b32 v41, s55, 61
-; SI-NEXT: v_readlane_b32 s16, v42, 47
-; SI-NEXT: v_writelane_b32 v41, s80, 62
+; SI-NEXT: s_lshl_b32 s78, s87, 24
+; SI-NEXT: v_writelane_b32 v46, s80, 53
; SI-NEXT: s_or_b32 s80, s78, s77
-; SI-NEXT: s_and_b32 s77, s16, 0xff
-; SI-NEXT: v_readlane_b32 s16, v42, 46
+; SI-NEXT: s_and_b32 s77, s36, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_lshl_b32 s78, s48, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_readlane_b32 s16, v42, 45
; SI-NEXT: s_or_b32 s48, s78, s77
; SI-NEXT: s_or_b32 s49, s76, s80
-; SI-NEXT: s_and_b32 s76, s16, 0xff
-; SI-NEXT: s_lshl_b32 s77, s69, 8
+; SI-NEXT: s_and_b32 s76, s85, 0xff
+; SI-NEXT: s_lshl_b32 s77, s64, 8
+; SI-NEXT: v_writelane_b32 v46, s98, 54
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s87, 0xff
+; SI-NEXT: s_and_b32 s77, s50, 0xff
+; SI-NEXT: v_writelane_b32 v46, s24, 55
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s86, 24
-; SI-NEXT: s_mov_b32 s92, s81
-; SI-NEXT: v_writelane_b32 v41, s98, 63
+; SI-NEXT: s_lshl_b32 s78, s51, 24
+; SI-NEXT: v_writelane_b32 v46, s34, 56
+; SI-NEXT: v_writelane_b32 v46, s81, 57
; SI-NEXT: s_or_b32 s81, s78, s77
-; SI-NEXT: s_and_b32 s77, s45, 0xff
+; SI-NEXT: s_and_b32 s77, s57, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s82, 24
+; SI-NEXT: s_lshl_b32 s78, s58, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_readlane_b32 s16, v41, 55
; SI-NEXT: s_or_b32 s50, s78, s77
; SI-NEXT: s_or_b32 s51, s76, s81
-; SI-NEXT: s_and_b32 s76, s16, 0xff
-; SI-NEXT: s_lshl_b32 s77, s25, 8
+; SI-NEXT: s_and_b32 s76, s56, 0xff
+; SI-NEXT: s_lshl_b32 s77, s45, 8
+; SI-NEXT: v_writelane_b32 v46, s22, 58
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s83, 0xff
-; SI-NEXT: v_readlane_b32 s16, v42, 43
+; SI-NEXT: s_and_b32 s77, s53, 0xff
+; SI-NEXT: v_writelane_b32 v46, s65, 59
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_lshl_b32 s78, s52, 24
+; SI-NEXT: v_writelane_b32 v46, s67, 60
+; SI-NEXT: v_writelane_b32 v46, s94, 61
+; SI-NEXT: s_mov_b32 s94, s82
; SI-NEXT: s_or_b32 s82, s78, s77
-; SI-NEXT: s_and_b32 s77, s44, 0xff
-; SI-NEXT: v_readlane_b32 s16, v42, 44
+; SI-NEXT: s_and_b32 s77, s62, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_lshl_b32 s78, s60, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_readlane_b32 s16, v41, 46
; SI-NEXT: s_or_b32 s52, s78, s77
; SI-NEXT: s_or_b32 s53, s76, s82
-; SI-NEXT: s_and_b32 s76, s85, 0xff
-; SI-NEXT: s_lshl_b32 s77, s16, 8
+; SI-NEXT: s_and_b32 s76, s44, 0xff
+; SI-NEXT: s_lshl_b32 s77, s54, 8
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s24, 0xff
-; SI-NEXT: v_readlane_b32 s16, v41, 54
+; SI-NEXT: s_and_b32 s77, s28, 0xff
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
-; SI-NEXT: v_readlane_b32 s16, v42, 42
-; SI-NEXT: s_mov_b32 s18, s84
-; SI-NEXT: s_or_b32 s84, s78, s77
-; SI-NEXT: s_and_b32 s77, s16, 0xff
-; SI-NEXT: v_readlane_b32 s16, v42, 41
+; SI-NEXT: s_lshl_b32 s78, s27, 24
+; SI-NEXT: v_writelane_b32 v46, s97, 62
+; SI-NEXT: s_mov_b32 s92, s28
+; SI-NEXT: s_mov_b32 s28, s27
+; SI-NEXT: s_mov_b32 s27, s26
+; SI-NEXT: s_mov_b32 s26, s25
+; SI-NEXT: s_mov_b32 s25, s87
+; SI-NEXT: s_or_b32 s87, s78, s77
+; SI-NEXT: s_and_b32 s77, s61, 0xff
+; SI-NEXT: s_mov_b32 s24, s23
+; SI-NEXT: s_mov_b32 s23, s16
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_lshl_b32 s78, s59, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
+; SI-NEXT: v_readlane_b32 s16, v46, 45
+; SI-NEXT: s_mov_b32 s85, s55
; SI-NEXT: s_or_b32 s54, s78, s77
-; SI-NEXT: s_or_b32 s55, s76, s84
-; SI-NEXT: s_and_b32 s76, s47, 0xff
-; SI-NEXT: s_lshl_b32 s77, s46, 8
-; SI-NEXT: v_readlane_b32 s16, v42, 40
+; SI-NEXT: s_or_b32 s55, s76, s87
+; SI-NEXT: s_and_b32 s76, s29, 0xff
+; SI-NEXT: s_lshl_b32 s77, s16, 8
+; SI-NEXT: v_readlane_b32 s18, v46, 26
; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s16, 0xff
-; SI-NEXT: v_readlane_b32 s16, v41, 47
-; SI-NEXT: s_lshl_b32 s78, s16, 24
-; SI-NEXT: s_mov_b32 s16, s18
-; SI-NEXT: v_readlane_b32 s18, v41, 38
-; SI-NEXT: s_lshl_b32 s77, s77, 16
+; SI-NEXT: s_and_b32 s77, s19, 0xff
+; SI-NEXT: v_readlane_b32 s16, v46, 49
; SI-NEXT: s_and_b32 s44, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 40
-; SI-NEXT: s_or_b32 s85, s78, s77
-; SI-NEXT: s_and_b32 s77, s56, 0xff
-; SI-NEXT: s_and_b32 s45, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 42
+; SI-NEXT: v_readlane_b32 s18, v46, 28
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s57, 24
-; SI-NEXT: s_and_b32 s76, s76, 0xffff
+; SI-NEXT: s_lshl_b32 s78, s16, 24
+; SI-NEXT: s_and_b32 s45, s18, 0xffff
+; SI-NEXT: v_readlane_b32 s18, v46, 30
+; SI-NEXT: s_mov_b32 s20, s19
+; SI-NEXT: s_mov_b32 s19, s37
+; SI-NEXT: s_mov_b32 s37, s35
+; SI-NEXT: s_mov_b32 s35, s31
+; SI-NEXT: s_mov_b32 s31, s79
+; SI-NEXT: s_mov_b32 s79, s90
+; SI-NEXT: s_mov_b32 s90, s96
+; SI-NEXT: s_or_b32 s96, s78, s77
+; SI-NEXT: s_lshl_b32 s78, s46, 24
; SI-NEXT: s_and_b32 s46, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 44
-; SI-NEXT: s_or_b32 s64, s78, s77
-; SI-NEXT: s_or_b32 s65, s76, s85
-; SI-NEXT: s_and_b32 s76, s28, 0xff
-; SI-NEXT: s_lshl_b32 s77, s59, 8
+; SI-NEXT: v_readlane_b32 s18, v46, 32
+; SI-NEXT: s_and_b32 s77, s47, 0xff
; SI-NEXT: s_and_b32 s47, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 48
-; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_or_b32 s76, s76, s77
-; SI-NEXT: s_and_b32 s77, s58, 0xff
-; SI-NEXT: s_and_b32 s56, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 49
-; SI-NEXT: s_or_b32 s7, s7, s89
-; SI-NEXT: s_or_b32 s15, s15, s91
+; SI-NEXT: v_readlane_b32 s18, v46, 34
; SI-NEXT: s_lshl_b32 s77, s77, 16
-; SI-NEXT: s_lshl_b32 s78, s97, 24
+; SI-NEXT: s_and_b32 s76, s76, 0xffff
+; SI-NEXT: s_and_b32 s56, s18, 0xffff
+; SI-NEXT: v_readlane_b32 s18, v46, 36
+; SI-NEXT: s_or_b32 s64, s78, s77
+; SI-NEXT: s_or_b32 s65, s76, s96
+; SI-NEXT: s_and_b32 s76, s17, 0xff
+; SI-NEXT: s_lshl_b32 s77, s99, 8
; SI-NEXT: s_and_b32 s57, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 50
-; SI-NEXT: s_and_b32 s41, s41, 0xffff
-; SI-NEXT: s_mov_b32 s31, s97
-; SI-NEXT: s_or_b32 s96, s78, s77
-; SI-NEXT: s_mov_b32 s90, s21
-; SI-NEXT: s_lshl_b32 s78, s21, 24
+; SI-NEXT: v_readlane_b32 s18, v46, 38
+; SI-NEXT: s_or_b32 s76, s76, s77
+; SI-NEXT: s_and_b32 s77, s86, 0xff
; SI-NEXT: s_and_b32 s30, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 51
-; SI-NEXT: s_and_b32 s87, s72, 0xffff
-; SI-NEXT: s_and_b32 s97, s73, 0xffff
-; SI-NEXT: s_or_b32 s72, s45, s6
-; SI-NEXT: s_mov_b32 s73, s7
-; SI-NEXT: s_lshr_b64 s[20:21], s[6:7], 16
-; SI-NEXT: s_lshr_b64 s[6:7], s[14:15], 16
-; SI-NEXT: s_or_b32 s41, s41, s88
+; SI-NEXT: v_readlane_b32 s18, v46, 40
+; SI-NEXT: s_lshl_b32 s77, s77, 16
+; SI-NEXT: s_lshl_b32 s78, s83, 24
; SI-NEXT: s_and_b32 s34, s18, 0xffff
-; SI-NEXT: v_readlane_b32 s18, v41, 52
-; SI-NEXT: v_writelane_b32 v41, s6, 38
-; SI-NEXT: s_and_b32 s43, s43, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s7, 39
-; SI-NEXT: s_lshr_b64 s[6:7], s[40:41], 16
-; SI-NEXT: s_or_b32 s43, s43, s19
-; SI-NEXT: v_writelane_b32 v41, s6, 40
-; SI-NEXT: v_writelane_b32 v41, s7, 41
-; SI-NEXT: s_lshr_b64 s[6:7], s[42:43], 16
+; SI-NEXT: v_readlane_b32 s18, v46, 42
; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_and_b32 s13, s13, 0xffff
-; SI-NEXT: s_and_b32 s77, s60, 0xff
-; SI-NEXT: v_writelane_b32 v41, s6, 42
-; SI-NEXT: s_or_b32 s5, s5, s79
-; SI-NEXT: s_and_b32 s9, s9, 0xffff
-; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: s_or_b32 s13, s13, s95
+; SI-NEXT: s_mov_b32 s16, s83
+; SI-NEXT: s_or_b32 s83, s78, s77
+; SI-NEXT: s_and_b32 s77, s84, 0xff
+; SI-NEXT: s_and_b32 s36, s18, 0xffff
+; SI-NEXT: v_readlane_b32 s18, v46, 46
+; SI-NEXT: s_or_b32 s5, s5, s68
; SI-NEXT: s_lshl_b32 s77, s77, 16
+; SI-NEXT: s_lshl_b32 s78, s66, 24
; SI-NEXT: s_and_b32 s76, s76, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s7, 43
-; SI-NEXT: s_lshr_b64 s[6:7], vcc, 16
-; SI-NEXT: s_or_b32 s9, s9, s23
-; SI-NEXT: s_or_b32 s11, s11, s93
+; SI-NEXT: s_and_b32 s84, s18, 0xffff
+; SI-NEXT: v_readlane_b32 s18, v46, 47
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s66, s78, s77
-; SI-NEXT: s_or_b32 s67, s76, s96
-; SI-NEXT: s_and_b32 s36, s18, 0xffff
-; SI-NEXT: s_and_b32 s83, s61, 0xffff
-; SI-NEXT: s_and_b32 s86, s62, 0xffff
-; SI-NEXT: s_and_b32 s98, s63, 0xffff
+; SI-NEXT: s_or_b32 s67, s76, s83
+; SI-NEXT: s_mov_b32 s78, s86
+; SI-NEXT: s_and_b32 s86, s18, 0xffff
+; SI-NEXT: s_mov_b32 s76, s99
; SI-NEXT: s_and_b32 s99, s74, 0xffff
; SI-NEXT: s_and_b32 s18, s75, 0xffff
; SI-NEXT: s_or_b32 s74, s44, s4
; SI-NEXT: s_mov_b32 s75, s5
-; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 16
+; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
+; SI-NEXT: s_or_b32 s7, s7, s91
+; SI-NEXT: v_writelane_b32 v46, s4, 26
+; SI-NEXT: s_and_b32 s9, s9, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 27
+; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
+; SI-NEXT: s_or_b32 s9, s9, s88
+; SI-NEXT: v_writelane_b32 v46, s4, 28
+; SI-NEXT: s_and_b32 s11, s11, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 29
+; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 16
+; SI-NEXT: s_or_b32 s11, s11, s95
+; SI-NEXT: v_writelane_b32 v46, s4, 30
+; SI-NEXT: s_and_b32 s13, s13, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 31
+; SI-NEXT: s_lshr_b64 s[4:5], s[10:11], 16
+; SI-NEXT: s_or_b32 s13, s13, s89
+; SI-NEXT: v_writelane_b32 v46, s4, 32
+; SI-NEXT: s_and_b32 s15, s15, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 33
; SI-NEXT: s_lshr_b64 s[4:5], s[12:13], 16
-; SI-NEXT: v_writelane_b32 v41, s6, 44
-; SI-NEXT: s_mov_b32 s17, s92
-; SI-NEXT: s_mov_b32 s92, s59
-; SI-NEXT: s_mov_b32 s94, s60
+; SI-NEXT: s_or_b32 s15, s15, s93
+; SI-NEXT: v_writelane_b32 v46, s4, 34
+; SI-NEXT: s_and_b32 s41, s41, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 35
+; SI-NEXT: s_lshr_b64 s[4:5], s[14:15], 16
+; SI-NEXT: s_or_b32 s41, s41, s21
+; SI-NEXT: v_writelane_b32 v46, s4, 36
+; SI-NEXT: s_and_b32 s43, s43, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s5, 37
+; SI-NEXT: s_lshr_b64 s[4:5], s[40:41], 16
+; SI-NEXT: s_or_b32 s43, s43, s69
+; SI-NEXT: v_writelane_b32 v46, s4, 38
+; SI-NEXT: v_writelane_b32 v46, s5, 39
+; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v46, s4, 40
+; SI-NEXT: v_writelane_b32 v46, s5, 41
+; SI-NEXT: s_lshr_b64 s[4:5], vcc, 16
+; SI-NEXT: s_and_b32 s97, s63, 0xffff
+; SI-NEXT: s_and_b32 s98, s72, 0xffff
+; SI-NEXT: s_and_b32 s22, s73, 0xffff
+; SI-NEXT: v_writelane_b32 v46, s4, 42
+; SI-NEXT: s_or_b32 s72, s45, s6
+; SI-NEXT: s_mov_b32 s73, s7
; SI-NEXT: s_or_b32 s62, s46, s8
; SI-NEXT: s_mov_b32 s63, s9
-; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 16
; SI-NEXT: s_or_b32 s60, s47, s10
; SI-NEXT: s_mov_b32 s61, s11
-; SI-NEXT: s_lshr_b64 s[28:29], s[10:11], 16
; SI-NEXT: s_or_b32 s58, s56, s12
; SI-NEXT: s_mov_b32 s59, s13
; SI-NEXT: s_or_b32 s56, s57, s14
; SI-NEXT: s_mov_b32 s57, s15
; SI-NEXT: s_or_b32 s46, s30, s40
; SI-NEXT: s_mov_b32 s47, s41
-; SI-NEXT: v_writelane_b32 v41, s7, 45
-; SI-NEXT: s_or_b32 s40, s83, s38
+; SI-NEXT: v_writelane_b32 v46, s5, 43
+; SI-NEXT: s_or_b32 s40, s84, s38
; SI-NEXT: s_mov_b32 s41, s39
; SI-NEXT: s_lshr_b64 s[38:39], s[38:39], 16
; SI-NEXT: s_or_b32 s14, s86, s48
; SI-NEXT: s_mov_b32 s15, s49
; SI-NEXT: s_lshr_b64 s[48:49], s[48:49], 16
-; SI-NEXT: s_or_b32 s12, s98, s50
+; SI-NEXT: s_or_b32 s12, s97, s50
; SI-NEXT: s_mov_b32 s13, s51
; SI-NEXT: s_lshr_b64 s[50:51], s[50:51], 16
-; SI-NEXT: s_or_b32 s10, s87, s52
-; SI-NEXT: s_mov_b32 s86, s4
+; SI-NEXT: s_or_b32 s10, s98, s52
; SI-NEXT: s_mov_b32 s11, s53
; SI-NEXT: s_lshr_b64 s[52:53], s[52:53], 16
-; SI-NEXT: s_or_b32 s8, s97, s54
+; SI-NEXT: s_or_b32 s8, s22, s54
; SI-NEXT: s_mov_b32 s9, s55
; SI-NEXT: s_lshr_b64 s[54:55], s[54:55], 16
; SI-NEXT: s_or_b32 s6, s99, s64
@@ -193433,141 +193522,155 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_mov_b32 s45, s43
; SI-NEXT: s_or_b32 s42, s36, vcc_lo
; SI-NEXT: s_mov_b32 s43, vcc_hi
-; SI-NEXT: s_lshr_b32 s77, s79, 16
-; SI-NEXT: s_lshr_b32 s67, s89, 16
-; SI-NEXT: s_lshr_b32 s23, s23, 16
-; SI-NEXT: s_lshr_b32 s79, s93, 16
-; SI-NEXT: s_lshr_b32 s89, s95, 16
-; SI-NEXT: s_lshr_b32 s91, s91, 16
-; SI-NEXT: s_lshr_b32 s93, s88, 16
-; SI-NEXT: s_lshr_b32 s95, s19, 16
+; SI-NEXT: s_mov_b32 s86, s78
+; SI-NEXT: s_mov_b32 s99, s76
+; SI-NEXT: v_readlane_b32 s18, v46, 50
+; SI-NEXT: s_lshr_b32 s77, s68, 16
+; SI-NEXT: s_lshr_b32 s68, s91, 16
+; SI-NEXT: s_lshr_b32 s88, s88, 16
+; SI-NEXT: s_lshr_b32 s84, s95, 16
+; SI-NEXT: s_lshr_b32 s89, s89, 16
+; SI-NEXT: s_lshr_b32 s91, s93, 16
+; SI-NEXT: s_lshr_b32 s93, s21, 16
+; SI-NEXT: s_lshr_b32 s95, s69, 16
; SI-NEXT: s_lshr_b32 s30, s70, 16
; SI-NEXT: s_lshr_b32 s34, s71, 16
-; SI-NEXT: v_readlane_b32 s78, v41, 59
-; SI-NEXT: v_readlane_b32 s70, v41, 58
-; SI-NEXT: v_readlane_b32 s71, v41, 57
-; SI-NEXT: v_readlane_b32 s65, v41, 56
; SI-NEXT: s_lshr_b32 s36, s80, 16
-; SI-NEXT: v_readlane_b32 s98, v41, 63
-; SI-NEXT: v_readlane_b32 s80, v41, 62
-; SI-NEXT: v_readlane_b32 s55, v41, 61
-; SI-NEXT: v_readlane_b32 s99, v41, 60
+; SI-NEXT: v_readlane_b32 s69, v46, 44
+; SI-NEXT: v_readlane_b32 s80, v46, 53
; SI-NEXT: s_lshr_b32 s39, s81, 16
-; SI-NEXT: v_readlane_b32 s27, v41, 46
+; SI-NEXT: v_readlane_b32 s81, v46, 57
+; SI-NEXT: v_readlane_b32 s76, v46, 56
+; SI-NEXT: v_readlane_b32 s21, v46, 55
+; SI-NEXT: v_readlane_b32 s98, v46, 54
; SI-NEXT: s_lshr_b32 s49, s82, 16
-; SI-NEXT: s_lshr_b32 s51, s84, 16
-; SI-NEXT: v_readlane_b32 s18, v41, 53
-; SI-NEXT: s_lshr_b32 s53, s85, 16
-; SI-NEXT: s_mov_b32 s81, s17
-; SI-NEXT: s_mov_b32 s17, s68
-; SI-NEXT: v_readlane_b32 s88, v41, 54
-; SI-NEXT: s_lshr_b32 s68, s96, 16
-; SI-NEXT: v_readlane_b32 s96, v41, 47
-; SI-NEXT: s_mov_b32 s84, s16
-; SI-NEXT: s_mov_b32 s16, s24
-; SI-NEXT: s_mov_b32 s24, s22
-; SI-NEXT: s_mov_b32 s22, s25
-; SI-NEXT: s_mov_b32 s25, s69
-; SI-NEXT: v_readlane_b32 s69, v41, 55
+; SI-NEXT: s_mov_b32 s82, s94
+; SI-NEXT: v_readlane_b32 s71, v46, 48
+; SI-NEXT: v_readlane_b32 s78, v46, 52
+; SI-NEXT: s_mov_b32 s55, s85
+; SI-NEXT: v_readlane_b32 s97, v46, 62
+; SI-NEXT: v_readlane_b32 s94, v46, 61
+; SI-NEXT: v_readlane_b32 s67, v46, 60
+; SI-NEXT: v_readlane_b32 s65, v46, 59
+; SI-NEXT: v_readlane_b32 s22, v46, 58
+; SI-NEXT: s_lshr_b32 s51, s87, 16
+; SI-NEXT: s_mov_b32 s70, s23
+; SI-NEXT: s_mov_b32 s23, s24
+; SI-NEXT: v_readlane_b32 s24, v46, 45
+; SI-NEXT: s_mov_b32 s87, s25
+; SI-NEXT: s_mov_b32 s25, s26
+; SI-NEXT: s_mov_b32 s26, s27
+; SI-NEXT: s_mov_b32 s27, s28
+; SI-NEXT: s_mov_b32 s28, s92
+; SI-NEXT: s_lshr_b32 s53, s96, 16
+; SI-NEXT: s_mov_b32 s96, s90
+; SI-NEXT: s_mov_b32 s90, s79
+; SI-NEXT: s_mov_b32 s79, s31
+; SI-NEXT: s_mov_b32 s31, s35
+; SI-NEXT: s_mov_b32 s35, s37
+; SI-NEXT: s_mov_b32 s37, s19
+; SI-NEXT: s_mov_b32 s19, s20
+; SI-NEXT: v_readlane_b32 s20, v46, 51
+; SI-NEXT: s_lshr_b32 s92, s83, 16
+; SI-NEXT: s_mov_b32 s83, s16
+; SI-NEXT: v_readlane_b32 s16, v46, 49
; SI-NEXT: s_cbranch_execnz .LBB97_3
; SI-NEXT: .LBB97_2: ; %cmp.true
-; SI-NEXT: v_readlane_b32 s4, v41, 35
-; SI-NEXT: s_add_i32 s19, s4, 3
-; SI-NEXT: v_readlane_b32 s5, v41, 34
-; SI-NEXT: s_and_b32 s4, s19, 0xff
+; SI-NEXT: v_readlane_b32 s4, v46, 11
+; SI-NEXT: s_add_i32 s85, s4, 3
+; SI-NEXT: v_readlane_b32 s5, v46, 6
+; SI-NEXT: v_readlane_b32 s6, v47, 60
+; SI-NEXT: s_and_b32 s4, s85, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 8
-; SI-NEXT: s_add_i32 s20, s94, 3
+; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: s_and_b32 s6, s20, 0xff
-; SI-NEXT: s_lshl_b32 s5, s90, 24
+; SI-NEXT: v_readlane_b32 s5, v47, 58
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: s_lshl_b32 s5, s5, 24
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_addk_i32 s4, 0x300
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_readlane_b32 s5, v41, 37
-; SI-NEXT: s_add_i32 s23, s5, 3
-; SI-NEXT: v_readlane_b32 s7, v41, 36
-; SI-NEXT: s_and_b32 s5, s23, 0xff
-; SI-NEXT: s_lshl_b32 s6, s92, 8
-; SI-NEXT: s_add_i32 s7, s7, 3
+; SI-NEXT: s_add_i32 s5, s17, 3
+; SI-NEXT: s_and_b32 s5, s5, 0xff
+; SI-NEXT: s_lshl_b32 s6, s99, 8
+; SI-NEXT: s_add_i32 s7, s86, 3
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: s_lshl_b32 s6, s31, 24
+; SI-NEXT: s_lshl_b32 s6, s83, 24
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_addk_i32 s5, 0x300
; SI-NEXT: s_or_b32 s6, s6, s7
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_readlane_b32 s6, v41, 33
-; SI-NEXT: s_add_i32 s68, s6, 3
-; SI-NEXT: v_readlane_b32 s7, v41, 32
-; SI-NEXT: v_readlane_b32 s8, v41, 29
-; SI-NEXT: s_and_b32 s6, s68, 0xff
+; SI-NEXT: v_readlane_b32 s6, v46, 20
+; SI-NEXT: s_add_i32 s6, s6, 3
+; SI-NEXT: v_readlane_b32 s7, v46, 14
+; SI-NEXT: v_readlane_b32 s8, v46, 9
+; SI-NEXT: s_and_b32 s6, s6, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 8
-; SI-NEXT: s_add_i32 s87, s8, 3
+; SI-NEXT: s_add_i32 s83, s8, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: v_readlane_b32 s7, v41, 30
-; SI-NEXT: s_and_b32 s8, s87, 0xff
+; SI-NEXT: v_readlane_b32 s7, v46, 8
+; SI-NEXT: s_and_b32 s8, s83, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_addk_i32 s6, 0x300
; SI-NEXT: s_or_b32 s7, s7, s8
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: v_readlane_b32 s7, v41, 25
-; SI-NEXT: s_add_i32 s83, s7, 3
-; SI-NEXT: v_readlane_b32 s8, v41, 24
-; SI-NEXT: v_readlane_b32 s9, v42, 40
-; SI-NEXT: s_and_b32 s7, s83, 0xff
-; SI-NEXT: s_lshl_b32 s8, s8, 8
-; SI-NEXT: s_add_i32 s9, s9, 3
+; SI-NEXT: s_add_i32 s7, s29, 3
+; SI-NEXT: s_and_b32 s7, s7, 0xff
+; SI-NEXT: s_lshl_b32 s8, s24, 8
+; SI-NEXT: s_add_i32 s9, s19, 3
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: s_and_b32 s9, s9, 0xff
-; SI-NEXT: s_lshl_b32 s8, s96, 24
+; SI-NEXT: s_lshl_b32 s8, s16, 24
; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_addk_i32 s7, 0x300
; SI-NEXT: s_or_b32 s8, s8, s9
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: v_readlane_b32 s8, v41, 22
+; SI-NEXT: v_readlane_b32 s8, v46, 23
; SI-NEXT: s_add_i32 s8, s8, 3
-; SI-NEXT: v_readlane_b32 s9, v41, 19
-; SI-NEXT: v_readlane_b32 s10, v42, 42
+; SI-NEXT: v_readlane_b32 s9, v46, 22
+; SI-NEXT: v_readlane_b32 s10, v46, 19
; SI-NEXT: s_and_b32 s8, s8, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 8
-; SI-NEXT: s_add_i32 s10, s10, 3
+; SI-NEXT: s_add_i32 s68, s10, 3
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: v_readlane_b32 s9, v42, 41
-; SI-NEXT: s_and_b32 s10, s10, 0xff
+; SI-NEXT: v_readlane_b32 s9, v46, 16
+; SI-NEXT: s_and_b32 s10, s68, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 24
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_addk_i32 s8, 0x300
; SI-NEXT: s_or_b32 s9, s9, s10
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: v_readlane_b32 s9, v41, 18
+; SI-NEXT: v_readlane_b32 s9, v46, 4
; SI-NEXT: s_add_i32 s9, s9, 3
+; SI-NEXT: v_readlane_b32 s10, v46, 0
; SI-NEXT: s_and_b32 s9, s9, 0xff
-; SI-NEXT: s_lshl_b32 s10, s27, 8
-; SI-NEXT: s_add_i32 s11, s16, 3
+; SI-NEXT: s_lshl_b32 s10, s10, 8
+; SI-NEXT: s_add_i32 s11, s28, 3
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: s_lshl_b32 s10, s88, 24
+; SI-NEXT: s_lshl_b32 s10, s27, 24
; SI-NEXT: s_lshl_b32 s11, s11, 16
; SI-NEXT: s_addk_i32 s9, 0x300
; SI-NEXT: s_or_b32 s10, s10, s11
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_or_b32 s9, s10, s9
-; SI-NEXT: v_readlane_b32 s10, v41, 28
-; SI-NEXT: s_add_i32 s86, s10, 3
-; SI-NEXT: v_readlane_b32 s11, v41, 26
-; SI-NEXT: v_readlane_b32 s12, v41, 20
-; SI-NEXT: s_and_b32 s10, s86, 0xff
+; SI-NEXT: v_readlane_b32 s10, v46, 25
+; SI-NEXT: s_add_i32 s17, s10, 3
+; SI-NEXT: v_readlane_b32 s11, v46, 24
+; SI-NEXT: v_readlane_b32 s12, v46, 21
+; SI-NEXT: s_and_b32 s10, s17, 0xff
; SI-NEXT: s_lshl_b32 s11, s11, 8
; SI-NEXT: s_add_i32 s12, s12, 3
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: v_readlane_b32 s11, v42, 44
+; SI-NEXT: v_readlane_b32 s11, v46, 18
; SI-NEXT: s_and_b32 s12, s12, 0xff
; SI-NEXT: s_lshl_b32 s11, s11, 24
; SI-NEXT: s_lshl_b32 s12, s12, 16
@@ -193575,13 +193678,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s11, s11, s12
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: s_add_i32 s11, s69, 3
-; SI-NEXT: v_readlane_b32 s13, v41, 12
-; SI-NEXT: s_and_b32 s11, s11, 0xff
-; SI-NEXT: s_lshl_b32 s12, s22, 8
+; SI-NEXT: v_readlane_b32 s11, v46, 10
+; SI-NEXT: s_add_i32 s84, s11, 3
+; SI-NEXT: v_readlane_b32 s12, v46, 7
+; SI-NEXT: v_readlane_b32 s13, v46, 1
+; SI-NEXT: s_and_b32 s11, s84, 0xff
+; SI-NEXT: s_lshl_b32 s12, s12, 8
; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: v_readlane_b32 s12, v42, 43
+; SI-NEXT: v_readlane_b32 s12, v47, 59
; SI-NEXT: s_and_b32 s13, s13, 0xff
; SI-NEXT: s_lshl_b32 s12, s12, 24
; SI-NEXT: s_lshl_b32 s13, s13, 16
@@ -193589,30 +193694,31 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s12, s12, s13
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: v_readlane_b32 s12, v41, 31
-; SI-NEXT: s_add_i32 s97, s12, 3
-; SI-NEXT: v_readlane_b32 s13, v41, 27
-; SI-NEXT: v_readlane_b32 s14, v41, 23
-; SI-NEXT: s_and_b32 s12, s97, 0xff
+; SI-NEXT: v_readlane_b32 s12, v46, 17
+; SI-NEXT: s_add_i32 s99, s12, 3
+; SI-NEXT: v_readlane_b32 s13, v46, 15
+; SI-NEXT: v_readlane_b32 s14, v46, 12
+; SI-NEXT: s_and_b32 s12, s99, 0xff
; SI-NEXT: s_lshl_b32 s13, s13, 8
-; SI-NEXT: s_add_i32 s14, s14, 3
+; SI-NEXT: s_add_i32 s86, s14, 3
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: v_readlane_b32 s13, v41, 21
-; SI-NEXT: s_and_b32 s14, s14, 0xff
+; SI-NEXT: v_readlane_b32 s13, v46, 13
+; SI-NEXT: s_and_b32 s14, s86, 0xff
; SI-NEXT: s_lshl_b32 s13, s13, 24
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_addk_i32 s12, 0x300
; SI-NEXT: s_or_b32 s13, s13, s14
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: v_readlane_b32 s13, v42, 45
+; SI-NEXT: v_readlane_b32 s13, v46, 5
; SI-NEXT: s_add_i32 s13, s13, 3
-; SI-NEXT: v_readlane_b32 s15, v41, 15
+; SI-NEXT: v_readlane_b32 s14, v46, 3
+; SI-NEXT: v_readlane_b32 s15, v47, 62
; SI-NEXT: s_and_b32 s13, s13, 0xff
-; SI-NEXT: s_lshl_b32 s14, s25, 8
+; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_add_i32 s15, s15, 3
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: v_readlane_b32 s14, v41, 13
+; SI-NEXT: v_readlane_b32 s14, v47, 63
; SI-NEXT: s_and_b32 s15, s15, 0xff
; SI-NEXT: s_lshl_b32 s14, s14, 24
; SI-NEXT: s_lshl_b32 s15, s15, 16
@@ -193620,15 +193726,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s14, s14, s15
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: v_readlane_b32 s14, v41, 17
+; SI-NEXT: v_readlane_b32 s14, v46, 2
; SI-NEXT: s_add_i32 s14, s14, 3
-; SI-NEXT: v_readlane_b32 s15, v41, 16
-; SI-NEXT: v_readlane_b32 s16, v42, 47
+; SI-NEXT: v_readlane_b32 s15, v47, 61
+; SI-NEXT: v_readlane_b32 s16, v47, 56
; SI-NEXT: s_and_b32 s14, s14, 0xff
; SI-NEXT: s_lshl_b32 s15, s15, 8
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: v_readlane_b32 s15, v42, 46
+; SI-NEXT: v_readlane_b32 s15, v47, 57
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s15, s15, 24
; SI-NEXT: s_lshl_b32 s16, s16, 16
@@ -193636,113 +193742,93 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s15, s15, s16
; SI-NEXT: s_and_b32 s14, s14, 0xffff
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: s_add_i32 s15, s24, 3
-; SI-NEXT: s_lshl_b32 s16, s17, 8
-; SI-NEXT: v_readlane_b32 s17, v41, 10
+; SI-NEXT: s_add_i32 s15, s26, 3
; SI-NEXT: s_and_b32 s15, s15, 0xff
-; SI-NEXT: s_add_i32 s17, s17, 3
+; SI-NEXT: s_lshl_b32 s16, s25, 8
+; SI-NEXT: s_add_i32 s17, s23, 3
; SI-NEXT: s_or_b32 s15, s16, s15
-; SI-NEXT: v_readlane_b32 s16, v41, 11
; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: s_lshl_b32 s16, s16, 24
+; SI-NEXT: s_lshl_b32 s16, s87, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_addk_i32 s15, 0x300
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s15, s15, 0xffff
; SI-NEXT: s_or_b32 s15, s16, s15
-; SI-NEXT: v_readlane_b32 s16, v41, 14
-; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: s_add_i32 s16, s20, 3
; SI-NEXT: s_lshl_b32 s17, s18, 8
-; SI-NEXT: v_readlane_b32 s18, v41, 8
+; SI-NEXT: v_readlane_b32 s18, v47, 54
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v41, 9
+; SI-NEXT: v_readlane_b32 s17, v47, 55
; SI-NEXT: s_and_b32 s18, s18, 0xff
+; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v41, 7
-; SI-NEXT: s_add_i32 s17, s17, 3
-; SI-NEXT: v_readlane_b32 s18, v41, 6
-; SI-NEXT: v_readlane_b32 s19, v41, 3
-; SI-NEXT: s_and_b32 s17, s17, 0xff
-; SI-NEXT: s_lshl_b32 s18, s18, 8
-; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: v_readlane_b32 s18, v41, 4
-; SI-NEXT: s_and_b32 s19, s19, 0xff
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_lshl_b32 s19, s19, 16
-; SI-NEXT: s_addk_i32 s17, 0x300
-; SI-NEXT: s_or_b32 s18, s18, s19
-; SI-NEXT: s_and_b32 s17, s17, 0xffff
-; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_add_i32 s40, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v41, 5
-; SI-NEXT: s_add_i32 s41, s17, 0x3000000
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v41, 2
-; SI-NEXT: v_readlane_b32 s18, v41, 0
+; SI-NEXT: s_add_i32 s16, s22, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_lshl_b32 s17, s65, 8
+; SI-NEXT: s_add_i32 s18, s94, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v41, 1
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
+; SI-NEXT: s_lshl_b32 s17, s67, 24
+; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s17, s18
+; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s41, s16, 0x3000000
+; SI-NEXT: s_add_i32 s16, s71, 3
+; SI-NEXT: s_and_b32 s16, s16, 0xff
+; SI-NEXT: s_lshl_b32 s17, s81, 8
+; SI-NEXT: s_add_i32 s18, s55, 3
+; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_and_b32 s18, s18, 0xff
+; SI-NEXT: s_addk_i32 s16, 0x300
+; SI-NEXT: s_lshl_b32 s17, s97, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s42, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 63
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 62
-; SI-NEXT: v_readlane_b32 s18, v42, 58
+; SI-NEXT: s_add_i32 s16, s98, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_lshl_b32 s17, s78, 8
+; SI-NEXT: s_add_i32 s18, s31, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 59
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
+; SI-NEXT: s_lshl_b32 s17, s35, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s43, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 61
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 60
-; SI-NEXT: v_readlane_b32 s18, v42, 56
+; SI-NEXT: s_add_i32 s16, s82, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_lshl_b32 s17, s37, 8
+; SI-NEXT: s_add_i32 s18, s90, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 57
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
+; SI-NEXT: s_lshl_b32 s17, s79, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s44, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 55
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 54
-; SI-NEXT: v_readlane_b32 s18, v42, 50
+; SI-NEXT: s_add_i32 s16, s96, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 46
+; SI-NEXT: v_readlane_b32 s18, v47, 45
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 51
+; SI-NEXT: v_readlane_b32 s17, v47, 44
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193751,15 +193837,12 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s45, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 53
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 52
-; SI-NEXT: v_readlane_b32 s18, v42, 48
+; SI-NEXT: s_add_i32 s16, s21, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: s_lshl_b32 s17, s76, 8
+; SI-NEXT: s_add_i32 s18, s70, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 49
+; SI-NEXT: v_readlane_b32 s17, v47, 50
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193768,28 +193851,31 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s46, s16, 0x3000000
-; SI-NEXT: s_add_i32 s16, s99, 3
+; SI-NEXT: s_add_i32 s16, s80, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 49
+; SI-NEXT: v_readlane_b32 s18, v47, 48
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s55, 8
-; SI-NEXT: s_add_i32 s18, s98, 3
+; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: v_readlane_b32 s17, v47, 47
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s80, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s47, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 18
+; SI-NEXT: v_readlane_b32 s16, v47, 18
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 17
-; SI-NEXT: v_readlane_b32 s18, v42, 16
+; SI-NEXT: v_readlane_b32 s17, v47, 17
+; SI-NEXT: v_readlane_b32 s18, v47, 16
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 15
+; SI-NEXT: v_readlane_b32 s17, v47, 15
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193798,28 +193884,32 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s56, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 14
+; SI-NEXT: v_readlane_b32 s16, v47, 14
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 53
+; SI-NEXT: v_readlane_b32 s18, v47, 52
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s84, 8
-; SI-NEXT: s_add_i32 s18, s71, 3
+; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: v_readlane_b32 s17, v47, 51
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
-; SI-NEXT: s_lshl_b32 s17, s65, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s57, s16, 0x3000000
-; SI-NEXT: s_add_i32 s16, s70, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 25
-; SI-NEXT: v_readlane_b32 s18, v42, 24
+; SI-NEXT: v_readlane_b32 s16, v47, 26
+; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 25
+; SI-NEXT: v_readlane_b32 s18, v47, 24
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 23
+; SI-NEXT: v_readlane_b32 s17, v47, 23
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193828,15 +193918,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s58, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 22
+; SI-NEXT: v_readlane_b32 s16, v47, 22
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 21
-; SI-NEXT: v_readlane_b32 s18, v42, 20
+; SI-NEXT: v_readlane_b32 s17, v47, 21
+; SI-NEXT: v_readlane_b32 s18, v47, 20
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 19
+; SI-NEXT: v_readlane_b32 s17, v47, 19
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193845,13 +193935,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s59, s16, 0x3000000
-; SI-NEXT: s_add_i32 s16, s78, 3
-; SI-NEXT: v_readlane_b32 s18, v42, 31
+; SI-NEXT: v_readlane_b32 s16, v47, 34
+; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 33
+; SI-NEXT: v_readlane_b32 s18, v47, 32
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s81, 8
+; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 30
+; SI-NEXT: v_readlane_b32 s17, v47, 31
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193860,15 +193952,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s60, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 29
+; SI-NEXT: v_readlane_b32 s16, v47, 30
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 28
-; SI-NEXT: v_readlane_b32 s18, v42, 27
+; SI-NEXT: v_readlane_b32 s17, v47, 29
+; SI-NEXT: v_readlane_b32 s18, v47, 28
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 26
+; SI-NEXT: v_readlane_b32 s17, v47, 27
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193877,13 +193969,14 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s61, s16, 0x3000000
-; SI-NEXT: s_add_i32 s16, s37, 3
-; SI-NEXT: v_readlane_b32 s18, v42, 37
+; SI-NEXT: s_add_i32 s16, s69, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 41
+; SI-NEXT: v_readlane_b32 s18, v47, 40
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: s_lshl_b32 s17, s35, 8
+; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 36
+; SI-NEXT: v_readlane_b32 s17, v47, 39
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193892,15 +193985,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s62, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 35
+; SI-NEXT: v_readlane_b32 s16, v47, 38
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 34
-; SI-NEXT: v_readlane_b32 s18, v42, 33
+; SI-NEXT: v_readlane_b32 s17, v47, 37
+; SI-NEXT: v_readlane_b32 s18, v47, 36
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 32
+; SI-NEXT: v_readlane_b32 s17, v47, 35
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193909,15 +194002,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s63, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 5
+; SI-NEXT: v_readlane_b32 s16, v47, 5
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 4
-; SI-NEXT: v_readlane_b32 s18, v42, 3
+; SI-NEXT: v_readlane_b32 s17, v47, 4
+; SI-NEXT: v_readlane_b32 s18, v47, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 2
+; SI-NEXT: v_readlane_b32 s17, v47, 2
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193926,15 +194019,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s72, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 1
+; SI-NEXT: v_readlane_b32 s16, v47, 1
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 0
-; SI-NEXT: v_readlane_b32 s18, v42, 39
+; SI-NEXT: v_readlane_b32 s17, v47, 0
+; SI-NEXT: v_readlane_b32 s18, v47, 43
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 38
+; SI-NEXT: v_readlane_b32 s17, v47, 42
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193943,15 +194036,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s73, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 13
+; SI-NEXT: v_readlane_b32 s16, v47, 13
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 12
-; SI-NEXT: v_readlane_b32 s18, v42, 11
+; SI-NEXT: v_readlane_b32 s17, v47, 12
+; SI-NEXT: v_readlane_b32 s18, v47, 11
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 10
+; SI-NEXT: v_readlane_b32 s17, v47, 10
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193960,15 +194053,15 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s74, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v42, 9
+; SI-NEXT: v_readlane_b32 s16, v47, 9
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v42, 8
-; SI-NEXT: v_readlane_b32 s18, v42, 7
+; SI-NEXT: v_readlane_b32 s17, v47, 8
+; SI-NEXT: v_readlane_b32 s18, v47, 7
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v42, 6
+; SI-NEXT: v_readlane_b32 s17, v47, 6
; SI-NEXT: s_and_b32 s18, s18, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
@@ -193977,45 +194070,55 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s75, s16, 0x3000000
+; SI-NEXT: s_lshr_b64 s[16:17], s[74:75], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 26
+; SI-NEXT: v_writelane_b32 v46, s17, 27
+; SI-NEXT: s_lshr_b64 s[16:17], s[72:73], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 28
+; SI-NEXT: v_writelane_b32 v46, s17, 29
+; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 30
+; SI-NEXT: v_writelane_b32 v46, s17, 31
+; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 32
+; SI-NEXT: v_writelane_b32 v46, s17, 33
+; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16
+; SI-NEXT: v_writelane_b32 v46, s16, 34
+; SI-NEXT: v_writelane_b32 v46, s17, 35
; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
-; SI-NEXT: v_writelane_b32 v41, s16, 38
-; SI-NEXT: v_writelane_b32 v41, s17, 39
+; SI-NEXT: v_writelane_b32 v46, s16, 36
+; SI-NEXT: v_writelane_b32 v46, s17, 37
; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
-; SI-NEXT: v_writelane_b32 v41, s16, 40
-; SI-NEXT: v_writelane_b32 v41, s17, 41
+; SI-NEXT: v_writelane_b32 v46, s16, 38
+; SI-NEXT: v_writelane_b32 v46, s17, 39
; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
-; SI-NEXT: s_add_i32 s4, s4, 0x3000000
-; SI-NEXT: s_add_i32 s5, s5, 0x3000000
; SI-NEXT: s_add_i32 s10, s10, 0x3000000
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
; SI-NEXT: s_add_i32 s13, s13, 0x3000000
; SI-NEXT: s_add_i32 s14, s14, 0x3000000
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
-; SI-NEXT: v_writelane_b32 v41, s16, 42
+; SI-NEXT: v_writelane_b32 v46, s16, 40
+; SI-NEXT: s_add_i32 s4, s4, 0x3000000
+; SI-NEXT: s_add_i32 s5, s5, 0x3000000
; SI-NEXT: s_add_i32 s6, s6, 0x3000000
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
; SI-NEXT: s_add_i32 s8, s8, 0x3000000
; SI-NEXT: s_add_i32 s9, s9, 0x3000000
-; SI-NEXT: s_lshr_b64 s[76:77], s[74:75], 16
-; SI-NEXT: v_writelane_b32 v41, s17, 43
+; SI-NEXT: v_writelane_b32 v46, s17, 41
; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
; SI-NEXT: s_lshr_b64 s[38:39], s[40:41], 16
; SI-NEXT: s_lshr_b64 s[48:49], s[14:15], 16
; SI-NEXT: s_lshr_b64 s[50:51], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[52:53], s[10:11], 16
-; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[20:21], s[72:73], 16
-; SI-NEXT: s_lshr_b64 s[26:27], s[62:63], 16
-; SI-NEXT: s_lshr_b64 s[28:29], s[60:61], 16
-; SI-NEXT: s_lshr_b64 s[86:87], s[58:59], 16
-; SI-NEXT: v_writelane_b32 v41, s16, 44
+; SI-NEXT: v_writelane_b32 v46, s16, 42
; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[64:65], s[6:7], 16
+; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 16
; SI-NEXT: s_lshr_b32 s77, s75, 16
-; SI-NEXT: s_lshr_b32 s67, s73, 16
-; SI-NEXT: s_lshr_b32 s23, s63, 16
-; SI-NEXT: s_lshr_b32 s79, s61, 16
+; SI-NEXT: s_lshr_b32 s68, s73, 16
+; SI-NEXT: s_lshr_b32 s88, s63, 16
+; SI-NEXT: s_lshr_b32 s84, s61, 16
; SI-NEXT: s_lshr_b32 s89, s59, 16
; SI-NEXT: s_lshr_b32 s91, s57, 16
; SI-NEXT: s_lshr_b32 s93, s47, 16
@@ -194027,63 +194130,78 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_lshr_b32 s49, s11, 16
; SI-NEXT: s_lshr_b32 s51, s9, 16
; SI-NEXT: s_lshr_b32 s53, s7, 16
-; SI-NEXT: s_lshr_b32 s68, s5, 16
-; SI-NEXT: v_writelane_b32 v41, s17, 45
+; SI-NEXT: s_lshr_b32 s92, s5, 16
+; SI-NEXT: v_writelane_b32 v46, s17, 43
; SI-NEXT: .LBB97_3: ; %end
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; SI-NEXT: v_readlane_b32 s18, v46, 26
; SI-NEXT: s_and_b32 s17, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s18, s76, 16
+; SI-NEXT: v_readlane_b32 s19, v46, 27
+; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s75, 0xffff
; SI-NEXT: s_lshl_b32 s19, s77, 16
+; SI-NEXT: v_readlane_b32 s20, v46, 28
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s72, 0xffff
+; SI-NEXT: v_readlane_b32 s21, v46, 29
; SI-NEXT: s_lshl_b32 s20, s20, 16
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_and_b32 s20, s73, 0xffff
-; SI-NEXT: s_lshl_b32 s21, s67, 16
+; SI-NEXT: s_lshl_b32 s21, s68, 16
+; SI-NEXT: v_readlane_b32 s22, v46, 30
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s62, 0xffff
-; SI-NEXT: s_lshl_b32 s22, s26, 16
+; SI-NEXT: v_readlane_b32 s23, v46, 31
+; SI-NEXT: s_lshl_b32 s22, s22, 16
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s63, 0xffff
-; SI-NEXT: s_lshl_b32 s23, s23, 16
+; SI-NEXT: s_lshl_b32 s23, s88, 16
+; SI-NEXT: v_readlane_b32 s24, v46, 32
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s60, 0xffff
-; SI-NEXT: s_lshl_b32 s24, s28, 16
+; SI-NEXT: v_readlane_b32 s25, v46, 33
+; SI-NEXT: s_lshl_b32 s24, s24, 16
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s24, s61, 0xffff
-; SI-NEXT: s_lshl_b32 s25, s79, 16
+; SI-NEXT: s_lshl_b32 s25, s84, 16
+; SI-NEXT: v_readlane_b32 s26, v46, 34
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s58, 0xffff
-; SI-NEXT: s_lshl_b32 s26, s86, 16
+; SI-NEXT: v_readlane_b32 s27, v46, 35
+; SI-NEXT: s_lshl_b32 s26, s26, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s59, 0xffff
; SI-NEXT: s_lshl_b32 s27, s89, 16
-; SI-NEXT: v_readlane_b32 s28, v41, 38
+; SI-NEXT: v_readlane_b32 s28, v46, 36
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s56, 0xffff
-; SI-NEXT: v_readlane_b32 s29, v41, 39
+; SI-NEXT: v_readlane_b32 s29, v46, 37
; SI-NEXT: s_lshl_b32 s28, s28, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s57, 0xffff
; SI-NEXT: s_lshl_b32 s29, s91, 16
-; SI-NEXT: v_readlane_b32 s56, v41, 40
+; SI-NEXT: v_readlane_b32 s56, v46, 38
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s29, s46, 0xffff
-; SI-NEXT: v_readlane_b32 s57, v41, 41
+; SI-NEXT: v_readlane_b32 s57, v46, 39
; SI-NEXT: s_lshl_b32 s46, s56, 16
; SI-NEXT: s_or_b32 s29, s29, s46
; SI-NEXT: s_and_b32 s46, s47, 0xffff
; SI-NEXT: s_lshl_b32 s47, s93, 16
-; SI-NEXT: v_readlane_b32 s56, v41, 42
+; SI-NEXT: v_readlane_b32 s56, v46, 40
; SI-NEXT: s_or_b32 s46, s46, s47
; SI-NEXT: s_and_b32 s44, s44, 0xffff
-; SI-NEXT: v_readlane_b32 s57, v41, 43
+; SI-NEXT: v_readlane_b32 s57, v46, 41
; SI-NEXT: s_lshl_b32 s47, s56, 16
; SI-NEXT: s_or_b32 s44, s44, s47
; SI-NEXT: s_and_b32 s45, s45, 0xffff
; SI-NEXT: s_lshl_b32 s47, s95, 16
-; SI-NEXT: v_readlane_b32 s56, v41, 44
+; SI-NEXT: v_readlane_b32 s56, v46, 42
; SI-NEXT: s_or_b32 s45, s45, s47
; SI-NEXT: s_and_b32 s42, s42, 0xffff
; SI-NEXT: s_lshl_b32 s47, s56, 16
@@ -194130,11 +194248,11 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s47, s66, 16
; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_lshl_b32 s16, s68, 16
+; SI-NEXT: s_lshl_b32 s16, s92, 16
; SI-NEXT: s_or_b32 s4, s4, s47
; SI-NEXT: s_or_b32 s5, s5, s16
-; SI-NEXT: v_readlane_b32 s30, v40, 34
-; SI-NEXT: v_readlane_b32 s57, v41, 45
+; SI-NEXT: v_readlane_b32 s30, v45, 34
+; SI-NEXT: v_readlane_b32 s57, v46, 43
; SI-NEXT: v_mov_b32_e32 v0, s17
; SI-NEXT: v_mov_b32_e32 v1, s18
; SI-NEXT: v_mov_b32_e32 v2, s19
@@ -194167,78 +194285,62 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: v_mov_b32_e32 v29, s7
; SI-NEXT: v_mov_b32_e32 v30, s4
; SI-NEXT: v_mov_b32_e32 v31, s5
-; SI-NEXT: v_readlane_b32 s31, v40, 35
-; SI-NEXT: v_readlane_b32 s99, v40, 33
-; SI-NEXT: v_readlane_b32 s98, v40, 32
-; SI-NEXT: v_readlane_b32 s97, v40, 31
-; SI-NEXT: v_readlane_b32 s96, v40, 30
-; SI-NEXT: v_readlane_b32 s87, v40, 29
-; SI-NEXT: v_readlane_b32 s86, v40, 28
-; SI-NEXT: v_readlane_b32 s85, v40, 27
-; SI-NEXT: v_readlane_b32 s84, v40, 26
-; SI-NEXT: v_readlane_b32 s83, v40, 25
-; SI-NEXT: v_readlane_b32 s82, v40, 24
-; SI-NEXT: v_readlane_b32 s81, v40, 23
-; SI-NEXT: v_readlane_b32 s80, v40, 22
-; SI-NEXT: v_readlane_b32 s71, v40, 21
-; SI-NEXT: v_readlane_b32 s70, v40, 20
-; SI-NEXT: v_readlane_b32 s69, v40, 19
-; SI-NEXT: v_readlane_b32 s68, v40, 18
-; SI-NEXT: v_readlane_b32 s67, v40, 17
-; SI-NEXT: v_readlane_b32 s66, v40, 16
-; SI-NEXT: v_readlane_b32 s65, v40, 15
-; SI-NEXT: v_readlane_b32 s64, v40, 14
-; SI-NEXT: v_readlane_b32 s55, v40, 13
-; SI-NEXT: v_readlane_b32 s54, v40, 12
-; SI-NEXT: v_readlane_b32 s53, v40, 11
-; SI-NEXT: v_readlane_b32 s52, v40, 10
-; SI-NEXT: v_readlane_b32 s51, v40, 9
-; SI-NEXT: v_readlane_b32 s50, v40, 8
-; SI-NEXT: v_readlane_b32 s49, v40, 7
-; SI-NEXT: v_readlane_b32 s48, v40, 6
-; SI-NEXT: v_readlane_b32 s39, v40, 5
-; SI-NEXT: v_readlane_b32 s38, v40, 4
-; SI-NEXT: v_readlane_b32 s37, v40, 3
-; SI-NEXT: v_readlane_b32 s36, v40, 2
-; SI-NEXT: v_readlane_b32 s35, v40, 1
-; SI-NEXT: v_readlane_b32 s34, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v45, 35
+; SI-NEXT: v_readlane_b32 s99, v45, 33
+; SI-NEXT: v_readlane_b32 s98, v45, 32
+; SI-NEXT: v_readlane_b32 s97, v45, 31
+; SI-NEXT: v_readlane_b32 s96, v45, 30
+; SI-NEXT: v_readlane_b32 s87, v45, 29
+; SI-NEXT: v_readlane_b32 s86, v45, 28
+; SI-NEXT: v_readlane_b32 s85, v45, 27
+; SI-NEXT: v_readlane_b32 s84, v45, 26
+; SI-NEXT: v_readlane_b32 s83, v45, 25
+; SI-NEXT: v_readlane_b32 s82, v45, 24
+; SI-NEXT: v_readlane_b32 s81, v45, 23
+; SI-NEXT: v_readlane_b32 s80, v45, 22
+; SI-NEXT: v_readlane_b32 s71, v45, 21
+; SI-NEXT: v_readlane_b32 s70, v45, 20
+; SI-NEXT: v_readlane_b32 s69, v45, 19
+; SI-NEXT: v_readlane_b32 s68, v45, 18
+; SI-NEXT: v_readlane_b32 s67, v45, 17
+; SI-NEXT: v_readlane_b32 s66, v45, 16
+; SI-NEXT: v_readlane_b32 s65, v45, 15
+; SI-NEXT: v_readlane_b32 s64, v45, 14
+; SI-NEXT: v_readlane_b32 s55, v45, 13
+; SI-NEXT: v_readlane_b32 s54, v45, 12
+; SI-NEXT: v_readlane_b32 s53, v45, 11
+; SI-NEXT: v_readlane_b32 s52, v45, 10
+; SI-NEXT: v_readlane_b32 s51, v45, 9
+; SI-NEXT: v_readlane_b32 s50, v45, 8
+; SI-NEXT: v_readlane_b32 s49, v45, 7
+; SI-NEXT: v_readlane_b32 s48, v45, 6
+; SI-NEXT: v_readlane_b32 s39, v45, 5
+; SI-NEXT: v_readlane_b32 s38, v45, 4
+; SI-NEXT: v_readlane_b32 s37, v45, 3
+; SI-NEXT: v_readlane_b32 s36, v45, 2
+; SI-NEXT: v_readlane_b32 s35, v45, 1
+; SI-NEXT: v_readlane_b32 s34, v45, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB97_4:
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_mov_b32 s90, s21
-; SI-NEXT: v_writelane_b32 v41, s4, 38
-; SI-NEXT: v_writelane_b32 v41, s5, 39
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_mov_b32 s94, s60
-; SI-NEXT: v_writelane_b32 v41, s4, 40
-; SI-NEXT: v_writelane_b32 v41, s5, 41
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_mov_b32 s92, s59
-; SI-NEXT: v_writelane_b32 v41, s4, 42
-; SI-NEXT: v_writelane_b32 v41, s5, 43
+; SI-NEXT: v_writelane_b32 v46, s4, 26
+; SI-NEXT: v_writelane_b32 v46, s5, 27
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_mov_b32 s31, s97
-; SI-NEXT: v_writelane_b32 v41, s4, 44
; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr77
; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr20
-; SI-NEXT: ; implicit-def: $sgpr67
+; SI-NEXT: ; implicit-def: $sgpr68
; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $sgpr26
-; SI-NEXT: ; implicit-def: $sgpr23
+; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr28
-; SI-NEXT: ; implicit-def: $sgpr79
+; SI-NEXT: ; implicit-def: $sgpr84
; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr86
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr91
@@ -194247,7 +194349,6 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr42
-; SI-NEXT: v_writelane_b32 v41, s5, 45
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr38
@@ -194267,9 +194368,32 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr64
; SI-NEXT: ; implicit-def: $sgpr53
-; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: ; implicit-def: $sgpr68
+; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: v_writelane_b32 v46, s4, 28
+; SI-NEXT: v_writelane_b32 v46, s5, 29
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 30
+; SI-NEXT: v_writelane_b32 v46, s5, 31
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 32
+; SI-NEXT: v_writelane_b32 v46, s5, 33
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 34
+; SI-NEXT: v_writelane_b32 v46, s5, 35
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 36
+; SI-NEXT: v_writelane_b32 v46, s5, 37
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 38
+; SI-NEXT: v_writelane_b32 v46, s5, 39
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 40
+; SI-NEXT: v_writelane_b32 v46, s5, 41
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v46, s4, 42
+; SI-NEXT: v_writelane_b32 v46, s5, 43
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_branch .LBB97_2
;
; VI-LABEL: bitcast_v128i8_to_v64i16_scalar:
@@ -202103,8 +202227,9 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_writelane_b32 v20, s34, 0
; SI-NEXT: v_writelane_b32 v20, s35, 1
; SI-NEXT: v_writelane_b32 v20, s36, 2
@@ -202141,1039 +202266,1035 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: v_writelane_b32 v20, s99, 33
; SI-NEXT: v_writelane_b32 v20, s30, 34
; SI-NEXT: v_writelane_b32 v20, s31, 35
-; SI-NEXT: v_readfirstlane_b32 s37, v1
-; SI-NEXT: v_readfirstlane_b32 s39, v3
-; SI-NEXT: s_lshr_b32 s6, s37, 16
+; SI-NEXT: s_lshr_b32 s5, s16, 16
+; SI-NEXT: v_readfirstlane_b32 s49, v18
+; SI-NEXT: v_readfirstlane_b32 s51, v17
+; SI-NEXT: v_readfirstlane_b32 s38, v16
+; SI-NEXT: v_readfirstlane_b32 s48, v15
+; SI-NEXT: v_readfirstlane_b32 s37, v14
+; SI-NEXT: v_readfirstlane_b32 s95, v13
+; SI-NEXT: v_readfirstlane_b32 s96, v12
+; SI-NEXT: v_readfirstlane_b32 s36, v11
+; SI-NEXT: v_readfirstlane_b32 s85, v10
+; SI-NEXT: v_readfirstlane_b32 s87, v9
+; SI-NEXT: v_readfirstlane_b32 s34, v8
+; SI-NEXT: v_readfirstlane_b32 s84, v7
+; SI-NEXT: v_readfirstlane_b32 s71, v6
+; SI-NEXT: v_readfirstlane_b32 s81, v5
+; SI-NEXT: v_readfirstlane_b32 s68, v4
+; SI-NEXT: v_readfirstlane_b32 s70, v3
+; SI-NEXT: v_readfirstlane_b32 s67, v2
+; SI-NEXT: v_readfirstlane_b32 s31, v1
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
-; SI-NEXT: v_readfirstlane_b32 s49, v5
-; SI-NEXT: s_lshr_b32 s7, s39, 16
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v21, s6, 0
-; SI-NEXT: v_readfirstlane_b32 s51, v7
-; SI-NEXT: s_lshr_b32 s8, s49, 16
-; SI-NEXT: v_writelane_b32 v21, s7, 1
-; SI-NEXT: v_readfirstlane_b32 s53, v9
-; SI-NEXT: s_lshr_b32 s9, s51, 16
-; SI-NEXT: v_writelane_b32 v21, s8, 2
-; SI-NEXT: v_readfirstlane_b32 s55, v11
-; SI-NEXT: s_lshr_b32 s10, s53, 16
-; SI-NEXT: v_writelane_b32 v21, s9, 3
-; SI-NEXT: v_readfirstlane_b32 s65, v13
-; SI-NEXT: s_lshr_b32 s11, s55, 16
-; SI-NEXT: v_writelane_b32 v21, s10, 4
-; SI-NEXT: v_readfirstlane_b32 s68, v18
-; SI-NEXT: v_readfirstlane_b32 s69, v17
-; SI-NEXT: v_readfirstlane_b32 s66, v16
-; SI-NEXT: v_readfirstlane_b32 s67, v15
-; SI-NEXT: v_readfirstlane_b32 s64, v14
-; SI-NEXT: s_lshr_b32 vcc_lo, s65, 16
-; SI-NEXT: v_readfirstlane_b32 s54, v12
-; SI-NEXT: v_readfirstlane_b32 s52, v10
-; SI-NEXT: v_readfirstlane_b32 s50, v8
-; SI-NEXT: v_readfirstlane_b32 s48, v6
-; SI-NEXT: v_readfirstlane_b32 s38, v4
-; SI-NEXT: v_readfirstlane_b32 s36, v2
-; SI-NEXT: v_writelane_b32 v21, s11, 5
-; SI-NEXT: s_lshr_b32 s92, s29, 16
-; SI-NEXT: s_lshr_b32 s99, s28, 16
-; SI-NEXT: s_lshr_b32 s94, s27, 16
-; SI-NEXT: s_lshr_b32 s97, s26, 16
-; SI-NEXT: s_lshr_b32 s95, s25, 16
-; SI-NEXT: s_lshr_b32 s87, s24, 16
-; SI-NEXT: s_lshr_b32 s30, s23, 16
-; SI-NEXT: s_lshr_b32 s85, s22, 16
-; SI-NEXT: s_lshr_b32 s31, s21, 16
-; SI-NEXT: s_lshr_b32 s83, s20, 16
-; SI-NEXT: s_lshr_b32 s34, s19, 16
-; SI-NEXT: s_lshr_b32 s81, s18, 16
-; SI-NEXT: s_lshr_b32 s35, s17, 16
-; SI-NEXT: s_lshr_b32 s71, s16, 16
-; SI-NEXT: s_lshr_b32 s76, s68, 16
-; SI-NEXT: s_lshr_b32 s70, s69, 16
-; SI-NEXT: s_lshr_b32 s77, s66, 16
-; SI-NEXT: s_lshr_b32 vcc_hi, s67, 16
-; SI-NEXT: s_lshr_b32 s78, s64, 16
-; SI-NEXT: s_lshr_b32 s79, s54, 16
-; SI-NEXT: s_lshr_b32 s88, s52, 16
-; SI-NEXT: s_lshr_b32 s89, s50, 16
-; SI-NEXT: s_lshr_b32 s90, s48, 16
-; SI-NEXT: s_lshr_b32 s91, s38, 16
-; SI-NEXT: s_lshr_b32 s93, s36, 16
+; SI-NEXT: s_lshr_b32 s75, s29, 16
+; SI-NEXT: s_lshr_b32 s66, s28, 16
+; SI-NEXT: s_lshr_b32 s78, s27, 16
+; SI-NEXT: s_lshr_b32 s55, s26, 16
+; SI-NEXT: s_lshr_b32 s79, s25, 16
+; SI-NEXT: s_lshr_b32 s54, s24, 16
+; SI-NEXT: s_lshr_b32 s90, s23, 16
+; SI-NEXT: s_lshr_b32 s7, s22, 16
+; SI-NEXT: s_lshr_b32 s91, s21, 16
+; SI-NEXT: s_lshr_b32 s53, s20, 16
+; SI-NEXT: s_lshr_b32 s92, s19, 16
+; SI-NEXT: s_lshr_b32 s6, s18, 16
+; SI-NEXT: s_lshr_b32 s93, s17, 16
+; SI-NEXT: s_lshr_b32 s58, s49, 16
+; SI-NEXT: s_lshr_b32 s50, s51, 16
+; SI-NEXT: s_lshr_b32 s59, s38, 16
+; SI-NEXT: s_lshr_b32 s39, s48, 16
+; SI-NEXT: s_lshr_b32 s60, s37, 16
+; SI-NEXT: s_lshr_b32 s94, s95, 16
+; SI-NEXT: s_lshr_b32 s61, s96, 16
+; SI-NEXT: s_lshr_b32 s97, s36, 16
+; SI-NEXT: s_lshr_b32 s62, s85, 16
+; SI-NEXT: s_lshr_b32 s86, s87, 16
+; SI-NEXT: s_lshr_b32 s63, s34, 16
+; SI-NEXT: s_lshr_b32 s35, s84, 16
+; SI-NEXT: s_lshr_b32 s72, s71, 16
+; SI-NEXT: s_lshr_b32 s80, s81, 16
+; SI-NEXT: s_lshr_b32 s73, s68, 16
+; SI-NEXT: s_lshr_b32 s69, s70, 16
+; SI-NEXT: s_lshr_b32 s74, s67, 16
+; SI-NEXT: s_lshr_b32 s30, s31, 16
; SI-NEXT: v_readfirstlane_b32 s4, v19
-; SI-NEXT: v_writelane_b32 v21, vcc_lo, 6
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_writelane_b32 v21, s5, 0
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v21, vcc_hi, 7
-; SI-NEXT: v_writelane_b32 v21, s70, 8
+; SI-NEXT: v_writelane_b32 v21, s6, 1
+; SI-NEXT: v_writelane_b32 v21, s7, 2
; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
+; SI-NEXT: ; implicit-def: $vgpr23 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB99_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s71, 16
-; SI-NEXT: s_or_b32 s72, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: s_or_b32 s98, s4, s5
; SI-NEXT: s_and_b32 s4, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s35, 16
-; SI-NEXT: s_or_b32 s73, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s93, 16
+; SI-NEXT: s_or_b32 s99, s4, s5
; SI-NEXT: s_and_b32 s4, s18, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s81, 16
-; SI-NEXT: s_or_b32 s62, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s6, 16
+; SI-NEXT: s_or_b32 s82, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s34, 16
-; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s92, 16
+; SI-NEXT: s_or_b32 s83, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s83, 16
-; SI-NEXT: s_or_b32 s58, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s53, 16
+; SI-NEXT: s_or_b32 s64, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s31, 16
-; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s91, 16
+; SI-NEXT: s_or_b32 s65, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s85, 16
-; SI-NEXT: s_or_b32 s46, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s7, 16
+; SI-NEXT: s_or_b32 s88, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s30, 16
-; SI-NEXT: s_or_b32 s47, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s90, 16
+; SI-NEXT: s_or_b32 s89, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s87, 16
-; SI-NEXT: s_or_b32 s44, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s54, 16
+; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s95, 16
-; SI-NEXT: s_or_b32 s45, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s79, 16
+; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s97, 16
-; SI-NEXT: s_or_b32 s74, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s55, 16
+; SI-NEXT: s_or_b32 s76, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s94, 16
-; SI-NEXT: s_or_b32 s75, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s78, 16
+; SI-NEXT: s_or_b32 s77, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s99, 16
-; SI-NEXT: s_or_b32 s60, s4, s5
+; SI-NEXT: s_lshl_b32 s5, s66, 16
+; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s92, 16
-; SI-NEXT: s_or_b32 s61, s4, s5
-; SI-NEXT: s_and_b32 s4, s37, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s6, 16
-; SI-NEXT: s_or_b32 s56, s4, s5
-; SI-NEXT: s_and_b32 s4, s36, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s93, 16
-; SI-NEXT: s_or_b32 s57, s4, s5
-; SI-NEXT: s_and_b32 s4, s39, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s7, 16
+; SI-NEXT: s_lshl_b32 s5, s75, 16
+; SI-NEXT: s_or_b32 s47, s4, s5
+; SI-NEXT: s_and_b32 s4, s31, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s30, 16
+; SI-NEXT: s_or_b32 s44, s4, s5
+; SI-NEXT: s_and_b32 s4, s67, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s74, 16
+; SI-NEXT: s_or_b32 s45, s4, s5
+; SI-NEXT: s_and_b32 s4, s70, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s69, 16
; SI-NEXT: s_or_b32 s42, s4, s5
-; SI-NEXT: s_and_b32 s4, s38, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s91, 16
+; SI-NEXT: s_and_b32 s4, s68, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s43, s4, s5
-; SI-NEXT: s_and_b32 s4, s49, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s8, 16
+; SI-NEXT: s_and_b32 s4, s81, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s80, 16
; SI-NEXT: s_or_b32 s40, s4, s5
-; SI-NEXT: s_and_b32 s4, s48, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s90, 16
+; SI-NEXT: s_and_b32 s4, s71, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s41, s4, s5
-; SI-NEXT: s_and_b32 s4, s51, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s9, 16
+; SI-NEXT: s_and_b32 s4, s84, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s14, s4, s5
-; SI-NEXT: s_and_b32 s4, s50, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s89, 16
+; SI-NEXT: s_and_b32 s4, s34, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s15, s4, s5
-; SI-NEXT: s_and_b32 s4, s53, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s10, 16
+; SI-NEXT: s_and_b32 s4, s87, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s86, 16
; SI-NEXT: s_or_b32 s12, s4, s5
-; SI-NEXT: s_and_b32 s4, s52, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s88, 16
+; SI-NEXT: s_and_b32 s4, s85, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s13, s4, s5
-; SI-NEXT: s_and_b32 s4, s55, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s11, 16
+; SI-NEXT: s_and_b32 s4, s36, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s97, 16
; SI-NEXT: s_or_b32 s10, s4, s5
-; SI-NEXT: s_and_b32 s4, s54, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s79, 16
+; SI-NEXT: s_and_b32 s4, s96, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s11, s4, s5
-; SI-NEXT: s_and_b32 s4, s65, 0xffff
-; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; SI-NEXT: s_and_b32 s4, s95, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s94, 16
; SI-NEXT: s_or_b32 s8, s4, s5
-; SI-NEXT: s_and_b32 s4, s64, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s78, 16
+; SI-NEXT: s_and_b32 s4, s37, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s9, s4, s5
-; SI-NEXT: s_and_b32 s4, s67, 0xffff
-; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
+; SI-NEXT: s_and_b32 s4, s48, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s39, 16
; SI-NEXT: s_or_b32 s6, s4, s5
-; SI-NEXT: s_and_b32 s4, s66, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s77, 16
+; SI-NEXT: s_and_b32 s4, s38, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s59, 16
; SI-NEXT: s_or_b32 s7, s4, s5
-; SI-NEXT: s_and_b32 s4, s69, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s70, 16
+; SI-NEXT: s_and_b32 s4, s51, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s50, 16
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: s_and_b32 s5, s68, 0xffff
-; SI-NEXT: s_lshl_b32 vcc_lo, s76, 16
+; SI-NEXT: s_and_b32 s5, s49, 0xffff
+; SI-NEXT: s_lshl_b32 vcc_lo, s58, 16
; SI-NEXT: s_or_b32 s5, s5, vcc_lo
-; SI-NEXT: s_lshr_b32 vcc_lo, s73, 8
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 28
-; SI-NEXT: s_lshr_b32 vcc_lo, s63, 8
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 30
-; SI-NEXT: s_lshr_b32 vcc_lo, s59, 8
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 32
-; SI-NEXT: s_lshr_b32 vcc_lo, s47, 8
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 34
-; SI-NEXT: s_lshr_b32 vcc_lo, s45, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s99, 8
+; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 36
-; SI-NEXT: s_lshr_b32 vcc_lo, s75, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s83, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 38
-; SI-NEXT: s_lshr_b32 vcc_lo, s61, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s65, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 40
-; SI-NEXT: s_lshr_b32 vcc_lo, s57, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s89, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 42
-; SI-NEXT: s_lshr_b32 vcc_lo, s43, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s57, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 44
-; SI-NEXT: s_lshr_b32 vcc_lo, s41, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s77, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 46
-; SI-NEXT: s_lshr_b32 vcc_lo, s15, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s47, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 48
-; SI-NEXT: s_lshr_b32 vcc_lo, s13, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s45, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 50
-; SI-NEXT: s_lshr_b32 vcc_lo, s11, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s43, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 52
-; SI-NEXT: s_lshr_b32 vcc_lo, s9, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s41, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 54
-; SI-NEXT: s_lshr_b32 vcc_lo, s7, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s15, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 56
-; SI-NEXT: s_lshr_b32 vcc_lo, s5, 8
+; SI-NEXT: s_lshr_b32 vcc_lo, s13, 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 58
-; SI-NEXT: s_bfe_u32 vcc_lo, s35, 0x80008
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 27
-; SI-NEXT: s_bfe_u32 vcc_lo, s34, 0x80008
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 29
-; SI-NEXT: s_bfe_u32 vcc_lo, s31, 0x80008
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 31
-; SI-NEXT: s_bfe_u32 vcc_lo, s30, 0x80008
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 33
-; SI-NEXT: s_bfe_u32 vcc_lo, s95, 0x80008
+; SI-NEXT: s_lshr_b32 vcc_lo, s11, 8
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 60
+; SI-NEXT: s_lshr_b32 vcc_lo, s9, 8
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 62
+; SI-NEXT: s_lshr_b32 vcc_lo, s7, 8
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v23, vcc_lo, 0
+; SI-NEXT: s_bfe_u32 vcc_lo, s93, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 35
-; SI-NEXT: s_bfe_u32 vcc_lo, s94, 0x80008
-; SI-NEXT: v_writelane_b32 v22, vcc_lo, 37
; SI-NEXT: s_bfe_u32 vcc_lo, s92, 0x80008
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 37
+; SI-NEXT: s_bfe_u32 vcc_lo, s91, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 39
-; SI-NEXT: s_bfe_u32 vcc_lo, s93, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s90, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 41
-; SI-NEXT: s_bfe_u32 vcc_lo, s91, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s79, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 43
-; SI-NEXT: s_bfe_u32 vcc_lo, s90, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s78, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 45
-; SI-NEXT: s_bfe_u32 vcc_lo, s89, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s75, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 47
-; SI-NEXT: s_bfe_u32 vcc_lo, s88, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s74, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 49
-; SI-NEXT: s_bfe_u32 vcc_lo, s79, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s73, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 51
-; SI-NEXT: s_bfe_u32 vcc_lo, s78, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s72, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 53
-; SI-NEXT: s_bfe_u32 vcc_lo, s77, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s63, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 55
-; SI-NEXT: s_bfe_u32 vcc_lo, s76, 0x80008
+; SI-NEXT: s_bfe_u32 vcc_lo, s62, 0x80008
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 57
-; SI-NEXT: s_lshr_b64 vcc, s[72:73], 24
+; SI-NEXT: s_bfe_u32 vcc_lo, s61, 0x80008
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 59
+; SI-NEXT: s_bfe_u32 vcc_lo, s60, 0x80008
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 61
+; SI-NEXT: s_bfe_u32 vcc_lo, s59, 0x80008
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 63
+; SI-NEXT: s_bfe_u32 vcc_lo, s58, 0x80008
+; SI-NEXT: v_writelane_b32 v23, vcc_lo, 1
+; SI-NEXT: s_lshr_b64 vcc, s[98:99], 24
+; SI-NEXT: v_writelane_b32 v21, vcc_lo, 7
+; SI-NEXT: v_writelane_b32 v21, vcc_hi, 8
+; SI-NEXT: s_lshr_b64 vcc, s[98:99], 16
+; SI-NEXT: v_writelane_b32 v21, vcc_lo, 5
+; SI-NEXT: v_writelane_b32 v21, vcc_hi, 6
+; SI-NEXT: s_lshr_b64 vcc, s[98:99], 8
+; SI-NEXT: v_writelane_b32 v21, vcc_lo, 3
+; SI-NEXT: v_writelane_b32 v21, vcc_hi, 4
+; SI-NEXT: s_lshr_b64 vcc, s[82:83], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 13
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 14
-; SI-NEXT: s_lshr_b64 vcc, s[72:73], 16
+; SI-NEXT: s_lshr_b64 vcc, s[82:83], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 11
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 12
-; SI-NEXT: s_lshr_b64 vcc, s[72:73], 8
+; SI-NEXT: s_lshr_b64 vcc, s[82:83], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 9
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 10
-; SI-NEXT: s_lshr_b64 vcc, s[62:63], 24
+; SI-NEXT: s_lshr_b64 vcc, s[64:65], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 19
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 20
-; SI-NEXT: s_lshr_b64 vcc, s[62:63], 16
+; SI-NEXT: s_lshr_b64 vcc, s[64:65], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 17
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 18
-; SI-NEXT: s_lshr_b64 vcc, s[62:63], 8
+; SI-NEXT: s_lshr_b64 vcc, s[64:65], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 15
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 16
-; SI-NEXT: s_lshr_b64 vcc, s[58:59], 24
+; SI-NEXT: s_lshr_b64 vcc, s[88:89], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 25
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 26
-; SI-NEXT: s_lshr_b64 vcc, s[58:59], 16
+; SI-NEXT: s_lshr_b64 vcc, s[88:89], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 23
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 24
-; SI-NEXT: s_lshr_b64 vcc, s[58:59], 8
+; SI-NEXT: s_lshr_b64 vcc, s[88:89], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 21
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 22
-; SI-NEXT: s_lshr_b64 vcc, s[46:47], 24
+; SI-NEXT: s_lshr_b64 vcc, s[56:57], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 31
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 32
-; SI-NEXT: s_lshr_b64 vcc, s[46:47], 16
+; SI-NEXT: s_lshr_b64 vcc, s[56:57], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 29
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 30
-; SI-NEXT: s_lshr_b64 vcc, s[46:47], 8
+; SI-NEXT: s_lshr_b64 vcc, s[56:57], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 27
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 28
-; SI-NEXT: s_mov_b32 vcc_lo, s87
-; SI-NEXT: s_lshr_b64 s[86:87], s[44:45], 24
-; SI-NEXT: s_mov_b32 s87, vcc_lo
-; SI-NEXT: s_mov_b32 vcc_lo, s97
-; SI-NEXT: s_lshr_b64 s[96:97], s[44:45], 16
-; SI-NEXT: s_mov_b32 s97, vcc_lo
-; SI-NEXT: s_mov_b32 vcc_lo, s99
-; SI-NEXT: s_lshr_b64 s[98:99], s[44:45], 8
-; SI-NEXT: s_mov_b32 s99, vcc_lo
-; SI-NEXT: s_mov_b32 vcc_lo, s81
-; SI-NEXT: s_lshr_b64 s[80:81], s[74:75], 24
-; SI-NEXT: s_mov_b32 s81, vcc_lo
-; SI-NEXT: s_mov_b32 vcc_lo, s83
-; SI-NEXT: s_lshr_b64 s[82:83], s[74:75], 16
-; SI-NEXT: s_mov_b32 s83, vcc_lo
-; SI-NEXT: s_mov_b32 vcc_lo, s85
-; SI-NEXT: s_lshr_b64 s[84:85], s[74:75], 8
-; SI-NEXT: s_mov_b32 s85, vcc_lo
-; SI-NEXT: s_lshr_b64 vcc, s[60:61], 24
+; SI-NEXT: s_lshr_b64 vcc, s[76:77], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 37
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 38
-; SI-NEXT: s_lshr_b64 vcc, s[60:61], 16
+; SI-NEXT: s_lshr_b64 vcc, s[76:77], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 35
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 36
-; SI-NEXT: s_lshr_b64 vcc, s[60:61], 8
+; SI-NEXT: s_lshr_b64 vcc, s[76:77], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 33
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 34
-; SI-NEXT: s_lshr_b64 vcc, s[56:57], 24
+; SI-NEXT: s_lshr_b64 vcc, s[46:47], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 43
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 44
-; SI-NEXT: s_lshr_b64 vcc, s[56:57], 16
+; SI-NEXT: s_lshr_b64 vcc, s[46:47], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 41
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 42
-; SI-NEXT: s_lshr_b64 vcc, s[56:57], 8
+; SI-NEXT: s_lshr_b64 vcc, s[46:47], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 39
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 40
-; SI-NEXT: s_lshr_b64 vcc, s[42:43], 24
+; SI-NEXT: s_lshr_b64 vcc, s[44:45], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 49
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 50
-; SI-NEXT: s_lshr_b64 vcc, s[42:43], 16
+; SI-NEXT: s_lshr_b64 vcc, s[44:45], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 47
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 48
-; SI-NEXT: s_lshr_b64 vcc, s[42:43], 8
+; SI-NEXT: s_lshr_b64 vcc, s[44:45], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 45
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 46
-; SI-NEXT: s_lshr_b64 vcc, s[40:41], 24
+; SI-NEXT: s_lshr_b64 vcc, s[42:43], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 55
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 56
-; SI-NEXT: s_lshr_b64 vcc, s[40:41], 16
+; SI-NEXT: s_lshr_b64 vcc, s[42:43], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 53
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 54
-; SI-NEXT: s_lshr_b64 vcc, s[40:41], 8
+; SI-NEXT: s_lshr_b64 vcc, s[42:43], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 51
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 52
-; SI-NEXT: s_lshr_b64 vcc, s[14:15], 24
+; SI-NEXT: s_lshr_b64 vcc, s[40:41], 24
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 61
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 62
-; SI-NEXT: s_lshr_b64 vcc, s[14:15], 16
+; SI-NEXT: s_lshr_b64 vcc, s[40:41], 16
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 59
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 60
-; SI-NEXT: s_lshr_b64 vcc, s[14:15], 8
+; SI-NEXT: s_lshr_b64 vcc, s[40:41], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 57
; SI-NEXT: v_writelane_b32 v21, vcc_hi, 58
-; SI-NEXT: s_lshr_b64 vcc, s[12:13], 24
+; SI-NEXT: s_lshr_b64 vcc, s[14:15], 24
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 3
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 4
-; SI-NEXT: s_lshr_b64 vcc, s[12:13], 16
+; SI-NEXT: s_lshr_b64 vcc, s[14:15], 16
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 1
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 2
-; SI-NEXT: s_lshr_b64 vcc, s[12:13], 8
+; SI-NEXT: s_lshr_b64 vcc, s[14:15], 8
; SI-NEXT: v_writelane_b32 v21, vcc_lo, 63
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 0
-; SI-NEXT: s_lshr_b64 vcc, s[10:11], 24
+; SI-NEXT: s_lshr_b64 vcc, s[12:13], 24
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 9
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 10
-; SI-NEXT: s_lshr_b64 vcc, s[10:11], 16
+; SI-NEXT: s_lshr_b64 vcc, s[12:13], 16
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 7
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 8
-; SI-NEXT: s_lshr_b64 vcc, s[10:11], 8
+; SI-NEXT: s_lshr_b64 vcc, s[12:13], 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 5
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 6
-; SI-NEXT: s_lshr_b64 vcc, s[8:9], 24
+; SI-NEXT: s_lshr_b64 vcc, s[10:11], 24
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 15
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 16
-; SI-NEXT: s_lshr_b64 vcc, s[8:9], 16
+; SI-NEXT: s_lshr_b64 vcc, s[10:11], 16
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 13
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 14
-; SI-NEXT: s_lshr_b64 vcc, s[8:9], 8
+; SI-NEXT: s_lshr_b64 vcc, s[10:11], 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 11
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 12
-; SI-NEXT: s_lshr_b64 vcc, s[6:7], 24
+; SI-NEXT: s_lshr_b64 vcc, s[8:9], 24
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 21
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 22
-; SI-NEXT: s_lshr_b64 vcc, s[6:7], 16
+; SI-NEXT: s_lshr_b64 vcc, s[8:9], 16
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 19
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 20
-; SI-NEXT: s_lshr_b64 vcc, s[6:7], 8
+; SI-NEXT: s_lshr_b64 vcc, s[8:9], 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 17
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 18
-; SI-NEXT: s_lshr_b64 vcc, s[4:5], 24
+; SI-NEXT: s_lshr_b64 vcc, s[6:7], 24
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 27
+; SI-NEXT: v_writelane_b32 v22, vcc_hi, 28
+; SI-NEXT: s_lshr_b64 vcc, s[6:7], 16
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 25
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 26
-; SI-NEXT: s_mov_b32 vcc_lo, s71
-; SI-NEXT: s_lshr_b64 s[70:71], s[4:5], 16
-; SI-NEXT: s_mov_b32 s71, vcc_lo
-; SI-NEXT: s_lshr_b64 vcc, s[4:5], 8
+; SI-NEXT: s_lshr_b64 vcc, s[6:7], 8
; SI-NEXT: v_writelane_b32 v22, vcc_lo, 23
; SI-NEXT: v_writelane_b32 v22, vcc_hi, 24
+; SI-NEXT: s_lshr_b64 vcc, s[4:5], 24
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 33
+; SI-NEXT: v_writelane_b32 v22, vcc_hi, 34
+; SI-NEXT: s_lshr_b64 vcc, s[4:5], 16
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 31
+; SI-NEXT: v_writelane_b32 v22, vcc_hi, 32
+; SI-NEXT: s_lshr_b64 vcc, s[4:5], 8
+; SI-NEXT: v_writelane_b32 v22, vcc_lo, 29
+; SI-NEXT: s_lshr_b32 s52, s5, 8
+; SI-NEXT: v_writelane_b32 v22, vcc_hi, 30
; SI-NEXT: s_cbranch_execnz .LBB99_3
; SI-NEXT: .LBB99_2: ; %cmp.true
-; SI-NEXT: s_add_i32 s69, s69, 3
-; SI-NEXT: v_readlane_b32 s5, v21, 8
-; SI-NEXT: s_and_b32 s4, s69, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_add_i32 s68, s68, 3
+; SI-NEXT: s_add_i32 s51, s51, 3
+; SI-NEXT: s_and_b32 s4, s51, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s50, 16
+; SI-NEXT: s_add_i32 s49, s49, 3
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: s_and_b32 s5, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s6, s76, 16
-; SI-NEXT: s_add_i32 s67, s67, 3
-; SI-NEXT: v_readlane_b32 s7, v21, 7
+; SI-NEXT: s_and_b32 s5, s49, 0xffff
+; SI-NEXT: s_lshl_b32 s6, s58, 16
+; SI-NEXT: s_add_i32 s48, s48, 3
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: s_and_b32 s6, s67, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_add_i32 s66, s66, 3
+; SI-NEXT: s_and_b32 s6, s48, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s39, 16
+; SI-NEXT: s_add_i32 s38, s38, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_and_b32 s7, s66, 0xffff
-; SI-NEXT: s_lshl_b32 s8, s77, 16
-; SI-NEXT: s_add_i32 s65, s65, 3
-; SI-NEXT: v_readlane_b32 s9, v21, 6
+; SI-NEXT: s_and_b32 s7, s38, 0xffff
+; SI-NEXT: s_lshl_b32 s8, s59, 16
+; SI-NEXT: s_add_i32 s95, s95, 3
; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: s_and_b32 s8, s65, 0xffff
-; SI-NEXT: s_lshl_b32 s9, s9, 16
-; SI-NEXT: s_add_i32 s64, s64, 3
+; SI-NEXT: s_and_b32 s8, s95, 0xffff
+; SI-NEXT: s_lshl_b32 s9, s94, 16
+; SI-NEXT: s_add_i32 s37, s37, 3
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: s_and_b32 s9, s64, 0xffff
-; SI-NEXT: s_lshl_b32 s10, s78, 16
-; SI-NEXT: s_add_i32 s55, s55, 3
-; SI-NEXT: v_readlane_b32 s11, v21, 5
+; SI-NEXT: s_and_b32 s9, s37, 0xffff
+; SI-NEXT: s_lshl_b32 s10, s60, 16
+; SI-NEXT: s_add_i32 s36, s36, 3
; SI-NEXT: s_or_b32 s9, s10, s9
-; SI-NEXT: s_and_b32 s10, s55, 0xffff
-; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: s_add_i32 s54, s54, 3
+; SI-NEXT: s_and_b32 s10, s36, 0xffff
+; SI-NEXT: s_lshl_b32 s11, s97, 16
+; SI-NEXT: s_add_i32 s96, s96, 3
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: s_and_b32 s11, s54, 0xffff
-; SI-NEXT: s_lshl_b32 s12, s79, 16
-; SI-NEXT: s_add_i32 s53, s53, 3
-; SI-NEXT: v_readlane_b32 s13, v21, 4
+; SI-NEXT: s_and_b32 s11, s96, 0xffff
+; SI-NEXT: s_lshl_b32 s12, s61, 16
+; SI-NEXT: s_add_i32 s87, s87, 3
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: s_and_b32 s12, s53, 0xffff
-; SI-NEXT: s_lshl_b32 s13, s13, 16
-; SI-NEXT: s_add_i32 s52, s52, 3
+; SI-NEXT: s_and_b32 s12, s87, 0xffff
+; SI-NEXT: s_lshl_b32 s13, s86, 16
+; SI-NEXT: s_add_i32 s85, s85, 3
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: s_and_b32 s13, s52, 0xffff
-; SI-NEXT: s_lshl_b32 s14, s88, 16
-; SI-NEXT: s_add_i32 s51, s51, 3
-; SI-NEXT: v_readlane_b32 s15, v21, 3
+; SI-NEXT: s_and_b32 s13, s85, 0xffff
+; SI-NEXT: s_lshl_b32 s14, s62, 16
+; SI-NEXT: s_add_i32 s84, s84, 3
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: s_and_b32 s14, s51, 0xffff
-; SI-NEXT: s_lshl_b32 s15, s15, 16
-; SI-NEXT: s_add_i32 s50, s50, 3
+; SI-NEXT: s_and_b32 s14, s84, 0xffff
+; SI-NEXT: s_lshl_b32 s15, s35, 16
+; SI-NEXT: s_add_i32 s34, s34, 3
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: s_and_b32 s15, s50, 0xffff
-; SI-NEXT: s_lshl_b32 s40, s89, 16
-; SI-NEXT: s_add_i32 s49, s49, 3
-; SI-NEXT: v_readlane_b32 s41, v21, 2
+; SI-NEXT: s_and_b32 s15, s34, 0xffff
+; SI-NEXT: s_lshl_b32 s40, s63, 16
+; SI-NEXT: s_add_i32 s81, s81, 3
; SI-NEXT: s_or_b32 s15, s40, s15
-; SI-NEXT: s_and_b32 s40, s49, 0xffff
-; SI-NEXT: s_lshl_b32 s41, s41, 16
-; SI-NEXT: s_add_i32 s48, s48, 3
+; SI-NEXT: s_and_b32 s40, s81, 0xffff
+; SI-NEXT: s_lshl_b32 s41, s80, 16
+; SI-NEXT: s_add_i32 s71, s71, 3
; SI-NEXT: s_or_b32 s40, s41, s40
-; SI-NEXT: s_and_b32 s41, s48, 0xffff
-; SI-NEXT: s_lshl_b32 s42, s90, 16
-; SI-NEXT: s_add_i32 s39, s39, 3
-; SI-NEXT: v_readlane_b32 s43, v21, 1
+; SI-NEXT: s_and_b32 s41, s71, 0xffff
+; SI-NEXT: s_lshl_b32 s42, s72, 16
+; SI-NEXT: s_add_i32 s70, s70, 3
; SI-NEXT: s_or_b32 s41, s42, s41
-; SI-NEXT: s_and_b32 s42, s39, 0xffff
-; SI-NEXT: s_lshl_b32 s43, s43, 16
-; SI-NEXT: s_add_i32 s38, s38, 3
+; SI-NEXT: s_and_b32 s42, s70, 0xffff
+; SI-NEXT: s_lshl_b32 s43, s69, 16
+; SI-NEXT: s_add_i32 s68, s68, 3
; SI-NEXT: s_or_b32 s42, s43, s42
-; SI-NEXT: s_and_b32 s43, s38, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s91, 16
-; SI-NEXT: s_add_i32 s37, s37, 3
-; SI-NEXT: v_readlane_b32 s45, v21, 0
+; SI-NEXT: s_and_b32 s43, s68, 0xffff
+; SI-NEXT: s_lshl_b32 s44, s73, 16
+; SI-NEXT: s_add_i32 s31, s31, 3
; SI-NEXT: s_or_b32 s43, s44, s43
-; SI-NEXT: s_and_b32 s44, s37, 0xffff
-; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_or_b32 s44, s45, s44
-; SI-NEXT: s_add_i32 s36, s36, 3
-; SI-NEXT: s_add_i32 s56, s44, 0x30000
-; SI-NEXT: s_and_b32 s44, s36, 0xffff
-; SI-NEXT: s_lshl_b32 s45, s93, 16
+; SI-NEXT: s_and_b32 s44, s31, 0xffff
+; SI-NEXT: s_lshl_b32 s45, s30, 16
+; SI-NEXT: s_add_i32 s67, s67, 3
; SI-NEXT: s_or_b32 s44, s45, s44
+; SI-NEXT: s_and_b32 s45, s67, 0xffff
+; SI-NEXT: s_lshl_b32 s46, s74, 16
; SI-NEXT: s_add_i32 s28, s28, 3
-; SI-NEXT: s_add_i32 s57, s44, 0x30000
+; SI-NEXT: s_or_b32 s45, s46, s45
; SI-NEXT: s_and_b32 s28, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s99, 16
-; SI-NEXT: s_or_b32 s28, s44, s28
+; SI-NEXT: s_lshl_b32 s46, s66, 16
+; SI-NEXT: s_or_b32 s28, s46, s28
; SI-NEXT: s_add_i32 s29, s29, 3
-; SI-NEXT: s_add_i32 s60, s28, 0x30000
+; SI-NEXT: s_add_i32 s46, s28, 0x30000
; SI-NEXT: s_and_b32 s28, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s29, s92, 16
+; SI-NEXT: s_lshl_b32 s29, s75, 16
; SI-NEXT: s_or_b32 s28, s29, s28
; SI-NEXT: s_add_i32 s26, s26, 3
-; SI-NEXT: s_add_i32 s61, s28, 0x30000
+; SI-NEXT: s_add_i32 s47, s28, 0x30000
; SI-NEXT: s_and_b32 s26, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s28, s97, 16
+; SI-NEXT: s_lshl_b32 s28, s55, 16
; SI-NEXT: s_or_b32 s26, s28, s26
; SI-NEXT: s_add_i32 s27, s27, 3
-; SI-NEXT: s_add_i32 s74, s26, 0x30000
+; SI-NEXT: s_add_i32 s76, s26, 0x30000
; SI-NEXT: s_and_b32 s26, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s27, s94, 16
+; SI-NEXT: s_lshl_b32 s27, s78, 16
; SI-NEXT: s_or_b32 s26, s27, s26
; SI-NEXT: s_add_i32 s24, s24, 3
-; SI-NEXT: s_add_i32 s75, s26, 0x30000
+; SI-NEXT: s_add_i32 s77, s26, 0x30000
; SI-NEXT: s_and_b32 s24, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s26, s87, 16
+; SI-NEXT: s_lshl_b32 s26, s54, 16
; SI-NEXT: s_or_b32 s24, s26, s24
; SI-NEXT: s_add_i32 s25, s25, 3
-; SI-NEXT: s_add_i32 s44, s24, 0x30000
+; SI-NEXT: s_add_i32 s56, s24, 0x30000
; SI-NEXT: s_and_b32 s24, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s25, s95, 16
+; SI-NEXT: s_lshl_b32 s25, s79, 16
; SI-NEXT: s_or_b32 s24, s25, s24
+; SI-NEXT: s_add_i32 s57, s24, 0x30000
; SI-NEXT: s_add_i32 s22, s22, 3
-; SI-NEXT: s_add_i32 s45, s24, 0x30000
+; SI-NEXT: v_readlane_b32 s24, v21, 2
; SI-NEXT: s_and_b32 s22, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s24, s85, 16
+; SI-NEXT: s_lshl_b32 s24, s24, 16
; SI-NEXT: s_or_b32 s22, s24, s22
; SI-NEXT: s_add_i32 s23, s23, 3
-; SI-NEXT: s_add_i32 s46, s22, 0x30000
+; SI-NEXT: s_add_i32 s88, s22, 0x30000
; SI-NEXT: s_and_b32 s22, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s23, s30, 16
+; SI-NEXT: s_lshl_b32 s23, s90, 16
; SI-NEXT: s_or_b32 s22, s23, s22
; SI-NEXT: s_add_i32 s20, s20, 3
-; SI-NEXT: s_add_i32 s47, s22, 0x30000
+; SI-NEXT: s_add_i32 s89, s22, 0x30000
; SI-NEXT: s_and_b32 s20, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s22, s83, 16
+; SI-NEXT: s_lshl_b32 s22, s53, 16
; SI-NEXT: s_or_b32 s20, s22, s20
; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: s_add_i32 s58, s20, 0x30000
+; SI-NEXT: s_add_i32 s64, s20, 0x30000
; SI-NEXT: s_and_b32 s20, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s21, s31, 16
+; SI-NEXT: s_lshl_b32 s21, s91, 16
; SI-NEXT: s_or_b32 s20, s21, s20
+; SI-NEXT: s_add_i32 s65, s20, 0x30000
; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_add_i32 s59, s20, 0x30000
+; SI-NEXT: v_readlane_b32 s20, v21, 1
; SI-NEXT: s_and_b32 s18, s18, 0xffff
-; SI-NEXT: s_lshl_b32 s20, s81, 16
+; SI-NEXT: s_lshl_b32 s20, s20, 16
; SI-NEXT: s_or_b32 s18, s20, s18
; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: s_add_i32 s62, s18, 0x30000
+; SI-NEXT: s_add_i32 s82, s18, 0x30000
; SI-NEXT: s_and_b32 s18, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s19, s34, 16
+; SI-NEXT: s_lshl_b32 s19, s92, 16
; SI-NEXT: s_or_b32 s18, s19, s18
+; SI-NEXT: s_add_i32 s83, s18, 0x30000
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: s_add_i32 s63, s18, 0x30000
+; SI-NEXT: v_readlane_b32 s18, v21, 0
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s18, s71, 16
+; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: s_or_b32 s16, s18, s16
; SI-NEXT: s_add_i32 s17, s17, 3
-; SI-NEXT: s_add_i32 s72, s16, 0x30000
+; SI-NEXT: s_add_i32 s98, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s35, 16
+; SI-NEXT: s_lshl_b32 s17, s93, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s73, s16, 0x30000
-; SI-NEXT: s_lshr_b64 s[16:17], s[72:73], 24
+; SI-NEXT: s_add_i32 s99, s16, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[98:99], 24
+; SI-NEXT: v_writelane_b32 v21, s16, 7
+; SI-NEXT: v_writelane_b32 v21, s17, 8
+; SI-NEXT: s_lshr_b64 s[16:17], s[98:99], 16
+; SI-NEXT: v_writelane_b32 v21, s16, 5
+; SI-NEXT: v_writelane_b32 v21, s17, 6
+; SI-NEXT: s_lshr_b64 s[16:17], s[98:99], 8
+; SI-NEXT: v_writelane_b32 v21, s16, 3
+; SI-NEXT: v_writelane_b32 v21, s17, 4
+; SI-NEXT: s_lshr_b64 s[16:17], s[82:83], 24
; SI-NEXT: v_writelane_b32 v21, s16, 13
; SI-NEXT: v_writelane_b32 v21, s17, 14
-; SI-NEXT: s_lshr_b64 s[16:17], s[72:73], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[82:83], 16
; SI-NEXT: v_writelane_b32 v21, s16, 11
; SI-NEXT: v_writelane_b32 v21, s17, 12
-; SI-NEXT: s_lshr_b64 s[16:17], s[72:73], 8
+; SI-NEXT: s_lshr_b64 s[16:17], s[82:83], 8
; SI-NEXT: v_writelane_b32 v21, s16, 9
; SI-NEXT: v_writelane_b32 v21, s17, 10
-; SI-NEXT: s_lshr_b32 s16, s73, 24
-; SI-NEXT: v_writelane_b32 v22, s16, 27
-; SI-NEXT: s_lshr_b32 s16, s73, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 28
-; SI-NEXT: s_lshr_b32 s16, s63, 24
-; SI-NEXT: v_writelane_b32 v22, s16, 29
-; SI-NEXT: s_lshr_b32 s16, s63, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 30
-; SI-NEXT: s_lshr_b32 s16, s59, 24
-; SI-NEXT: v_writelane_b32 v22, s16, 31
-; SI-NEXT: s_lshr_b32 s16, s59, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 32
-; SI-NEXT: s_lshr_b32 s16, s47, 24
-; SI-NEXT: v_writelane_b32 v22, s16, 33
-; SI-NEXT: s_lshr_b32 s16, s47, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 34
-; SI-NEXT: s_lshr_b32 s16, s45, 24
-; SI-NEXT: v_writelane_b32 v22, s16, 35
-; SI-NEXT: s_lshr_b32 s16, s45, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 36
-; SI-NEXT: s_lshr_b32 s16, s75, 24
-; SI-NEXT: v_writelane_b32 v22, s16, 37
-; SI-NEXT: s_lshr_b32 s16, s75, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 38
-; SI-NEXT: s_lshr_b32 s16, s61, 24
-; SI-NEXT: v_writelane_b32 v22, s16, 39
-; SI-NEXT: s_lshr_b32 s16, s61, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 40
-; SI-NEXT: s_lshr_b32 s16, s57, 24
-; SI-NEXT: s_add_i32 s43, s43, 0x30000
-; SI-NEXT: v_writelane_b32 v22, s16, 41
-; SI-NEXT: s_lshr_b32 s16, s57, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 42
-; SI-NEXT: s_lshr_b32 s16, s43, 24
-; SI-NEXT: s_add_i32 s41, s41, 0x30000
-; SI-NEXT: v_writelane_b32 v22, s16, 43
-; SI-NEXT: s_lshr_b32 s16, s43, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 44
-; SI-NEXT: s_lshr_b32 s16, s41, 24
-; SI-NEXT: s_add_i32 s15, s15, 0x30000
-; SI-NEXT: v_writelane_b32 v22, s16, 45
-; SI-NEXT: s_lshr_b32 s16, s41, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 46
-; SI-NEXT: s_lshr_b32 s16, s15, 24
-; SI-NEXT: s_add_i32 s13, s13, 0x30000
-; SI-NEXT: v_writelane_b32 v22, s16, 47
-; SI-NEXT: s_lshr_b32 s16, s15, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 48
-; SI-NEXT: s_lshr_b32 s16, s13, 24
-; SI-NEXT: s_add_i32 s11, s11, 0x30000
-; SI-NEXT: v_writelane_b32 v22, s16, 49
-; SI-NEXT: s_lshr_b32 s16, s13, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 50
-; SI-NEXT: s_lshr_b32 s16, s11, 24
-; SI-NEXT: s_add_i32 s9, s9, 0x30000
-; SI-NEXT: v_writelane_b32 v22, s16, 51
-; SI-NEXT: s_lshr_b32 s16, s11, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 52
-; SI-NEXT: s_lshr_b32 s16, s9, 24
-; SI-NEXT: s_add_i32 s7, s7, 0x30000
-; SI-NEXT: v_writelane_b32 v22, s16, 53
-; SI-NEXT: s_lshr_b32 s16, s9, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 54
-; SI-NEXT: s_lshr_b32 s16, s7, 24
-; SI-NEXT: s_add_i32 s5, s5, 0x30000
-; SI-NEXT: v_writelane_b32 v22, s16, 55
-; SI-NEXT: s_lshr_b32 s16, s7, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 56
-; SI-NEXT: s_lshr_b32 s16, s5, 24
-; SI-NEXT: v_writelane_b32 v22, s16, 57
-; SI-NEXT: s_lshr_b32 s16, s5, 8
-; SI-NEXT: v_writelane_b32 v22, s16, 58
-; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[64:65], 24
; SI-NEXT: v_writelane_b32 v21, s16, 19
; SI-NEXT: v_writelane_b32 v21, s17, 20
-; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[64:65], 16
; SI-NEXT: v_writelane_b32 v21, s16, 17
; SI-NEXT: v_writelane_b32 v21, s17, 18
-; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 8
+; SI-NEXT: s_lshr_b64 s[16:17], s[64:65], 8
; SI-NEXT: v_writelane_b32 v21, s16, 15
; SI-NEXT: v_writelane_b32 v21, s17, 16
-; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[88:89], 24
; SI-NEXT: v_writelane_b32 v21, s16, 25
; SI-NEXT: v_writelane_b32 v21, s17, 26
-; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[88:89], 16
; SI-NEXT: v_writelane_b32 v21, s16, 23
; SI-NEXT: v_writelane_b32 v21, s17, 24
-; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 8
+; SI-NEXT: s_lshr_b64 s[16:17], s[88:89], 8
; SI-NEXT: v_writelane_b32 v21, s16, 21
; SI-NEXT: v_writelane_b32 v21, s17, 22
-; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 24
; SI-NEXT: v_writelane_b32 v21, s16, 31
; SI-NEXT: v_writelane_b32 v21, s17, 32
-; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
; SI-NEXT: v_writelane_b32 v21, s16, 29
; SI-NEXT: v_writelane_b32 v21, s17, 30
-; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 8
+; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 8
; SI-NEXT: v_writelane_b32 v21, s16, 27
; SI-NEXT: v_writelane_b32 v21, s17, 28
-; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[76:77], 24
; SI-NEXT: v_writelane_b32 v21, s16, 37
; SI-NEXT: v_writelane_b32 v21, s17, 38
-; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[76:77], 16
; SI-NEXT: v_writelane_b32 v21, s16, 35
; SI-NEXT: v_writelane_b32 v21, s17, 36
-; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 8
+; SI-NEXT: s_lshr_b64 s[16:17], s[76:77], 8
; SI-NEXT: v_writelane_b32 v21, s16, 33
; SI-NEXT: v_writelane_b32 v21, s17, 34
-; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 24
; SI-NEXT: v_writelane_b32 v21, s16, 43
; SI-NEXT: v_writelane_b32 v21, s17, 44
-; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
; SI-NEXT: v_writelane_b32 v21, s16, 41
; SI-NEXT: v_writelane_b32 v21, s17, 42
-; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 8
-; SI-NEXT: s_add_i32 s42, s42, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 8
+; SI-NEXT: s_add_i32 s44, s44, 0x30000
+; SI-NEXT: s_add_i32 s45, s45, 0x30000
; SI-NEXT: v_writelane_b32 v21, s16, 39
; SI-NEXT: v_writelane_b32 v21, s17, 40
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 24
; SI-NEXT: v_writelane_b32 v21, s16, 49
; SI-NEXT: v_writelane_b32 v21, s17, 50
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
; SI-NEXT: v_writelane_b32 v21, s16, 47
; SI-NEXT: v_writelane_b32 v21, s17, 48
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 8
-; SI-NEXT: s_add_i32 s40, s40, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 8
+; SI-NEXT: s_add_i32 s42, s42, 0x30000
+; SI-NEXT: s_add_i32 s43, s43, 0x30000
; SI-NEXT: v_writelane_b32 v21, s16, 45
; SI-NEXT: v_writelane_b32 v21, s17, 46
-; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 24
; SI-NEXT: v_writelane_b32 v21, s16, 55
; SI-NEXT: v_writelane_b32 v21, s17, 56
-; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
; SI-NEXT: v_writelane_b32 v21, s16, 53
; SI-NEXT: v_writelane_b32 v21, s17, 54
-; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 8
-; SI-NEXT: s_add_i32 s14, s14, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 8
+; SI-NEXT: s_add_i32 s40, s40, 0x30000
+; SI-NEXT: s_add_i32 s41, s41, 0x30000
; SI-NEXT: v_writelane_b32 v21, s16, 51
; SI-NEXT: v_writelane_b32 v21, s17, 52
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 24
; SI-NEXT: v_writelane_b32 v21, s16, 61
; SI-NEXT: v_writelane_b32 v21, s17, 62
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 16
; SI-NEXT: v_writelane_b32 v21, s16, 59
; SI-NEXT: v_writelane_b32 v21, s17, 60
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 8
-; SI-NEXT: s_add_i32 s12, s12, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 8
+; SI-NEXT: s_add_i32 s14, s14, 0x30000
+; SI-NEXT: s_add_i32 s15, s15, 0x30000
; SI-NEXT: v_writelane_b32 v21, s16, 57
; SI-NEXT: v_writelane_b32 v21, s17, 58
-; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 24
; SI-NEXT: v_writelane_b32 v22, s16, 3
; SI-NEXT: v_writelane_b32 v22, s17, 4
-; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
; SI-NEXT: v_writelane_b32 v22, s16, 1
; SI-NEXT: v_writelane_b32 v22, s17, 2
-; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 8
-; SI-NEXT: s_add_i32 s10, s10, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 8
+; SI-NEXT: s_add_i32 s12, s12, 0x30000
+; SI-NEXT: s_add_i32 s13, s13, 0x30000
; SI-NEXT: v_writelane_b32 v21, s16, 63
; SI-NEXT: v_writelane_b32 v22, s17, 0
-; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 24
; SI-NEXT: v_writelane_b32 v22, s16, 9
; SI-NEXT: v_writelane_b32 v22, s17, 10
-; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 16
; SI-NEXT: v_writelane_b32 v22, s16, 7
; SI-NEXT: v_writelane_b32 v22, s17, 8
-; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 8
-; SI-NEXT: s_add_i32 s8, s8, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 8
+; SI-NEXT: s_add_i32 s10, s10, 0x30000
+; SI-NEXT: s_add_i32 s11, s11, 0x30000
; SI-NEXT: v_writelane_b32 v22, s16, 5
; SI-NEXT: v_writelane_b32 v22, s17, 6
-; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 24
; SI-NEXT: v_writelane_b32 v22, s16, 15
; SI-NEXT: v_writelane_b32 v22, s17, 16
-; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 16
; SI-NEXT: v_writelane_b32 v22, s16, 13
; SI-NEXT: v_writelane_b32 v22, s17, 14
-; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 8
-; SI-NEXT: s_add_i32 s6, s6, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 8
+; SI-NEXT: s_add_i32 s8, s8, 0x30000
+; SI-NEXT: s_add_i32 s9, s9, 0x30000
; SI-NEXT: v_writelane_b32 v22, s16, 11
; SI-NEXT: v_writelane_b32 v22, s17, 12
-; SI-NEXT: s_lshr_b64 s[16:17], s[6:7], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 24
; SI-NEXT: v_writelane_b32 v22, s16, 21
; SI-NEXT: v_writelane_b32 v22, s17, 22
-; SI-NEXT: s_lshr_b64 s[16:17], s[6:7], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16
; SI-NEXT: v_writelane_b32 v22, s16, 19
; SI-NEXT: v_writelane_b32 v22, s17, 20
-; SI-NEXT: s_lshr_b64 s[16:17], s[6:7], 8
-; SI-NEXT: s_add_i32 s4, s4, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 8
+; SI-NEXT: s_add_i32 s6, s6, 0x30000
+; SI-NEXT: s_add_i32 s7, s7, 0x30000
; SI-NEXT: v_writelane_b32 v22, s16, 17
; SI-NEXT: v_writelane_b32 v22, s17, 18
-; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[6:7], 24
+; SI-NEXT: v_writelane_b32 v22, s16, 27
+; SI-NEXT: v_writelane_b32 v22, s17, 28
+; SI-NEXT: s_lshr_b64 s[16:17], s[6:7], 16
; SI-NEXT: v_writelane_b32 v22, s16, 25
; SI-NEXT: v_writelane_b32 v22, s17, 26
-; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 8
-; SI-NEXT: s_lshr_b32 s35, s73, 16
-; SI-NEXT: s_lshr_b32 s34, s63, 16
-; SI-NEXT: s_lshr_b32 s31, s59, 16
-; SI-NEXT: s_lshr_b32 s30, s47, 16
-; SI-NEXT: s_lshr_b32 s95, s45, 16
-; SI-NEXT: s_lshr_b32 s94, s75, 16
-; SI-NEXT: s_lshr_b32 s92, s61, 16
-; SI-NEXT: s_lshr_b32 s93, s57, 16
-; SI-NEXT: s_lshr_b32 s91, s43, 16
-; SI-NEXT: s_lshr_b32 s90, s41, 16
-; SI-NEXT: s_lshr_b32 s89, s15, 16
-; SI-NEXT: s_lshr_b32 s88, s13, 16
-; SI-NEXT: s_lshr_b32 s79, s11, 16
-; SI-NEXT: s_lshr_b32 s78, s9, 16
-; SI-NEXT: s_lshr_b32 s77, s7, 16
-; SI-NEXT: s_lshr_b32 s76, s5, 16
-; SI-NEXT: s_lshr_b64 s[86:87], s[44:45], 24
-; SI-NEXT: s_lshr_b64 s[96:97], s[44:45], 16
-; SI-NEXT: s_lshr_b64 s[98:99], s[44:45], 8
-; SI-NEXT: s_lshr_b64 s[80:81], s[74:75], 24
-; SI-NEXT: s_lshr_b64 s[82:83], s[74:75], 16
-; SI-NEXT: s_lshr_b64 s[84:85], s[74:75], 8
-; SI-NEXT: s_lshr_b64 s[70:71], s[4:5], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[6:7], 8
+; SI-NEXT: s_add_i32 s4, s4, 0x30000
+; SI-NEXT: s_add_i32 s5, s5, 0x30000
; SI-NEXT: v_writelane_b32 v22, s16, 23
; SI-NEXT: v_writelane_b32 v22, s17, 24
+; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 24
+; SI-NEXT: v_writelane_b32 v22, s16, 33
+; SI-NEXT: v_writelane_b32 v22, s17, 34
+; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16
+; SI-NEXT: v_writelane_b32 v22, s16, 31
+; SI-NEXT: v_writelane_b32 v22, s17, 32
+; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 8
+; SI-NEXT: v_writelane_b32 v22, s16, 29
+; SI-NEXT: v_writelane_b32 v22, s17, 30
+; SI-NEXT: s_lshr_b32 s16, s99, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 35
+; SI-NEXT: s_lshr_b32 s16, s99, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 36
+; SI-NEXT: s_lshr_b32 s16, s83, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 37
+; SI-NEXT: s_lshr_b32 s16, s83, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 38
+; SI-NEXT: s_lshr_b32 s16, s65, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 39
+; SI-NEXT: s_lshr_b32 s16, s65, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 40
+; SI-NEXT: s_lshr_b32 s16, s89, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 41
+; SI-NEXT: s_lshr_b32 s16, s89, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 42
+; SI-NEXT: s_lshr_b32 s16, s57, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 43
+; SI-NEXT: s_lshr_b32 s16, s57, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 44
+; SI-NEXT: s_lshr_b32 s16, s77, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 45
+; SI-NEXT: s_lshr_b32 s16, s77, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 46
+; SI-NEXT: s_lshr_b32 s16, s47, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 47
+; SI-NEXT: s_lshr_b32 s16, s47, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 48
+; SI-NEXT: s_lshr_b32 s16, s45, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 49
+; SI-NEXT: s_lshr_b32 s16, s45, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 50
+; SI-NEXT: s_lshr_b32 s16, s43, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 51
+; SI-NEXT: s_lshr_b32 s16, s43, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 52
+; SI-NEXT: s_lshr_b32 s16, s41, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 53
+; SI-NEXT: s_lshr_b32 s16, s41, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 54
+; SI-NEXT: s_lshr_b32 s16, s15, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 55
+; SI-NEXT: s_lshr_b32 s16, s15, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 56
+; SI-NEXT: s_lshr_b32 s16, s13, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 57
+; SI-NEXT: s_lshr_b32 s16, s13, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 58
+; SI-NEXT: s_lshr_b32 s16, s11, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 59
+; SI-NEXT: s_lshr_b32 s16, s11, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 60
+; SI-NEXT: s_lshr_b32 s16, s9, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 61
+; SI-NEXT: s_lshr_b32 s16, s9, 8
+; SI-NEXT: v_writelane_b32 v22, s16, 62
+; SI-NEXT: s_lshr_b32 s16, s7, 24
+; SI-NEXT: v_writelane_b32 v22, s16, 63
+; SI-NEXT: s_lshr_b32 s16, s7, 8
+; SI-NEXT: s_lshr_b32 s93, s99, 16
+; SI-NEXT: s_lshr_b32 s92, s83, 16
+; SI-NEXT: s_lshr_b32 s91, s65, 16
+; SI-NEXT: s_lshr_b32 s90, s89, 16
+; SI-NEXT: s_lshr_b32 s79, s57, 16
+; SI-NEXT: s_lshr_b32 s78, s77, 16
+; SI-NEXT: s_lshr_b32 s75, s47, 16
+; SI-NEXT: s_lshr_b32 s74, s45, 16
+; SI-NEXT: s_lshr_b32 s73, s43, 16
+; SI-NEXT: s_lshr_b32 s72, s41, 16
+; SI-NEXT: s_lshr_b32 s63, s15, 16
+; SI-NEXT: s_lshr_b32 s62, s13, 16
+; SI-NEXT: s_lshr_b32 s61, s11, 16
+; SI-NEXT: s_lshr_b32 s60, s9, 16
+; SI-NEXT: s_lshr_b32 s59, s7, 16
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v23, s16, 0
+; SI-NEXT: s_lshr_b32 s16, s5, 24
+; SI-NEXT: s_lshr_b32 s58, s5, 16
+; SI-NEXT: s_lshr_b32 s52, s5, 8
+; SI-NEXT: v_writelane_b32 v23, s16, 1
; SI-NEXT: .LBB99_3: ; %end
-; SI-NEXT: v_readlane_b32 s16, v21, 9
-; SI-NEXT: v_readlane_b32 s17, v21, 10
-; SI-NEXT: v_readlane_b32 s18, v21, 11
-; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: s_and_b32 s17, s72, 0xff
-; SI-NEXT: v_readlane_b32 s19, v21, 12
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: v_readlane_b32 s18, v21, 3
+; SI-NEXT: v_readlane_b32 s19, v21, 4
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 5
+; SI-NEXT: s_and_b32 s16, s98, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 6
+; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s18, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 13
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: v_readlane_b32 s18, v21, 7
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 28
+; SI-NEXT: v_readlane_b32 s17, v22, 36
; SI-NEXT: v_mov_b32_e32 v1, s16
-; SI-NEXT: s_and_b32 s16, s73, 0xff
+; SI-NEXT: s_and_b32 s16, s99, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s35, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 27
+; SI-NEXT: s_and_b32 s17, s93, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 35
+; SI-NEXT: v_readlane_b32 s19, v21, 8
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 9
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 10
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s19, v21, 14
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 11
; SI-NEXT: v_mov_b32_e32 v2, s16
-; SI-NEXT: v_readlane_b32 s16, v21, 15
-; SI-NEXT: v_readlane_b32 s17, v21, 16
-; SI-NEXT: v_readlane_b32 s18, v21, 17
-; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: s_and_b32 s17, s62, 0xff
-; SI-NEXT: v_readlane_b32 s19, v21, 18
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_and_b32 s16, s82, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 12
+; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s18, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 19
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: v_readlane_b32 s18, v21, 13
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 30
-; SI-NEXT: v_mov_b32_e32 v3, s16
-; SI-NEXT: s_and_b32 s16, s63, 0xff
+; SI-NEXT: v_readlane_b32 s17, v22, 38
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s83, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s34, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 29
+; SI-NEXT: s_and_b32 s17, s92, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 37
+; SI-NEXT: v_readlane_b32 s19, v21, 14
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 15
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 16
+; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 17
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s64, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 18
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s19, v21, 20
-; SI-NEXT: v_mov_b32_e32 v4, s16
-; SI-NEXT: v_readlane_b32 s16, v21, 21
-; SI-NEXT: v_readlane_b32 s17, v21, 22
-; SI-NEXT: v_readlane_b32 s18, v21, 23
-; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: s_and_b32 s17, s58, 0xff
-; SI-NEXT: v_readlane_b32 s19, v21, 24
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s18, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 25
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: v_readlane_b32 s18, v21, 19
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 32
-; SI-NEXT: v_mov_b32_e32 v5, s16
-; SI-NEXT: s_and_b32 s16, s59, 0xff
+; SI-NEXT: v_readlane_b32 s17, v22, 40
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s65, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s31, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 31
+; SI-NEXT: s_and_b32 s17, s91, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 39
+; SI-NEXT: v_readlane_b32 s19, v21, 20
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 21
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 22
+; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 23
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s88, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 24
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s19, v21, 26
-; SI-NEXT: v_mov_b32_e32 v6, s16
-; SI-NEXT: v_readlane_b32 s16, v21, 27
-; SI-NEXT: v_readlane_b32 s17, v21, 28
-; SI-NEXT: v_readlane_b32 s18, v21, 29
-; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: s_and_b32 s17, s46, 0xff
-; SI-NEXT: v_readlane_b32 s19, v21, 30
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s18, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 31
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: v_readlane_b32 s18, v21, 25
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 34
-; SI-NEXT: v_mov_b32_e32 v7, s16
-; SI-NEXT: s_and_b32 s16, s47, 0xff
+; SI-NEXT: v_readlane_b32 s17, v22, 42
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s89, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s30, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 33
+; SI-NEXT: s_and_b32 s17, s90, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 41
+; SI-NEXT: v_readlane_b32 s19, v21, 26
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 27
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 28
+; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v8, s16
-; SI-NEXT: s_lshl_b32 s16, s98, 8
-; SI-NEXT: s_and_b32 s17, s44, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s17, s96, 0xff
-; SI-NEXT: s_lshl_b32 s18, s86, 24
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 36
-; SI-NEXT: v_mov_b32_e32 v9, s16
-; SI-NEXT: s_and_b32 s16, s45, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 29
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s56, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 30
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s95, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 35
+; SI-NEXT: s_and_b32 s17, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v21, 31
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_mov_b32_e32 v10, s16
-; SI-NEXT: s_lshl_b32 s16, s84, 8
-; SI-NEXT: s_and_b32 s17, s74, 0xff
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s17, s82, 0xff
-; SI-NEXT: s_lshl_b32 s18, s80, 24
-; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 38
-; SI-NEXT: v_mov_b32_e32 v11, s16
-; SI-NEXT: s_and_b32 s16, s75, 0xff
+; SI-NEXT: v_readlane_b32 s17, v22, 44
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s57, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s94, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 37
+; SI-NEXT: s_and_b32 s17, s79, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 43
+; SI-NEXT: v_readlane_b32 s19, v21, 32
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 33
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 34
+; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s19, v21, 32
-; SI-NEXT: v_mov_b32_e32 v12, s16
-; SI-NEXT: v_readlane_b32 s16, v21, 33
-; SI-NEXT: v_readlane_b32 s17, v21, 34
+; SI-NEXT: s_lshl_b32 s17, s18, 8
; SI-NEXT: v_readlane_b32 s18, v21, 35
-; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: s_and_b32 s17, s60, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s76, 0xff
; SI-NEXT: v_readlane_b32 s19, v21, 36
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s18, 0xff
; SI-NEXT: v_readlane_b32 s18, v21, 37
-; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 40
-; SI-NEXT: v_mov_b32_e32 v13, s16
-; SI-NEXT: s_and_b32 s16, s61, 0xff
+; SI-NEXT: v_readlane_b32 s17, v22, 46
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s77, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s92, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 39
+; SI-NEXT: s_and_b32 s17, s78, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 45
+; SI-NEXT: v_readlane_b32 s19, v21, 38
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 39
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 40
+; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s19, v21, 38
-; SI-NEXT: v_mov_b32_e32 v14, s16
-; SI-NEXT: v_readlane_b32 s16, v21, 39
-; SI-NEXT: v_readlane_b32 s17, v21, 40
+; SI-NEXT: s_lshl_b32 s17, s18, 8
; SI-NEXT: v_readlane_b32 s18, v21, 41
-; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: s_and_b32 s17, s56, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s46, 0xff
; SI-NEXT: v_readlane_b32 s19, v21, 42
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s18, 0xff
; SI-NEXT: v_readlane_b32 s18, v21, 43
-; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 42
-; SI-NEXT: v_mov_b32_e32 v15, s16
-; SI-NEXT: s_and_b32 s16, s57, 0xff
+; SI-NEXT: v_readlane_b32 s17, v22, 48
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s47, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s93, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 41
+; SI-NEXT: s_and_b32 s17, s75, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 47
+; SI-NEXT: v_readlane_b32 s19, v21, 44
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 45
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
+; SI-NEXT: v_readlane_b32 s19, v21, 46
+; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
-; SI-NEXT: v_readlane_b32 s19, v21, 44
-; SI-NEXT: v_mov_b32_e32 v16, s16
-; SI-NEXT: v_readlane_b32 s16, v21, 45
-; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
-; SI-NEXT: v_readlane_b32 s17, v21, 46
+; SI-NEXT: s_lshl_b32 s17, s18, 8
; SI-NEXT: v_readlane_b32 s18, v21, 47
-; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
-; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: s_and_b32 s17, s42, 0xff
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s44, 0xff
; SI-NEXT: v_readlane_b32 s19, v21, 48
-; SI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s18, 0xff
; SI-NEXT: v_readlane_b32 s18, v21, 49
-; SI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
-; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
+; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
-; SI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 44
-; SI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
+; SI-NEXT: v_readlane_b32 s17, v22, 50
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
-; SI-NEXT: s_and_b32 s16, s43, 0xff
+; SI-NEXT: s_and_b32 s16, s45, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s91, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 43
+; SI-NEXT: s_and_b32 s17, s74, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 49
; SI-NEXT: v_readlane_b32 s19, v21, 50
-; SI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
-; SI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: v_readlane_b32 s18, v21, 51
-; SI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: v_readlane_b32 s19, v21, 52
-; SI-NEXT: buffer_store_dword v16, v1, s[0:3], 0 offen
-; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_lshl_b32 s17, s18, 8
; SI-NEXT: v_readlane_b32 s18, v21, 53
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
-; SI-NEXT: s_and_b32 s16, s40, 0xff
+; SI-NEXT: s_and_b32 s16, s42, 0xff
; SI-NEXT: v_readlane_b32 s19, v21, 54
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s18, 0xff
@@ -203182,17 +203303,51 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: v_readlane_b32 s17, v22, 52
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s43, 0xff
+; SI-NEXT: s_lshl_b32 s17, s17, 8
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s17, s73, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 51
+; SI-NEXT: v_readlane_b32 s19, v21, 56
+; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: s_or_b32 s17, s18, s17
+; SI-NEXT: v_readlane_b32 s18, v21, 57
+; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: v_readlane_b32 s19, v21, 58
+; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_lshl_b32 s17, s18, 8
+; SI-NEXT: v_readlane_b32 s18, v21, 59
+; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: s_and_b32 s16, s40, 0xff
+; SI-NEXT: v_readlane_b32 s19, v21, 60
+; SI-NEXT: s_or_b32 s16, s16, s17
+; SI-NEXT: s_and_b32 s17, s18, 0xff
+; SI-NEXT: v_readlane_b32 s18, v21, 61
+; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: s_and_b32 s16, s16, 0xffff
+; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: v_readlane_b32 s17, v22, 46
+; SI-NEXT: v_readlane_b32 s17, v22, 54
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
; SI-NEXT: s_and_b32 s16, s41, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s90, 0xff
-; SI-NEXT: v_readlane_b32 s18, v22, 45
+; SI-NEXT: s_and_b32 s17, s72, 0xff
+; SI-NEXT: v_readlane_b32 s18, v22, 53
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_lshl_b32 s18, s18, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
@@ -203202,16 +203357,16 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s16
-; SI-NEXT: v_readlane_b32 s16, v21, 57
+; SI-NEXT: v_readlane_b32 s16, v21, 63
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_readlane_b32 s17, v21, 58
+; SI-NEXT: v_readlane_b32 s17, v22, 0
; SI-NEXT: s_lshl_b32 s16, s16, 8
-; SI-NEXT: v_readlane_b32 s19, v21, 56
+; SI-NEXT: v_readlane_b32 s19, v21, 62
; SI-NEXT: s_or_b32 s14, s14, s16
-; SI-NEXT: v_readlane_b32 s16, v21, 59
-; SI-NEXT: v_readlane_b32 s17, v21, 60
+; SI-NEXT: v_readlane_b32 s16, v22, 1
+; SI-NEXT: v_readlane_b32 s17, v22, 2
; SI-NEXT: s_and_b32 s16, s16, 0xff
-; SI-NEXT: v_readlane_b32 s18, v21, 61
+; SI-NEXT: v_readlane_b32 s18, v22, 3
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s17, s18, 24
; SI-NEXT: s_and_b32 s14, s14, 0xffff
@@ -203222,11 +203377,11 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s14
; SI-NEXT: s_and_b32 s14, s15, 0xff
-; SI-NEXT: v_readlane_b32 s15, v22, 48
+; SI-NEXT: v_readlane_b32 s15, v22, 56
; SI-NEXT: s_lshl_b32 s15, s15, 8
; SI-NEXT: s_or_b32 s14, s14, s15
-; SI-NEXT: s_and_b32 s15, s89, 0xff
-; SI-NEXT: v_readlane_b32 s16, v22, 47
+; SI-NEXT: s_and_b32 s15, s63, 0xff
+; SI-NEXT: v_readlane_b32 s16, v22, 55
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_lshl_b32 s16, s16, 24
; SI-NEXT: s_and_b32 s14, s14, 0xffff
@@ -203236,15 +203391,15 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s14
-; SI-NEXT: v_readlane_b32 s14, v21, 63
+; SI-NEXT: v_readlane_b32 s14, v22, 5
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s15, v22, 0
+; SI-NEXT: v_readlane_b32 s15, v22, 6
; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_or_b32 s12, s12, s14
-; SI-NEXT: v_readlane_b32 s14, v22, 1
-; SI-NEXT: v_readlane_b32 s15, v22, 2
+; SI-NEXT: v_readlane_b32 s14, v22, 7
+; SI-NEXT: v_readlane_b32 s15, v22, 8
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_readlane_b32 s16, v22, 3
+; SI-NEXT: v_readlane_b32 s16, v22, 9
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_lshl_b32 s15, s16, 24
; SI-NEXT: s_and_b32 s12, s12, 0xffff
@@ -203255,11 +203410,11 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s12
; SI-NEXT: s_and_b32 s12, s13, 0xff
-; SI-NEXT: v_readlane_b32 s13, v22, 50
+; SI-NEXT: v_readlane_b32 s13, v22, 58
; SI-NEXT: s_lshl_b32 s13, s13, 8
; SI-NEXT: s_or_b32 s12, s12, s13
-; SI-NEXT: s_and_b32 s13, s88, 0xff
-; SI-NEXT: v_readlane_b32 s14, v22, 49
+; SI-NEXT: s_and_b32 s13, s62, 0xff
+; SI-NEXT: v_readlane_b32 s14, v22, 57
; SI-NEXT: s_lshl_b32 s13, s13, 16
; SI-NEXT: s_lshl_b32 s14, s14, 24
; SI-NEXT: s_and_b32 s12, s12, 0xffff
@@ -203269,15 +203424,15 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s12
-; SI-NEXT: v_readlane_b32 s12, v22, 5
+; SI-NEXT: v_readlane_b32 s12, v22, 11
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s13, v22, 6
+; SI-NEXT: v_readlane_b32 s13, v22, 12
; SI-NEXT: s_lshl_b32 s12, s12, 8
; SI-NEXT: s_or_b32 s10, s10, s12
-; SI-NEXT: v_readlane_b32 s12, v22, 7
-; SI-NEXT: v_readlane_b32 s13, v22, 8
+; SI-NEXT: v_readlane_b32 s12, v22, 13
+; SI-NEXT: v_readlane_b32 s13, v22, 14
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s14, v22, 9
+; SI-NEXT: v_readlane_b32 s14, v22, 15
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_lshl_b32 s13, s14, 24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
@@ -203288,11 +203443,11 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: s_and_b32 s10, s11, 0xff
-; SI-NEXT: v_readlane_b32 s11, v22, 52
+; SI-NEXT: v_readlane_b32 s11, v22, 60
; SI-NEXT: s_lshl_b32 s11, s11, 8
; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: s_and_b32 s11, s79, 0xff
-; SI-NEXT: v_readlane_b32 s12, v22, 51
+; SI-NEXT: s_and_b32 s11, s61, 0xff
+; SI-NEXT: v_readlane_b32 s12, v22, 59
; SI-NEXT: s_lshl_b32 s11, s11, 16
; SI-NEXT: s_lshl_b32 s12, s12, 24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
@@ -203302,15 +203457,15 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s10
-; SI-NEXT: v_readlane_b32 s10, v22, 11
+; SI-NEXT: v_readlane_b32 s10, v22, 17
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s11, v22, 12
+; SI-NEXT: v_readlane_b32 s11, v22, 18
; SI-NEXT: s_lshl_b32 s10, s10, 8
; SI-NEXT: s_or_b32 s8, s8, s10
-; SI-NEXT: v_readlane_b32 s10, v22, 13
-; SI-NEXT: v_readlane_b32 s11, v22, 14
+; SI-NEXT: v_readlane_b32 s10, v22, 19
+; SI-NEXT: v_readlane_b32 s11, v22, 20
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s12, v22, 15
+; SI-NEXT: v_readlane_b32 s12, v22, 21
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_lshl_b32 s11, s12, 24
; SI-NEXT: s_and_b32 s8, s8, 0xffff
@@ -203321,11 +203476,11 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s8
; SI-NEXT: s_and_b32 s8, s9, 0xff
-; SI-NEXT: v_readlane_b32 s9, v22, 54
+; SI-NEXT: v_readlane_b32 s9, v22, 62
; SI-NEXT: s_lshl_b32 s9, s9, 8
; SI-NEXT: s_or_b32 s8, s8, s9
-; SI-NEXT: s_and_b32 s9, s78, 0xff
-; SI-NEXT: v_readlane_b32 s10, v22, 53
+; SI-NEXT: s_and_b32 s9, s60, 0xff
+; SI-NEXT: v_readlane_b32 s10, v22, 61
; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_lshl_b32 s10, s10, 24
; SI-NEXT: s_and_b32 s8, s8, 0xffff
@@ -203335,15 +203490,15 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s8
-; SI-NEXT: v_readlane_b32 s8, v22, 17
+; SI-NEXT: v_readlane_b32 s8, v22, 23
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s9, v22, 18
+; SI-NEXT: v_readlane_b32 s9, v22, 24
; SI-NEXT: s_lshl_b32 s8, s8, 8
; SI-NEXT: s_or_b32 s6, s6, s8
-; SI-NEXT: v_readlane_b32 s8, v22, 19
-; SI-NEXT: v_readlane_b32 s9, v22, 20
+; SI-NEXT: v_readlane_b32 s8, v22, 25
+; SI-NEXT: v_readlane_b32 s9, v22, 26
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s10, v22, 21
+; SI-NEXT: v_readlane_b32 s10, v22, 27
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_lshl_b32 s9, s10, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
@@ -203354,11 +203509,11 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_and_b32 s6, s7, 0xff
-; SI-NEXT: v_readlane_b32 s7, v22, 56
+; SI-NEXT: v_readlane_b32 s7, v23, 0
; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: s_and_b32 s7, s77, 0xff
-; SI-NEXT: v_readlane_b32 s8, v22, 55
+; SI-NEXT: s_and_b32 s7, s59, 0xff
+; SI-NEXT: v_readlane_b32 s8, v22, 63
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_lshl_b32 s8, s8, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
@@ -203368,13 +203523,15 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
-; SI-NEXT: v_readlane_b32 s6, v22, 23
+; SI-NEXT: v_readlane_b32 s6, v22, 29
; SI-NEXT: s_and_b32 s4, s4, 0xff
+; SI-NEXT: v_readlane_b32 s7, v22, 30
; SI-NEXT: s_lshl_b32 s6, s6, 8
-; SI-NEXT: v_readlane_b32 s7, v22, 24
; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: s_and_b32 s6, s70, 0xff
-; SI-NEXT: v_readlane_b32 s8, v22, 25
+; SI-NEXT: v_readlane_b32 s6, v22, 31
+; SI-NEXT: v_readlane_b32 s7, v22, 32
+; SI-NEXT: s_and_b32 s6, s6, 0xff
+; SI-NEXT: v_readlane_b32 s8, v22, 33
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s7, s8, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
@@ -203385,11 +203542,10 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: s_and_b32 s4, s5, 0xff
-; SI-NEXT: v_readlane_b32 s5, v22, 58
-; SI-NEXT: s_lshl_b32 s5, s5, 8
+; SI-NEXT: s_lshl_b32 s5, s52, 8
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: s_and_b32 s5, s76, 0xff
-; SI-NEXT: v_readlane_b32 s6, v22, 57
+; SI-NEXT: s_and_b32 s5, s58, 0xff
+; SI-NEXT: v_readlane_b32 s6, v23, 1
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s6, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
@@ -203400,12 +203556,12 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: v_readlane_b32 s30, v20, 34
-; SI-NEXT: v_readlane_b32 s19, v21, 62
-; SI-NEXT: v_readlane_b32 s17, v22, 4
-; SI-NEXT: v_readlane_b32 s15, v22, 10
-; SI-NEXT: v_readlane_b32 s13, v22, 16
-; SI-NEXT: v_readlane_b32 s11, v22, 22
-; SI-NEXT: v_readlane_b32 s9, v22, 26
+; SI-NEXT: v_readlane_b32 s19, v22, 4
+; SI-NEXT: v_readlane_b32 s17, v22, 10
+; SI-NEXT: v_readlane_b32 s15, v22, 16
+; SI-NEXT: v_readlane_b32 s13, v22, 22
+; SI-NEXT: v_readlane_b32 s11, v22, 28
+; SI-NEXT: v_readlane_b32 s9, v22, 34
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: v_readlane_b32 s31, v20, 35
; SI-NEXT: v_readlane_b32 s99, v20, 33
@@ -203446,29 +203602,24 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB99_4:
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; implicit-def: $sgpr70
-; SI-NEXT: v_writelane_b32 v21, s4, 9
-; SI-NEXT: v_writelane_b32 v21, s5, 10
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: v_writelane_b32 v21, s4, 3
+; SI-NEXT: v_writelane_b32 v21, s5, 4
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr98
-; SI-NEXT: ; implicit-def: $sgpr96
-; SI-NEXT: ; implicit-def: $sgpr86
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr84
; SI-NEXT: ; implicit-def: $sgpr82
-; SI-NEXT: ; implicit-def: $sgpr80
-; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr76
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr14
@@ -203476,6 +203627,19 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: ; implicit-def: $sgpr10
; SI-NEXT: ; implicit-def: $sgpr8
; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v21, s4, 5
+; SI-NEXT: v_writelane_b32 v21, s5, 6
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v21, s4, 7
+; SI-NEXT: v_writelane_b32 v21, s5, 8
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; kill: killed $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; kill: killed $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v21, s4, 9
+; SI-NEXT: v_writelane_b32 v21, s5, 10
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: v_writelane_b32 v21, s4, 11
; SI-NEXT: v_writelane_b32 v21, s5, 12
; SI-NEXT: ; implicit-def: $sgpr4
@@ -203512,15 +203676,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v21, s4, 27
-; SI-NEXT: v_writelane_b32 v21, s5, 28
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v21, s4, 29
-; SI-NEXT: v_writelane_b32 v21, s5, 30
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v21, s4, 31
-; SI-NEXT: v_writelane_b32 v21, s5, 32
-; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
@@ -203567,11 +203722,14 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; kill: killed $sgpr4
+; SI-NEXT: v_writelane_b32 v21, s4, 27
+; SI-NEXT: v_writelane_b32 v21, s5, 28
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; kill: killed $sgpr4
+; SI-NEXT: v_writelane_b32 v21, s4, 29
+; SI-NEXT: v_writelane_b32 v21, s5, 30
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; kill: killed $sgpr4
+; SI-NEXT: v_writelane_b32 v21, s4, 31
+; SI-NEXT: v_writelane_b32 v21, s5, 32
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: v_writelane_b32 v21, s4, 33
; SI-NEXT: v_writelane_b32 v21, s5, 34
@@ -203619,7 +203777,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: v_writelane_b32 v21, s5, 62
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: v_writelane_b32 v21, s4, 63
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v22, s5, 0
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: v_writelane_b32 v22, s4, 1
@@ -203654,13 +203812,25 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: v_writelane_b32 v22, s4, 21
; SI-NEXT: v_writelane_b32 v22, s5, 22
-; SI-NEXT: v_writelane_b32 v22, s70, 23
-; SI-NEXT: v_writelane_b32 v22, s71, 24
-; SI-NEXT: ; implicit-def: $sgpr70
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v22, s70, 25
-; SI-NEXT: v_writelane_b32 v22, s71, 26
-; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: v_writelane_b32 v22, s4, 23
+; SI-NEXT: v_writelane_b32 v22, s5, 24
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v22, s4, 25
+; SI-NEXT: v_writelane_b32 v22, s5, 26
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v22, s4, 27
+; SI-NEXT: v_writelane_b32 v22, s5, 28
+; SI-NEXT: v_writelane_b32 v22, s52, 29
+; SI-NEXT: v_writelane_b32 v22, s53, 30
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v22, s52, 31
+; SI-NEXT: v_writelane_b32 v22, s53, 32
+; SI-NEXT: ; implicit-def: $sgpr52
+; SI-NEXT: v_writelane_b32 v22, s52, 33
+; SI-NEXT: v_writelane_b32 v22, s53, 34
+; SI-NEXT: ; implicit-def: $sgpr52
; SI-NEXT: s_branch .LBB99_2
;
; VI-LABEL: bitcast_v64i16_to_v128i8_scalar:
@@ -204258,88 +204428,88 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_perm_b32 v16, s16, v16, v1
; VI-NEXT: v_readlane_b32 s16, v33, 21
; VI-NEXT: v_or_b32_e32 v2, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: v_mov_b32_e32 v26, s16
; VI-NEXT: v_readlane_b32 s16, v33, 22
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
; VI-NEXT: v_perm_b32 v26, s16, v26, v1
; VI-NEXT: v_or_b32_e32 v2, v7, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: v_mov_b32_e32 v19, s34
; VI-NEXT: v_readlane_b32 s16, v33, 20
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
; VI-NEXT: v_perm_b32 v19, s16, v19, v1
; VI-NEXT: v_readlane_b32 s16, v33, 18
; VI-NEXT: v_or_b32_e32 v2, v6, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: v_mov_b32_e32 v27, s16
; VI-NEXT: v_readlane_b32 s16, v33, 19
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
; VI-NEXT: v_perm_b32 v27, s16, v27, v1
; VI-NEXT: v_or_b32_e32 v2, v9, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: v_mov_b32_e32 v20, s30
; VI-NEXT: v_readlane_b32 s16, v33, 17
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
; VI-NEXT: v_perm_b32 v20, s16, v20, v1
; VI-NEXT: v_readlane_b32 s16, v33, 15
; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: v_mov_b32_e32 v28, s16
; VI-NEXT: v_readlane_b32 s16, v33, 16
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
; VI-NEXT: v_perm_b32 v28, s16, v28, v1
; VI-NEXT: v_or_b32_e32 v2, v12, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: v_mov_b32_e32 v21, s90
; VI-NEXT: v_readlane_b32 s16, v33, 13
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 10
; VI-NEXT: v_or_b32_e32 v2, v11, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 11
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
; VI-NEXT: v_perm_b32 v29, s16, v29, v1
; VI-NEXT: v_or_b32_e32 v2, v15, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: v_mov_b32_e32 v22, s88
; VI-NEXT: v_readlane_b32 s16, v33, 8
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 5
; VI-NEXT: v_or_b32_e32 v2, v14, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: v_perm_b32 v18, s28, v17, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 6
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 4
; VI-NEXT: v_or_b32_e32 v2, v18, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
+; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: v_perm_b32 v17, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 3
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
-; VI-NEXT: v_perm_b32 v3, s16, v23, v1
+; VI-NEXT: v_perm_b32 v23, s16, v23, v1
; VI-NEXT: v_or_b32_e32 v2, v17, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v23
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 2
@@ -230064,659 +230234,631 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; SI-NEXT: v_writelane_b32 v32, s99, 33
; SI-NEXT: v_writelane_b32 v32, s30, 34
; SI-NEXT: v_writelane_b32 v32, s31, 35
-; SI-NEXT: s_lshr_b32 s4, s29, 16
+; SI-NEXT: s_lshr_b32 s4, s21, 16
; SI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
-; SI-NEXT: s_mov_b32 s56, s16
+; SI-NEXT: s_lshr_b32 s30, s20, 16
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v33, s4, 0
-; SI-NEXT: s_lshr_b32 s4, s27, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 1
-; SI-NEXT: s_lshr_b32 s4, s25, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 2
-; SI-NEXT: s_lshr_b32 s4, s23, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 3
-; SI-NEXT: s_lshr_b32 s4, s21, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 4
-; SI-NEXT: v_writelane_b32 v33, s19, 5
+; SI-NEXT: v_writelane_b32 v33, s20, 1
+; SI-NEXT: v_writelane_b32 v33, s19, 2
; SI-NEXT: s_lshr_b32 s4, s19, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 6
-; SI-NEXT: v_writelane_b32 v33, s17, 7
-; SI-NEXT: s_lshr_b32 s4, s17, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 8
-; SI-NEXT: s_lshr_b32 s4, s16, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 9
-; SI-NEXT: s_mov_b32 s57, s18
-; SI-NEXT: v_writelane_b32 v33, s56, 10
-; SI-NEXT: s_mov_b32 s59, s20
-; SI-NEXT: v_writelane_b32 v33, s57, 11
-; SI-NEXT: v_writelane_b32 v33, s59, 12
-; SI-NEXT: v_writelane_b32 v33, s22, 13
-; SI-NEXT: v_writelane_b32 v33, s24, 14
-; SI-NEXT: v_readfirstlane_b32 s77, v10
-; SI-NEXT: v_writelane_b32 v33, s26, 15
-; SI-NEXT: s_lshr_b32 s93, s18, 16
-; SI-NEXT: s_lshr_b32 s18, s77, 16
-; SI-NEXT: v_writelane_b32 v33, s28, 16
-; SI-NEXT: s_lshr_b32 s34, s20, 16
-; SI-NEXT: v_readfirstlane_b32 s20, v15
-; SI-NEXT: v_readfirstlane_b32 s79, v12
-; SI-NEXT: v_writelane_b32 v33, s18, 17
-; SI-NEXT: s_lshr_b32 s47, s79, 16
-; SI-NEXT: v_writelane_b32 v33, s20, 18
-; SI-NEXT: s_mov_b32 s92, s25
-; SI-NEXT: v_readfirstlane_b32 s60, v17
-; SI-NEXT: v_readfirstlane_b32 s25, v16
-; SI-NEXT: v_readfirstlane_b32 s35, v14
-; SI-NEXT: v_readfirstlane_b32 s31, v13
-; SI-NEXT: v_readfirstlane_b32 s96, v11
+; SI-NEXT: v_writelane_b32 v33, s4, 3
+; SI-NEXT: v_writelane_b32 v33, s18, 4
+; SI-NEXT: v_writelane_b32 v33, s17, 5
+; SI-NEXT: v_writelane_b32 v33, s16, 6
+; SI-NEXT: v_writelane_b32 v33, s22, 7
+; SI-NEXT: v_writelane_b32 v33, s24, 8
+; SI-NEXT: s_lshr_b32 s94, s18, 16
+; SI-NEXT: s_lshr_b32 s34, s17, 16
+; SI-NEXT: s_lshr_b32 s95, s16, 16
+; SI-NEXT: v_readfirstlane_b32 s89, v17
+; SI-NEXT: v_readfirstlane_b32 s20, v16
+; SI-NEXT: v_readfirstlane_b32 s19, v15
+; SI-NEXT: v_readfirstlane_b32 s88, v14
+; SI-NEXT: v_readfirstlane_b32 s79, v13
+; SI-NEXT: v_readfirstlane_b32 s18, v12
+; SI-NEXT: v_readfirstlane_b32 s77, v11
+; SI-NEXT: v_readfirstlane_b32 s78, v10
; SI-NEXT: v_readfirstlane_b32 s16, v9
-; SI-NEXT: v_readfirstlane_b32 s49, v8
+; SI-NEXT: v_readfirstlane_b32 s76, v8
; SI-NEXT: v_readfirstlane_b32 s17, v7
; SI-NEXT: v_readfirstlane_b32 s82, v6
-; SI-NEXT: v_readfirstlane_b32 s80, v5
+; SI-NEXT: v_readfirstlane_b32 s39, v5
; SI-NEXT: v_readfirstlane_b32 s81, v4
-; SI-NEXT: v_readfirstlane_b32 s70, v3
-; SI-NEXT: v_readfirstlane_b32 s71, v2
-; SI-NEXT: v_readfirstlane_b32 s68, v1
-; SI-NEXT: v_readfirstlane_b32 s69, v0
-; SI-NEXT: v_writelane_b32 v33, s47, 19
-; SI-NEXT: s_lshr_b32 s83, s28, 16
-; SI-NEXT: s_lshr_b32 s91, s26, 16
-; SI-NEXT: s_lshr_b32 s38, s24, 16
-; SI-NEXT: s_lshr_b32 s36, s22, 16
-; SI-NEXT: s_lshr_b32 s98, s60, 16
-; SI-NEXT: s_lshr_b32 s62, s25, 16
-; SI-NEXT: s_lshr_b32 s97, s20, 16
-; SI-NEXT: s_lshr_b32 s61, s35, 16
-; SI-NEXT: s_lshr_b32 s67, s31, 16
-; SI-NEXT: s_lshr_b32 s65, s96, 16
-; SI-NEXT: s_lshr_b32 s55, s16, 16
-; SI-NEXT: s_lshr_b32 s84, s49, 16
-; SI-NEXT: s_lshr_b32 s53, s17, 16
-; SI-NEXT: s_lshr_b32 s87, s82, 16
-; SI-NEXT: s_lshr_b32 s94, s80, 16
-; SI-NEXT: s_lshr_b32 s86, s81, 16
-; SI-NEXT: s_lshr_b32 s51, s70, 16
-; SI-NEXT: s_lshr_b32 s85, s71, 16
-; SI-NEXT: s_lshr_b32 s48, s68, 16
-; SI-NEXT: s_lshr_b32 s39, s69, 16
+; SI-NEXT: v_readfirstlane_b32 s54, v3
+; SI-NEXT: v_readfirstlane_b32 s55, v2
+; SI-NEXT: v_readfirstlane_b32 s52, v1
+; SI-NEXT: v_readfirstlane_b32 s70, v0
+; SI-NEXT: v_writelane_b32 v33, s26, 9
+; SI-NEXT: s_lshr_b32 s93, s29, 16
+; SI-NEXT: s_lshr_b32 s48, s28, 16
+; SI-NEXT: s_lshr_b32 s37, s27, 16
+; SI-NEXT: s_lshr_b32 s38, s26, 16
+; SI-NEXT: s_lshr_b32 s35, s25, 16
+; SI-NEXT: s_lshr_b32 s36, s24, 16
+; SI-NEXT: s_lshr_b32 s31, s23, 16
+; SI-NEXT: s_lshr_b32 s84, s22, 16
+; SI-NEXT: s_lshr_b32 s98, s89, 16
+; SI-NEXT: s_lshr_b32 s72, s20, 16
+; SI-NEXT: s_lshr_b32 s99, s19, 16
+; SI-NEXT: s_lshr_b32 s85, s88, 16
+; SI-NEXT: s_lshr_b32 s87, s79, 16
+; SI-NEXT: s_lshr_b32 s51, s18, 16
+; SI-NEXT: s_lshr_b32 s97, s77, 16
+; SI-NEXT: s_lshr_b32 s49, s78, 16
+; SI-NEXT: s_lshr_b32 s83, s16, 16
+; SI-NEXT: s_lshr_b32 s71, s76, 16
+; SI-NEXT: s_lshr_b32 s67, s17, 16
+; SI-NEXT: s_lshr_b32 s91, s82, 16
+; SI-NEXT: s_lshr_b32 s92, s39, 16
+; SI-NEXT: s_lshr_b32 s69, s81, 16
+; SI-NEXT: s_lshr_b32 s90, s54, 16
+; SI-NEXT: s_lshr_b32 s68, s55, 16
+; SI-NEXT: s_lshr_b32 s65, s52, 16
+; SI-NEXT: s_lshr_b32 s53, s70, 16
; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_writelane_b32 v33, s60, 20
-; SI-NEXT: s_mov_b32 s30, s29
-; SI-NEXT: s_mov_b32 s37, s27
+; SI-NEXT: v_writelane_b32 v33, s28, 10
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v33, s61, 21
-; SI-NEXT: v_writelane_b32 v33, s62, 22
+; SI-NEXT: v_writelane_b32 v33, s70, 11
+; SI-NEXT: v_writelane_b32 v33, s72, 12
; SI-NEXT: s_cbranch_scc0 .LBB111_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_readlane_b32 s5, v33, 7
-; SI-NEXT: v_readlane_b32 s7, v33, 8
-; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_or_b32 s45, s5, s7
; SI-NEXT: v_readlane_b32 s5, v33, 5
-; SI-NEXT: v_readlane_b32 s7, v33, 6
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s34, 16
+; SI-NEXT: s_or_b32 s61, s5, s7
+; SI-NEXT: v_readlane_b32 s5, v33, 2
+; SI-NEXT: v_readlane_b32 s7, v33, 3
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_or_b32 s43, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v33, 4
+; SI-NEXT: s_or_b32 s59, s5, s7
+; SI-NEXT: v_readlane_b32 s7, v33, 0
; SI-NEXT: s_and_b32 s5, s21, 0xffff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_or_b32 s41, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v33, 3
+; SI-NEXT: s_or_b32 s57, s5, s7
; SI-NEXT: s_and_b32 s5, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_lshl_b32 s7, s31, 16
+; SI-NEXT: s_or_b32 s47, s5, s7
+; SI-NEXT: s_and_b32 s5, s25, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s35, 16
+; SI-NEXT: s_or_b32 s45, s5, s7
+; SI-NEXT: s_and_b32 s5, s27, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s37, 16
+; SI-NEXT: s_or_b32 s43, s5, s7
+; SI-NEXT: s_and_b32 s5, s29, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s93, 16
+; SI-NEXT: s_or_b32 s41, s5, s7
+; SI-NEXT: s_and_b32 s5, s52, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s65, 16
; SI-NEXT: s_or_b32 s15, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v33, 2
-; SI-NEXT: s_and_b32 s5, s92, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_and_b32 s5, s54, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s90, 16
; SI-NEXT: s_or_b32 s13, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v33, 1
-; SI-NEXT: s_and_b32 s5, s37, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_and_b32 s5, s39, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s92, 16
; SI-NEXT: s_or_b32 s11, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v33, 0
-; SI-NEXT: s_and_b32 s5, s30, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: v_readlane_b32 s4, v33, 9
+; SI-NEXT: s_and_b32 s5, s17, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s67, 16
; SI-NEXT: s_or_b32 s9, s5, s7
-; SI-NEXT: s_and_b32 s5, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s48, 16
-; SI-NEXT: v_writelane_b32 v33, s49, 35
+; SI-NEXT: s_and_b32 s5, s16, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s83, 16
; SI-NEXT: s_or_b32 s7, s5, s7
-; SI-NEXT: s_and_b32 s5, s70, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s51, 16
-; SI-NEXT: v_writelane_b32 v33, s17, 36
-; SI-NEXT: s_or_b32 s5, s5, s46
-; SI-NEXT: s_and_b32 s58, s80, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s94, 16
-; SI-NEXT: v_writelane_b32 v33, s80, 37
-; SI-NEXT: s_or_b32 vcc_hi, s58, s46
-; SI-NEXT: s_and_b32 s58, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s53, 16
-; SI-NEXT: v_writelane_b32 v33, s39, 38
-; SI-NEXT: v_writelane_b32 v33, s21, 39
-; SI-NEXT: s_or_b32 s49, s58, s46
-; SI-NEXT: s_and_b32 s21, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s55, 16
-; SI-NEXT: s_lshl_b32 vcc_lo, s86, 16
-; SI-NEXT: v_writelane_b32 v33, s35, 40
-; SI-NEXT: s_mov_b32 s35, s86
-; SI-NEXT: s_mov_b32 s86, s94
-; SI-NEXT: s_mov_b32 s94, s51
-; SI-NEXT: s_or_b32 s51, s21, s46
-; SI-NEXT: s_and_b32 s21, s96, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s65, 16
-; SI-NEXT: s_mov_b32 s80, s48
-; SI-NEXT: s_lshl_b32 s48, s87, 16
-; SI-NEXT: s_mov_b32 s29, s87
-; SI-NEXT: s_mov_b32 s87, s53
-; SI-NEXT: s_or_b32 s53, s21, s46
-; SI-NEXT: s_and_b32 s21, s31, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s67, 16
-; SI-NEXT: s_mov_b32 s19, s93
-; SI-NEXT: s_lshl_b32 s42, s93, 16
-; SI-NEXT: v_writelane_b32 v33, s79, 41
-; SI-NEXT: s_mov_b32 s93, s96
-; SI-NEXT: s_mov_b32 s96, s55
-; SI-NEXT: s_or_b32 s55, s21, s46
-; SI-NEXT: s_and_b32 s21, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s97, 16
-; SI-NEXT: v_writelane_b32 v33, s77, 42
-; SI-NEXT: s_mov_b32 s99, s97
-; SI-NEXT: s_mov_b32 s97, s65
-; SI-NEXT: s_or_b32 s65, s21, s46
-; SI-NEXT: s_and_b32 s21, s60, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s98, 16
-; SI-NEXT: s_lshl_b32 s44, s4, 16
-; SI-NEXT: v_writelane_b32 v33, s70, 43
-; SI-NEXT: s_mov_b32 s70, s68
-; SI-NEXT: s_mov_b32 s68, s30
-; SI-NEXT: s_mov_b32 s30, s67
-; SI-NEXT: s_or_b32 s67, s21, s46
-; SI-NEXT: s_and_b32 s21, s56, 0xffff
-; SI-NEXT: s_lshl_b32 s66, s62, 16
-; SI-NEXT: s_or_b32 s62, s21, s44
-; SI-NEXT: s_and_b32 s21, s57, 0xffff
-; SI-NEXT: s_lshl_b32 s40, s34, 16
-; SI-NEXT: s_or_b32 s74, s21, s42
-; SI-NEXT: s_and_b32 s21, s59, 0xffff
-; SI-NEXT: s_lshl_b32 s14, s36, 16
-; SI-NEXT: s_or_b32 s72, s21, s40
-; SI-NEXT: s_and_b32 s21, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s12, s38, 16
-; SI-NEXT: s_lshl_b32 s52, s18, 16
-; SI-NEXT: s_mov_b32 s20, s38
+; SI-NEXT: s_and_b32 s5, s77, 0xffff
+; SI-NEXT: s_lshl_b32 s62, s97, 16
+; SI-NEXT: s_or_b32 s5, s5, s62
+; SI-NEXT: s_and_b32 s63, s79, 0xffff
+; SI-NEXT: s_lshl_b32 s62, s87, 16
+; SI-NEXT: s_or_b32 vcc_hi, s63, s62
+; SI-NEXT: s_and_b32 s63, s19, 0xffff
+; SI-NEXT: s_lshl_b32 s62, s99, 16
+; SI-NEXT: s_mov_b32 s96, s83
+; SI-NEXT: s_mov_b32 s83, s21
+; SI-NEXT: s_mov_b32 s86, s92
+; SI-NEXT: s_mov_b32 s92, s90
+; SI-NEXT: s_mov_b32 s90, s65
+; SI-NEXT: s_or_b32 s65, s63, s62
+; SI-NEXT: s_and_b32 s21, s89, 0xffff
+; SI-NEXT: s_lshl_b32 s62, s98, 16
+; SI-NEXT: s_lshl_b32 s58, s94, 16
+; SI-NEXT: s_lshl_b32 s56, s30, 16
+; SI-NEXT: s_lshl_b32 s46, s84, 16
+; SI-NEXT: s_lshl_b32 s44, s36, 16
+; SI-NEXT: s_lshl_b32 s42, s38, 16
+; SI-NEXT: s_lshl_b32 s40, s48, 16
+; SI-NEXT: s_mov_b32 s50, s48
+; SI-NEXT: s_mov_b32 s48, s38
; SI-NEXT: s_mov_b32 s38, s36
-; SI-NEXT: s_mov_b32 s36, s34
-; SI-NEXT: s_mov_b32 s34, s98
-; SI-NEXT: s_mov_b32 s98, s19
-; SI-NEXT: s_or_b32 s60, s21, s14
-; SI-NEXT: s_lshr_b64 s[18:19], s[14:15], 16
-; SI-NEXT: s_and_b32 s14, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s10, s91, 16
-; SI-NEXT: s_or_b32 s58, s14, s12
-; SI-NEXT: s_lshr_b64 s[76:77], s[12:13], 16
-; SI-NEXT: s_and_b32 s12, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s8, s83, 16
-; SI-NEXT: s_or_b32 s56, s12, s10
-; SI-NEXT: s_lshr_b64 s[88:89], s[10:11], 16
-; SI-NEXT: s_and_b32 s10, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s54, s47, 16
-; SI-NEXT: s_or_b32 s46, s10, s8
-; SI-NEXT: s_mov_b32 s47, s9
+; SI-NEXT: s_mov_b32 s36, s84
+; SI-NEXT: s_mov_b32 s84, s30
+; SI-NEXT: s_mov_b32 s30, s98
+; SI-NEXT: s_mov_b32 s98, s87
+; SI-NEXT: s_mov_b32 s87, s94
+; SI-NEXT: s_mov_b32 s94, s67
+; SI-NEXT: s_or_b32 s67, s21, s62
+; SI-NEXT: v_readlane_b32 s21, v33, 6
+; SI-NEXT: s_lshl_b32 s60, s95, 16
+; SI-NEXT: s_and_b32 s21, s21, 0xffff
+; SI-NEXT: s_or_b32 s62, s21, s60
+; SI-NEXT: s_mov_b32 s63, s61
+; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
+; SI-NEXT: v_writelane_b32 v33, s60, 13
+; SI-NEXT: v_writelane_b32 v33, s61, 14
+; SI-NEXT: v_readlane_b32 s21, v33, 4
+; SI-NEXT: s_and_b32 s21, s21, 0xffff
+; SI-NEXT: s_or_b32 s74, s21, s58
+; SI-NEXT: s_mov_b32 s75, s59
+; SI-NEXT: s_lshr_b64 s[58:59], s[58:59], 16
+; SI-NEXT: v_writelane_b32 v33, s58, 15
+; SI-NEXT: v_writelane_b32 v33, s59, 16
+; SI-NEXT: v_readlane_b32 s21, v33, 1
+; SI-NEXT: s_and_b32 s21, s21, 0xffff
+; SI-NEXT: s_lshl_b32 s66, s72, 16
+; SI-NEXT: s_or_b32 s72, s21, s56
+; SI-NEXT: s_mov_b32 s73, s57
+; SI-NEXT: s_lshr_b64 s[56:57], s[56:57], 16
+; SI-NEXT: v_writelane_b32 v33, s56, 17
+; SI-NEXT: s_and_b32 s21, s22, 0xffff
+; SI-NEXT: v_writelane_b32 v33, s57, 18
+; SI-NEXT: s_or_b32 s60, s21, s46
+; SI-NEXT: s_mov_b32 s61, s47
+; SI-NEXT: s_lshr_b64 s[46:47], s[46:47], 16
+; SI-NEXT: v_writelane_b32 v33, s46, 19
+; SI-NEXT: s_and_b32 s21, s24, 0xffff
+; SI-NEXT: v_writelane_b32 v33, s47, 20
+; SI-NEXT: s_or_b32 s58, s21, s44
+; SI-NEXT: s_mov_b32 s59, s45
+; SI-NEXT: s_lshr_b64 s[44:45], s[44:45], 16
+; SI-NEXT: v_writelane_b32 v33, s44, 21
+; SI-NEXT: s_and_b32 s21, s26, 0xffff
+; SI-NEXT: v_writelane_b32 v33, s45, 22
+; SI-NEXT: s_or_b32 s56, s21, s42
+; SI-NEXT: s_mov_b32 s57, s43
+; SI-NEXT: s_lshr_b64 s[42:43], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v33, s42, 23
+; SI-NEXT: s_and_b32 s21, s28, 0xffff
+; SI-NEXT: v_writelane_b32 v33, s43, 24
+; SI-NEXT: s_or_b32 s46, s21, s40
+; SI-NEXT: s_mov_b32 s47, s41
+; SI-NEXT: s_lshr_b64 s[40:41], s[40:41], 16
+; SI-NEXT: s_lshl_b32 s14, s53, 16
+; SI-NEXT: v_writelane_b32 v33, s40, 25
+; SI-NEXT: s_and_b32 s21, s70, 0xffff
+; SI-NEXT: v_writelane_b32 v33, s41, 26
+; SI-NEXT: s_or_b32 s44, s21, s14
+; SI-NEXT: s_mov_b32 s45, s15
+; SI-NEXT: s_lshr_b64 s[14:15], s[14:15], 16
+; SI-NEXT: v_writelane_b32 v33, s14, 27
+; SI-NEXT: s_lshl_b32 s12, s68, 16
+; SI-NEXT: v_writelane_b32 v33, s15, 28
+; SI-NEXT: s_and_b32 s14, s55, 0xffff
+; SI-NEXT: s_or_b32 s42, s14, s12
+; SI-NEXT: s_mov_b32 s43, s13
+; SI-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
+; SI-NEXT: v_writelane_b32 v33, s12, 29
+; SI-NEXT: s_lshl_b32 s10, s69, 16
+; SI-NEXT: v_writelane_b32 v33, s13, 30
+; SI-NEXT: s_and_b32 s12, s81, 0xffff
+; SI-NEXT: s_or_b32 s40, s12, s10
+; SI-NEXT: s_mov_b32 s41, s11
+; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
+; SI-NEXT: v_writelane_b32 v33, s10, 31
+; SI-NEXT: s_lshl_b32 s8, s91, 16
+; SI-NEXT: v_writelane_b32 v33, s11, 32
+; SI-NEXT: s_and_b32 s10, s82, 0xffff
+; SI-NEXT: s_or_b32 s14, s10, s8
+; SI-NEXT: s_mov_b32 s15, s9
; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
-; SI-NEXT: v_writelane_b32 v33, s8, 23
-; SI-NEXT: s_lshl_b32 s6, s39, 16
-; SI-NEXT: v_writelane_b32 v33, s9, 24
-; SI-NEXT: s_and_b32 s8, s69, 0xffff
-; SI-NEXT: s_mov_b32 s63, s45
-; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 16
-; SI-NEXT: s_or_b32 s44, s8, s6
-; SI-NEXT: s_mov_b32 s45, s7
+; SI-NEXT: v_writelane_b32 v33, s8, 33
+; SI-NEXT: s_lshl_b32 s6, s71, 16
+; SI-NEXT: v_writelane_b32 v33, s9, 34
+; SI-NEXT: s_and_b32 s8, s76, 0xffff
+; SI-NEXT: s_or_b32 s12, s8, s6
+; SI-NEXT: s_mov_b32 s13, s7
; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
-; SI-NEXT: v_writelane_b32 v33, s6, 25
-; SI-NEXT: s_lshl_b32 s4, s85, 16
-; SI-NEXT: v_writelane_b32 v33, s7, 26
-; SI-NEXT: s_and_b32 s6, s71, 0xffff
-; SI-NEXT: s_mov_b32 s95, s16
-; SI-NEXT: s_mov_b32 s75, s43
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
-; SI-NEXT: s_or_b32 s42, s6, s4
-; SI-NEXT: s_mov_b32 s43, s5
+; SI-NEXT: v_writelane_b32 v33, s6, 35
+; SI-NEXT: s_lshl_b32 s4, s49, 16
+; SI-NEXT: v_writelane_b32 v33, s7, 36
+; SI-NEXT: s_and_b32 s6, s78, 0xffff
+; SI-NEXT: s_or_b32 s10, s6, s4
+; SI-NEXT: s_mov_b32 s11, s5
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
-; SI-NEXT: v_writelane_b32 v33, s4, 27
-; SI-NEXT: v_writelane_b32 v33, s5, 28
-; SI-NEXT: s_and_b32 s4, s81, 0xffff
-; SI-NEXT: s_mov_b32 s27, s23
-; SI-NEXT: s_mov_b32 s23, s83
-; SI-NEXT: s_mov_b32 s83, s91
-; SI-NEXT: s_lshr_b64 s[90:91], s[40:41], 16
-; SI-NEXT: s_or_b32 s40, s4, vcc_lo
-; SI-NEXT: s_lshr_b64 s[4:5], vcc, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 29
-; SI-NEXT: v_writelane_b32 v33, s5, 30
-; SI-NEXT: s_and_b32 s4, s82, 0xffff
-; SI-NEXT: s_or_b32 s14, s4, s48
-; SI-NEXT: s_lshr_b64 s[4:5], s[48:49], 16
-; SI-NEXT: v_writelane_b32 v33, s4, 31
-; SI-NEXT: v_writelane_b32 v33, s5, 32
-; SI-NEXT: s_lshl_b32 s64, s61, 16
-; SI-NEXT: s_mov_b32 s61, s15
-; SI-NEXT: s_mov_b32 s15, s49
-; SI-NEXT: v_readlane_b32 s49, v33, 35
-; SI-NEXT: s_lshl_b32 s50, s84, 16
-; SI-NEXT: s_and_b32 s4, s49, 0xffff
-; SI-NEXT: v_readlane_b32 s77, v33, 42
-; SI-NEXT: s_or_b32 s12, s4, s50
-; SI-NEXT: s_and_b32 s4, s77, 0xffff
-; SI-NEXT: s_mov_b32 s59, s13
-; SI-NEXT: s_mov_b32 s57, s11
-; SI-NEXT: s_mov_b32 s13, s51
-; SI-NEXT: s_lshr_b64 s[50:51], s[50:51], 16
-; SI-NEXT: v_readlane_b32 s79, v33, 41
-; SI-NEXT: s_or_b32 s10, s4, s52
-; SI-NEXT: s_mov_b32 s11, s53
-; SI-NEXT: s_lshr_b64 s[52:53], s[52:53], 16
-; SI-NEXT: s_mov_b32 s51, s94
-; SI-NEXT: s_mov_b32 s94, s86
-; SI-NEXT: s_mov_b32 s86, s35
-; SI-NEXT: v_readlane_b32 s35, v33, 40
-; SI-NEXT: s_mov_b32 s53, s87
-; SI-NEXT: s_mov_b32 s87, s29
-; SI-NEXT: s_and_b32 s4, s79, 0xffff
-; SI-NEXT: s_lshr_b64 s[28:29], s[66:67], 16
-; SI-NEXT: s_mov_b32 s48, s80
-; SI-NEXT: v_readlane_b32 s21, v33, 39
-; SI-NEXT: v_readlane_b32 s39, v33, 38
-; SI-NEXT: v_readlane_b32 s80, v33, 37
-; SI-NEXT: v_readlane_b32 s17, v33, 36
-; SI-NEXT: s_or_b32 s8, s4, s54
-; SI-NEXT: s_and_b32 s4, s35, 0xffff
-; SI-NEXT: v_writelane_b32 v33, s28, 33
-; SI-NEXT: s_mov_b32 s9, s55
-; SI-NEXT: s_lshr_b64 s[54:55], s[54:55], 16
+; SI-NEXT: s_lshl_b32 vcc_lo, s51, 16
+; SI-NEXT: v_writelane_b32 v33, s4, 37
+; SI-NEXT: v_writelane_b32 v33, s5, 38
+; SI-NEXT: s_and_b32 s4, s18, 0xffff
+; SI-NEXT: s_lshr_b64 s[6:7], vcc, 16
+; SI-NEXT: s_lshl_b32 s64, s85, 16
+; SI-NEXT: s_or_b32 s8, s4, vcc_lo
+; SI-NEXT: v_writelane_b32 v33, s6, 39
+; SI-NEXT: s_and_b32 s4, s88, 0xffff
+; SI-NEXT: v_writelane_b32 v33, s7, 40
; SI-NEXT: s_or_b32 s6, s4, s64
+; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_mov_b32 s7, s65
; SI-NEXT: s_lshr_b64 s[64:65], s[64:65], 16
-; SI-NEXT: s_and_b32 s4, s25, 0xffff
-; SI-NEXT: v_writelane_b32 v33, s29, 34
-; SI-NEXT: s_mov_b32 s73, s41
-; SI-NEXT: s_mov_b32 s41, vcc_hi
-; SI-NEXT: s_mov_b32 s55, s96
-; SI-NEXT: s_mov_b32 s96, s93
-; SI-NEXT: s_mov_b32 s24, s16
-; SI-NEXT: s_mov_b32 s65, s97
-; SI-NEXT: s_mov_b32 s97, s99
; SI-NEXT: s_or_b32 s4, s4, s66
; SI-NEXT: s_mov_b32 s5, s67
-; SI-NEXT: s_mov_b32 s67, s30
-; SI-NEXT: s_mov_b32 s93, s98
-; SI-NEXT: s_mov_b32 s98, s34
-; SI-NEXT: s_mov_b32 s34, s36
+; SI-NEXT: s_lshr_b64 s[66:67], s[66:67], 16
+; SI-NEXT: s_mov_b32 s9, vcc_hi
+; SI-NEXT: s_mov_b32 s65, s90
+; SI-NEXT: s_mov_b32 s90, s92
+; SI-NEXT: s_mov_b32 s92, s86
+; SI-NEXT: s_mov_b32 s21, s83
+; SI-NEXT: s_mov_b32 s83, s96
+; SI-NEXT: s_mov_b32 s67, s94
+; SI-NEXT: s_mov_b32 s94, s87
+; SI-NEXT: s_mov_b32 s87, s98
+; SI-NEXT: s_mov_b32 s98, s30
+; SI-NEXT: s_mov_b32 s30, s84
+; SI-NEXT: s_mov_b32 s84, s36
; SI-NEXT: s_mov_b32 s36, s38
-; SI-NEXT: s_mov_b32 s38, s20
-; SI-NEXT: s_mov_b32 s91, s83
-; SI-NEXT: s_mov_b32 s83, s23
-; SI-NEXT: s_mov_b32 s23, s27
-; SI-NEXT: s_mov_b32 s30, s68
-; SI-NEXT: s_mov_b32 s68, s70
-; SI-NEXT: v_readlane_b32 s70, v33, 43
-; SI-NEXT: s_mov_b32 s28, s18
-; SI-NEXT: s_mov_b32 s16, s95
+; SI-NEXT: s_mov_b32 s38, s48
+; SI-NEXT: s_mov_b32 s48, s50
; SI-NEXT: s_cbranch_execnz .LBB111_3
; SI-NEXT: .LBB111_2: ; %cmp.true
-; SI-NEXT: s_add_i32 s20, s25, 3
-; SI-NEXT: v_readlane_b32 s5, v33, 22
+; SI-NEXT: s_add_i32 s20, s20, 3
+; SI-NEXT: v_readlane_b32 s5, v33, 12
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: s_add_i32 s89, s89, 3
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_readlane_b32 s5, v33, 20
-; SI-NEXT: s_add_i32 s89, s5, 3
; SI-NEXT: s_and_b32 s5, s89, 0xffff
; SI-NEXT: s_lshl_b32 s6, s98, 16
-; SI-NEXT: s_add_i32 s88, s35, 3
-; SI-NEXT: v_readlane_b32 s7, v33, 21
+; SI-NEXT: s_add_i32 s88, s88, 3
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: s_and_b32 s6, s88, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_lshl_b32 s7, s85, 16
+; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: v_readlane_b32 s7, v33, 18
-; SI-NEXT: s_add_i32 s19, s7, 3
; SI-NEXT: s_and_b32 s7, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s8, s97, 16
-; SI-NEXT: s_add_i32 s18, s79, 3
-; SI-NEXT: v_readlane_b32 s9, v33, 19
+; SI-NEXT: s_lshl_b32 s8, s99, 16
+; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: s_and_b32 s8, s18, 0xffff
-; SI-NEXT: s_lshl_b32 s9, s9, 16
-; SI-NEXT: s_add_i32 s79, s31, 3
+; SI-NEXT: s_lshl_b32 s9, s51, 16
+; SI-NEXT: s_add_i32 s79, s79, 3
; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_and_b32 s9, s79, 0xffff
-; SI-NEXT: s_lshl_b32 s10, s67, 16
-; SI-NEXT: s_add_i32 s78, s77, 3
-; SI-NEXT: v_readlane_b32 s11, v33, 17
+; SI-NEXT: s_lshl_b32 s10, s87, 16
+; SI-NEXT: s_add_i32 s78, s78, 3
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: s_and_b32 s10, s78, 0xffff
-; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: s_add_i32 s77, s96, 3
+; SI-NEXT: s_lshl_b32 s11, s49, 16
+; SI-NEXT: s_add_i32 s77, s77, 3
; SI-NEXT: s_or_b32 s10, s11, s10
; SI-NEXT: s_and_b32 s11, s77, 0xffff
-; SI-NEXT: s_lshl_b32 s12, s65, 16
-; SI-NEXT: s_add_i32 s76, s49, 3
+; SI-NEXT: s_lshl_b32 s12, s97, 16
+; SI-NEXT: s_add_i32 s76, s76, 3
; SI-NEXT: s_or_b32 s11, s12, s11
; SI-NEXT: s_and_b32 s12, s76, 0xffff
-; SI-NEXT: s_lshl_b32 s13, s84, 16
+; SI-NEXT: s_lshl_b32 s13, s71, 16
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_or_b32 s12, s13, s12
; SI-NEXT: s_and_b32 s13, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s14, s55, 16
+; SI-NEXT: s_lshl_b32 s14, s83, 16
; SI-NEXT: s_add_i32 s82, s82, 3
; SI-NEXT: s_or_b32 s13, s14, s13
; SI-NEXT: s_and_b32 s14, s82, 0xffff
-; SI-NEXT: s_lshl_b32 s15, s87, 16
+; SI-NEXT: s_lshl_b32 s15, s91, 16
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_or_b32 s14, s15, s14
; SI-NEXT: s_and_b32 s15, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s16, s53, 16
+; SI-NEXT: s_lshl_b32 s16, s67, 16
; SI-NEXT: s_add_i32 s81, s81, 3
; SI-NEXT: s_or_b32 s15, s16, s15
; SI-NEXT: s_and_b32 s16, s81, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s86, 16
+; SI-NEXT: s_lshl_b32 s17, s69, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s80, s80, 3
+; SI-NEXT: s_add_i32 s80, s39, 3
; SI-NEXT: s_add_i32 s40, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s80, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s94, 16
+; SI-NEXT: s_lshl_b32 s17, s92, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s71, s71, 3
+; SI-NEXT: s_add_i32 s71, s55, 3
; SI-NEXT: s_add_i32 s41, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s71, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s85, 16
+; SI-NEXT: s_lshl_b32 s17, s68, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s70, s70, 3
+; SI-NEXT: s_add_i32 s70, s54, 3
; SI-NEXT: s_add_i32 s42, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s70, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s51, 16
+; SI-NEXT: s_lshl_b32 s17, s90, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s69, s69, 3
; SI-NEXT: s_add_i32 s43, s16, 0x30000
+; SI-NEXT: v_readlane_b32 s16, v33, 11
+; SI-NEXT: s_add_i32 s69, s16, 3
; SI-NEXT: s_and_b32 s16, s69, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s39, 16
+; SI-NEXT: s_lshl_b32 s17, s53, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s68, s68, 3
+; SI-NEXT: s_add_i32 s68, s52, 3
; SI-NEXT: s_add_i32 s44, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s48, 16
+; SI-NEXT: s_lshl_b32 s17, s65, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s45, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 16
+; SI-NEXT: v_readlane_b32 s16, v33, 10
; SI-NEXT: s_add_i32 s28, s16, 3
; SI-NEXT: s_and_b32 s16, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s83, 16
+; SI-NEXT: s_lshl_b32 s17, s48, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s29, s30, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 0
+; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s46, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s93, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s47, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 15
+; SI-NEXT: v_readlane_b32 s16, v33, 9
; SI-NEXT: s_add_i32 s26, s16, 3
; SI-NEXT: s_and_b32 s16, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s91, 16
+; SI-NEXT: s_lshl_b32 s17, s38, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s27, s37, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 1
+; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s56, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s37, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s57, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 14
+; SI-NEXT: v_readlane_b32 s16, v33, 8
; SI-NEXT: s_add_i32 s24, s16, 3
; SI-NEXT: s_and_b32 s16, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s38, 16
+; SI-NEXT: s_lshl_b32 s17, s36, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s25, s92, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 2
+; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s58, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s35, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s59, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 13
+; SI-NEXT: v_readlane_b32 s16, v33, 7
; SI-NEXT: s_add_i32 s22, s16, 3
; SI-NEXT: s_and_b32 s16, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s36, 16
+; SI-NEXT: s_lshl_b32 s17, s84, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s23, s23, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 3
; SI-NEXT: s_add_i32 s60, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s31, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s61, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 12
+; SI-NEXT: v_readlane_b32 s16, v33, 1
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s34, 16
+; SI-NEXT: s_lshl_b32 s17, s30, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s72, s16, 0x30000
; SI-NEXT: s_add_i32 s16, s21, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 4
+; SI-NEXT: v_readlane_b32 s17, v33, 0
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s73, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 11
+; SI-NEXT: v_readlane_b32 s16, v33, 4
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s93, 16
+; SI-NEXT: s_lshl_b32 s17, s94, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s74, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 5
+; SI-NEXT: v_readlane_b32 s16, v33, 2
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 6
+; SI-NEXT: v_readlane_b32 s17, v33, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s75, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 10
+; SI-NEXT: v_readlane_b32 s16, v33, 6
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 9
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s95, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s62, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 7
+; SI-NEXT: v_readlane_b32 s16, v33, 5
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 8
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s34, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s63, s16, 0x30000
-; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 13
+; SI-NEXT: v_writelane_b32 v33, s17, 14
+; SI-NEXT: s_lshr_b64 s[16:17], s[74:75], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 15
+; SI-NEXT: v_writelane_b32 v33, s17, 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[72:73], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 17
+; SI-NEXT: v_writelane_b32 v33, s17, 18
+; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 19
+; SI-NEXT: v_writelane_b32 v33, s17, 20
+; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 21
+; SI-NEXT: v_writelane_b32 v33, s17, 22
+; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
; SI-NEXT: v_writelane_b32 v33, s16, 23
; SI-NEXT: v_writelane_b32 v33, s17, 24
-; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
; SI-NEXT: v_writelane_b32 v33, s16, 25
; SI-NEXT: v_writelane_b32 v33, s17, 26
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
; SI-NEXT: v_writelane_b32 v33, s16, 27
; SI-NEXT: v_writelane_b32 v33, s17, 28
+; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 29
+; SI-NEXT: v_writelane_b32 v33, s17, 30
; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 16
; SI-NEXT: s_add_i32 s14, s14, 0x30000
; SI-NEXT: s_add_i32 s15, s15, 0x30000
-; SI-NEXT: v_writelane_b32 v33, s16, 29
-; SI-NEXT: v_writelane_b32 v33, s17, 30
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
-; SI-NEXT: s_add_i32 s4, s4, 0x30000
-; SI-NEXT: s_add_i32 s5, s5, 0x30000
; SI-NEXT: v_writelane_b32 v33, s16, 31
; SI-NEXT: v_writelane_b32 v33, s17, 32
-; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
+; SI-NEXT: s_add_i32 s12, s12, 0x30000
+; SI-NEXT: s_add_i32 s13, s13, 0x30000
; SI-NEXT: v_writelane_b32 v33, s16, 33
; SI-NEXT: v_writelane_b32 v33, s17, 34
-; SI-NEXT: s_lshr_b32 s16, s63, 16
-; SI-NEXT: v_writelane_b32 v33, s16, 8
-; SI-NEXT: s_lshr_b32 s16, s75, 16
-; SI-NEXT: v_writelane_b32 v33, s16, 6
-; SI-NEXT: s_lshr_b32 s16, s73, 16
-; SI-NEXT: v_writelane_b32 v33, s16, 4
-; SI-NEXT: s_lshr_b32 s16, s61, 16
-; SI-NEXT: s_add_i32 s6, s6, 0x30000
-; SI-NEXT: s_add_i32 s7, s7, 0x30000
-; SI-NEXT: s_add_i32 s8, s8, 0x30000
-; SI-NEXT: s_add_i32 s9, s9, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 16
; SI-NEXT: s_add_i32 s10, s10, 0x30000
; SI-NEXT: s_add_i32 s11, s11, 0x30000
-; SI-NEXT: s_add_i32 s12, s12, 0x30000
-; SI-NEXT: s_add_i32 s13, s13, 0x30000
-; SI-NEXT: v_writelane_b32 v33, s16, 3
-; SI-NEXT: s_lshr_b32 s16, s59, 16
-; SI-NEXT: s_lshr_b64 s[50:51], s[12:13], 16
-; SI-NEXT: s_lshr_b64 s[52:53], s[10:11], 16
-; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 35
+; SI-NEXT: v_writelane_b32 v33, s17, 36
+; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 16
+; SI-NEXT: s_add_i32 s8, s8, 0x30000
+; SI-NEXT: s_add_i32 s9, s9, 0x30000
+; SI-NEXT: v_writelane_b32 v33, s16, 37
+; SI-NEXT: v_writelane_b32 v33, s17, 38
+; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16
+; SI-NEXT: s_add_i32 s4, s4, 0x30000
+; SI-NEXT: s_add_i32 s5, s5, 0x30000
+; SI-NEXT: s_add_i32 s6, s6, 0x30000
+; SI-NEXT: s_add_i32 s7, s7, 0x30000
+; SI-NEXT: v_writelane_b32 v33, s16, 39
+; SI-NEXT: v_writelane_b32 v33, s17, 40
; SI-NEXT: s_lshr_b64 s[64:65], s[6:7], 16
-; SI-NEXT: v_writelane_b32 v33, s16, 2
-; SI-NEXT: s_lshr_b32 s16, s57, 16
-; SI-NEXT: s_lshr_b64 s[78:79], s[62:63], 16
-; SI-NEXT: s_lshr_b64 s[24:25], s[74:75], 16
-; SI-NEXT: s_lshr_b64 s[90:91], s[72:73], 16
-; SI-NEXT: s_lshr_b64 s[28:29], s[60:61], 16
-; SI-NEXT: s_lshr_b64 s[76:77], s[58:59], 16
-; SI-NEXT: s_lshr_b64 s[88:89], s[56:57], 16
-; SI-NEXT: v_writelane_b32 v33, s16, 1
-; SI-NEXT: s_lshr_b32 s16, s47, 16
-; SI-NEXT: s_lshr_b32 s48, s45, 16
-; SI-NEXT: s_lshr_b32 s51, s43, 16
-; SI-NEXT: s_lshr_b32 s94, s41, 16
-; SI-NEXT: s_lshr_b32 s53, s15, 16
-; SI-NEXT: s_lshr_b32 s55, s13, 16
-; SI-NEXT: s_lshr_b32 s65, s11, 16
-; SI-NEXT: s_lshr_b32 s67, s9, 16
-; SI-NEXT: s_lshr_b32 s97, s7, 16
+; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 16
+; SI-NEXT: s_lshr_b32 s16, s75, 16
+; SI-NEXT: s_lshr_b32 s34, s63, 16
+; SI-NEXT: v_writelane_b32 v33, s16, 3
+; SI-NEXT: s_lshr_b32 s16, s73, 16
+; SI-NEXT: s_lshr_b32 s31, s61, 16
+; SI-NEXT: s_lshr_b32 s35, s59, 16
+; SI-NEXT: s_lshr_b32 s37, s57, 16
+; SI-NEXT: s_lshr_b32 s93, s47, 16
+; SI-NEXT: s_lshr_b32 s65, s45, 16
+; SI-NEXT: s_lshr_b32 s90, s43, 16
+; SI-NEXT: s_lshr_b32 s92, s41, 16
+; SI-NEXT: s_lshr_b32 s67, s15, 16
+; SI-NEXT: s_lshr_b32 s83, s13, 16
+; SI-NEXT: s_lshr_b32 s97, s11, 16
+; SI-NEXT: s_lshr_b32 s87, s9, 16
+; SI-NEXT: s_lshr_b32 s99, s7, 16
; SI-NEXT: s_lshr_b32 s98, s5, 16
; SI-NEXT: v_writelane_b32 v33, s16, 0
; SI-NEXT: .LBB111_3: ; %end
+; SI-NEXT: v_readlane_b32 s18, v33, 13
; SI-NEXT: s_and_b32 s16, s62, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s78, 16
-; SI-NEXT: v_readlane_b32 s18, v33, 8
+; SI-NEXT: s_lshl_b32 s17, s18, 16
+; SI-NEXT: v_readlane_b32 s19, v33, 14
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s63, 0xffff
-; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_lshl_b32 s18, s34, 16
+; SI-NEXT: v_readlane_b32 s20, v33, 15
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s19, s24, 16
-; SI-NEXT: v_readlane_b32 s20, v33, 6
+; SI-NEXT: s_lshl_b32 s19, s20, 16
+; SI-NEXT: v_readlane_b32 s20, v33, 3
+; SI-NEXT: v_readlane_b32 s21, v33, 16
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s75, 0xffff
; SI-NEXT: s_lshl_b32 s20, s20, 16
+; SI-NEXT: v_readlane_b32 s22, v33, 17
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_and_b32 s20, s72, 0xffff
-; SI-NEXT: s_lshl_b32 s21, s90, 16
-; SI-NEXT: v_readlane_b32 s22, v33, 4
+; SI-NEXT: s_lshl_b32 s21, s22, 16
+; SI-NEXT: v_readlane_b32 s22, v33, 0
+; SI-NEXT: v_readlane_b32 s23, v33, 18
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s73, 0xffff
; SI-NEXT: s_lshl_b32 s22, s22, 16
+; SI-NEXT: v_readlane_b32 s24, v33, 19
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s60, 0xffff
-; SI-NEXT: s_lshl_b32 s23, s28, 16
-; SI-NEXT: v_readlane_b32 s24, v33, 3
+; SI-NEXT: s_lshl_b32 s23, s24, 16
+; SI-NEXT: v_readlane_b32 s25, v33, 20
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s61, 0xffff
-; SI-NEXT: s_lshl_b32 s24, s24, 16
+; SI-NEXT: s_lshl_b32 s24, s31, 16
+; SI-NEXT: v_readlane_b32 s26, v33, 21
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s24, s58, 0xffff
-; SI-NEXT: s_lshl_b32 s25, s76, 16
-; SI-NEXT: v_readlane_b32 s26, v33, 2
+; SI-NEXT: s_lshl_b32 s25, s26, 16
+; SI-NEXT: v_readlane_b32 s27, v33, 22
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s59, 0xffff
-; SI-NEXT: s_lshl_b32 s26, s26, 16
+; SI-NEXT: s_lshl_b32 s26, s35, 16
+; SI-NEXT: v_readlane_b32 s28, v33, 23
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s56, 0xffff
-; SI-NEXT: s_lshl_b32 s27, s88, 16
-; SI-NEXT: v_readlane_b32 s28, v33, 1
+; SI-NEXT: s_lshl_b32 s27, s28, 16
+; SI-NEXT: v_readlane_b32 s29, v33, 24
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s57, 0xffff
-; SI-NEXT: s_lshl_b32 s28, s28, 16
-; SI-NEXT: v_readlane_b32 s56, v33, 23
+; SI-NEXT: s_lshl_b32 s28, s37, 16
+; SI-NEXT: v_readlane_b32 s56, v33, 25
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s46, 0xffff
; SI-NEXT: s_lshl_b32 s29, s56, 16
-; SI-NEXT: v_readlane_b32 s46, v33, 0
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s29, s47, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s46, 16
+; SI-NEXT: s_lshl_b32 s46, s93, 16
; SI-NEXT: s_or_b32 s29, s29, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 25
+; SI-NEXT: v_readlane_b32 s46, v33, 27
; SI-NEXT: s_and_b32 s44, s44, 0xffff
; SI-NEXT: s_lshl_b32 s46, s46, 16
-; SI-NEXT: v_readlane_b32 s47, v33, 26
+; SI-NEXT: v_readlane_b32 s47, v33, 28
; SI-NEXT: s_or_b32 s44, s44, s46
; SI-NEXT: s_and_b32 s45, s45, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s48, 16
+; SI-NEXT: s_lshl_b32 s46, s65, 16
; SI-NEXT: s_or_b32 s45, s45, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 27
+; SI-NEXT: v_readlane_b32 s46, v33, 29
; SI-NEXT: s_and_b32 s42, s42, 0xffff
; SI-NEXT: s_lshl_b32 s46, s46, 16
-; SI-NEXT: v_readlane_b32 s47, v33, 28
+; SI-NEXT: v_readlane_b32 s47, v33, 30
; SI-NEXT: s_or_b32 s42, s42, s46
; SI-NEXT: s_and_b32 s43, s43, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s51, 16
+; SI-NEXT: s_lshl_b32 s46, s90, 16
; SI-NEXT: s_or_b32 s43, s43, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 29
+; SI-NEXT: v_readlane_b32 s46, v33, 31
; SI-NEXT: s_and_b32 s40, s40, 0xffff
; SI-NEXT: s_lshl_b32 s46, s46, 16
-; SI-NEXT: v_readlane_b32 s47, v33, 30
+; SI-NEXT: v_readlane_b32 s47, v33, 32
; SI-NEXT: s_or_b32 s40, s40, s46
; SI-NEXT: s_and_b32 s41, s41, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s94, 16
+; SI-NEXT: s_lshl_b32 s46, s92, 16
; SI-NEXT: s_or_b32 s41, s41, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 31
+; SI-NEXT: v_readlane_b32 s46, v33, 33
; SI-NEXT: s_and_b32 s14, s14, 0xffff
; SI-NEXT: s_lshl_b32 s46, s46, 16
+; SI-NEXT: v_readlane_b32 s47, v33, 34
; SI-NEXT: s_or_b32 s14, s14, s46
; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s53, 16
+; SI-NEXT: s_lshl_b32 s46, s67, 16
; SI-NEXT: s_or_b32 s15, s15, s46
+; SI-NEXT: v_readlane_b32 s46, v33, 35
; SI-NEXT: s_and_b32 s12, s12, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s50, 16
+; SI-NEXT: s_lshl_b32 s46, s46, 16
+; SI-NEXT: v_readlane_b32 s47, v33, 36
; SI-NEXT: s_or_b32 s12, s12, s46
; SI-NEXT: s_and_b32 s13, s13, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s55, 16
+; SI-NEXT: s_lshl_b32 s46, s83, 16
; SI-NEXT: s_or_b32 s13, s13, s46
+; SI-NEXT: v_readlane_b32 s46, v33, 37
; SI-NEXT: s_and_b32 s10, s10, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s52, 16
+; SI-NEXT: s_lshl_b32 s46, s46, 16
+; SI-NEXT: v_readlane_b32 s47, v33, 38
; SI-NEXT: s_or_b32 s10, s10, s46
; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s65, 16
+; SI-NEXT: s_lshl_b32 s46, s97, 16
; SI-NEXT: s_or_b32 s11, s11, s46
+; SI-NEXT: v_readlane_b32 s46, v33, 39
; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s54, 16
+; SI-NEXT: s_lshl_b32 s46, s46, 16
; SI-NEXT: s_or_b32 s8, s8, s46
; SI-NEXT: s_and_b32 s9, s9, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s67, 16
+; SI-NEXT: s_lshl_b32 s46, s87, 16
; SI-NEXT: s_or_b32 s9, s9, s46
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s46, s64, 16
-; SI-NEXT: v_readlane_b32 s47, v33, 32
; SI-NEXT: s_or_b32 s6, s6, s46
; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s97, 16
+; SI-NEXT: s_lshl_b32 s46, s99, 16
; SI-NEXT: s_or_b32 s7, s7, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 33
; SI-NEXT: s_and_b32 s4, s4, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s46, 16
+; SI-NEXT: s_lshl_b32 s46, s66, 16
; SI-NEXT: s_or_b32 s4, s4, s46
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s46, s98, 16
; SI-NEXT: s_or_b32 s5, s5, s46
; SI-NEXT: v_readlane_b32 s30, v32, 34
-; SI-NEXT: v_readlane_b32 s57, v33, 24
-; SI-NEXT: v_readlane_b32 s47, v33, 34
+; SI-NEXT: v_readlane_b32 s57, v33, 26
+; SI-NEXT: v_readlane_b32 s47, v33, 40
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
@@ -230792,35 +230934,41 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB111_4:
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; implicit-def: $sgpr18
-; SI-NEXT: v_writelane_b32 v33, s4, 23
-; SI-NEXT: v_writelane_b32 v33, s5, 24
+; SI-NEXT: v_writelane_b32 v33, s4, 13
+; SI-NEXT: v_writelane_b32 v33, s5, 14
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $sgpr78
; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr24
; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr28
; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr56
-; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr12
-; SI-NEXT: ; implicit-def: $sgpr50
; SI-NEXT: ; implicit-def: $sgpr10
-; SI-NEXT: ; implicit-def: $sgpr52
; SI-NEXT: ; implicit-def: $sgpr8
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: v_writelane_b32 v33, s4, 15
+; SI-NEXT: v_writelane_b32 v33, s5, 16
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 17
+; SI-NEXT: v_writelane_b32 v33, s5, 18
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 19
+; SI-NEXT: v_writelane_b32 v33, s5, 20
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 21
+; SI-NEXT: v_writelane_b32 v33, s5, 22
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 23
+; SI-NEXT: v_writelane_b32 v33, s5, 24
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: v_writelane_b32 v33, s4, 25
; SI-NEXT: v_writelane_b32 v33, s5, 26
; SI-NEXT: ; implicit-def: $sgpr4
@@ -230832,9 +230980,19 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: v_writelane_b32 v33, s4, 31
; SI-NEXT: v_writelane_b32 v33, s5, 32
-; SI-NEXT: v_writelane_b32 v33, s18, 33
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v33, s19, 34
+; SI-NEXT: v_writelane_b32 v33, s4, 33
+; SI-NEXT: v_writelane_b32 v33, s5, 34
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 35
+; SI-NEXT: v_writelane_b32 v33, s5, 36
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 37
+; SI-NEXT: v_writelane_b32 v33, s5, 38
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 39
+; SI-NEXT: v_writelane_b32 v33, s5, 40
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_branch .LBB111_2
;
; VI-LABEL: bitcast_v64i16_to_v64f16_scalar:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index d43b0226756d5..092528a4feb1e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -69644,338 +69644,346 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_writelane_b32 v43, s34, 0
+; SI-NEXT: v_writelane_b32 v43, s35, 1
+; SI-NEXT: v_writelane_b32 v43, s36, 2
+; SI-NEXT: v_writelane_b32 v43, s37, 3
+; SI-NEXT: v_writelane_b32 v43, s38, 4
+; SI-NEXT: v_writelane_b32 v43, s39, 5
+; SI-NEXT: v_writelane_b32 v43, s48, 6
+; SI-NEXT: v_writelane_b32 v43, s49, 7
+; SI-NEXT: v_writelane_b32 v43, s50, 8
+; SI-NEXT: v_writelane_b32 v43, s51, 9
+; SI-NEXT: v_writelane_b32 v43, s52, 10
+; SI-NEXT: v_writelane_b32 v43, s53, 11
+; SI-NEXT: v_writelane_b32 v43, s54, 12
+; SI-NEXT: v_writelane_b32 v43, s55, 13
+; SI-NEXT: v_writelane_b32 v43, s64, 14
+; SI-NEXT: v_writelane_b32 v43, s65, 15
+; SI-NEXT: v_writelane_b32 v43, s66, 16
+; SI-NEXT: v_writelane_b32 v43, s67, 17
+; SI-NEXT: v_writelane_b32 v43, s68, 18
+; SI-NEXT: v_writelane_b32 v43, s69, 19
+; SI-NEXT: v_writelane_b32 v43, s70, 20
+; SI-NEXT: v_writelane_b32 v43, s71, 21
+; SI-NEXT: v_writelane_b32 v43, s80, 22
+; SI-NEXT: v_writelane_b32 v43, s81, 23
+; SI-NEXT: v_writelane_b32 v43, s82, 24
+; SI-NEXT: v_writelane_b32 v43, s83, 25
+; SI-NEXT: v_writelane_b32 v43, s84, 26
+; SI-NEXT: v_writelane_b32 v43, s85, 27
+; SI-NEXT: v_writelane_b32 v43, s86, 28
+; SI-NEXT: v_writelane_b32 v43, s87, 29
+; SI-NEXT: v_writelane_b32 v43, s96, 30
+; SI-NEXT: v_writelane_b32 v43, s97, 31
+; SI-NEXT: v_writelane_b32 v43, s98, 32
+; SI-NEXT: v_writelane_b32 v43, s99, 33
+; SI-NEXT: v_writelane_b32 v43, s30, 34
+; SI-NEXT: v_writelane_b32 v43, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v40, s34, 0
-; SI-NEXT: v_writelane_b32 v40, s35, 1
-; SI-NEXT: v_writelane_b32 v40, s36, 2
-; SI-NEXT: v_writelane_b32 v40, s37, 3
-; SI-NEXT: v_writelane_b32 v40, s38, 4
-; SI-NEXT: v_writelane_b32 v40, s39, 5
-; SI-NEXT: v_writelane_b32 v40, s48, 6
-; SI-NEXT: v_writelane_b32 v40, s49, 7
-; SI-NEXT: v_writelane_b32 v40, s50, 8
-; SI-NEXT: v_writelane_b32 v40, s51, 9
-; SI-NEXT: v_writelane_b32 v40, s52, 10
-; SI-NEXT: v_writelane_b32 v40, s53, 11
-; SI-NEXT: v_writelane_b32 v40, s54, 12
-; SI-NEXT: v_writelane_b32 v40, s55, 13
-; SI-NEXT: v_writelane_b32 v40, s64, 14
-; SI-NEXT: v_writelane_b32 v40, s65, 15
-; SI-NEXT: v_writelane_b32 v40, s66, 16
-; SI-NEXT: v_writelane_b32 v40, s67, 17
-; SI-NEXT: v_writelane_b32 v40, s68, 18
-; SI-NEXT: v_writelane_b32 v40, s69, 19
-; SI-NEXT: v_writelane_b32 v40, s70, 20
-; SI-NEXT: v_writelane_b32 v40, s71, 21
-; SI-NEXT: v_writelane_b32 v40, s80, 22
-; SI-NEXT: v_writelane_b32 v40, s81, 23
-; SI-NEXT: v_writelane_b32 v40, s82, 24
-; SI-NEXT: v_writelane_b32 v40, s83, 25
-; SI-NEXT: v_writelane_b32 v40, s84, 26
-; SI-NEXT: v_writelane_b32 v40, s85, 27
-; SI-NEXT: v_writelane_b32 v40, s86, 28
-; SI-NEXT: v_writelane_b32 v40, s87, 29
-; SI-NEXT: v_writelane_b32 v40, s96, 30
-; SI-NEXT: v_writelane_b32 v40, s97, 31
-; SI-NEXT: v_writelane_b32 v40, s98, 32
-; SI-NEXT: v_writelane_b32 v40, s99, 33
-; SI-NEXT: v_writelane_b32 v40, s30, 34
-; SI-NEXT: v_writelane_b32 v40, s31, 35
-; SI-NEXT: v_readfirstlane_b32 s79, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76
-; SI-NEXT: s_mov_b32 s31, s16
-; SI-NEXT: v_readfirstlane_b32 s89, v30
-; SI-NEXT: v_readfirstlane_b32 s36, v29
-; SI-NEXT: v_readfirstlane_b32 s94, v27
-; SI-NEXT: v_readfirstlane_b32 s55, v26
-; SI-NEXT: v_readfirstlane_b32 s30, v25
-; SI-NEXT: v_readfirstlane_b32 s16, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
-; SI-NEXT: v_readfirstlane_b32 s95, v23
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v41, s29, 0
-; SI-NEXT: v_writelane_b32 v41, s28, 1
-; SI-NEXT: v_writelane_b32 v41, s23, 2
-; SI-NEXT: v_writelane_b32 v41, s22, 3
-; SI-NEXT: v_writelane_b32 v41, s21, 4
-; SI-NEXT: v_writelane_b32 v41, s20, 5
-; SI-NEXT: v_readfirstlane_b32 s64, v22
-; SI-NEXT: v_readfirstlane_b32 s66, v21
-; SI-NEXT: v_readfirstlane_b32 s81, v20
-; SI-NEXT: v_readfirstlane_b32 s82, v19
-; SI-NEXT: v_readfirstlane_b32 s68, v18
-; SI-NEXT: v_readfirstlane_b32 s39, v17
-; SI-NEXT: v_readfirstlane_b32 s52, v16
-; SI-NEXT: v_readfirstlane_b32 s65, v15
-; SI-NEXT: v_readfirstlane_b32 s48, v14
-; SI-NEXT: v_readfirstlane_b32 s50, v13
-; SI-NEXT: v_readfirstlane_b32 s70, v12
-; SI-NEXT: v_readfirstlane_b32 s71, v11
-; SI-NEXT: v_readfirstlane_b32 s37, v10
-; SI-NEXT: v_readfirstlane_b32 s29, v9
-; SI-NEXT: v_readfirstlane_b32 s93, v8
-; SI-NEXT: v_readfirstlane_b32 s28, v7
-; SI-NEXT: v_readfirstlane_b32 s38, v6
-; SI-NEXT: v_readfirstlane_b32 s49, v5
-; SI-NEXT: v_readfirstlane_b32 s51, v4
-; SI-NEXT: v_readfirstlane_b32 s53, v3
-; SI-NEXT: v_readfirstlane_b32 s67, v2
-; SI-NEXT: v_readfirstlane_b32 s90, v1
-; SI-NEXT: v_readfirstlane_b32 s91, v0
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32
+; SI-NEXT: ; implicit-def: $vgpr44 : SGPR spill to VGPR lane
+; SI-NEXT: v_readfirstlane_b32 s4, v16
+; SI-NEXT: v_writelane_b32 v44, s23, 0
+; SI-NEXT: v_writelane_b32 v44, s22, 1
+; SI-NEXT: v_writelane_b32 v44, s21, 2
+; SI-NEXT: v_writelane_b32 v44, s20, 3
+; SI-NEXT: v_writelane_b32 v44, s4, 4
+; SI-NEXT: s_mov_b32 s82, s29
+; SI-NEXT: s_mov_b32 s85, s25
+; SI-NEXT: s_mov_b32 s29, s24
+; SI-NEXT: s_mov_b32 s44, s16
+; SI-NEXT: v_readfirstlane_b32 s64, v30
+; SI-NEXT: v_readfirstlane_b32 s55, v29
+; SI-NEXT: v_readfirstlane_b32 s66, v28
+; SI-NEXT: v_readfirstlane_b32 s69, v27
+; SI-NEXT: v_readfirstlane_b32 s68, v26
+; SI-NEXT: v_readfirstlane_b32 s39, v25
+; SI-NEXT: v_readfirstlane_b32 s50, v24
+; SI-NEXT: v_readfirstlane_b32 s65, v23
+; SI-NEXT: v_readfirstlane_b32 s51, v22
+; SI-NEXT: v_readfirstlane_b32 s37, v21
+; SI-NEXT: v_readfirstlane_b32 s53, v20
+; SI-NEXT: v_readfirstlane_b32 s88, v19
+; SI-NEXT: v_readfirstlane_b32 s31, v18
+; SI-NEXT: v_readfirstlane_b32 s95, v17
+; SI-NEXT: v_readfirstlane_b32 s48, v15
+; SI-NEXT: v_readfirstlane_b32 s35, v14
+; SI-NEXT: v_readfirstlane_b32 s34, v13
+; SI-NEXT: v_readfirstlane_b32 s52, v12
+; SI-NEXT: v_readfirstlane_b32 s16, v11
+; SI-NEXT: v_readfirstlane_b32 s96, v10
+; SI-NEXT: v_readfirstlane_b32 s20, v9
+; SI-NEXT: v_readfirstlane_b32 s89, v8
+; SI-NEXT: v_readfirstlane_b32 s92, v7
+; SI-NEXT: v_readfirstlane_b32 s91, v6
+; SI-NEXT: v_readfirstlane_b32 s93, v5
+; SI-NEXT: v_readfirstlane_b32 s30, v4
+; SI-NEXT: v_readfirstlane_b32 s38, v3
+; SI-NEXT: v_readfirstlane_b32 s49, v2
+; SI-NEXT: v_readfirstlane_b32 s54, v1
+; SI-NEXT: v_readfirstlane_b32 s90, v0
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s47, v24
-; SI-NEXT: v_readfirstlane_b32 s86, v25
-; SI-NEXT: v_readfirstlane_b32 s58, v26
-; SI-NEXT: v_readfirstlane_b32 s99, v27
-; SI-NEXT: v_readfirstlane_b32 s46, v29
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s56, v32
+; SI-NEXT: v_readfirstlane_b32 s86, v33
+; SI-NEXT: v_readfirstlane_b32 s58, v34
+; SI-NEXT: v_readfirstlane_b32 s99, v35
+; SI-NEXT: v_readfirstlane_b32 s24, v36
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_readfirstlane_b32 s78, v30
+; SI-NEXT: v_readfirstlane_b32 s78, v37
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_readfirstlane_b32 s88, v31
+; SI-NEXT: v_readfirstlane_b32 s25, v38
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s21, v32
+; SI-NEXT: v_readfirstlane_b32 s21, v39
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s98, v33
+; SI-NEXT: v_readfirstlane_b32 s22, v48
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_readfirstlane_b32 s96, v34
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s23, v49
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_readfirstlane_b32 s34, v35
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_readfirstlane_b32 s83, v36
+; SI-NEXT: v_readfirstlane_b32 s87, v50
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_readfirstlane_b32 s20, v37
+; SI-NEXT: v_readfirstlane_b32 s47, v52
+; SI-NEXT: v_readfirstlane_b32 s83, v51
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_readfirstlane_b32 s84, v38
+; SI-NEXT: v_readfirstlane_b32 s84, v53
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_readfirstlane_b32 s44, v39
+; SI-NEXT: v_readfirstlane_b32 s36, v54
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_readfirstlane_b32 s87, v48
+; SI-NEXT: v_readfirstlane_b32 s79, v55
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_readfirstlane_b32 s85, v49
+; SI-NEXT: v_readfirstlane_b32 s71, v40
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_readfirstlane_b32 s69, v50
+; SI-NEXT: v_readfirstlane_b32 s98, v41
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s35, v51
-; SI-NEXT: v_writelane_b32 v41, s47, 6
-; SI-NEXT: v_writelane_b32 v41, s58, 7
+; SI-NEXT: v_readfirstlane_b32 s81, v42
+; SI-NEXT: v_writelane_b32 v44, s47, 5
+; SI-NEXT: v_writelane_b32 v44, s58, 6
; SI-NEXT: s_cbranch_scc0 .LBB99_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: s_and_b32 s4, s31, 0xff
+; SI-NEXT: s_and_b32 s4, s44, 0xff
; SI-NEXT: s_lshl_b32 s5, s17, 8
; SI-NEXT: s_or_b32 s12, s4, s5
; SI-NEXT: s_and_b32 s4, s18, 0xff
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s5, s19, 24
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: s_and_b32 s5, s24, 0xff
-; SI-NEXT: s_lshl_b32 s6, s25, 8
+; SI-NEXT: s_and_b32 s5, s29, 0xff
+; SI-NEXT: s_lshl_b32 s6, s85, 8
; SI-NEXT: s_or_b32 s13, s5, s6
; SI-NEXT: s_and_b32 s5, s26, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s27, 24
; SI-NEXT: s_or_b32 s6, s6, s5
-; SI-NEXT: s_and_b32 s5, s67, 0xff
-; SI-NEXT: s_lshl_b32 s7, s53, 8
+; SI-NEXT: s_and_b32 s5, s49, 0xff
+; SI-NEXT: s_lshl_b32 s7, s38, 8
; SI-NEXT: s_or_b32 s14, s5, s7
-; SI-NEXT: s_and_b32 s5, s51, 0xff
+; SI-NEXT: s_and_b32 s5, s30, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s7, s49, 24
+; SI-NEXT: s_lshl_b32 s7, s93, 24
; SI-NEXT: s_or_b32 s8, s7, s5
-; SI-NEXT: s_and_b32 s5, s37, 0xff
-; SI-NEXT: s_lshl_b32 s7, s71, 8
+; SI-NEXT: s_and_b32 s5, s96, 0xff
+; SI-NEXT: s_lshl_b32 s7, s16, 8
; SI-NEXT: s_or_b32 s15, s5, s7
-; SI-NEXT: s_and_b32 s5, s70, 0xff
+; SI-NEXT: s_and_b32 s5, s52, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s7, s50, 24
+; SI-NEXT: s_lshl_b32 s7, s34, 24
; SI-NEXT: s_or_b32 s10, s7, s5
-; SI-NEXT: s_and_b32 s5, s68, 0xff
-; SI-NEXT: s_lshl_b32 s7, s82, 8
+; SI-NEXT: s_and_b32 s5, s31, 0xff
+; SI-NEXT: s_lshl_b32 s7, s88, 8
; SI-NEXT: s_or_b32 s40, s5, s7
-; SI-NEXT: s_and_b32 s5, s81, 0xff
+; SI-NEXT: s_and_b32 s5, s53, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s7, s66, 24
+; SI-NEXT: s_lshl_b32 s7, s37, 24
; SI-NEXT: s_or_b32 s60, s7, s5
-; SI-NEXT: s_and_b32 s5, s55, 0xff
-; SI-NEXT: s_lshl_b32 s7, s94, 8
+; SI-NEXT: s_and_b32 s5, s68, 0xff
+; SI-NEXT: s_lshl_b32 s7, s69, 8
; SI-NEXT: s_or_b32 s41, s5, s7
-; SI-NEXT: s_and_b32 s5, s79, 0xff
+; SI-NEXT: s_and_b32 s5, s66, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s7, s36, 24
+; SI-NEXT: s_lshl_b32 s7, s55, 24
; SI-NEXT: s_or_b32 s62, s7, s5
-; SI-NEXT: s_and_b32 s5, s87, 0xff
-; SI-NEXT: s_lshl_b32 s7, s44, 8
+; SI-NEXT: s_and_b32 s5, s79, 0xff
+; SI-NEXT: s_lshl_b32 s7, s36, 8
; SI-NEXT: s_or_b32 s42, s5, s7
; SI-NEXT: s_and_b32 s5, s21, 0xff
-; SI-NEXT: s_lshl_b32 s7, s88, 8
+; SI-NEXT: s_lshl_b32 s7, s25, 8
; SI-NEXT: s_or_b32 s43, s5, s7
-; SI-NEXT: v_readlane_b32 s5, v41, 5
-; SI-NEXT: v_readlane_b32 s7, v41, 4
+; SI-NEXT: v_readlane_b32 s5, v44, 3
+; SI-NEXT: v_readlane_b32 s7, v44, 2
; SI-NEXT: s_and_b32 s5, s5, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_or_b32 s5, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v41, 3
+; SI-NEXT: v_readlane_b32 s7, v44, 1
; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: v_readlane_b32 s9, v41, 2
+; SI-NEXT: v_readlane_b32 s9, v44, 0
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_lshl_b32 s9, s9, 24
; SI-NEXT: s_or_b32 s57, s9, s7
-; SI-NEXT: v_readlane_b32 s7, v41, 1
-; SI-NEXT: v_readlane_b32 s9, v41, 0
-; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: s_lshl_b32 s9, s9, 8
+; SI-NEXT: s_and_b32 s7, s28, 0xff
+; SI-NEXT: s_lshl_b32 s9, s82, 8
; SI-NEXT: s_or_b32 s7, s7, s9
-; SI-NEXT: s_and_b32 s9, s91, 0xff
+; SI-NEXT: s_and_b32 s9, s90, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 16
-; SI-NEXT: s_lshl_b32 s11, s90, 24
+; SI-NEXT: s_lshl_b32 s11, s54, 24
; SI-NEXT: s_or_b32 s77, s11, s9
-; SI-NEXT: s_and_b32 s9, s38, 0xff
-; SI-NEXT: s_lshl_b32 s11, s28, 8
+; SI-NEXT: s_and_b32 s9, s91, 0xff
+; SI-NEXT: s_lshl_b32 s11, s92, 8
; SI-NEXT: s_or_b32 s9, s9, s11
-; SI-NEXT: s_and_b32 s11, s93, 0xff
+; SI-NEXT: s_and_b32 s11, s89, 0xff
+; SI-NEXT: s_mov_b32 s72, s44
; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: v_writelane_b32 v41, s44, 12
-; SI-NEXT: s_lshl_b32 s44, s29, 24
+; SI-NEXT: s_lshl_b32 s44, s20, 24
+; SI-NEXT: s_mov_b32 s59, s16
; SI-NEXT: s_or_b32 vcc_lo, s44, s11
-; SI-NEXT: s_and_b32 s11, s48, 0xff
-; SI-NEXT: s_lshl_b32 s44, s65, 8
+; SI-NEXT: s_and_b32 s11, s35, 0xff
+; SI-NEXT: s_lshl_b32 s44, s48, 8
+; SI-NEXT: v_readlane_b32 s16, v44, 4
; SI-NEXT: s_or_b32 s11, s11, s44
-; SI-NEXT: s_and_b32 s44, s52, 0xff
+; SI-NEXT: s_and_b32 s44, s16, 0xff
; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: s_lshl_b32 s45, s39, 24
+; SI-NEXT: s_lshl_b32 s45, s95, 24
; SI-NEXT: s_or_b32 vcc_hi, s45, s44
-; SI-NEXT: s_and_b32 s44, s64, 0xff
-; SI-NEXT: s_lshl_b32 s45, s95, 8
+; SI-NEXT: s_and_b32 s44, s51, 0xff
+; SI-NEXT: s_lshl_b32 s45, s65, 8
; SI-NEXT: s_or_b32 s44, s44, s45
-; SI-NEXT: s_and_b32 s45, s16, 0xff
+; SI-NEXT: s_and_b32 s45, s50, 0xff
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_mov_b32 s59, s46
-; SI-NEXT: s_lshl_b32 s46, s30, 24
-; SI-NEXT: v_writelane_b32 v41, s55, 13
+; SI-NEXT: s_lshl_b32 s46, s39, 24
; SI-NEXT: s_and_b32 s44, s44, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s79, 14
-; SI-NEXT: s_or_b32 s79, s46, s45
-; SI-NEXT: s_or_b32 s61, s44, s79
-; SI-NEXT: s_and_b32 s44, s89, 0xff
-; SI-NEXT: s_lshl_b32 s45, s35, 8
+; SI-NEXT: s_mov_b32 s67, s20
+; SI-NEXT: s_or_b32 s20, s46, s45
+; SI-NEXT: s_or_b32 s61, s44, s20
+; SI-NEXT: s_and_b32 s44, s64, 0xff
+; SI-NEXT: s_lshl_b32 s45, s81, 8
; SI-NEXT: s_or_b32 s44, s44, s45
-; SI-NEXT: s_and_b32 s45, s69, 0xff
+; SI-NEXT: s_and_b32 s45, s98, 0xff
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s85, 24
+; SI-NEXT: s_lshl_b32 s46, s71, 24
; SI-NEXT: s_and_b32 s44, s44, 0xffff
-; SI-NEXT: s_mov_b32 s23, s21
-; SI-NEXT: s_mov_b32 s21, s87
-; SI-NEXT: s_mov_b32 s87, s18
+; SI-NEXT: s_mov_b32 s70, s39
+; SI-NEXT: s_mov_b32 s39, s91
+; SI-NEXT: s_mov_b32 s91, s82
+; SI-NEXT: s_mov_b32 s82, s88
+; SI-NEXT: s_mov_b32 s88, s18
; SI-NEXT: s_or_b32 s18, s46, s45
; SI-NEXT: s_or_b32 s63, s44, s18
; SI-NEXT: s_and_b32 s44, s83, 0xff
-; SI-NEXT: s_lshl_b32 s45, s34, 8
+; SI-NEXT: s_lshl_b32 s45, s87, 8
; SI-NEXT: s_or_b32 s44, s44, s45
-; SI-NEXT: s_and_b32 s45, s96, 0xff
+; SI-NEXT: s_and_b32 s45, s23, 0xff
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s98, 24
-; SI-NEXT: s_mov_b32 s56, s83
-; SI-NEXT: s_mov_b32 s83, s64
-; SI-NEXT: s_mov_b32 s64, s39
-; SI-NEXT: s_mov_b32 s39, s91
-; SI-NEXT: s_mov_b32 s91, s19
+; SI-NEXT: s_lshl_b32 s46, s22, 24
+; SI-NEXT: s_mov_b32 s80, s31
+; SI-NEXT: s_mov_b32 s31, s53
+; SI-NEXT: s_mov_b32 s53, s38
+; SI-NEXT: s_mov_b32 s38, s90
+; SI-NEXT: s_mov_b32 s90, s19
; SI-NEXT: s_or_b32 s19, s46, s45
; SI-NEXT: s_and_b32 s45, s84, 0xff
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s20, 24
+; SI-NEXT: s_lshl_b32 s46, s47, 24
; SI-NEXT: s_and_b32 s44, s44, 0xffff
+; SI-NEXT: s_mov_b32 s97, s22
+; SI-NEXT: s_mov_b32 s22, s55
+; SI-NEXT: s_mov_b32 s55, s49
+; SI-NEXT: s_mov_b32 s49, s92
+; SI-NEXT: s_mov_b32 s92, s72
; SI-NEXT: s_or_b32 s72, s46, s45
; SI-NEXT: s_or_b32 s73, s44, s19
; SI-NEXT: s_and_b32 s44, s99, 0xff
; SI-NEXT: s_lshl_b32 s45, s58, 8
; SI-NEXT: s_or_b32 s44, s44, s45
; SI-NEXT: s_and_b32 s45, s86, 0xff
-; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s47, 24
; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_mov_b32 s76, s20
-; SI-NEXT: s_mov_b32 s20, s84
-; SI-NEXT: s_mov_b32 s84, s81
-; SI-NEXT: s_mov_b32 s81, s70
-; SI-NEXT: s_mov_b32 s70, s65
-; SI-NEXT: s_mov_b32 s65, s49
-; SI-NEXT: s_mov_b32 s49, s90
-; SI-NEXT: s_mov_b32 s90, s17
-; SI-NEXT: s_or_b32 s17, s46, s45
-; SI-NEXT: s_and_b32 s45, s78, 0xff
-; SI-NEXT: s_or_b32 s5, s5, s57
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s59, 24
+; SI-NEXT: s_lshl_b32 s46, s56, 24
+; SI-NEXT: s_or_b32 s5, s5, s57
+; SI-NEXT: s_mov_b32 s76, s56
+; SI-NEXT: s_mov_b32 s56, s86
+; SI-NEXT: s_mov_b32 s86, s81
+; SI-NEXT: s_mov_b32 s81, s65
+; SI-NEXT: s_mov_b32 s65, s48
+; SI-NEXT: s_mov_b32 s48, s89
+; SI-NEXT: s_mov_b32 s89, s17
+; SI-NEXT: s_or_b32 s17, s46, s45
; SI-NEXT: s_and_b32 s44, s44, 0xffff
; SI-NEXT: s_and_b32 s12, s12, 0xffff
-; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_or_b32 s74, s46, s45
+; SI-NEXT: s_and_b32 s9, s9, 0xffff
+; SI-NEXT: v_writelane_b32 v44, s68, 11
+; SI-NEXT: s_mov_b32 s94, s51
+; SI-NEXT: s_mov_b32 s51, s95
+; SI-NEXT: s_mov_b32 s95, s27
; SI-NEXT: s_or_b32 s75, s44, s17
-; SI-NEXT: s_mov_b32 s46, s28
+; SI-NEXT: s_mov_b32 s44, s93
+; SI-NEXT: s_mov_b32 s93, s28
; SI-NEXT: s_and_b32 s28, s42, 0xffff
-; SI-NEXT: s_mov_b32 s44, s30
-; SI-NEXT: s_mov_b32 s30, s26
-; SI-NEXT: s_and_b32 s26, s43, 0xffff
+; SI-NEXT: s_and_b32 s27, s43, 0xffff
; SI-NEXT: s_or_b32 s42, s12, s4
; SI-NEXT: s_mov_b32 s43, s5
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
-; SI-NEXT: s_or_b32 s7, s7, s77
-; SI-NEXT: v_writelane_b32 v41, s4, 8
-; SI-NEXT: s_and_b32 s9, s9, 0xffff
-; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s5, 9
-; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
; SI-NEXT: s_or_b32 s9, s9, vcc_lo
+; SI-NEXT: s_and_b32 s45, s78, 0xff
+; SI-NEXT: v_writelane_b32 v44, s4, 7
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_and_b32 s11, s11, 0xffff
+; SI-NEXT: s_lshl_b32 s45, s45, 16
+; SI-NEXT: s_lshl_b32 s46, s24, 24
+; SI-NEXT: v_writelane_b32 v44, s5, 8
+; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 16
+; SI-NEXT: s_or_b32 s7, s7, s77
; SI-NEXT: s_or_b32 s11, s11, vcc_hi
-; SI-NEXT: s_mov_b32 s92, s16
-; SI-NEXT: s_mov_b32 s97, s48
-; SI-NEXT: s_mov_b32 s48, s29
+; SI-NEXT: s_mov_b32 s68, s34
+; SI-NEXT: s_or_b32 s74, s46, s45
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_and_b32 s14, s14, 0xffff
; SI-NEXT: s_and_b32 s58, s15, 0xffff
; SI-NEXT: s_and_b32 s16, s40, 0xffff
+; SI-NEXT: s_mov_b32 s34, s29
; SI-NEXT: s_and_b32 s29, s41, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s4, 10
-; SI-NEXT: s_mov_b32 s22, s51
-; SI-NEXT: s_mov_b32 s51, s93
-; SI-NEXT: s_mov_b32 s45, s99
-; SI-NEXT: s_mov_b32 s99, s96
-; SI-NEXT: s_mov_b32 s96, s82
-; SI-NEXT: s_mov_b32 s82, s95
-; SI-NEXT: s_mov_b32 s95, s94
-; SI-NEXT: s_mov_b32 s94, s92
+; SI-NEXT: v_writelane_b32 v44, s4, 9
+; SI-NEXT: s_mov_b32 s45, s78
+; SI-NEXT: s_mov_b32 s78, s84
+; SI-NEXT: s_mov_b32 s84, s69
+; SI-NEXT: s_mov_b32 s69, s59
; SI-NEXT: s_or_b32 s40, s13, s6
; SI-NEXT: s_mov_b32 s41, s7
-; SI-NEXT: v_writelane_b32 v41, s5, 11
+; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16
; SI-NEXT: s_or_b32 s14, s14, s8
; SI-NEXT: s_mov_b32 s15, s9
-; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
+; SI-NEXT: v_writelane_b32 v44, s5, 10
; SI-NEXT: s_or_b32 s12, s58, s10
; SI-NEXT: s_mov_b32 s13, s11
-; SI-NEXT: s_lshr_b64 s[92:93], s[10:11], 16
+; SI-NEXT: s_lshr_b64 s[58:59], s[10:11], 16
; SI-NEXT: s_or_b32 s10, s16, s60
; SI-NEXT: s_mov_b32 s11, s61
; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
@@ -69985,67 +69993,69 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_or_b32 s6, s28, s72
; SI-NEXT: s_mov_b32 s7, s73
; SI-NEXT: s_lshr_b64 s[72:73], s[72:73], 16
-; SI-NEXT: s_or_b32 s4, s26, s74
+; SI-NEXT: s_or_b32 s4, s27, s74
; SI-NEXT: s_mov_b32 s5, s75
; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16
-; SI-NEXT: s_mov_b32 s16, s94
-; SI-NEXT: s_mov_b32 s94, s95
-; SI-NEXT: s_mov_b32 s95, s82
-; SI-NEXT: s_mov_b32 s82, s96
-; SI-NEXT: s_mov_b32 s96, s99
-; SI-NEXT: s_mov_b32 s99, s45
-; SI-NEXT: s_mov_b32 s28, s46
-; SI-NEXT: s_mov_b32 s46, s59
-; SI-NEXT: s_mov_b32 s26, s30
-; SI-NEXT: s_mov_b32 s30, s44
-; SI-NEXT: v_readlane_b32 s44, v41, 12
+; SI-NEXT: s_mov_b32 s29, s34
+; SI-NEXT: s_mov_b32 s16, s69
+; SI-NEXT: s_mov_b32 s69, s84
+; SI-NEXT: s_mov_b32 s84, s78
+; SI-NEXT: s_mov_b32 s78, s45
+; SI-NEXT: s_mov_b32 s28, s93
+; SI-NEXT: s_mov_b32 s93, s44
; SI-NEXT: s_lshr_b32 s47, s57, 16
; SI-NEXT: s_lshr_b32 s57, s77, 16
; SI-NEXT: s_lshr_b32 s59, vcc_lo, 16
; SI-NEXT: s_lshr_b32 s61, vcc_hi, 16
-; SI-NEXT: s_lshr_b32 s63, s79, 16
-; SI-NEXT: v_readlane_b32 s79, v41, 14
-; SI-NEXT: v_readlane_b32 s55, v41, 13
+; SI-NEXT: s_lshr_b32 s63, s20, 16
+; SI-NEXT: s_mov_b32 s20, s67
+; SI-NEXT: s_mov_b32 s34, s68
+; SI-NEXT: v_readlane_b32 s68, v44, 11
; SI-NEXT: s_lshr_b32 s73, s18, 16
-; SI-NEXT: s_mov_b32 s18, s87
-; SI-NEXT: s_mov_b32 s29, s48
-; SI-NEXT: s_mov_b32 s48, s97
-; SI-NEXT: s_mov_b32 s87, s21
-; SI-NEXT: s_mov_b32 s21, s23
-; SI-NEXT: s_mov_b32 s93, s51
-; SI-NEXT: s_mov_b32 s51, s22
-; SI-NEXT: s_lshr_b32 s75, s19, 16
-; SI-NEXT: s_mov_b32 s19, s91
+; SI-NEXT: s_mov_b32 s18, s88
+; SI-NEXT: s_mov_b32 s27, s95
+; SI-NEXT: s_mov_b32 s95, s51
+; SI-NEXT: s_mov_b32 s51, s94
+; SI-NEXT: s_mov_b32 s88, s82
+; SI-NEXT: s_mov_b32 s82, s91
; SI-NEXT: s_mov_b32 s91, s39
-; SI-NEXT: s_mov_b32 s39, s64
-; SI-NEXT: s_mov_b32 s64, s83
-; SI-NEXT: s_mov_b32 s83, s56
+; SI-NEXT: s_mov_b32 s39, s70
+; SI-NEXT: s_lshr_b32 s75, s19, 16
+; SI-NEXT: s_mov_b32 s19, s90
+; SI-NEXT: s_mov_b32 s90, s38
+; SI-NEXT: s_mov_b32 s38, s53
+; SI-NEXT: s_mov_b32 s53, s31
+; SI-NEXT: s_mov_b32 s44, s92
+; SI-NEXT: s_mov_b32 s92, s49
+; SI-NEXT: s_mov_b32 s49, s55
+; SI-NEXT: s_mov_b32 s55, s22
+; SI-NEXT: s_mov_b32 s31, s80
+; SI-NEXT: s_mov_b32 s22, s97
; SI-NEXT: s_lshr_b32 s45, s17, 16
-; SI-NEXT: s_mov_b32 s17, s90
-; SI-NEXT: s_mov_b32 s90, s49
-; SI-NEXT: s_mov_b32 s49, s65
-; SI-NEXT: s_mov_b32 s65, s70
-; SI-NEXT: s_mov_b32 s70, s81
-; SI-NEXT: s_mov_b32 s81, s84
-; SI-NEXT: s_mov_b32 s84, s20
-; SI-NEXT: s_mov_b32 s20, s76
+; SI-NEXT: s_mov_b32 s17, s89
+; SI-NEXT: s_mov_b32 s89, s48
+; SI-NEXT: s_mov_b32 s48, s65
+; SI-NEXT: s_mov_b32 s65, s81
+; SI-NEXT: s_mov_b32 s81, s86
+; SI-NEXT: s_mov_b32 s86, s56
+; SI-NEXT: s_mov_b32 s56, s76
; SI-NEXT: s_mov_b64 s[76:77], 0
; SI-NEXT: s_branch .LBB99_3
; SI-NEXT: .LBB99_2:
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_mov_b64 s[76:77], -1
-; SI-NEXT: v_writelane_b32 v41, s4, 8
-; SI-NEXT: v_writelane_b32 v41, s5, 9
+; SI-NEXT: v_writelane_b32 v44, s4, 7
+; SI-NEXT: v_writelane_b32 v44, s5, 8
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr47
; SI-NEXT: ; implicit-def: $sgpr40
+; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr57
; SI-NEXT: ; implicit-def: $sgpr14
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; implicit-def: $sgpr59
; SI-NEXT: ; implicit-def: $sgpr12
-; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr61
; SI-NEXT: ; implicit-def: $sgpr10
; SI-NEXT: ; implicit-def: $sgpr60
@@ -70058,218 +70068,213 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: ; implicit-def: $sgpr75
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr45
-; SI-NEXT: v_writelane_b32 v41, s4, 10
-; SI-NEXT: v_writelane_b32 v41, s5, 11
+; SI-NEXT: v_writelane_b32 v44, s4, 9
+; SI-NEXT: v_writelane_b32 v44, s5, 10
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB99_3: ; %Flow
; SI-NEXT: s_andn2_b64 vcc, exec, s[76:77]
-; SI-NEXT: v_readlane_b32 s76, v41, 8
-; SI-NEXT: v_readlane_b32 s77, v41, 9
-; SI-NEXT: s_mov_b32 s22, s76
-; SI-NEXT: v_readlane_b32 s76, v41, 10
-; SI-NEXT: s_mov_b32 s56, s76
-; SI-NEXT: v_readlane_b32 s77, v41, 11
+; SI-NEXT: v_readlane_b32 s76, v44, 7
+; SI-NEXT: v_readlane_b32 s77, v44, 8
; SI-NEXT: s_cbranch_vccnz .LBB99_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_and_b32 s4, s21, 0xff
-; SI-NEXT: s_lshl_b32 s5, s88, 8
+; SI-NEXT: s_lshl_b32 s5, s25, 8
; SI-NEXT: s_add_i32 s78, s78, 3
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_and_b32 s6, s78, 0xff
; SI-NEXT: s_addk_i32 s4, 0x300
-; SI-NEXT: s_lshl_b32 s5, s46, 24
+; SI-NEXT: s_lshl_b32 s5, s24, 24
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_add_i32 s99, s99, 3
-; SI-NEXT: v_readlane_b32 s6, v41, 7
+; SI-NEXT: v_readlane_b32 s6, v44, 6
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_and_b32 s5, s99, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 8
; SI-NEXT: s_add_i32 s86, s86, 3
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_readlane_b32 s6, v41, 6
; SI-NEXT: s_and_b32 s7, s86, 0xff
; SI-NEXT: s_addk_i32 s5, 0x300
-; SI-NEXT: s_lshl_b32 s6, s6, 24
+; SI-NEXT: s_lshl_b32 s6, s56, 24
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: s_add_i32 s97, s87, 3
+; SI-NEXT: s_add_i32 s97, s79, 3
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: s_and_b32 s6, s97, 0xff
-; SI-NEXT: s_lshl_b32 s7, s44, 8
+; SI-NEXT: s_lshl_b32 s7, s36, 8
; SI-NEXT: s_add_i32 s84, s84, 3
; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: v_readlane_b32 s7, v44, 5
; SI-NEXT: s_and_b32 s8, s84, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
-; SI-NEXT: s_lshl_b32 s7, s20, 24
+; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s7, s7, s8
; SI-NEXT: s_add_i32 s83, s83, 3
; SI-NEXT: s_or_b32 s6, s7, s6
; SI-NEXT: s_and_b32 s7, s83, 0xff
-; SI-NEXT: s_lshl_b32 s8, s34, 8
-; SI-NEXT: s_add_i32 s80, s96, 3
+; SI-NEXT: s_lshl_b32 s8, s87, 8
+; SI-NEXT: s_add_i32 s80, s23, 3
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: s_and_b32 s9, s80, 0xff
; SI-NEXT: s_addk_i32 s7, 0x300
-; SI-NEXT: s_lshl_b32 s8, s98, 24
+; SI-NEXT: s_lshl_b32 s8, s22, 24
; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s8, s8, s9
-; SI-NEXT: s_add_i32 s55, s55, 3
+; SI-NEXT: s_add_i32 s68, s68, 3
; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: s_and_b32 s8, s55, 0xff
-; SI-NEXT: s_lshl_b32 s9, s94, 8
-; SI-NEXT: s_add_i32 s88, s79, 3
+; SI-NEXT: s_and_b32 s8, s68, 0xff
+; SI-NEXT: s_lshl_b32 s9, s69, 8
+; SI-NEXT: s_add_i32 s66, s66, 3
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: s_and_b32 s10, s88, 0xff
+; SI-NEXT: s_and_b32 s10, s66, 0xff
; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_lshl_b32 s9, s36, 24
+; SI-NEXT: s_lshl_b32 s9, s55, 24
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_or_b32 s9, s9, s10
-; SI-NEXT: s_add_i32 s20, s89, 3
+; SI-NEXT: s_add_i32 s64, s64, 3
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: s_and_b32 s9, s20, 0xff
-; SI-NEXT: s_lshl_b32 s10, s35, 8
-; SI-NEXT: s_add_i32 s69, s69, 3
+; SI-NEXT: s_and_b32 s9, s64, 0xff
+; SI-NEXT: s_lshl_b32 s10, s81, 8
+; SI-NEXT: s_add_i32 s69, s98, 3
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: s_and_b32 s11, s69, 0xff
; SI-NEXT: s_addk_i32 s9, 0x300
-; SI-NEXT: s_lshl_b32 s10, s85, 24
+; SI-NEXT: s_lshl_b32 s10, s71, 24
; SI-NEXT: s_lshl_b32 s11, s11, 16
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: s_add_i32 s68, s68, 3
+; SI-NEXT: s_add_i32 s55, s31, 3
; SI-NEXT: s_or_b32 s9, s10, s9
-; SI-NEXT: s_and_b32 s10, s68, 0xff
-; SI-NEXT: s_lshl_b32 s11, s82, 8
+; SI-NEXT: s_and_b32 s10, s55, 0xff
+; SI-NEXT: s_lshl_b32 s11, s88, 8
+; SI-NEXT: s_add_i32 s53, s53, 3
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: s_lshl_b32 s11, s66, 24
-; SI-NEXT: s_add_i32 s66, s81, 3
-; SI-NEXT: s_and_b32 s12, s66, 0xff
+; SI-NEXT: s_and_b32 s12, s53, 0xff
; SI-NEXT: s_addk_i32 s10, 0x300
+; SI-NEXT: s_lshl_b32 s11, s37, 24
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_or_b32 s11, s11, s12
-; SI-NEXT: s_add_i32 s64, s64, 3
+; SI-NEXT: s_add_i32 s51, s51, 3
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: s_and_b32 s11, s64, 0xff
-; SI-NEXT: s_lshl_b32 s12, s95, 8
-; SI-NEXT: s_add_i32 s94, s16, 3
+; SI-NEXT: s_and_b32 s11, s51, 0xff
+; SI-NEXT: s_lshl_b32 s12, s65, 8
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: s_and_b32 s13, s94, 0xff
+; SI-NEXT: s_lshl_b32 s12, s39, 24
+; SI-NEXT: s_add_i32 s39, s50, 3
+; SI-NEXT: s_and_b32 s13, s39, 0xff
; SI-NEXT: s_addk_i32 s11, 0x300
-; SI-NEXT: s_lshl_b32 s12, s30, 24
; SI-NEXT: s_lshl_b32 s13, s13, 16
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_or_b32 s12, s12, s13
-; SI-NEXT: s_add_i32 s54, s37, 3
+; SI-NEXT: s_add_i32 s50, s96, 3
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: s_and_b32 s12, s54, 0xff
-; SI-NEXT: s_lshl_b32 s13, s71, 8
+; SI-NEXT: s_and_b32 s12, s50, 0xff
+; SI-NEXT: s_lshl_b32 s13, s16, 8
+; SI-NEXT: s_add_i32 s37, s52, 3
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: s_lshl_b32 s13, s50, 24
-; SI-NEXT: s_add_i32 s50, s70, 3
-; SI-NEXT: s_and_b32 s14, s50, 0xff
+; SI-NEXT: s_and_b32 s14, s37, 0xff
; SI-NEXT: s_addk_i32 s12, 0x300
+; SI-NEXT: s_lshl_b32 s13, s34, 24
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_or_b32 s13, s13, s14
-; SI-NEXT: s_add_i32 s48, s48, 3
+; SI-NEXT: s_add_i32 s35, s35, 3
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: s_and_b32 s13, s48, 0xff
-; SI-NEXT: s_lshl_b32 s14, s65, 8
-; SI-NEXT: s_add_i32 s36, s52, 3
+; SI-NEXT: s_and_b32 s13, s35, 0xff
+; SI-NEXT: s_lshl_b32 s14, s48, 8
+; SI-NEXT: v_readlane_b32 s15, v44, 4
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: s_and_b32 s15, s36, 0xff
+; SI-NEXT: s_lshl_b32 s14, s95, 24
+; SI-NEXT: s_add_i32 s95, s15, 3
+; SI-NEXT: s_and_b32 s15, s95, 0xff
; SI-NEXT: s_addk_i32 s13, 0x300
-; SI-NEXT: s_lshl_b32 s14, s39, 24
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_or_b32 s14, s14, s15
-; SI-NEXT: s_add_i32 s39, s67, 3
+; SI-NEXT: s_add_i32 s34, s49, 3
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: s_and_b32 s14, s39, 0xff
-; SI-NEXT: s_lshl_b32 s15, s53, 8
-; SI-NEXT: s_add_i32 s34, s51, 3
+; SI-NEXT: s_and_b32 s14, s34, 0xff
+; SI-NEXT: s_lshl_b32 s15, s38, 8
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: s_and_b32 s20, s34, 0xff
+; SI-NEXT: s_lshl_b32 s15, s93, 24
+; SI-NEXT: s_add_i32 s93, s30, 3
+; SI-NEXT: s_and_b32 s21, s93, 0xff
; SI-NEXT: s_addk_i32 s14, 0x300
-; SI-NEXT: s_lshl_b32 s15, s49, 24
-; SI-NEXT: s_lshl_b32 s20, s20, 16
+; SI-NEXT: s_lshl_b32 s21, s21, 16
; SI-NEXT: s_and_b32 s14, s14, 0xffff
-; SI-NEXT: s_or_b32 s15, s15, s20
-; SI-NEXT: s_add_i32 s30, s38, 3
+; SI-NEXT: s_or_b32 s15, s15, s21
+; SI-NEXT: s_add_i32 s91, s91, 3
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: s_and_b32 s15, s30, 0xff
-; SI-NEXT: s_lshl_b32 s20, s28, 8
-; SI-NEXT: s_add_i32 s92, s93, 3
-; SI-NEXT: s_or_b32 s15, s20, s15
-; SI-NEXT: s_and_b32 s21, s92, 0xff
+; SI-NEXT: s_and_b32 s15, s91, 0xff
+; SI-NEXT: s_lshl_b32 s21, s92, 8
+; SI-NEXT: s_add_i32 s89, s89, 3
+; SI-NEXT: s_or_b32 s15, s21, s15
+; SI-NEXT: s_and_b32 s22, s89, 0xff
; SI-NEXT: s_addk_i32 s15, 0x300
-; SI-NEXT: s_lshl_b32 s20, s29, 24
-; SI-NEXT: s_lshl_b32 s21, s21, 16
+; SI-NEXT: s_lshl_b32 s21, s20, 24
+; SI-NEXT: s_lshl_b32 s22, s22, 16
+; SI-NEXT: s_add_i32 s16, s44, 3
; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_or_b32 s20, s20, s21
-; SI-NEXT: s_add_i32 s24, s24, 3
-; SI-NEXT: s_or_b32 s15, s20, s15
-; SI-NEXT: s_and_b32 s20, s24, 0xff
-; SI-NEXT: s_lshl_b32 s21, s25, 8
-; SI-NEXT: s_add_i32 s26, s26, 3
-; SI-NEXT: s_or_b32 s20, s21, s20
-; SI-NEXT: s_and_b32 s24, s26, 0xff
-; SI-NEXT: s_add_i32 s16, s31, 3
-; SI-NEXT: s_addk_i32 s20, 0x300
-; SI-NEXT: s_lshl_b32 s21, s27, 24
-; SI-NEXT: s_lshl_b32 s24, s24, 16
+; SI-NEXT: s_or_b32 s21, s21, s22
+; SI-NEXT: s_add_i32 s24, s29, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_and_b32 s20, s20, 0xffff
-; SI-NEXT: s_or_b32 s21, s21, s24
+; SI-NEXT: s_or_b32 s15, s21, s15
+; SI-NEXT: s_and_b32 s21, s24, 0xff
+; SI-NEXT: s_lshl_b32 s22, s85, 8
+; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_or_b32 s20, s21, s20
+; SI-NEXT: s_or_b32 s21, s22, s21
+; SI-NEXT: s_and_b32 s20, s26, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s19, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_add_i32 s40, s20, 0x3000000
-; SI-NEXT: v_readlane_b32 s20, v41, 1
+; SI-NEXT: s_addk_i32 s21, 0x300
+; SI-NEXT: s_lshl_b32 s22, s27, 24
+; SI-NEXT: s_lshl_b32 s20, s20, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_add_i32 s28, s20, 3
-; SI-NEXT: v_readlane_b32 s21, v41, 0
+; SI-NEXT: s_and_b32 s21, s21, 0xffff
+; SI-NEXT: s_or_b32 s22, s22, s20
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s20, s28, 0xff
-; SI-NEXT: s_lshl_b32 s21, s21, 8
+; SI-NEXT: s_or_b32 s21, s22, s21
+; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s42, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v41, 5
-; SI-NEXT: s_or_b32 s20, s21, s20
-; SI-NEXT: s_lshl_b32 s21, s90, 24
-; SI-NEXT: s_add_i32 s90, s91, 3
+; SI-NEXT: v_readlane_b32 s16, v44, 3
+; SI-NEXT: s_add_i32 s40, s21, 0x3000000
+; SI-NEXT: s_and_b32 s21, s28, 0xff
+; SI-NEXT: s_lshl_b32 s22, s82, 8
+; SI-NEXT: s_add_i32 s79, s90, 3
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v41, 4
-; SI-NEXT: v_readlane_b32 s18, v41, 3
-; SI-NEXT: s_and_b32 s24, s90, 0xff
+; SI-NEXT: v_readlane_b32 s17, v44, 2
+; SI-NEXT: v_readlane_b32 s18, v44, 1
+; SI-NEXT: s_or_b32 s21, s22, s21
+; SI-NEXT: s_and_b32 s22, s79, 0xff
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_addk_i32 s20, 0x300
-; SI-NEXT: s_lshl_b32 s24, s24, 16
+; SI-NEXT: s_addk_i32 s21, 0x300
+; SI-NEXT: s_lshl_b32 s20, s54, 24
+; SI-NEXT: s_lshl_b32 s22, s22, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v41, 2
+; SI-NEXT: v_readlane_b32 s17, v44, 0
; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_and_b32 s20, s20, 0xffff
-; SI-NEXT: s_or_b32 s21, s21, s24
+; SI-NEXT: s_and_b32 s21, s21, 0xffff
+; SI-NEXT: s_or_b32 s20, s20, s22
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_or_b32 s20, s21, s20
+; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
@@ -70280,21 +70285,22 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_add_i32 s9, s9, 0x3000000
; SI-NEXT: s_add_i32 s10, s10, 0x3000000
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
-; SI-NEXT: s_add_i32 s41, s20, 0x3000000
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
; SI-NEXT: s_add_i32 s13, s13, 0x3000000
; SI-NEXT: s_add_i32 s14, s14, 0x3000000
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
+; SI-NEXT: s_add_i32 s41, s20, 0x3000000
+; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s43, s16, 0x3000000
-; SI-NEXT: s_lshr_b64 s[56:57], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
+; SI-NEXT: s_lshr_b64 s[58:59], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[22:23], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[54:55], s[14:15], 16
-; SI-NEXT: s_lshr_b64 s[92:93], s[12:13], 16
+; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v44, s16, 9
; SI-NEXT: s_lshr_b32 s47, s43, 16
; SI-NEXT: s_lshr_b32 s57, s41, 16
; SI-NEXT: s_lshr_b32 s59, s15, 16
@@ -70303,27 +70309,32 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_lshr_b32 s73, s9, 16
; SI-NEXT: s_lshr_b32 s75, s7, 16
; SI-NEXT: s_lshr_b32 s45, s5, 16
+; SI-NEXT: v_writelane_b32 v44, s17, 10
; SI-NEXT: .LBB99_5: ; %end
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s16, s42, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s22, 16
+; SI-NEXT: s_lshl_b32 s17, s76, 16
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s43, 0xffff
; SI-NEXT: s_lshl_b32 s18, s47, 16
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s40, 0xffff
-; SI-NEXT: s_lshl_b32 s19, s56, 16
+; SI-NEXT: s_lshl_b32 s19, s46, 16
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s41, 0xffff
; SI-NEXT: s_lshl_b32 s20, s57, 16
; SI-NEXT: s_or_b32 s19, s19, s20
+; SI-NEXT: v_readlane_b32 s20, v44, 9
; SI-NEXT: s_and_b32 s14, s14, 0xffff
-; SI-NEXT: s_lshl_b32 s20, s54, 16
+; SI-NEXT: s_lshl_b32 s20, s20, 16
; SI-NEXT: s_or_b32 s14, s14, s20
; SI-NEXT: s_and_b32 s15, s15, 0xffff
; SI-NEXT: s_lshl_b32 s20, s59, 16
; SI-NEXT: s_or_b32 s15, s15, s20
; SI-NEXT: s_and_b32 s12, s12, 0xffff
-; SI-NEXT: s_lshl_b32 s20, s92, 16
+; SI-NEXT: s_lshl_b32 s20, s58, 16
; SI-NEXT: s_or_b32 s12, s12, s20
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_lshl_b32 s20, s61, 16
@@ -70352,7 +70363,8 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s20, s45, 16
; SI-NEXT: s_or_b32 s5, s5, s20
-; SI-NEXT: v_readlane_b32 s30, v40, 34
+; SI-NEXT: v_readlane_b32 s30, v43, 34
+; SI-NEXT: v_readlane_b32 s21, v44, 10
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
@@ -70369,44 +70381,44 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: v_mov_b32_e32 v13, s7
; SI-NEXT: v_mov_b32_e32 v14, s4
; SI-NEXT: v_mov_b32_e32 v15, s5
-; SI-NEXT: v_readlane_b32 s31, v40, 35
-; SI-NEXT: v_readlane_b32 s99, v40, 33
-; SI-NEXT: v_readlane_b32 s98, v40, 32
-; SI-NEXT: v_readlane_b32 s97, v40, 31
-; SI-NEXT: v_readlane_b32 s96, v40, 30
-; SI-NEXT: v_readlane_b32 s87, v40, 29
-; SI-NEXT: v_readlane_b32 s86, v40, 28
-; SI-NEXT: v_readlane_b32 s85, v40, 27
-; SI-NEXT: v_readlane_b32 s84, v40, 26
-; SI-NEXT: v_readlane_b32 s83, v40, 25
-; SI-NEXT: v_readlane_b32 s82, v40, 24
-; SI-NEXT: v_readlane_b32 s81, v40, 23
-; SI-NEXT: v_readlane_b32 s80, v40, 22
-; SI-NEXT: v_readlane_b32 s71, v40, 21
-; SI-NEXT: v_readlane_b32 s70, v40, 20
-; SI-NEXT: v_readlane_b32 s69, v40, 19
-; SI-NEXT: v_readlane_b32 s68, v40, 18
-; SI-NEXT: v_readlane_b32 s67, v40, 17
-; SI-NEXT: v_readlane_b32 s66, v40, 16
-; SI-NEXT: v_readlane_b32 s65, v40, 15
-; SI-NEXT: v_readlane_b32 s64, v40, 14
-; SI-NEXT: v_readlane_b32 s55, v40, 13
-; SI-NEXT: v_readlane_b32 s54, v40, 12
-; SI-NEXT: v_readlane_b32 s53, v40, 11
-; SI-NEXT: v_readlane_b32 s52, v40, 10
-; SI-NEXT: v_readlane_b32 s51, v40, 9
-; SI-NEXT: v_readlane_b32 s50, v40, 8
-; SI-NEXT: v_readlane_b32 s49, v40, 7
-; SI-NEXT: v_readlane_b32 s48, v40, 6
-; SI-NEXT: v_readlane_b32 s39, v40, 5
-; SI-NEXT: v_readlane_b32 s38, v40, 4
-; SI-NEXT: v_readlane_b32 s37, v40, 3
-; SI-NEXT: v_readlane_b32 s36, v40, 2
-; SI-NEXT: v_readlane_b32 s35, v40, 1
-; SI-NEXT: v_readlane_b32 s34, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v43, 35
+; SI-NEXT: v_readlane_b32 s99, v43, 33
+; SI-NEXT: v_readlane_b32 s98, v43, 32
+; SI-NEXT: v_readlane_b32 s97, v43, 31
+; SI-NEXT: v_readlane_b32 s96, v43, 30
+; SI-NEXT: v_readlane_b32 s87, v43, 29
+; SI-NEXT: v_readlane_b32 s86, v43, 28
+; SI-NEXT: v_readlane_b32 s85, v43, 27
+; SI-NEXT: v_readlane_b32 s84, v43, 26
+; SI-NEXT: v_readlane_b32 s83, v43, 25
+; SI-NEXT: v_readlane_b32 s82, v43, 24
+; SI-NEXT: v_readlane_b32 s81, v43, 23
+; SI-NEXT: v_readlane_b32 s80, v43, 22
+; SI-NEXT: v_readlane_b32 s71, v43, 21
+; SI-NEXT: v_readlane_b32 s70, v43, 20
+; SI-NEXT: v_readlane_b32 s69, v43, 19
+; SI-NEXT: v_readlane_b32 s68, v43, 18
+; SI-NEXT: v_readlane_b32 s67, v43, 17
+; SI-NEXT: v_readlane_b32 s66, v43, 16
+; SI-NEXT: v_readlane_b32 s65, v43, 15
+; SI-NEXT: v_readlane_b32 s64, v43, 14
+; SI-NEXT: v_readlane_b32 s55, v43, 13
+; SI-NEXT: v_readlane_b32 s54, v43, 12
+; SI-NEXT: v_readlane_b32 s53, v43, 11
+; SI-NEXT: v_readlane_b32 s52, v43, 10
+; SI-NEXT: v_readlane_b32 s51, v43, 9
+; SI-NEXT: v_readlane_b32 s50, v43, 8
+; SI-NEXT: v_readlane_b32 s49, v43, 7
+; SI-NEXT: v_readlane_b32 s48, v43, 6
+; SI-NEXT: v_readlane_b32 s39, v43, 5
+; SI-NEXT: v_readlane_b32 s38, v43, 4
+; SI-NEXT: v_readlane_b32 s37, v43, 3
+; SI-NEXT: v_readlane_b32 s36, v43, 2
+; SI-NEXT: v_readlane_b32 s35, v43, 1
+; SI-NEXT: v_readlane_b32 s34, v43, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -82389,338 +82401,346 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_writelane_b32 v43, s34, 0
+; SI-NEXT: v_writelane_b32 v43, s35, 1
+; SI-NEXT: v_writelane_b32 v43, s36, 2
+; SI-NEXT: v_writelane_b32 v43, s37, 3
+; SI-NEXT: v_writelane_b32 v43, s38, 4
+; SI-NEXT: v_writelane_b32 v43, s39, 5
+; SI-NEXT: v_writelane_b32 v43, s48, 6
+; SI-NEXT: v_writelane_b32 v43, s49, 7
+; SI-NEXT: v_writelane_b32 v43, s50, 8
+; SI-NEXT: v_writelane_b32 v43, s51, 9
+; SI-NEXT: v_writelane_b32 v43, s52, 10
+; SI-NEXT: v_writelane_b32 v43, s53, 11
+; SI-NEXT: v_writelane_b32 v43, s54, 12
+; SI-NEXT: v_writelane_b32 v43, s55, 13
+; SI-NEXT: v_writelane_b32 v43, s64, 14
+; SI-NEXT: v_writelane_b32 v43, s65, 15
+; SI-NEXT: v_writelane_b32 v43, s66, 16
+; SI-NEXT: v_writelane_b32 v43, s67, 17
+; SI-NEXT: v_writelane_b32 v43, s68, 18
+; SI-NEXT: v_writelane_b32 v43, s69, 19
+; SI-NEXT: v_writelane_b32 v43, s70, 20
+; SI-NEXT: v_writelane_b32 v43, s71, 21
+; SI-NEXT: v_writelane_b32 v43, s80, 22
+; SI-NEXT: v_writelane_b32 v43, s81, 23
+; SI-NEXT: v_writelane_b32 v43, s82, 24
+; SI-NEXT: v_writelane_b32 v43, s83, 25
+; SI-NEXT: v_writelane_b32 v43, s84, 26
+; SI-NEXT: v_writelane_b32 v43, s85, 27
+; SI-NEXT: v_writelane_b32 v43, s86, 28
+; SI-NEXT: v_writelane_b32 v43, s87, 29
+; SI-NEXT: v_writelane_b32 v43, s96, 30
+; SI-NEXT: v_writelane_b32 v43, s97, 31
+; SI-NEXT: v_writelane_b32 v43, s98, 32
+; SI-NEXT: v_writelane_b32 v43, s99, 33
+; SI-NEXT: v_writelane_b32 v43, s30, 34
+; SI-NEXT: v_writelane_b32 v43, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v40, s34, 0
-; SI-NEXT: v_writelane_b32 v40, s35, 1
-; SI-NEXT: v_writelane_b32 v40, s36, 2
-; SI-NEXT: v_writelane_b32 v40, s37, 3
-; SI-NEXT: v_writelane_b32 v40, s38, 4
-; SI-NEXT: v_writelane_b32 v40, s39, 5
-; SI-NEXT: v_writelane_b32 v40, s48, 6
-; SI-NEXT: v_writelane_b32 v40, s49, 7
-; SI-NEXT: v_writelane_b32 v40, s50, 8
-; SI-NEXT: v_writelane_b32 v40, s51, 9
-; SI-NEXT: v_writelane_b32 v40, s52, 10
-; SI-NEXT: v_writelane_b32 v40, s53, 11
-; SI-NEXT: v_writelane_b32 v40, s54, 12
-; SI-NEXT: v_writelane_b32 v40, s55, 13
-; SI-NEXT: v_writelane_b32 v40, s64, 14
-; SI-NEXT: v_writelane_b32 v40, s65, 15
-; SI-NEXT: v_writelane_b32 v40, s66, 16
-; SI-NEXT: v_writelane_b32 v40, s67, 17
-; SI-NEXT: v_writelane_b32 v40, s68, 18
-; SI-NEXT: v_writelane_b32 v40, s69, 19
-; SI-NEXT: v_writelane_b32 v40, s70, 20
-; SI-NEXT: v_writelane_b32 v40, s71, 21
-; SI-NEXT: v_writelane_b32 v40, s80, 22
-; SI-NEXT: v_writelane_b32 v40, s81, 23
-; SI-NEXT: v_writelane_b32 v40, s82, 24
-; SI-NEXT: v_writelane_b32 v40, s83, 25
-; SI-NEXT: v_writelane_b32 v40, s84, 26
-; SI-NEXT: v_writelane_b32 v40, s85, 27
-; SI-NEXT: v_writelane_b32 v40, s86, 28
-; SI-NEXT: v_writelane_b32 v40, s87, 29
-; SI-NEXT: v_writelane_b32 v40, s96, 30
-; SI-NEXT: v_writelane_b32 v40, s97, 31
-; SI-NEXT: v_writelane_b32 v40, s98, 32
-; SI-NEXT: v_writelane_b32 v40, s99, 33
-; SI-NEXT: v_writelane_b32 v40, s30, 34
-; SI-NEXT: v_writelane_b32 v40, s31, 35
-; SI-NEXT: v_readfirstlane_b32 s79, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76
-; SI-NEXT: s_mov_b32 s31, s16
-; SI-NEXT: v_readfirstlane_b32 s89, v30
-; SI-NEXT: v_readfirstlane_b32 s36, v29
-; SI-NEXT: v_readfirstlane_b32 s94, v27
-; SI-NEXT: v_readfirstlane_b32 s55, v26
-; SI-NEXT: v_readfirstlane_b32 s30, v25
-; SI-NEXT: v_readfirstlane_b32 s16, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
-; SI-NEXT: v_readfirstlane_b32 s95, v23
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v41, s29, 0
-; SI-NEXT: v_writelane_b32 v41, s28, 1
-; SI-NEXT: v_writelane_b32 v41, s23, 2
-; SI-NEXT: v_writelane_b32 v41, s22, 3
-; SI-NEXT: v_writelane_b32 v41, s21, 4
-; SI-NEXT: v_writelane_b32 v41, s20, 5
-; SI-NEXT: v_readfirstlane_b32 s64, v22
-; SI-NEXT: v_readfirstlane_b32 s66, v21
-; SI-NEXT: v_readfirstlane_b32 s81, v20
-; SI-NEXT: v_readfirstlane_b32 s82, v19
-; SI-NEXT: v_readfirstlane_b32 s68, v18
-; SI-NEXT: v_readfirstlane_b32 s39, v17
-; SI-NEXT: v_readfirstlane_b32 s52, v16
-; SI-NEXT: v_readfirstlane_b32 s65, v15
-; SI-NEXT: v_readfirstlane_b32 s48, v14
-; SI-NEXT: v_readfirstlane_b32 s50, v13
-; SI-NEXT: v_readfirstlane_b32 s70, v12
-; SI-NEXT: v_readfirstlane_b32 s71, v11
-; SI-NEXT: v_readfirstlane_b32 s37, v10
-; SI-NEXT: v_readfirstlane_b32 s29, v9
-; SI-NEXT: v_readfirstlane_b32 s93, v8
-; SI-NEXT: v_readfirstlane_b32 s28, v7
-; SI-NEXT: v_readfirstlane_b32 s38, v6
-; SI-NEXT: v_readfirstlane_b32 s49, v5
-; SI-NEXT: v_readfirstlane_b32 s51, v4
-; SI-NEXT: v_readfirstlane_b32 s53, v3
-; SI-NEXT: v_readfirstlane_b32 s67, v2
-; SI-NEXT: v_readfirstlane_b32 s90, v1
-; SI-NEXT: v_readfirstlane_b32 s91, v0
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32
+; SI-NEXT: ; implicit-def: $vgpr44 : SGPR spill to VGPR lane
+; SI-NEXT: v_readfirstlane_b32 s4, v16
+; SI-NEXT: v_writelane_b32 v44, s23, 0
+; SI-NEXT: v_writelane_b32 v44, s22, 1
+; SI-NEXT: v_writelane_b32 v44, s21, 2
+; SI-NEXT: v_writelane_b32 v44, s20, 3
+; SI-NEXT: v_writelane_b32 v44, s4, 4
+; SI-NEXT: s_mov_b32 s82, s29
+; SI-NEXT: s_mov_b32 s85, s25
+; SI-NEXT: s_mov_b32 s29, s24
+; SI-NEXT: s_mov_b32 s44, s16
+; SI-NEXT: v_readfirstlane_b32 s64, v30
+; SI-NEXT: v_readfirstlane_b32 s55, v29
+; SI-NEXT: v_readfirstlane_b32 s66, v28
+; SI-NEXT: v_readfirstlane_b32 s69, v27
+; SI-NEXT: v_readfirstlane_b32 s68, v26
+; SI-NEXT: v_readfirstlane_b32 s39, v25
+; SI-NEXT: v_readfirstlane_b32 s50, v24
+; SI-NEXT: v_readfirstlane_b32 s65, v23
+; SI-NEXT: v_readfirstlane_b32 s51, v22
+; SI-NEXT: v_readfirstlane_b32 s37, v21
+; SI-NEXT: v_readfirstlane_b32 s53, v20
+; SI-NEXT: v_readfirstlane_b32 s88, v19
+; SI-NEXT: v_readfirstlane_b32 s31, v18
+; SI-NEXT: v_readfirstlane_b32 s95, v17
+; SI-NEXT: v_readfirstlane_b32 s48, v15
+; SI-NEXT: v_readfirstlane_b32 s35, v14
+; SI-NEXT: v_readfirstlane_b32 s34, v13
+; SI-NEXT: v_readfirstlane_b32 s52, v12
+; SI-NEXT: v_readfirstlane_b32 s16, v11
+; SI-NEXT: v_readfirstlane_b32 s96, v10
+; SI-NEXT: v_readfirstlane_b32 s20, v9
+; SI-NEXT: v_readfirstlane_b32 s89, v8
+; SI-NEXT: v_readfirstlane_b32 s92, v7
+; SI-NEXT: v_readfirstlane_b32 s91, v6
+; SI-NEXT: v_readfirstlane_b32 s93, v5
+; SI-NEXT: v_readfirstlane_b32 s30, v4
+; SI-NEXT: v_readfirstlane_b32 s38, v3
+; SI-NEXT: v_readfirstlane_b32 s49, v2
+; SI-NEXT: v_readfirstlane_b32 s54, v1
+; SI-NEXT: v_readfirstlane_b32 s90, v0
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s47, v24
-; SI-NEXT: v_readfirstlane_b32 s86, v25
-; SI-NEXT: v_readfirstlane_b32 s58, v26
-; SI-NEXT: v_readfirstlane_b32 s99, v27
-; SI-NEXT: v_readfirstlane_b32 s46, v29
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s56, v32
+; SI-NEXT: v_readfirstlane_b32 s86, v33
+; SI-NEXT: v_readfirstlane_b32 s58, v34
+; SI-NEXT: v_readfirstlane_b32 s99, v35
+; SI-NEXT: v_readfirstlane_b32 s24, v36
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_readfirstlane_b32 s78, v30
+; SI-NEXT: v_readfirstlane_b32 s78, v37
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_readfirstlane_b32 s88, v31
+; SI-NEXT: v_readfirstlane_b32 s25, v38
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s21, v32
+; SI-NEXT: v_readfirstlane_b32 s21, v39
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s98, v33
+; SI-NEXT: v_readfirstlane_b32 s22, v48
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_readfirstlane_b32 s96, v34
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s23, v49
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_readfirstlane_b32 s34, v35
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_readfirstlane_b32 s83, v36
+; SI-NEXT: v_readfirstlane_b32 s87, v50
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_readfirstlane_b32 s20, v37
+; SI-NEXT: v_readfirstlane_b32 s47, v52
+; SI-NEXT: v_readfirstlane_b32 s83, v51
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_readfirstlane_b32 s84, v38
+; SI-NEXT: v_readfirstlane_b32 s84, v53
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_readfirstlane_b32 s44, v39
+; SI-NEXT: v_readfirstlane_b32 s36, v54
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_readfirstlane_b32 s87, v48
+; SI-NEXT: v_readfirstlane_b32 s79, v55
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_readfirstlane_b32 s85, v49
+; SI-NEXT: v_readfirstlane_b32 s71, v40
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_readfirstlane_b32 s69, v50
+; SI-NEXT: v_readfirstlane_b32 s98, v41
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s35, v51
-; SI-NEXT: v_writelane_b32 v41, s47, 6
-; SI-NEXT: v_writelane_b32 v41, s58, 7
+; SI-NEXT: v_readfirstlane_b32 s81, v42
+; SI-NEXT: v_writelane_b32 v44, s47, 5
+; SI-NEXT: v_writelane_b32 v44, s58, 6
; SI-NEXT: s_cbranch_scc0 .LBB107_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: s_and_b32 s4, s31, 0xff
+; SI-NEXT: s_and_b32 s4, s44, 0xff
; SI-NEXT: s_lshl_b32 s5, s17, 8
; SI-NEXT: s_or_b32 s12, s4, s5
; SI-NEXT: s_and_b32 s4, s18, 0xff
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s5, s19, 24
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: s_and_b32 s5, s24, 0xff
-; SI-NEXT: s_lshl_b32 s6, s25, 8
+; SI-NEXT: s_and_b32 s5, s29, 0xff
+; SI-NEXT: s_lshl_b32 s6, s85, 8
; SI-NEXT: s_or_b32 s13, s5, s6
; SI-NEXT: s_and_b32 s5, s26, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s27, 24
; SI-NEXT: s_or_b32 s6, s6, s5
-; SI-NEXT: s_and_b32 s5, s67, 0xff
-; SI-NEXT: s_lshl_b32 s7, s53, 8
+; SI-NEXT: s_and_b32 s5, s49, 0xff
+; SI-NEXT: s_lshl_b32 s7, s38, 8
; SI-NEXT: s_or_b32 s14, s5, s7
-; SI-NEXT: s_and_b32 s5, s51, 0xff
+; SI-NEXT: s_and_b32 s5, s30, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s7, s49, 24
+; SI-NEXT: s_lshl_b32 s7, s93, 24
; SI-NEXT: s_or_b32 s8, s7, s5
-; SI-NEXT: s_and_b32 s5, s37, 0xff
-; SI-NEXT: s_lshl_b32 s7, s71, 8
+; SI-NEXT: s_and_b32 s5, s96, 0xff
+; SI-NEXT: s_lshl_b32 s7, s16, 8
; SI-NEXT: s_or_b32 s15, s5, s7
-; SI-NEXT: s_and_b32 s5, s70, 0xff
+; SI-NEXT: s_and_b32 s5, s52, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s7, s50, 24
+; SI-NEXT: s_lshl_b32 s7, s34, 24
; SI-NEXT: s_or_b32 s10, s7, s5
-; SI-NEXT: s_and_b32 s5, s68, 0xff
-; SI-NEXT: s_lshl_b32 s7, s82, 8
+; SI-NEXT: s_and_b32 s5, s31, 0xff
+; SI-NEXT: s_lshl_b32 s7, s88, 8
; SI-NEXT: s_or_b32 s40, s5, s7
-; SI-NEXT: s_and_b32 s5, s81, 0xff
+; SI-NEXT: s_and_b32 s5, s53, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s7, s66, 24
+; SI-NEXT: s_lshl_b32 s7, s37, 24
; SI-NEXT: s_or_b32 s60, s7, s5
-; SI-NEXT: s_and_b32 s5, s55, 0xff
-; SI-NEXT: s_lshl_b32 s7, s94, 8
+; SI-NEXT: s_and_b32 s5, s68, 0xff
+; SI-NEXT: s_lshl_b32 s7, s69, 8
; SI-NEXT: s_or_b32 s41, s5, s7
-; SI-NEXT: s_and_b32 s5, s79, 0xff
+; SI-NEXT: s_and_b32 s5, s66, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_lshl_b32 s7, s36, 24
+; SI-NEXT: s_lshl_b32 s7, s55, 24
; SI-NEXT: s_or_b32 s62, s7, s5
-; SI-NEXT: s_and_b32 s5, s87, 0xff
-; SI-NEXT: s_lshl_b32 s7, s44, 8
+; SI-NEXT: s_and_b32 s5, s79, 0xff
+; SI-NEXT: s_lshl_b32 s7, s36, 8
; SI-NEXT: s_or_b32 s42, s5, s7
; SI-NEXT: s_and_b32 s5, s21, 0xff
-; SI-NEXT: s_lshl_b32 s7, s88, 8
+; SI-NEXT: s_lshl_b32 s7, s25, 8
; SI-NEXT: s_or_b32 s43, s5, s7
-; SI-NEXT: v_readlane_b32 s5, v41, 5
-; SI-NEXT: v_readlane_b32 s7, v41, 4
+; SI-NEXT: v_readlane_b32 s5, v44, 3
+; SI-NEXT: v_readlane_b32 s7, v44, 2
; SI-NEXT: s_and_b32 s5, s5, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 8
; SI-NEXT: s_or_b32 s5, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v41, 3
+; SI-NEXT: v_readlane_b32 s7, v44, 1
; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: v_readlane_b32 s9, v41, 2
+; SI-NEXT: v_readlane_b32 s9, v44, 0
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_lshl_b32 s9, s9, 24
; SI-NEXT: s_or_b32 s57, s9, s7
-; SI-NEXT: v_readlane_b32 s7, v41, 1
-; SI-NEXT: v_readlane_b32 s9, v41, 0
-; SI-NEXT: s_and_b32 s7, s7, 0xff
-; SI-NEXT: s_lshl_b32 s9, s9, 8
+; SI-NEXT: s_and_b32 s7, s28, 0xff
+; SI-NEXT: s_lshl_b32 s9, s82, 8
; SI-NEXT: s_or_b32 s7, s7, s9
-; SI-NEXT: s_and_b32 s9, s91, 0xff
+; SI-NEXT: s_and_b32 s9, s90, 0xff
; SI-NEXT: s_lshl_b32 s9, s9, 16
-; SI-NEXT: s_lshl_b32 s11, s90, 24
+; SI-NEXT: s_lshl_b32 s11, s54, 24
; SI-NEXT: s_or_b32 s77, s11, s9
-; SI-NEXT: s_and_b32 s9, s38, 0xff
-; SI-NEXT: s_lshl_b32 s11, s28, 8
+; SI-NEXT: s_and_b32 s9, s91, 0xff
+; SI-NEXT: s_lshl_b32 s11, s92, 8
; SI-NEXT: s_or_b32 s9, s9, s11
-; SI-NEXT: s_and_b32 s11, s93, 0xff
+; SI-NEXT: s_and_b32 s11, s89, 0xff
+; SI-NEXT: s_mov_b32 s72, s44
; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: v_writelane_b32 v41, s44, 12
-; SI-NEXT: s_lshl_b32 s44, s29, 24
+; SI-NEXT: s_lshl_b32 s44, s20, 24
+; SI-NEXT: s_mov_b32 s59, s16
; SI-NEXT: s_or_b32 vcc_lo, s44, s11
-; SI-NEXT: s_and_b32 s11, s48, 0xff
-; SI-NEXT: s_lshl_b32 s44, s65, 8
+; SI-NEXT: s_and_b32 s11, s35, 0xff
+; SI-NEXT: s_lshl_b32 s44, s48, 8
+; SI-NEXT: v_readlane_b32 s16, v44, 4
; SI-NEXT: s_or_b32 s11, s11, s44
-; SI-NEXT: s_and_b32 s44, s52, 0xff
+; SI-NEXT: s_and_b32 s44, s16, 0xff
; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: s_lshl_b32 s45, s39, 24
+; SI-NEXT: s_lshl_b32 s45, s95, 24
; SI-NEXT: s_or_b32 vcc_hi, s45, s44
-; SI-NEXT: s_and_b32 s44, s64, 0xff
-; SI-NEXT: s_lshl_b32 s45, s95, 8
+; SI-NEXT: s_and_b32 s44, s51, 0xff
+; SI-NEXT: s_lshl_b32 s45, s65, 8
; SI-NEXT: s_or_b32 s44, s44, s45
-; SI-NEXT: s_and_b32 s45, s16, 0xff
+; SI-NEXT: s_and_b32 s45, s50, 0xff
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_mov_b32 s59, s46
-; SI-NEXT: s_lshl_b32 s46, s30, 24
-; SI-NEXT: v_writelane_b32 v41, s55, 13
+; SI-NEXT: s_lshl_b32 s46, s39, 24
; SI-NEXT: s_and_b32 s44, s44, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s79, 14
-; SI-NEXT: s_or_b32 s79, s46, s45
-; SI-NEXT: s_or_b32 s61, s44, s79
-; SI-NEXT: s_and_b32 s44, s89, 0xff
-; SI-NEXT: s_lshl_b32 s45, s35, 8
+; SI-NEXT: s_mov_b32 s67, s20
+; SI-NEXT: s_or_b32 s20, s46, s45
+; SI-NEXT: s_or_b32 s61, s44, s20
+; SI-NEXT: s_and_b32 s44, s64, 0xff
+; SI-NEXT: s_lshl_b32 s45, s81, 8
; SI-NEXT: s_or_b32 s44, s44, s45
-; SI-NEXT: s_and_b32 s45, s69, 0xff
+; SI-NEXT: s_and_b32 s45, s98, 0xff
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s85, 24
+; SI-NEXT: s_lshl_b32 s46, s71, 24
; SI-NEXT: s_and_b32 s44, s44, 0xffff
-; SI-NEXT: s_mov_b32 s23, s21
-; SI-NEXT: s_mov_b32 s21, s87
-; SI-NEXT: s_mov_b32 s87, s18
+; SI-NEXT: s_mov_b32 s70, s39
+; SI-NEXT: s_mov_b32 s39, s91
+; SI-NEXT: s_mov_b32 s91, s82
+; SI-NEXT: s_mov_b32 s82, s88
+; SI-NEXT: s_mov_b32 s88, s18
; SI-NEXT: s_or_b32 s18, s46, s45
; SI-NEXT: s_or_b32 s63, s44, s18
; SI-NEXT: s_and_b32 s44, s83, 0xff
-; SI-NEXT: s_lshl_b32 s45, s34, 8
+; SI-NEXT: s_lshl_b32 s45, s87, 8
; SI-NEXT: s_or_b32 s44, s44, s45
-; SI-NEXT: s_and_b32 s45, s96, 0xff
+; SI-NEXT: s_and_b32 s45, s23, 0xff
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s98, 24
-; SI-NEXT: s_mov_b32 s56, s83
-; SI-NEXT: s_mov_b32 s83, s64
-; SI-NEXT: s_mov_b32 s64, s39
-; SI-NEXT: s_mov_b32 s39, s91
-; SI-NEXT: s_mov_b32 s91, s19
+; SI-NEXT: s_lshl_b32 s46, s22, 24
+; SI-NEXT: s_mov_b32 s80, s31
+; SI-NEXT: s_mov_b32 s31, s53
+; SI-NEXT: s_mov_b32 s53, s38
+; SI-NEXT: s_mov_b32 s38, s90
+; SI-NEXT: s_mov_b32 s90, s19
; SI-NEXT: s_or_b32 s19, s46, s45
; SI-NEXT: s_and_b32 s45, s84, 0xff
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s20, 24
+; SI-NEXT: s_lshl_b32 s46, s47, 24
; SI-NEXT: s_and_b32 s44, s44, 0xffff
+; SI-NEXT: s_mov_b32 s97, s22
+; SI-NEXT: s_mov_b32 s22, s55
+; SI-NEXT: s_mov_b32 s55, s49
+; SI-NEXT: s_mov_b32 s49, s92
+; SI-NEXT: s_mov_b32 s92, s72
; SI-NEXT: s_or_b32 s72, s46, s45
; SI-NEXT: s_or_b32 s73, s44, s19
; SI-NEXT: s_and_b32 s44, s99, 0xff
; SI-NEXT: s_lshl_b32 s45, s58, 8
; SI-NEXT: s_or_b32 s44, s44, s45
; SI-NEXT: s_and_b32 s45, s86, 0xff
-; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s47, 24
; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_mov_b32 s76, s20
-; SI-NEXT: s_mov_b32 s20, s84
-; SI-NEXT: s_mov_b32 s84, s81
-; SI-NEXT: s_mov_b32 s81, s70
-; SI-NEXT: s_mov_b32 s70, s65
-; SI-NEXT: s_mov_b32 s65, s49
-; SI-NEXT: s_mov_b32 s49, s90
-; SI-NEXT: s_mov_b32 s90, s17
-; SI-NEXT: s_or_b32 s17, s46, s45
-; SI-NEXT: s_and_b32 s45, s78, 0xff
-; SI-NEXT: s_or_b32 s5, s5, s57
; SI-NEXT: s_lshl_b32 s45, s45, 16
-; SI-NEXT: s_lshl_b32 s46, s59, 24
+; SI-NEXT: s_lshl_b32 s46, s56, 24
+; SI-NEXT: s_or_b32 s5, s5, s57
+; SI-NEXT: s_mov_b32 s76, s56
+; SI-NEXT: s_mov_b32 s56, s86
+; SI-NEXT: s_mov_b32 s86, s81
+; SI-NEXT: s_mov_b32 s81, s65
+; SI-NEXT: s_mov_b32 s65, s48
+; SI-NEXT: s_mov_b32 s48, s89
+; SI-NEXT: s_mov_b32 s89, s17
+; SI-NEXT: s_or_b32 s17, s46, s45
; SI-NEXT: s_and_b32 s44, s44, 0xffff
; SI-NEXT: s_and_b32 s12, s12, 0xffff
-; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_or_b32 s74, s46, s45
+; SI-NEXT: s_and_b32 s9, s9, 0xffff
+; SI-NEXT: v_writelane_b32 v44, s68, 11
+; SI-NEXT: s_mov_b32 s94, s51
+; SI-NEXT: s_mov_b32 s51, s95
+; SI-NEXT: s_mov_b32 s95, s27
; SI-NEXT: s_or_b32 s75, s44, s17
-; SI-NEXT: s_mov_b32 s46, s28
+; SI-NEXT: s_mov_b32 s44, s93
+; SI-NEXT: s_mov_b32 s93, s28
; SI-NEXT: s_and_b32 s28, s42, 0xffff
-; SI-NEXT: s_mov_b32 s44, s30
-; SI-NEXT: s_mov_b32 s30, s26
-; SI-NEXT: s_and_b32 s26, s43, 0xffff
+; SI-NEXT: s_and_b32 s27, s43, 0xffff
; SI-NEXT: s_or_b32 s42, s12, s4
; SI-NEXT: s_mov_b32 s43, s5
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
-; SI-NEXT: s_or_b32 s7, s7, s77
-; SI-NEXT: v_writelane_b32 v41, s4, 8
-; SI-NEXT: s_and_b32 s9, s9, 0xffff
-; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s5, 9
-; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
; SI-NEXT: s_or_b32 s9, s9, vcc_lo
+; SI-NEXT: s_and_b32 s45, s78, 0xff
+; SI-NEXT: v_writelane_b32 v44, s4, 7
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
+; SI-NEXT: s_and_b32 s11, s11, 0xffff
+; SI-NEXT: s_lshl_b32 s45, s45, 16
+; SI-NEXT: s_lshl_b32 s46, s24, 24
+; SI-NEXT: v_writelane_b32 v44, s5, 8
+; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 16
+; SI-NEXT: s_or_b32 s7, s7, s77
; SI-NEXT: s_or_b32 s11, s11, vcc_hi
-; SI-NEXT: s_mov_b32 s92, s16
-; SI-NEXT: s_mov_b32 s97, s48
-; SI-NEXT: s_mov_b32 s48, s29
+; SI-NEXT: s_mov_b32 s68, s34
+; SI-NEXT: s_or_b32 s74, s46, s45
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_and_b32 s14, s14, 0xffff
; SI-NEXT: s_and_b32 s58, s15, 0xffff
; SI-NEXT: s_and_b32 s16, s40, 0xffff
+; SI-NEXT: s_mov_b32 s34, s29
; SI-NEXT: s_and_b32 s29, s41, 0xffff
-; SI-NEXT: v_writelane_b32 v41, s4, 10
-; SI-NEXT: s_mov_b32 s22, s51
-; SI-NEXT: s_mov_b32 s51, s93
-; SI-NEXT: s_mov_b32 s45, s99
-; SI-NEXT: s_mov_b32 s99, s96
-; SI-NEXT: s_mov_b32 s96, s82
-; SI-NEXT: s_mov_b32 s82, s95
-; SI-NEXT: s_mov_b32 s95, s94
-; SI-NEXT: s_mov_b32 s94, s92
+; SI-NEXT: v_writelane_b32 v44, s4, 9
+; SI-NEXT: s_mov_b32 s45, s78
+; SI-NEXT: s_mov_b32 s78, s84
+; SI-NEXT: s_mov_b32 s84, s69
+; SI-NEXT: s_mov_b32 s69, s59
; SI-NEXT: s_or_b32 s40, s13, s6
; SI-NEXT: s_mov_b32 s41, s7
-; SI-NEXT: v_writelane_b32 v41, s5, 11
+; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16
; SI-NEXT: s_or_b32 s14, s14, s8
; SI-NEXT: s_mov_b32 s15, s9
-; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
+; SI-NEXT: v_writelane_b32 v44, s5, 10
; SI-NEXT: s_or_b32 s12, s58, s10
; SI-NEXT: s_mov_b32 s13, s11
-; SI-NEXT: s_lshr_b64 s[92:93], s[10:11], 16
+; SI-NEXT: s_lshr_b64 s[58:59], s[10:11], 16
; SI-NEXT: s_or_b32 s10, s16, s60
; SI-NEXT: s_mov_b32 s11, s61
; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
@@ -82730,67 +82750,69 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_or_b32 s6, s28, s72
; SI-NEXT: s_mov_b32 s7, s73
; SI-NEXT: s_lshr_b64 s[72:73], s[72:73], 16
-; SI-NEXT: s_or_b32 s4, s26, s74
+; SI-NEXT: s_or_b32 s4, s27, s74
; SI-NEXT: s_mov_b32 s5, s75
; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16
-; SI-NEXT: s_mov_b32 s16, s94
-; SI-NEXT: s_mov_b32 s94, s95
-; SI-NEXT: s_mov_b32 s95, s82
-; SI-NEXT: s_mov_b32 s82, s96
-; SI-NEXT: s_mov_b32 s96, s99
-; SI-NEXT: s_mov_b32 s99, s45
-; SI-NEXT: s_mov_b32 s28, s46
-; SI-NEXT: s_mov_b32 s46, s59
-; SI-NEXT: s_mov_b32 s26, s30
-; SI-NEXT: s_mov_b32 s30, s44
-; SI-NEXT: v_readlane_b32 s44, v41, 12
+; SI-NEXT: s_mov_b32 s29, s34
+; SI-NEXT: s_mov_b32 s16, s69
+; SI-NEXT: s_mov_b32 s69, s84
+; SI-NEXT: s_mov_b32 s84, s78
+; SI-NEXT: s_mov_b32 s78, s45
+; SI-NEXT: s_mov_b32 s28, s93
+; SI-NEXT: s_mov_b32 s93, s44
; SI-NEXT: s_lshr_b32 s47, s57, 16
; SI-NEXT: s_lshr_b32 s57, s77, 16
; SI-NEXT: s_lshr_b32 s59, vcc_lo, 16
; SI-NEXT: s_lshr_b32 s61, vcc_hi, 16
-; SI-NEXT: s_lshr_b32 s63, s79, 16
-; SI-NEXT: v_readlane_b32 s79, v41, 14
-; SI-NEXT: v_readlane_b32 s55, v41, 13
+; SI-NEXT: s_lshr_b32 s63, s20, 16
+; SI-NEXT: s_mov_b32 s20, s67
+; SI-NEXT: s_mov_b32 s34, s68
+; SI-NEXT: v_readlane_b32 s68, v44, 11
; SI-NEXT: s_lshr_b32 s73, s18, 16
-; SI-NEXT: s_mov_b32 s18, s87
-; SI-NEXT: s_mov_b32 s29, s48
-; SI-NEXT: s_mov_b32 s48, s97
-; SI-NEXT: s_mov_b32 s87, s21
-; SI-NEXT: s_mov_b32 s21, s23
-; SI-NEXT: s_mov_b32 s93, s51
-; SI-NEXT: s_mov_b32 s51, s22
-; SI-NEXT: s_lshr_b32 s75, s19, 16
-; SI-NEXT: s_mov_b32 s19, s91
+; SI-NEXT: s_mov_b32 s18, s88
+; SI-NEXT: s_mov_b32 s27, s95
+; SI-NEXT: s_mov_b32 s95, s51
+; SI-NEXT: s_mov_b32 s51, s94
+; SI-NEXT: s_mov_b32 s88, s82
+; SI-NEXT: s_mov_b32 s82, s91
; SI-NEXT: s_mov_b32 s91, s39
-; SI-NEXT: s_mov_b32 s39, s64
-; SI-NEXT: s_mov_b32 s64, s83
-; SI-NEXT: s_mov_b32 s83, s56
+; SI-NEXT: s_mov_b32 s39, s70
+; SI-NEXT: s_lshr_b32 s75, s19, 16
+; SI-NEXT: s_mov_b32 s19, s90
+; SI-NEXT: s_mov_b32 s90, s38
+; SI-NEXT: s_mov_b32 s38, s53
+; SI-NEXT: s_mov_b32 s53, s31
+; SI-NEXT: s_mov_b32 s44, s92
+; SI-NEXT: s_mov_b32 s92, s49
+; SI-NEXT: s_mov_b32 s49, s55
+; SI-NEXT: s_mov_b32 s55, s22
+; SI-NEXT: s_mov_b32 s31, s80
+; SI-NEXT: s_mov_b32 s22, s97
; SI-NEXT: s_lshr_b32 s45, s17, 16
-; SI-NEXT: s_mov_b32 s17, s90
-; SI-NEXT: s_mov_b32 s90, s49
-; SI-NEXT: s_mov_b32 s49, s65
-; SI-NEXT: s_mov_b32 s65, s70
-; SI-NEXT: s_mov_b32 s70, s81
-; SI-NEXT: s_mov_b32 s81, s84
-; SI-NEXT: s_mov_b32 s84, s20
-; SI-NEXT: s_mov_b32 s20, s76
+; SI-NEXT: s_mov_b32 s17, s89
+; SI-NEXT: s_mov_b32 s89, s48
+; SI-NEXT: s_mov_b32 s48, s65
+; SI-NEXT: s_mov_b32 s65, s81
+; SI-NEXT: s_mov_b32 s81, s86
+; SI-NEXT: s_mov_b32 s86, s56
+; SI-NEXT: s_mov_b32 s56, s76
; SI-NEXT: s_mov_b64 s[76:77], 0
; SI-NEXT: s_branch .LBB107_3
; SI-NEXT: .LBB107_2:
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_mov_b64 s[76:77], -1
-; SI-NEXT: v_writelane_b32 v41, s4, 8
-; SI-NEXT: v_writelane_b32 v41, s5, 9
+; SI-NEXT: v_writelane_b32 v44, s4, 7
+; SI-NEXT: v_writelane_b32 v44, s5, 8
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr47
; SI-NEXT: ; implicit-def: $sgpr40
+; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr57
; SI-NEXT: ; implicit-def: $sgpr14
-; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: ; implicit-def: $sgpr59
; SI-NEXT: ; implicit-def: $sgpr12
-; SI-NEXT: ; implicit-def: $sgpr92
+; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr61
; SI-NEXT: ; implicit-def: $sgpr10
; SI-NEXT: ; implicit-def: $sgpr60
@@ -82803,218 +82825,213 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: ; implicit-def: $sgpr75
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr45
-; SI-NEXT: v_writelane_b32 v41, s4, 10
-; SI-NEXT: v_writelane_b32 v41, s5, 11
+; SI-NEXT: v_writelane_b32 v44, s4, 9
+; SI-NEXT: v_writelane_b32 v44, s5, 10
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB107_3: ; %Flow
; SI-NEXT: s_andn2_b64 vcc, exec, s[76:77]
-; SI-NEXT: v_readlane_b32 s76, v41, 8
-; SI-NEXT: v_readlane_b32 s77, v41, 9
-; SI-NEXT: s_mov_b32 s22, s76
-; SI-NEXT: v_readlane_b32 s76, v41, 10
-; SI-NEXT: s_mov_b32 s56, s76
-; SI-NEXT: v_readlane_b32 s77, v41, 11
+; SI-NEXT: v_readlane_b32 s76, v44, 7
+; SI-NEXT: v_readlane_b32 s77, v44, 8
; SI-NEXT: s_cbranch_vccnz .LBB107_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_and_b32 s4, s21, 0xff
-; SI-NEXT: s_lshl_b32 s5, s88, 8
+; SI-NEXT: s_lshl_b32 s5, s25, 8
; SI-NEXT: s_add_i32 s78, s78, 3
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_and_b32 s6, s78, 0xff
; SI-NEXT: s_addk_i32 s4, 0x300
-; SI-NEXT: s_lshl_b32 s5, s46, 24
+; SI-NEXT: s_lshl_b32 s5, s24, 24
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_add_i32 s99, s99, 3
-; SI-NEXT: v_readlane_b32 s6, v41, 7
+; SI-NEXT: v_readlane_b32 s6, v44, 6
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_and_b32 s5, s99, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 8
; SI-NEXT: s_add_i32 s86, s86, 3
; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: v_readlane_b32 s6, v41, 6
; SI-NEXT: s_and_b32 s7, s86, 0xff
; SI-NEXT: s_addk_i32 s5, 0x300
-; SI-NEXT: s_lshl_b32 s6, s6, 24
+; SI-NEXT: s_lshl_b32 s6, s56, 24
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: s_add_i32 s97, s87, 3
+; SI-NEXT: s_add_i32 s97, s79, 3
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: s_and_b32 s6, s97, 0xff
-; SI-NEXT: s_lshl_b32 s7, s44, 8
+; SI-NEXT: s_lshl_b32 s7, s36, 8
; SI-NEXT: s_add_i32 s84, s84, 3
; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: v_readlane_b32 s7, v44, 5
; SI-NEXT: s_and_b32 s8, s84, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
-; SI-NEXT: s_lshl_b32 s7, s20, 24
+; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s7, s7, s8
; SI-NEXT: s_add_i32 s83, s83, 3
; SI-NEXT: s_or_b32 s6, s7, s6
; SI-NEXT: s_and_b32 s7, s83, 0xff
-; SI-NEXT: s_lshl_b32 s8, s34, 8
-; SI-NEXT: s_add_i32 s80, s96, 3
+; SI-NEXT: s_lshl_b32 s8, s87, 8
+; SI-NEXT: s_add_i32 s80, s23, 3
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: s_and_b32 s9, s80, 0xff
; SI-NEXT: s_addk_i32 s7, 0x300
-; SI-NEXT: s_lshl_b32 s8, s98, 24
+; SI-NEXT: s_lshl_b32 s8, s22, 24
; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s8, s8, s9
-; SI-NEXT: s_add_i32 s55, s55, 3
+; SI-NEXT: s_add_i32 s68, s68, 3
; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: s_and_b32 s8, s55, 0xff
-; SI-NEXT: s_lshl_b32 s9, s94, 8
-; SI-NEXT: s_add_i32 s88, s79, 3
+; SI-NEXT: s_and_b32 s8, s68, 0xff
+; SI-NEXT: s_lshl_b32 s9, s69, 8
+; SI-NEXT: s_add_i32 s66, s66, 3
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: s_and_b32 s10, s88, 0xff
+; SI-NEXT: s_and_b32 s10, s66, 0xff
; SI-NEXT: s_addk_i32 s8, 0x300
-; SI-NEXT: s_lshl_b32 s9, s36, 24
+; SI-NEXT: s_lshl_b32 s9, s55, 24
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_or_b32 s9, s9, s10
-; SI-NEXT: s_add_i32 s20, s89, 3
+; SI-NEXT: s_add_i32 s64, s64, 3
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: s_and_b32 s9, s20, 0xff
-; SI-NEXT: s_lshl_b32 s10, s35, 8
-; SI-NEXT: s_add_i32 s69, s69, 3
+; SI-NEXT: s_and_b32 s9, s64, 0xff
+; SI-NEXT: s_lshl_b32 s10, s81, 8
+; SI-NEXT: s_add_i32 s69, s98, 3
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: s_and_b32 s11, s69, 0xff
; SI-NEXT: s_addk_i32 s9, 0x300
-; SI-NEXT: s_lshl_b32 s10, s85, 24
+; SI-NEXT: s_lshl_b32 s10, s71, 24
; SI-NEXT: s_lshl_b32 s11, s11, 16
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_or_b32 s10, s10, s11
-; SI-NEXT: s_add_i32 s68, s68, 3
+; SI-NEXT: s_add_i32 s55, s31, 3
; SI-NEXT: s_or_b32 s9, s10, s9
-; SI-NEXT: s_and_b32 s10, s68, 0xff
-; SI-NEXT: s_lshl_b32 s11, s82, 8
+; SI-NEXT: s_and_b32 s10, s55, 0xff
+; SI-NEXT: s_lshl_b32 s11, s88, 8
+; SI-NEXT: s_add_i32 s53, s53, 3
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: s_lshl_b32 s11, s66, 24
-; SI-NEXT: s_add_i32 s66, s81, 3
-; SI-NEXT: s_and_b32 s12, s66, 0xff
+; SI-NEXT: s_and_b32 s12, s53, 0xff
; SI-NEXT: s_addk_i32 s10, 0x300
+; SI-NEXT: s_lshl_b32 s11, s37, 24
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_or_b32 s11, s11, s12
-; SI-NEXT: s_add_i32 s64, s64, 3
+; SI-NEXT: s_add_i32 s51, s51, 3
; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: s_and_b32 s11, s64, 0xff
-; SI-NEXT: s_lshl_b32 s12, s95, 8
-; SI-NEXT: s_add_i32 s94, s16, 3
+; SI-NEXT: s_and_b32 s11, s51, 0xff
+; SI-NEXT: s_lshl_b32 s12, s65, 8
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: s_and_b32 s13, s94, 0xff
+; SI-NEXT: s_lshl_b32 s12, s39, 24
+; SI-NEXT: s_add_i32 s39, s50, 3
+; SI-NEXT: s_and_b32 s13, s39, 0xff
; SI-NEXT: s_addk_i32 s11, 0x300
-; SI-NEXT: s_lshl_b32 s12, s30, 24
; SI-NEXT: s_lshl_b32 s13, s13, 16
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_or_b32 s12, s12, s13
-; SI-NEXT: s_add_i32 s54, s37, 3
+; SI-NEXT: s_add_i32 s50, s96, 3
; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: s_and_b32 s12, s54, 0xff
-; SI-NEXT: s_lshl_b32 s13, s71, 8
+; SI-NEXT: s_and_b32 s12, s50, 0xff
+; SI-NEXT: s_lshl_b32 s13, s16, 8
+; SI-NEXT: s_add_i32 s37, s52, 3
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: s_lshl_b32 s13, s50, 24
-; SI-NEXT: s_add_i32 s50, s70, 3
-; SI-NEXT: s_and_b32 s14, s50, 0xff
+; SI-NEXT: s_and_b32 s14, s37, 0xff
; SI-NEXT: s_addk_i32 s12, 0x300
+; SI-NEXT: s_lshl_b32 s13, s34, 24
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_or_b32 s13, s13, s14
-; SI-NEXT: s_add_i32 s48, s48, 3
+; SI-NEXT: s_add_i32 s35, s35, 3
; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: s_and_b32 s13, s48, 0xff
-; SI-NEXT: s_lshl_b32 s14, s65, 8
-; SI-NEXT: s_add_i32 s36, s52, 3
+; SI-NEXT: s_and_b32 s13, s35, 0xff
+; SI-NEXT: s_lshl_b32 s14, s48, 8
+; SI-NEXT: v_readlane_b32 s15, v44, 4
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: s_and_b32 s15, s36, 0xff
+; SI-NEXT: s_lshl_b32 s14, s95, 24
+; SI-NEXT: s_add_i32 s95, s15, 3
+; SI-NEXT: s_and_b32 s15, s95, 0xff
; SI-NEXT: s_addk_i32 s13, 0x300
-; SI-NEXT: s_lshl_b32 s14, s39, 24
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_or_b32 s14, s14, s15
-; SI-NEXT: s_add_i32 s39, s67, 3
+; SI-NEXT: s_add_i32 s34, s49, 3
; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: s_and_b32 s14, s39, 0xff
-; SI-NEXT: s_lshl_b32 s15, s53, 8
-; SI-NEXT: s_add_i32 s34, s51, 3
+; SI-NEXT: s_and_b32 s14, s34, 0xff
+; SI-NEXT: s_lshl_b32 s15, s38, 8
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: s_and_b32 s20, s34, 0xff
+; SI-NEXT: s_lshl_b32 s15, s93, 24
+; SI-NEXT: s_add_i32 s93, s30, 3
+; SI-NEXT: s_and_b32 s21, s93, 0xff
; SI-NEXT: s_addk_i32 s14, 0x300
-; SI-NEXT: s_lshl_b32 s15, s49, 24
-; SI-NEXT: s_lshl_b32 s20, s20, 16
+; SI-NEXT: s_lshl_b32 s21, s21, 16
; SI-NEXT: s_and_b32 s14, s14, 0xffff
-; SI-NEXT: s_or_b32 s15, s15, s20
-; SI-NEXT: s_add_i32 s30, s38, 3
+; SI-NEXT: s_or_b32 s15, s15, s21
+; SI-NEXT: s_add_i32 s91, s91, 3
; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: s_and_b32 s15, s30, 0xff
-; SI-NEXT: s_lshl_b32 s20, s28, 8
-; SI-NEXT: s_add_i32 s92, s93, 3
-; SI-NEXT: s_or_b32 s15, s20, s15
-; SI-NEXT: s_and_b32 s21, s92, 0xff
+; SI-NEXT: s_and_b32 s15, s91, 0xff
+; SI-NEXT: s_lshl_b32 s21, s92, 8
+; SI-NEXT: s_add_i32 s89, s89, 3
+; SI-NEXT: s_or_b32 s15, s21, s15
+; SI-NEXT: s_and_b32 s22, s89, 0xff
; SI-NEXT: s_addk_i32 s15, 0x300
-; SI-NEXT: s_lshl_b32 s20, s29, 24
-; SI-NEXT: s_lshl_b32 s21, s21, 16
+; SI-NEXT: s_lshl_b32 s21, s20, 24
+; SI-NEXT: s_lshl_b32 s22, s22, 16
+; SI-NEXT: s_add_i32 s16, s44, 3
; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_or_b32 s20, s20, s21
-; SI-NEXT: s_add_i32 s24, s24, 3
-; SI-NEXT: s_or_b32 s15, s20, s15
-; SI-NEXT: s_and_b32 s20, s24, 0xff
-; SI-NEXT: s_lshl_b32 s21, s25, 8
-; SI-NEXT: s_add_i32 s26, s26, 3
-; SI-NEXT: s_or_b32 s20, s21, s20
-; SI-NEXT: s_and_b32 s24, s26, 0xff
-; SI-NEXT: s_add_i32 s16, s31, 3
-; SI-NEXT: s_addk_i32 s20, 0x300
-; SI-NEXT: s_lshl_b32 s21, s27, 24
-; SI-NEXT: s_lshl_b32 s24, s24, 16
+; SI-NEXT: s_or_b32 s21, s21, s22
+; SI-NEXT: s_add_i32 s24, s29, 3
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_and_b32 s20, s20, 0xffff
-; SI-NEXT: s_or_b32 s21, s21, s24
+; SI-NEXT: s_or_b32 s15, s21, s15
+; SI-NEXT: s_and_b32 s21, s24, 0xff
+; SI-NEXT: s_lshl_b32 s22, s85, 8
+; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_or_b32 s20, s21, s20
+; SI-NEXT: s_or_b32 s21, s22, s21
+; SI-NEXT: s_and_b32 s20, s26, 0xff
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s19, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_add_i32 s40, s20, 0x3000000
-; SI-NEXT: v_readlane_b32 s20, v41, 1
+; SI-NEXT: s_addk_i32 s21, 0x300
+; SI-NEXT: s_lshl_b32 s22, s27, 24
+; SI-NEXT: s_lshl_b32 s20, s20, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_add_i32 s28, s20, 3
-; SI-NEXT: v_readlane_b32 s21, v41, 0
+; SI-NEXT: s_and_b32 s21, s21, 0xffff
+; SI-NEXT: s_or_b32 s22, s22, s20
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_and_b32 s20, s28, 0xff
-; SI-NEXT: s_lshl_b32 s21, s21, 8
+; SI-NEXT: s_or_b32 s21, s22, s21
+; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s42, s16, 0x3000000
-; SI-NEXT: v_readlane_b32 s16, v41, 5
-; SI-NEXT: s_or_b32 s20, s21, s20
-; SI-NEXT: s_lshl_b32 s21, s90, 24
-; SI-NEXT: s_add_i32 s90, s91, 3
+; SI-NEXT: v_readlane_b32 s16, v44, 3
+; SI-NEXT: s_add_i32 s40, s21, 0x3000000
+; SI-NEXT: s_and_b32 s21, s28, 0xff
+; SI-NEXT: s_lshl_b32 s22, s82, 8
+; SI-NEXT: s_add_i32 s79, s90, 3
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v41, 4
-; SI-NEXT: v_readlane_b32 s18, v41, 3
-; SI-NEXT: s_and_b32 s24, s90, 0xff
+; SI-NEXT: v_readlane_b32 s17, v44, 2
+; SI-NEXT: v_readlane_b32 s18, v44, 1
+; SI-NEXT: s_or_b32 s21, s22, s21
+; SI-NEXT: s_and_b32 s22, s79, 0xff
; SI-NEXT: s_and_b32 s16, s16, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 8
; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_addk_i32 s20, 0x300
-; SI-NEXT: s_lshl_b32 s24, s24, 16
+; SI-NEXT: s_addk_i32 s21, 0x300
+; SI-NEXT: s_lshl_b32 s20, s54, 24
+; SI-NEXT: s_lshl_b32 s22, s22, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: v_readlane_b32 s17, v41, 2
+; SI-NEXT: v_readlane_b32 s17, v44, 0
; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_and_b32 s20, s20, 0xffff
-; SI-NEXT: s_or_b32 s21, s21, s24
+; SI-NEXT: s_and_b32 s21, s21, 0xffff
+; SI-NEXT: s_or_b32 s20, s20, s22
; SI-NEXT: s_addk_i32 s16, 0x300
; SI-NEXT: s_lshl_b32 s17, s17, 24
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_or_b32 s20, s21, s20
+; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
@@ -83025,21 +83042,22 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_add_i32 s9, s9, 0x3000000
; SI-NEXT: s_add_i32 s10, s10, 0x3000000
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
-; SI-NEXT: s_add_i32 s41, s20, 0x3000000
-; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
; SI-NEXT: s_add_i32 s13, s13, 0x3000000
; SI-NEXT: s_add_i32 s14, s14, 0x3000000
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
+; SI-NEXT: s_add_i32 s41, s20, 0x3000000
+; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s43, s16, 0x3000000
-; SI-NEXT: s_lshr_b64 s[56:57], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
+; SI-NEXT: s_lshr_b64 s[58:59], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[22:23], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[54:55], s[14:15], 16
-; SI-NEXT: s_lshr_b64 s[92:93], s[12:13], 16
+; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v44, s16, 9
; SI-NEXT: s_lshr_b32 s47, s43, 16
; SI-NEXT: s_lshr_b32 s57, s41, 16
; SI-NEXT: s_lshr_b32 s59, s15, 16
@@ -83048,27 +83066,32 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_lshr_b32 s73, s9, 16
; SI-NEXT: s_lshr_b32 s75, s7, 16
; SI-NEXT: s_lshr_b32 s45, s5, 16
+; SI-NEXT: v_writelane_b32 v44, s17, 10
; SI-NEXT: .LBB107_5: ; %end
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_and_b32 s16, s42, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s22, 16
+; SI-NEXT: s_lshl_b32 s17, s76, 16
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s43, 0xffff
; SI-NEXT: s_lshl_b32 s18, s47, 16
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s40, 0xffff
-; SI-NEXT: s_lshl_b32 s19, s56, 16
+; SI-NEXT: s_lshl_b32 s19, s46, 16
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s41, 0xffff
; SI-NEXT: s_lshl_b32 s20, s57, 16
; SI-NEXT: s_or_b32 s19, s19, s20
+; SI-NEXT: v_readlane_b32 s20, v44, 9
; SI-NEXT: s_and_b32 s14, s14, 0xffff
-; SI-NEXT: s_lshl_b32 s20, s54, 16
+; SI-NEXT: s_lshl_b32 s20, s20, 16
; SI-NEXT: s_or_b32 s14, s14, s20
; SI-NEXT: s_and_b32 s15, s15, 0xffff
; SI-NEXT: s_lshl_b32 s20, s59, 16
; SI-NEXT: s_or_b32 s15, s15, s20
; SI-NEXT: s_and_b32 s12, s12, 0xffff
-; SI-NEXT: s_lshl_b32 s20, s92, 16
+; SI-NEXT: s_lshl_b32 s20, s58, 16
; SI-NEXT: s_or_b32 s12, s12, s20
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_lshl_b32 s20, s61, 16
@@ -83097,7 +83120,8 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s20, s45, 16
; SI-NEXT: s_or_b32 s5, s5, s20
-; SI-NEXT: v_readlane_b32 s30, v40, 34
+; SI-NEXT: v_readlane_b32 s30, v43, 34
+; SI-NEXT: v_readlane_b32 s21, v44, 10
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
@@ -83114,44 +83138,44 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: v_mov_b32_e32 v13, s7
; SI-NEXT: v_mov_b32_e32 v14, s4
; SI-NEXT: v_mov_b32_e32 v15, s5
-; SI-NEXT: v_readlane_b32 s31, v40, 35
-; SI-NEXT: v_readlane_b32 s99, v40, 33
-; SI-NEXT: v_readlane_b32 s98, v40, 32
-; SI-NEXT: v_readlane_b32 s97, v40, 31
-; SI-NEXT: v_readlane_b32 s96, v40, 30
-; SI-NEXT: v_readlane_b32 s87, v40, 29
-; SI-NEXT: v_readlane_b32 s86, v40, 28
-; SI-NEXT: v_readlane_b32 s85, v40, 27
-; SI-NEXT: v_readlane_b32 s84, v40, 26
-; SI-NEXT: v_readlane_b32 s83, v40, 25
-; SI-NEXT: v_readlane_b32 s82, v40, 24
-; SI-NEXT: v_readlane_b32 s81, v40, 23
-; SI-NEXT: v_readlane_b32 s80, v40, 22
-; SI-NEXT: v_readlane_b32 s71, v40, 21
-; SI-NEXT: v_readlane_b32 s70, v40, 20
-; SI-NEXT: v_readlane_b32 s69, v40, 19
-; SI-NEXT: v_readlane_b32 s68, v40, 18
-; SI-NEXT: v_readlane_b32 s67, v40, 17
-; SI-NEXT: v_readlane_b32 s66, v40, 16
-; SI-NEXT: v_readlane_b32 s65, v40, 15
-; SI-NEXT: v_readlane_b32 s64, v40, 14
-; SI-NEXT: v_readlane_b32 s55, v40, 13
-; SI-NEXT: v_readlane_b32 s54, v40, 12
-; SI-NEXT: v_readlane_b32 s53, v40, 11
-; SI-NEXT: v_readlane_b32 s52, v40, 10
-; SI-NEXT: v_readlane_b32 s51, v40, 9
-; SI-NEXT: v_readlane_b32 s50, v40, 8
-; SI-NEXT: v_readlane_b32 s49, v40, 7
-; SI-NEXT: v_readlane_b32 s48, v40, 6
-; SI-NEXT: v_readlane_b32 s39, v40, 5
-; SI-NEXT: v_readlane_b32 s38, v40, 4
-; SI-NEXT: v_readlane_b32 s37, v40, 3
-; SI-NEXT: v_readlane_b32 s36, v40, 2
-; SI-NEXT: v_readlane_b32 s35, v40, 1
-; SI-NEXT: v_readlane_b32 s34, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v43, 35
+; SI-NEXT: v_readlane_b32 s99, v43, 33
+; SI-NEXT: v_readlane_b32 s98, v43, 32
+; SI-NEXT: v_readlane_b32 s97, v43, 31
+; SI-NEXT: v_readlane_b32 s96, v43, 30
+; SI-NEXT: v_readlane_b32 s87, v43, 29
+; SI-NEXT: v_readlane_b32 s86, v43, 28
+; SI-NEXT: v_readlane_b32 s85, v43, 27
+; SI-NEXT: v_readlane_b32 s84, v43, 26
+; SI-NEXT: v_readlane_b32 s83, v43, 25
+; SI-NEXT: v_readlane_b32 s82, v43, 24
+; SI-NEXT: v_readlane_b32 s81, v43, 23
+; SI-NEXT: v_readlane_b32 s80, v43, 22
+; SI-NEXT: v_readlane_b32 s71, v43, 21
+; SI-NEXT: v_readlane_b32 s70, v43, 20
+; SI-NEXT: v_readlane_b32 s69, v43, 19
+; SI-NEXT: v_readlane_b32 s68, v43, 18
+; SI-NEXT: v_readlane_b32 s67, v43, 17
+; SI-NEXT: v_readlane_b32 s66, v43, 16
+; SI-NEXT: v_readlane_b32 s65, v43, 15
+; SI-NEXT: v_readlane_b32 s64, v43, 14
+; SI-NEXT: v_readlane_b32 s55, v43, 13
+; SI-NEXT: v_readlane_b32 s54, v43, 12
+; SI-NEXT: v_readlane_b32 s53, v43, 11
+; SI-NEXT: v_readlane_b32 s52, v43, 10
+; SI-NEXT: v_readlane_b32 s51, v43, 9
+; SI-NEXT: v_readlane_b32 s50, v43, 8
+; SI-NEXT: v_readlane_b32 s49, v43, 7
+; SI-NEXT: v_readlane_b32 s48, v43, 6
+; SI-NEXT: v_readlane_b32 s39, v43, 5
+; SI-NEXT: v_readlane_b32 s38, v43, 4
+; SI-NEXT: v_readlane_b32 s37, v43, 3
+; SI-NEXT: v_readlane_b32 s36, v43, 2
+; SI-NEXT: v_readlane_b32 s35, v43, 1
+; SI-NEXT: v_readlane_b32 s34, v43, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -93172,238 +93196,243 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_writelane_b32 v43, s34, 0
+; SI-NEXT: v_writelane_b32 v43, s35, 1
+; SI-NEXT: v_writelane_b32 v43, s36, 2
+; SI-NEXT: v_writelane_b32 v43, s37, 3
+; SI-NEXT: v_writelane_b32 v43, s38, 4
+; SI-NEXT: v_writelane_b32 v43, s39, 5
+; SI-NEXT: v_writelane_b32 v43, s48, 6
+; SI-NEXT: v_writelane_b32 v43, s49, 7
+; SI-NEXT: v_writelane_b32 v43, s50, 8
+; SI-NEXT: v_writelane_b32 v43, s51, 9
+; SI-NEXT: v_writelane_b32 v43, s52, 10
+; SI-NEXT: v_writelane_b32 v43, s53, 11
+; SI-NEXT: v_writelane_b32 v43, s54, 12
+; SI-NEXT: v_writelane_b32 v43, s55, 13
+; SI-NEXT: v_writelane_b32 v43, s64, 14
+; SI-NEXT: v_writelane_b32 v43, s65, 15
+; SI-NEXT: v_writelane_b32 v43, s66, 16
+; SI-NEXT: v_writelane_b32 v43, s67, 17
+; SI-NEXT: v_writelane_b32 v43, s68, 18
+; SI-NEXT: v_writelane_b32 v43, s69, 19
+; SI-NEXT: v_writelane_b32 v43, s70, 20
+; SI-NEXT: v_writelane_b32 v43, s71, 21
+; SI-NEXT: v_writelane_b32 v43, s80, 22
+; SI-NEXT: v_writelane_b32 v43, s81, 23
+; SI-NEXT: v_writelane_b32 v43, s82, 24
+; SI-NEXT: v_writelane_b32 v43, s83, 25
+; SI-NEXT: v_writelane_b32 v43, s84, 26
+; SI-NEXT: v_writelane_b32 v43, s85, 27
+; SI-NEXT: v_writelane_b32 v43, s86, 28
+; SI-NEXT: v_writelane_b32 v43, s87, 29
+; SI-NEXT: v_writelane_b32 v43, s96, 30
+; SI-NEXT: v_writelane_b32 v43, s97, 31
+; SI-NEXT: v_writelane_b32 v43, s98, 32
+; SI-NEXT: v_writelane_b32 v43, s99, 33
+; SI-NEXT: v_writelane_b32 v43, s30, 34
+; SI-NEXT: v_writelane_b32 v43, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v40, s34, 0
-; SI-NEXT: v_writelane_b32 v40, s35, 1
-; SI-NEXT: v_writelane_b32 v40, s36, 2
-; SI-NEXT: v_writelane_b32 v40, s37, 3
-; SI-NEXT: v_writelane_b32 v40, s38, 4
-; SI-NEXT: v_writelane_b32 v40, s39, 5
-; SI-NEXT: v_writelane_b32 v40, s48, 6
-; SI-NEXT: v_writelane_b32 v40, s49, 7
-; SI-NEXT: v_writelane_b32 v40, s50, 8
-; SI-NEXT: v_writelane_b32 v40, s51, 9
-; SI-NEXT: v_writelane_b32 v40, s52, 10
-; SI-NEXT: v_writelane_b32 v40, s53, 11
-; SI-NEXT: v_writelane_b32 v40, s54, 12
-; SI-NEXT: v_writelane_b32 v40, s55, 13
-; SI-NEXT: v_writelane_b32 v40, s64, 14
-; SI-NEXT: v_writelane_b32 v40, s65, 15
-; SI-NEXT: v_writelane_b32 v40, s66, 16
-; SI-NEXT: v_writelane_b32 v40, s67, 17
-; SI-NEXT: v_writelane_b32 v40, s68, 18
-; SI-NEXT: v_writelane_b32 v40, s69, 19
-; SI-NEXT: v_writelane_b32 v40, s70, 20
-; SI-NEXT: v_writelane_b32 v40, s71, 21
-; SI-NEXT: v_writelane_b32 v40, s80, 22
-; SI-NEXT: v_writelane_b32 v40, s81, 23
-; SI-NEXT: v_writelane_b32 v40, s82, 24
-; SI-NEXT: v_writelane_b32 v40, s83, 25
-; SI-NEXT: v_writelane_b32 v40, s84, 26
-; SI-NEXT: v_writelane_b32 v40, s85, 27
-; SI-NEXT: v_writelane_b32 v40, s86, 28
-; SI-NEXT: v_writelane_b32 v40, s87, 29
-; SI-NEXT: v_writelane_b32 v40, s96, 30
-; SI-NEXT: v_writelane_b32 v40, s97, 31
-; SI-NEXT: v_writelane_b32 v40, s98, 32
-; SI-NEXT: v_writelane_b32 v40, s99, 33
-; SI-NEXT: v_writelane_b32 v40, s30, 34
-; SI-NEXT: v_writelane_b32 v40, s31, 35
-; SI-NEXT: s_mov_b32 s6, s19
-; SI-NEXT: v_readfirstlane_b32 s19, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76
-; SI-NEXT: v_readfirstlane_b32 s8, v30
-; SI-NEXT: v_readfirstlane_b32 s37, v29
-; SI-NEXT: v_readfirstlane_b32 s47, v27
-; SI-NEXT: v_readfirstlane_b32 s56, v26
-; SI-NEXT: v_readfirstlane_b32 s13, v25
-; SI-NEXT: v_readfirstlane_b32 s14, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
-; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
-; SI-NEXT: v_readfirstlane_b32 s75, v23
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v41, s18, 0
-; SI-NEXT: v_writelane_b32 v41, s6, 1
-; SI-NEXT: v_writelane_b32 v41, s17, 2
-; SI-NEXT: v_writelane_b32 v41, s16, 3
-; SI-NEXT: v_writelane_b32 v41, s22, 4
-; SI-NEXT: v_writelane_b32 v41, s23, 5
-; SI-NEXT: v_writelane_b32 v41, s21, 6
-; SI-NEXT: v_writelane_b32 v41, s20, 7
-; SI-NEXT: v_writelane_b32 v41, s26, 8
-; SI-NEXT: v_writelane_b32 v41, s27, 9
-; SI-NEXT: v_writelane_b32 v41, s25, 10
-; SI-NEXT: v_writelane_b32 v41, s24, 11
-; SI-NEXT: v_writelane_b32 v41, s29, 12
-; SI-NEXT: v_readfirstlane_b32 s76, v22
-; SI-NEXT: v_readfirstlane_b32 s62, v21
-; SI-NEXT: v_readfirstlane_b32 s63, v20
-; SI-NEXT: v_readfirstlane_b32 s73, v19
-; SI-NEXT: v_readfirstlane_b32 s74, v18
-; SI-NEXT: v_readfirstlane_b32 s58, v17
-; SI-NEXT: v_readfirstlane_b32 s59, v16
-; SI-NEXT: v_readfirstlane_b32 s61, v15
-; SI-NEXT: v_readfirstlane_b32 s72, v14
-; SI-NEXT: v_readfirstlane_b32 s44, v13
-; SI-NEXT: v_readfirstlane_b32 s45, v12
-; SI-NEXT: v_readfirstlane_b32 s57, v11
-; SI-NEXT: v_readfirstlane_b32 s60, v10
-; SI-NEXT: v_readfirstlane_b32 s40, v9
-; SI-NEXT: v_readfirstlane_b32 s41, v8
-; SI-NEXT: v_readfirstlane_b32 s43, v7
-; SI-NEXT: v_readfirstlane_b32 s46, v6
-; SI-NEXT: v_readfirstlane_b32 s11, v5
-; SI-NEXT: v_readfirstlane_b32 s12, v4
-; SI-NEXT: v_readfirstlane_b32 s15, v3
-; SI-NEXT: v_readfirstlane_b32 s42, v2
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32
+; SI-NEXT: ; implicit-def: $vgpr44 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s7, v1
-; SI-NEXT: v_readfirstlane_b32 s10, v0
-; SI-NEXT: v_writelane_b32 v41, s28, 13
-; SI-NEXT: v_writelane_b32 v41, s7, 14
+; SI-NEXT: v_writelane_b32 v44, s18, 0
+; SI-NEXT: v_writelane_b32 v44, s17, 1
+; SI-NEXT: v_writelane_b32 v44, s16, 2
+; SI-NEXT: v_writelane_b32 v44, s22, 3
+; SI-NEXT: v_writelane_b32 v44, s23, 4
+; SI-NEXT: v_writelane_b32 v44, s21, 5
+; SI-NEXT: v_writelane_b32 v44, s20, 6
+; SI-NEXT: v_writelane_b32 v44, s26, 7
+; SI-NEXT: v_writelane_b32 v44, s27, 8
+; SI-NEXT: v_writelane_b32 v44, s25, 9
+; SI-NEXT: v_writelane_b32 v44, s24, 10
+; SI-NEXT: v_writelane_b32 v44, s29, 11
+; SI-NEXT: v_writelane_b32 v44, s28, 12
+; SI-NEXT: s_mov_b32 s6, s19
+; SI-NEXT: v_readfirstlane_b32 s89, v30
+; SI-NEXT: v_readfirstlane_b32 s63, v29
+; SI-NEXT: v_readfirstlane_b32 s72, v28
+; SI-NEXT: v_readfirstlane_b32 s75, v27
+; SI-NEXT: v_readfirstlane_b32 s77, v26
+; SI-NEXT: v_readfirstlane_b32 s59, v25
+; SI-NEXT: v_readfirstlane_b32 s60, v24
+; SI-NEXT: v_readfirstlane_b32 s62, v23
+; SI-NEXT: v_readfirstlane_b32 s73, v22
+; SI-NEXT: v_readfirstlane_b32 s47, v21
+; SI-NEXT: v_readfirstlane_b32 s56, v20
+; SI-NEXT: v_readfirstlane_b32 s58, v19
+; SI-NEXT: v_readfirstlane_b32 s61, v18
+; SI-NEXT: v_readfirstlane_b32 s43, v17
+; SI-NEXT: v_readfirstlane_b32 s44, v16
+; SI-NEXT: v_readfirstlane_b32 s46, v15
+; SI-NEXT: v_readfirstlane_b32 s57, v14
+; SI-NEXT: v_readfirstlane_b32 s15, v13
+; SI-NEXT: v_readfirstlane_b32 s40, v12
+; SI-NEXT: v_readfirstlane_b32 s42, v11
+; SI-NEXT: v_readfirstlane_b32 s45, v10
+; SI-NEXT: v_readfirstlane_b32 s11, v9
+; SI-NEXT: v_readfirstlane_b32 s12, v8
+; SI-NEXT: v_readfirstlane_b32 s14, v7
+; SI-NEXT: v_readfirstlane_b32 s41, v6
+; SI-NEXT: v_readfirstlane_b32 s19, v5
+; SI-NEXT: v_readfirstlane_b32 s9, v4
+; SI-NEXT: v_readfirstlane_b32 s10, v3
+; SI-NEXT: v_readfirstlane_b32 s13, v2
+; SI-NEXT: v_readfirstlane_b32 s90, v0
+; SI-NEXT: v_writelane_b32 v44, s7, 13
+; SI-NEXT: v_writelane_b32 v44, s90, 14
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_readfirstlane_b32 s87, v24
-; SI-NEXT: v_readfirstlane_b32 s86, v25
-; SI-NEXT: v_readfirstlane_b32 s98, v26
-; SI-NEXT: v_readfirstlane_b32 s99, v27
-; SI-NEXT: v_readfirstlane_b32 s82, v29
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s87, v32
+; SI-NEXT: v_readfirstlane_b32 s86, v33
+; SI-NEXT: v_readfirstlane_b32 s98, v34
+; SI-NEXT: v_readfirstlane_b32 s99, v35
+; SI-NEXT: v_readfirstlane_b32 s82, v36
; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_readfirstlane_b32 s81, v30
+; SI-NEXT: v_readfirstlane_b32 s81, v37
; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_readfirstlane_b32 s84, v31
+; SI-NEXT: v_readfirstlane_b32 s84, v38
; SI-NEXT: s_waitcnt vmcnt(11)
-; SI-NEXT: v_readfirstlane_b32 s85, v32
+; SI-NEXT: v_readfirstlane_b32 s85, v39
; SI-NEXT: s_waitcnt vmcnt(10)
-; SI-NEXT: v_readfirstlane_b32 s68, v33
+; SI-NEXT: v_readfirstlane_b32 s68, v48
; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_readfirstlane_b32 s67, v34
+; SI-NEXT: v_readfirstlane_b32 s67, v49
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_readfirstlane_b32 s70, v35
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s70, v50
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_readfirstlane_b32 s80, v36
+; SI-NEXT: v_readfirstlane_b32 s80, v51
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_readfirstlane_b32 s53, v37
+; SI-NEXT: v_readfirstlane_b32 s53, v52
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_readfirstlane_b32 s52, v38
+; SI-NEXT: v_readfirstlane_b32 s52, v53
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_readfirstlane_b32 s64, v39
+; SI-NEXT: v_readfirstlane_b32 s64, v54
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_readfirstlane_b32 s66, v48
+; SI-NEXT: v_readfirstlane_b32 s66, v55
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_readfirstlane_b32 s48, v49
+; SI-NEXT: v_readfirstlane_b32 s48, v40
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_readfirstlane_b32 s39, v50
+; SI-NEXT: v_readfirstlane_b32 s39, v41
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s51, v51
+; SI-NEXT: v_readfirstlane_b32 s51, v42
; SI-NEXT: s_cbranch_scc0 .LBB111_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xff
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s5, s17, 24
-; SI-NEXT: s_or_b32 s77, s5, s4
+; SI-NEXT: s_or_b32 s74, s5, s4
; SI-NEXT: s_and_b32 s4, s18, 0xff
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_lshl_b32 s5, s6, 24
-; SI-NEXT: s_or_b32 s78, s5, s4
+; SI-NEXT: s_or_b32 s76, s5, s4
; SI-NEXT: s_and_b32 s4, s20, 0xff
; SI-NEXT: s_lshl_b32 s5, s21, 8
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: s_and_b32 s5, s22, 0xff
+; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s23, 24
-; SI-NEXT: s_or_b32 s88, s6, s5
+; SI-NEXT: s_or_b32 s79, s6, s5
; SI-NEXT: s_and_b32 s5, s24, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s25, 24
-; SI-NEXT: s_or_b32 s79, s6, s5
+; SI-NEXT: s_or_b32 s78, s6, s5
; SI-NEXT: s_and_b32 s5, s26, 0xff
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_lshl_b32 s6, s27, 24
-; SI-NEXT: s_or_b32 s89, s6, s5
+; SI-NEXT: s_or_b32 s88, s6, s5
; SI-NEXT: s_and_b32 s5, s28, 0xff
; SI-NEXT: s_lshl_b32 s6, s29, 8
; SI-NEXT: s_or_b32 s5, s5, s6
-; SI-NEXT: s_and_b32 s6, s10, 0xff
+; SI-NEXT: s_and_b32 s6, s90, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s7, s7, 24
; SI-NEXT: s_or_b32 s91, s7, s6
-; SI-NEXT: s_and_b32 s6, s42, 0xff
+; SI-NEXT: s_and_b32 s6, s13, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s7, s15, 24
+; SI-NEXT: s_lshl_b32 s7, s10, 24
; SI-NEXT: s_or_b32 s90, s7, s6
-; SI-NEXT: s_and_b32 s6, s12, 0xff
+; SI-NEXT: s_and_b32 s6, s9, 0xff
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_lshl_b32 s7, s11, 24
+; SI-NEXT: s_lshl_b32 s7, s19, 24
; SI-NEXT: s_or_b32 s92, s7, s6
-; SI-NEXT: s_and_b32 s6, s46, 0xff
-; SI-NEXT: s_lshl_b32 s7, s43, 8
+; SI-NEXT: s_and_b32 s6, s41, 0xff
+; SI-NEXT: s_lshl_b32 s7, s14, 8
; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: s_and_b32 s7, s41, 0xff
+; SI-NEXT: s_and_b32 s7, s12, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s40, 24
+; SI-NEXT: s_lshl_b32 s17, s11, 24
; SI-NEXT: s_or_b32 s94, s17, s7
-; SI-NEXT: s_and_b32 s7, s60, 0xff
+; SI-NEXT: s_and_b32 s7, s45, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s57, 24
+; SI-NEXT: s_lshl_b32 s17, s42, 24
; SI-NEXT: s_or_b32 s93, s17, s7
-; SI-NEXT: s_and_b32 s7, s45, 0xff
+; SI-NEXT: s_and_b32 s7, s40, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s44, 24
+; SI-NEXT: s_lshl_b32 s17, s15, 24
; SI-NEXT: s_or_b32 s95, s17, s7
-; SI-NEXT: s_and_b32 s7, s72, 0xff
-; SI-NEXT: s_lshl_b32 s17, s61, 8
+; SI-NEXT: s_and_b32 s7, s57, 0xff
+; SI-NEXT: s_lshl_b32 s17, s46, 8
; SI-NEXT: s_or_b32 vcc_lo, s7, s17
-; SI-NEXT: s_and_b32 s7, s59, 0xff
+; SI-NEXT: s_and_b32 s7, s44, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s58, 24
+; SI-NEXT: s_lshl_b32 s17, s43, 24
; SI-NEXT: s_or_b32 s31, s17, s7
-; SI-NEXT: s_and_b32 s7, s74, 0xff
+; SI-NEXT: s_and_b32 s7, s61, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s73, 24
+; SI-NEXT: s_lshl_b32 s17, s58, 24
; SI-NEXT: s_or_b32 s30, s17, s7
-; SI-NEXT: s_and_b32 s7, s63, 0xff
+; SI-NEXT: s_and_b32 s7, s56, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s62, 24
+; SI-NEXT: s_lshl_b32 s17, s47, 24
; SI-NEXT: s_or_b32 s34, s17, s7
-; SI-NEXT: s_and_b32 s7, s76, 0xff
-; SI-NEXT: s_lshl_b32 s17, s75, 8
+; SI-NEXT: s_and_b32 s7, s73, 0xff
+; SI-NEXT: s_lshl_b32 s17, s62, 8
; SI-NEXT: s_or_b32 vcc_hi, s7, s17
-; SI-NEXT: s_and_b32 s7, s14, 0xff
+; SI-NEXT: s_and_b32 s7, s60, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s13, 24
+; SI-NEXT: s_lshl_b32 s17, s59, 24
; SI-NEXT: s_or_b32 s36, s17, s7
-; SI-NEXT: s_and_b32 s7, s56, 0xff
+; SI-NEXT: s_and_b32 s7, s77, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s47, 24
+; SI-NEXT: s_lshl_b32 s17, s75, 24
; SI-NEXT: s_or_b32 s35, s17, s7
-; SI-NEXT: s_and_b32 s7, s19, 0xff
+; SI-NEXT: s_and_b32 s7, s72, 0xff
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_lshl_b32 s17, s37, 24
-; SI-NEXT: s_mov_b32 s9, s37
+; SI-NEXT: s_lshl_b32 s17, s63, 24
; SI-NEXT: s_or_b32 s37, s17, s7
-; SI-NEXT: s_and_b32 s7, s8, 0xff
+; SI-NEXT: s_and_b32 s7, s89, 0xff
; SI-NEXT: s_lshl_b32 s17, s51, 8
; SI-NEXT: s_or_b32 s71, s7, s17
; SI-NEXT: s_and_b32 s7, s39, 0xff
@@ -93498,205 +93527,206 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s7, s7, s17
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_add_i32 s8, s8, 3
+; SI-NEXT: s_add_i32 s89, s89, 3
; SI-NEXT: s_add_i32 vcc_hi, s6, 0x3000000
-; SI-NEXT: s_and_b32 s6, s8, 0xff
+; SI-NEXT: s_and_b32 s6, s89, 0xff
; SI-NEXT: s_lshl_b32 s7, s51, 8
; SI-NEXT: s_add_i32 s39, s39, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_and_b32 s8, s39, 0xff
+; SI-NEXT: s_and_b32 s17, s39, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
; SI-NEXT: s_lshl_b32 s7, s48, 24
-; SI-NEXT: s_lshl_b32 s8, s8, 16
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_and_b32 s6, s6, 0xffff
-; SI-NEXT: s_or_b32 s7, s7, s8
+; SI-NEXT: s_or_b32 s7, s7, s17
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_add_i32 s56, s56, 3
-; SI-NEXT: s_add_i32 s8, s6, 0x3000000
-; SI-NEXT: s_and_b32 s6, s56, 0xff
-; SI-NEXT: s_lshl_b32 s7, s47, 8
-; SI-NEXT: s_add_i32 s19, s19, 3
+; SI-NEXT: s_add_i32 s77, s77, 3
+; SI-NEXT: s_add_i32 s89, s6, 0x3000000
+; SI-NEXT: s_and_b32 s6, s77, 0xff
+; SI-NEXT: s_lshl_b32 s7, s75, 8
+; SI-NEXT: s_add_i32 s72, s72, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_and_b32 s16, s19, 0xff
+; SI-NEXT: s_and_b32 s17, s72, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
-; SI-NEXT: s_lshl_b32 s7, s9, 24
-; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: s_lshl_b32 s7, s63, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_and_b32 s6, s6, 0xffff
-; SI-NEXT: s_or_b32 s7, s7, s16
+; SI-NEXT: s_or_b32 s7, s7, s17
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_add_i32 s76, s76, 3
-; SI-NEXT: s_add_i32 s16, s6, 0x3000000
-; SI-NEXT: s_and_b32 s6, s76, 0xff
-; SI-NEXT: s_lshl_b32 s7, s75, 8
-; SI-NEXT: s_add_i32 s14, s14, 3
+; SI-NEXT: s_add_i32 s73, s73, 3
+; SI-NEXT: s_add_i32 s63, s6, 0x3000000
+; SI-NEXT: s_and_b32 s6, s73, 0xff
+; SI-NEXT: s_lshl_b32 s7, s62, 8
+; SI-NEXT: s_add_i32 s60, s60, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_lshl_b32 s7, s13, 24
-; SI-NEXT: s_and_b32 s13, s14, 0xff
+; SI-NEXT: s_and_b32 s17, s60, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
-; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_lshl_b32 s7, s59, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_and_b32 s6, s6, 0xffff
-; SI-NEXT: s_or_b32 s7, s7, s13
+; SI-NEXT: s_or_b32 s7, s7, s17
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_add_i32 s74, s74, 3
-; SI-NEXT: s_add_i32 s13, s6, 0x3000000
-; SI-NEXT: s_and_b32 s6, s74, 0xff
-; SI-NEXT: s_lshl_b32 s7, s73, 8
-; SI-NEXT: s_add_i32 s63, s63, 3
+; SI-NEXT: s_add_i32 s61, s61, 3
+; SI-NEXT: s_add_i32 s59, s6, 0x3000000
+; SI-NEXT: s_and_b32 s6, s61, 0xff
+; SI-NEXT: s_lshl_b32 s7, s58, 8
+; SI-NEXT: s_add_i32 s56, s56, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_and_b32 s14, s63, 0xff
+; SI-NEXT: s_and_b32 s17, s56, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
-; SI-NEXT: s_lshl_b32 s7, s62, 24
-; SI-NEXT: s_lshl_b32 s14, s14, 16
+; SI-NEXT: s_lshl_b32 s7, s47, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_and_b32 s6, s6, 0xffff
-; SI-NEXT: s_or_b32 s7, s7, s14
+; SI-NEXT: s_or_b32 s7, s7, s17
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_add_i32 s72, s72, 3
-; SI-NEXT: s_add_i32 s14, s6, 0x3000000
-; SI-NEXT: s_and_b32 s6, s72, 0xff
-; SI-NEXT: s_lshl_b32 s7, s61, 8
-; SI-NEXT: s_add_i32 s59, s59, 3
+; SI-NEXT: s_add_i32 s57, s57, 3
+; SI-NEXT: s_add_i32 s47, s6, 0x3000000
+; SI-NEXT: s_and_b32 s6, s57, 0xff
+; SI-NEXT: s_lshl_b32 s7, s46, 8
+; SI-NEXT: s_add_i32 s44, s44, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_and_b32 s17, s59, 0xff
+; SI-NEXT: s_and_b32 s17, s44, 0xff
; SI-NEXT: s_addk_i32 s6, 0x300
-; SI-NEXT: s_lshl_b32 s7, s58, 24
+; SI-NEXT: s_lshl_b32 s7, s43, 24
; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_or_b32 s7, s7, s17
-; SI-NEXT: s_add_i32 s60, s60, 3
-; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_and_b32 s7, s60, 0xff
-; SI-NEXT: s_lshl_b32 s17, s57, 8
; SI-NEXT: s_add_i32 s45, s45, 3
+; SI-NEXT: s_or_b32 s6, s7, s6
+; SI-NEXT: s_and_b32 s7, s45, 0xff
+; SI-NEXT: s_lshl_b32 s17, s42, 8
+; SI-NEXT: s_add_i32 s40, s40, 3
; SI-NEXT: s_or_b32 s7, s17, s7
-; SI-NEXT: s_and_b32 s18, s45, 0xff
+; SI-NEXT: s_and_b32 s17, s40, 0xff
; SI-NEXT: s_addk_i32 s7, 0x300
-; SI-NEXT: s_lshl_b32 s17, s44, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_lshl_b32 s15, s15, 24
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_or_b32 s7, s17, s7
-; SI-NEXT: s_add_i32 s46, s46, 3
-; SI-NEXT: s_add_i32 s19, s7, 0x3000000
-; SI-NEXT: s_and_b32 s7, s46, 0xff
-; SI-NEXT: s_lshl_b32 s17, s43, 8
+; SI-NEXT: s_or_b32 s15, s15, s17
+; SI-NEXT: s_or_b32 s7, s15, s7
; SI-NEXT: s_add_i32 s41, s41, 3
-; SI-NEXT: s_or_b32 s7, s17, s7
-; SI-NEXT: s_and_b32 s18, s41, 0xff
-; SI-NEXT: s_addk_i32 s7, 0x300
-; SI-NEXT: s_lshl_b32 s17, s40, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_add_i32 s42, s42, 3
-; SI-NEXT: s_or_b32 s7, s17, s7
-; SI-NEXT: s_and_b32 s17, s42, 0xff
-; SI-NEXT: s_lshl_b32 s15, s15, 8
+; SI-NEXT: s_add_i32 s15, s7, 0x3000000
+; SI-NEXT: s_and_b32 s7, s41, 0xff
+; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_add_i32 s12, s12, 3
-; SI-NEXT: s_or_b32 s15, s15, s17
+; SI-NEXT: s_or_b32 s7, s14, s7
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: s_addk_i32 s15, 0x300
+; SI-NEXT: s_addk_i32 s7, 0x300
; SI-NEXT: s_lshl_b32 s11, s11, 24
; SI-NEXT: s_lshl_b32 s12, s12, 16
-; SI-NEXT: s_and_b32 s15, s15, 0xffff
+; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_or_b32 s11, s11, s12
-; SI-NEXT: v_readlane_b32 s12, v41, 13
-; SI-NEXT: s_or_b32 s11, s11, s15
-; SI-NEXT: s_add_i32 s28, s12, 3
-; SI-NEXT: v_readlane_b32 s15, v41, 12
-; SI-NEXT: s_and_b32 s12, s28, 0xff
-; SI-NEXT: s_lshl_b32 s15, s15, 8
-; SI-NEXT: s_add_i32 s10, s10, 3
-; SI-NEXT: s_or_b32 s12, s15, s12
-; SI-NEXT: v_readlane_b32 s9, v41, 14
-; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: s_addk_i32 s12, 0x300
-; SI-NEXT: s_lshl_b32 s9, s9, 24
-; SI-NEXT: s_lshl_b32 s10, s10, 16
-; SI-NEXT: s_and_b32 s12, s12, 0xffff
-; SI-NEXT: s_or_b32 s9, s9, s10
-; SI-NEXT: v_readlane_b32 s10, v41, 11
-; SI-NEXT: s_or_b32 s9, s9, s12
+; SI-NEXT: s_add_i32 s13, s13, 3
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: s_and_b32 s11, s13, 0xff
+; SI-NEXT: s_lshl_b32 s10, s10, 8
+; SI-NEXT: s_add_i32 s9, s9, 3
+; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_and_b32 s9, s9, 0xff
+; SI-NEXT: s_mov_b32 s16, s8
+; SI-NEXT: s_addk_i32 s10, 0x300
+; SI-NEXT: s_lshl_b32 s8, s19, 24
+; SI-NEXT: s_lshl_b32 s9, s9, 16
+; SI-NEXT: s_and_b32 s10, s10, 0xffff
+; SI-NEXT: s_or_b32 s8, s8, s9
+; SI-NEXT: v_readlane_b32 s9, v44, 12
+; SI-NEXT: s_or_b32 s8, s8, s10
+; SI-NEXT: s_add_i32 s28, s9, 3
+; SI-NEXT: v_readlane_b32 s10, v44, 11
+; SI-NEXT: v_readlane_b32 s11, v44, 14
+; SI-NEXT: s_and_b32 s9, s28, 0xff
+; SI-NEXT: s_lshl_b32 s10, s10, 8
+; SI-NEXT: s_add_i32 s19, s11, 3
+; SI-NEXT: s_or_b32 s9, s10, s9
+; SI-NEXT: v_readlane_b32 s10, v44, 13
+; SI-NEXT: s_and_b32 s11, s19, 0xff
+; SI-NEXT: s_addk_i32 s9, 0x300
+; SI-NEXT: s_lshl_b32 s10, s10, 24
+; SI-NEXT: s_lshl_b32 s11, s11, 16
+; SI-NEXT: s_and_b32 s9, s9, 0xffff
+; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_or_b32 s9, s10, s9
+; SI-NEXT: v_readlane_b32 s10, v44, 10
; SI-NEXT: s_add_i32 s24, s10, 3
-; SI-NEXT: v_readlane_b32 s12, v41, 10
-; SI-NEXT: v_readlane_b32 s15, v41, 8
+; SI-NEXT: v_readlane_b32 s11, v44, 9
+; SI-NEXT: v_readlane_b32 s12, v44, 7
; SI-NEXT: s_and_b32 s10, s24, 0xff
-; SI-NEXT: s_lshl_b32 s12, s12, 8
-; SI-NEXT: s_add_i32 s26, s15, 3
-; SI-NEXT: s_or_b32 s10, s12, s10
-; SI-NEXT: v_readlane_b32 s12, v41, 9
-; SI-NEXT: s_and_b32 s15, s26, 0xff
+; SI-NEXT: s_lshl_b32 s11, s11, 8
+; SI-NEXT: s_add_i32 s26, s12, 3
+; SI-NEXT: s_or_b32 s10, s11, s10
+; SI-NEXT: v_readlane_b32 s11, v44, 8
+; SI-NEXT: s_and_b32 s12, s26, 0xff
; SI-NEXT: s_addk_i32 s10, 0x300
-; SI-NEXT: s_lshl_b32 s12, s12, 24
-; SI-NEXT: s_lshl_b32 s15, s15, 16
+; SI-NEXT: s_lshl_b32 s11, s11, 24
+; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_and_b32 s10, s10, 0xffff
-; SI-NEXT: s_or_b32 s12, s12, s15
-; SI-NEXT: s_or_b32 s10, s12, s10
-; SI-NEXT: v_readlane_b32 s12, v41, 7
-; SI-NEXT: s_add_i32 s20, s12, 3
-; SI-NEXT: v_readlane_b32 s15, v41, 6
-; SI-NEXT: v_readlane_b32 s17, v41, 4
-; SI-NEXT: s_and_b32 s12, s20, 0xff
-; SI-NEXT: s_lshl_b32 s15, s15, 8
-; SI-NEXT: s_add_i32 s22, s17, 3
-; SI-NEXT: s_or_b32 s12, s15, s12
-; SI-NEXT: v_readlane_b32 s15, v41, 5
-; SI-NEXT: s_and_b32 s17, s22, 0xff
+; SI-NEXT: s_or_b32 s11, s11, s12
+; SI-NEXT: s_or_b32 s10, s11, s10
+; SI-NEXT: v_readlane_b32 s11, v44, 6
+; SI-NEXT: s_add_i32 s20, s11, 3
+; SI-NEXT: v_readlane_b32 s12, v44, 5
+; SI-NEXT: v_readlane_b32 s13, v44, 3
+; SI-NEXT: s_and_b32 s11, s20, 0xff
+; SI-NEXT: s_lshl_b32 s12, s12, 8
+; SI-NEXT: s_add_i32 s22, s13, 3
+; SI-NEXT: s_or_b32 s11, s12, s11
+; SI-NEXT: v_readlane_b32 s12, v44, 4
+; SI-NEXT: s_and_b32 s13, s22, 0xff
+; SI-NEXT: s_addk_i32 s11, 0x300
+; SI-NEXT: s_lshl_b32 s12, s12, 24
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_and_b32 s11, s11, 0xffff
+; SI-NEXT: s_or_b32 s12, s12, s13
+; SI-NEXT: s_or_b32 s11, s12, s11
+; SI-NEXT: v_readlane_b32 s12, v44, 2
+; SI-NEXT: s_add_i32 s12, s12, 3
+; SI-NEXT: v_readlane_b32 s13, v44, 1
+; SI-NEXT: v_readlane_b32 s14, v44, 0
+; SI-NEXT: s_and_b32 s12, s12, 0xff
+; SI-NEXT: s_lshl_b32 s13, s13, 8
+; SI-NEXT: s_add_i32 s14, s14, 3
+; SI-NEXT: s_or_b32 s12, s13, s12
+; SI-NEXT: s_and_b32 s14, s14, 0xff
; SI-NEXT: s_addk_i32 s12, 0x300
-; SI-NEXT: s_lshl_b32 s15, s15, 24
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s13, s16, 24
+; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_and_b32 s12, s12, 0xffff
-; SI-NEXT: s_or_b32 s15, s15, s17
-; SI-NEXT: s_or_b32 s12, s15, s12
-; SI-NEXT: v_readlane_b32 s15, v41, 3
-; SI-NEXT: s_add_i32 s15, s15, 3
-; SI-NEXT: v_readlane_b32 s17, v41, 2
-; SI-NEXT: v_readlane_b32 s18, v41, 0
-; SI-NEXT: s_and_b32 s15, s15, 0xff
-; SI-NEXT: s_lshl_b32 s17, s17, 8
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_or_b32 s15, s17, s15
-; SI-NEXT: v_readlane_b32 s17, v41, 1
-; SI-NEXT: s_and_b32 s18, s18, 0xff
-; SI-NEXT: s_addk_i32 s15, 0x300
-; SI-NEXT: s_lshl_b32 s17, s17, 24
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_or_b32 s15, s17, s15
+; SI-NEXT: s_or_b32 s13, s13, s14
+; SI-NEXT: s_or_b32 s12, s13, s12
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
; SI-NEXT: s_add_i32 vcc_lo, vcc_lo, 0x3000000
; SI-NEXT: s_add_i32 s6, s6, 0x3000000
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
-; SI-NEXT: s_add_i32 s11, s11, 0x3000000
+; SI-NEXT: s_add_i32 s8, s8, 0x3000000
; SI-NEXT: s_add_i32 s9, s9, 0x3000000
; SI-NEXT: s_add_i32 s10, s10, 0x3000000
+; SI-NEXT: s_add_i32 s11, s11, 0x3000000
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
-; SI-NEXT: s_add_i32 s15, s15, 0x3000000
-; SI-NEXT: s_and_b32 s78, s15, 0xffff0000
-; SI-NEXT: s_lshl_b32 s77, s15, 16
-; SI-NEXT: s_and_b32 s88, s12, 0xffff0000
-; SI-NEXT: s_lshl_b32 s17, s12, 16
-; SI-NEXT: s_and_b32 s89, s10, 0xffff0000
-; SI-NEXT: s_lshl_b32 s79, s10, 16
+; SI-NEXT: s_and_b32 s76, s12, 0xffff0000
+; SI-NEXT: s_lshl_b32 s74, s12, 16
+; SI-NEXT: s_and_b32 s79, s11, 0xffff0000
+; SI-NEXT: s_lshl_b32 s17, s11, 16
+; SI-NEXT: s_and_b32 s88, s10, 0xffff0000
+; SI-NEXT: s_lshl_b32 s78, s10, 16
; SI-NEXT: s_and_b32 s91, s9, 0xffff0000
; SI-NEXT: s_lshl_b32 s18, s9, 16
-; SI-NEXT: s_and_b32 s92, s11, 0xffff0000
-; SI-NEXT: s_lshl_b32 s90, s11, 16
+; SI-NEXT: s_and_b32 s92, s8, 0xffff0000
+; SI-NEXT: s_lshl_b32 s90, s8, 16
; SI-NEXT: s_and_b32 s94, s7, 0xffff0000
; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_and_b32 s95, s19, 0xffff0000
-; SI-NEXT: s_lshl_b32 s93, s19, 16
+; SI-NEXT: s_and_b32 s95, s15, 0xffff0000
+; SI-NEXT: s_lshl_b32 s93, s15, 16
; SI-NEXT: s_and_b32 s31, s6, 0xffff0000
; SI-NEXT: s_lshl_b32 s6, s6, 16
-; SI-NEXT: s_and_b32 s34, s14, 0xffff0000
-; SI-NEXT: s_lshl_b32 s30, s14, 16
-; SI-NEXT: s_and_b32 s36, s13, 0xffff0000
-; SI-NEXT: s_lshl_b32 s97, s13, 16
-; SI-NEXT: s_and_b32 s37, s16, 0xffff0000
-; SI-NEXT: s_lshl_b32 s35, s16, 16
-; SI-NEXT: s_and_b32 s49, s8, 0xffff0000
-; SI-NEXT: s_lshl_b32 s96, s8, 16
+; SI-NEXT: s_and_b32 s34, s47, 0xffff0000
+; SI-NEXT: s_lshl_b32 s30, s47, 16
+; SI-NEXT: s_and_b32 s36, s59, 0xffff0000
+; SI-NEXT: s_lshl_b32 s97, s59, 16
+; SI-NEXT: s_and_b32 s37, s63, 0xffff0000
+; SI-NEXT: s_lshl_b32 s35, s63, 16
+; SI-NEXT: s_and_b32 s49, s89, 0xffff0000
+; SI-NEXT: s_lshl_b32 s96, s89, 16
; SI-NEXT: s_and_b32 s50, vcc_hi, 0xffff0000
; SI-NEXT: s_lshl_b32 s38, vcc_hi, 16
; SI-NEXT: s_and_b32 s55, vcc_lo, 0xffff0000
@@ -93706,17 +93736,20 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; SI-NEXT: s_and_b32 s69, s4, 0xffff0000
; SI-NEXT: s_lshl_b32 s71, s4, 16
; SI-NEXT: .LBB111_3: ; %end
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s78
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e64 v0, 1.0, s76
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; SI-NEXT: v_mul_f32_e64 v0, 1.0, s77
+; SI-NEXT: v_mul_f32_e64 v0, 1.0, s74
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
-; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88
+; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s89
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s88
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; SI-NEXT: v_mul_f32_e64 v2, 1.0, s79
+; SI-NEXT: v_mul_f32_e64 v2, 1.0, s78
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s91
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
@@ -93769,57 +93802,57 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s69
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s71
-; SI-NEXT: v_readlane_b32 s30, v40, 34
+; SI-NEXT: v_readlane_b32 s30, v43, 34
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
-; SI-NEXT: v_readlane_b32 s31, v40, 35
-; SI-NEXT: v_readlane_b32 s99, v40, 33
-; SI-NEXT: v_readlane_b32 s98, v40, 32
-; SI-NEXT: v_readlane_b32 s97, v40, 31
-; SI-NEXT: v_readlane_b32 s96, v40, 30
-; SI-NEXT: v_readlane_b32 s87, v40, 29
-; SI-NEXT: v_readlane_b32 s86, v40, 28
-; SI-NEXT: v_readlane_b32 s85, v40, 27
-; SI-NEXT: v_readlane_b32 s84, v40, 26
-; SI-NEXT: v_readlane_b32 s83, v40, 25
-; SI-NEXT: v_readlane_b32 s82, v40, 24
-; SI-NEXT: v_readlane_b32 s81, v40, 23
-; SI-NEXT: v_readlane_b32 s80, v40, 22
-; SI-NEXT: v_readlane_b32 s71, v40, 21
-; SI-NEXT: v_readlane_b32 s70, v40, 20
-; SI-NEXT: v_readlane_b32 s69, v40, 19
-; SI-NEXT: v_readlane_b32 s68, v40, 18
-; SI-NEXT: v_readlane_b32 s67, v40, 17
-; SI-NEXT: v_readlane_b32 s66, v40, 16
-; SI-NEXT: v_readlane_b32 s65, v40, 15
-; SI-NEXT: v_readlane_b32 s64, v40, 14
-; SI-NEXT: v_readlane_b32 s55, v40, 13
-; SI-NEXT: v_readlane_b32 s54, v40, 12
-; SI-NEXT: v_readlane_b32 s53, v40, 11
-; SI-NEXT: v_readlane_b32 s52, v40, 10
-; SI-NEXT: v_readlane_b32 s51, v40, 9
-; SI-NEXT: v_readlane_b32 s50, v40, 8
-; SI-NEXT: v_readlane_b32 s49, v40, 7
-; SI-NEXT: v_readlane_b32 s48, v40, 6
-; SI-NEXT: v_readlane_b32 s39, v40, 5
-; SI-NEXT: v_readlane_b32 s38, v40, 4
-; SI-NEXT: v_readlane_b32 s37, v40, 3
-; SI-NEXT: v_readlane_b32 s36, v40, 2
-; SI-NEXT: v_readlane_b32 s35, v40, 1
-; SI-NEXT: v_readlane_b32 s34, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v43, 35
+; SI-NEXT: v_readlane_b32 s99, v43, 33
+; SI-NEXT: v_readlane_b32 s98, v43, 32
+; SI-NEXT: v_readlane_b32 s97, v43, 31
+; SI-NEXT: v_readlane_b32 s96, v43, 30
+; SI-NEXT: v_readlane_b32 s87, v43, 29
+; SI-NEXT: v_readlane_b32 s86, v43, 28
+; SI-NEXT: v_readlane_b32 s85, v43, 27
+; SI-NEXT: v_readlane_b32 s84, v43, 26
+; SI-NEXT: v_readlane_b32 s83, v43, 25
+; SI-NEXT: v_readlane_b32 s82, v43, 24
+; SI-NEXT: v_readlane_b32 s81, v43, 23
+; SI-NEXT: v_readlane_b32 s80, v43, 22
+; SI-NEXT: v_readlane_b32 s71, v43, 21
+; SI-NEXT: v_readlane_b32 s70, v43, 20
+; SI-NEXT: v_readlane_b32 s69, v43, 19
+; SI-NEXT: v_readlane_b32 s68, v43, 18
+; SI-NEXT: v_readlane_b32 s67, v43, 17
+; SI-NEXT: v_readlane_b32 s66, v43, 16
+; SI-NEXT: v_readlane_b32 s65, v43, 15
+; SI-NEXT: v_readlane_b32 s64, v43, 14
+; SI-NEXT: v_readlane_b32 s55, v43, 13
+; SI-NEXT: v_readlane_b32 s54, v43, 12
+; SI-NEXT: v_readlane_b32 s53, v43, 11
+; SI-NEXT: v_readlane_b32 s52, v43, 10
+; SI-NEXT: v_readlane_b32 s51, v43, 9
+; SI-NEXT: v_readlane_b32 s50, v43, 8
+; SI-NEXT: v_readlane_b32 s49, v43, 7
+; SI-NEXT: v_readlane_b32 s48, v43, 6
+; SI-NEXT: v_readlane_b32 s39, v43, 5
+; SI-NEXT: v_readlane_b32 s38, v43, 4
+; SI-NEXT: v_readlane_b32 s37, v43, 3
+; SI-NEXT: v_readlane_b32 s36, v43, 2
+; SI-NEXT: v_readlane_b32 s35, v43, 1
+; SI-NEXT: v_readlane_b32 s34, v43, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB111_4:
-; SI-NEXT: s_mov_b32 s9, s37
-; SI-NEXT: ; implicit-def: $sgpr77
-; SI-NEXT: ; implicit-def: $sgpr78
+; SI-NEXT: s_mov_b32 s8, s6
+; SI-NEXT: ; implicit-def: $sgpr74
+; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr17
-; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr79
-; SI-NEXT: ; implicit-def: $sgpr89
+; SI-NEXT: ; implicit-def: $sgpr78
+; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr18
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr90
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
index b4ce52b6d90f7..332c550eaaccf 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
@@ -5998,17 +5998,17 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s83, 16
; VI-NEXT: s_or_b32 s36, s4, s5
+; VI-NEXT: s_and_b32 s4, 0xffff, s17
+; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s80, 16
-; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s82, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s71, 16
-; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s70, 16
@@ -6072,14 +6072,14 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s83, 16
+; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
+; VI-NEXT: s_add_i32 s36, s4, 0x30000
+; VI-NEXT: s_and_b32 s4, s17, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s82, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s16, s82, 16
-; VI-NEXT: s_or_b32 s5, s16, s5
; VI-NEXT: s_add_i32 s18, s18, 3
-; VI-NEXT: s_add_i32 s36, s4, 0x30000
-; VI-NEXT: s_add_i32 s37, s5, 0x30000
+; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -9639,17 +9639,17 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s83, 16
; VI-NEXT: s_or_b32 s36, s4, s5
+; VI-NEXT: s_and_b32 s4, 0xffff, s17
+; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s80, 16
-; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s82, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s71, 16
-; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s70, 16
@@ -15712,17 +15712,17 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s83, 16
; VI-NEXT: s_or_b32 s36, s4, s5
+; VI-NEXT: s_and_b32 s4, 0xffff, s17
+; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s80, 16
-; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s82, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s71, 16
-; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s70, 16
@@ -15786,14 +15786,14 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s83, 16
+; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
+; VI-NEXT: s_add_i32 s36, s4, 0x30000
+; VI-NEXT: s_and_b32 s4, s17, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s82, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s16, s82, 16
-; VI-NEXT: s_or_b32 s5, s16, s5
; VI-NEXT: s_add_i32 s18, s18, 3
-; VI-NEXT: s_add_i32 s36, s4, 0x30000
-; VI-NEXT: s_add_i32 s37, s5, 0x30000
+; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -19613,17 +19613,17 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s83, 16
; VI-NEXT: s_or_b32 s36, s4, s5
+; VI-NEXT: s_and_b32 s4, 0xffff, s17
+; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s80, 16
-; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s82, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s71, 16
-; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s70, 16
@@ -24105,17 +24105,17 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s83, 16
; VI-NEXT: s_or_b32 s36, s4, s5
+; VI-NEXT: s_and_b32 s4, 0xffff, s17
+; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s80, 16
-; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s82, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s71, 16
-; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s70, 16
@@ -24179,14 +24179,14 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s83, 16
+; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
+; VI-NEXT: s_add_i32 s36, s4, 0x30000
+; VI-NEXT: s_and_b32 s4, s17, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s82, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s16, s82, 16
-; VI-NEXT: s_or_b32 s5, s16, s5
; VI-NEXT: s_add_i32 s18, s18, 3
-; VI-NEXT: s_add_i32 s36, s4, 0x30000
-; VI-NEXT: s_add_i32 s37, s5, 0x30000
+; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -27758,17 +27758,17 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s83, 16
; VI-NEXT: s_or_b32 s36, s4, s5
+; VI-NEXT: s_and_b32 s4, 0xffff, s17
+; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s80, 16
-; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s82, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s71, 16
-; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s70, 16
@@ -31357,17 +31357,17 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s83, 16
; VI-NEXT: s_or_b32 s36, s4, s5
+; VI-NEXT: s_and_b32 s4, 0xffff, s17
+; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s80, 16
-; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s82, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s71, 16
-; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s70, 16
@@ -31431,14 +31431,14 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s83, 16
+; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
+; VI-NEXT: s_add_i32 s36, s4, 0x30000
+; VI-NEXT: s_and_b32 s4, s17, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s82, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s16, s82, 16
-; VI-NEXT: s_or_b32 s5, s16, s5
; VI-NEXT: s_add_i32 s18, s18, 3
-; VI-NEXT: s_add_i32 s36, s4, 0x30000
-; VI-NEXT: s_add_i32 s37, s5, 0x30000
+; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -35162,17 +35162,17 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s83, 16
; VI-NEXT: s_or_b32 s36, s4, s5
+; VI-NEXT: s_and_b32 s4, 0xffff, s17
+; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s80, 16
-; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s82, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s71, 16
-; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s70, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
index aa26aa9929db5..bae36084f83f9 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
@@ -6539,14 +6539,14 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
+; VI-NEXT: s_add_i32 s36, s4, 0x30000
+; VI-NEXT: s_and_b32 s4, s17, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s16, s86, 16
-; VI-NEXT: s_or_b32 s5, s16, s5
; VI-NEXT: s_add_i32 s18, s18, 3
-; VI-NEXT: s_add_i32 s36, s4, 0x30000
-; VI-NEXT: s_add_i32 s37, s5, 0x30000
+; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s85, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -17081,14 +17081,14 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
+; VI-NEXT: s_add_i32 s36, s4, 0x30000
+; VI-NEXT: s_and_b32 s4, s17, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s16, s86, 16
-; VI-NEXT: s_or_b32 s5, s16, s5
; VI-NEXT: s_add_i32 s18, s18, 3
-; VI-NEXT: s_add_i32 s36, s4, 0x30000
-; VI-NEXT: s_add_i32 s37, s5, 0x30000
+; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s85, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -26258,14 +26258,14 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
+; VI-NEXT: s_add_i32 s36, s4, 0x30000
+; VI-NEXT: s_and_b32 s4, s17, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s16, s86, 16
-; VI-NEXT: s_or_b32 s5, s16, s5
; VI-NEXT: s_add_i32 s18, s18, 3
-; VI-NEXT: s_add_i32 s36, s4, 0x30000
-; VI-NEXT: s_add_i32 s37, s5, 0x30000
+; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s85, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -34242,14 +34242,14 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
+; VI-NEXT: s_add_i32 s36, s4, 0x30000
+; VI-NEXT: s_and_b32 s4, s17, 0xffff
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s16, s86, 16
-; VI-NEXT: s_or_b32 s5, s16, s5
; VI-NEXT: s_add_i32 s18, s18, 3
-; VI-NEXT: s_add_i32 s36, s4, 0x30000
-; VI-NEXT: s_add_i32 s37, s5, 0x30000
+; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s85, 16
; VI-NEXT: s_or_b32 s4, s5, s4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
index 38b6122ec9e7d..47a80c7161aae 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
@@ -47098,15 +47098,18 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; SI-NEXT: v_writelane_b32 v30, s99, 33
; SI-NEXT: v_writelane_b32 v30, s30, 34
; SI-NEXT: v_writelane_b32 v30, s31, 35
+; SI-NEXT: ; implicit-def: $vgpr31 : SGPR spill to VGPR lane
; SI-NEXT: s_mov_b32 s35, s17
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v31, s18, 0
+; SI-NEXT: v_writelane_b32 v31, s20, 1
; SI-NEXT: s_mov_b32 s37, s16
-; SI-NEXT: s_lshr_b32 s4, s17, 16
-; SI-NEXT: ; implicit-def: $vgpr31 : SGPR spill to VGPR lane
+; SI-NEXT: s_lshr_b32 s78, s17, 16
; SI-NEXT: s_lshr_b32 s48, s16, 16
-; SI-NEXT: v_readfirstlane_b32 s70, v15
-; SI-NEXT: v_readfirstlane_b32 s16, v14
-; SI-NEXT: v_readfirstlane_b32 s74, v13
-; SI-NEXT: v_readfirstlane_b32 s75, v12
+; SI-NEXT: v_readfirstlane_b32 s74, v15
+; SI-NEXT: v_readfirstlane_b32 s75, v14
+; SI-NEXT: v_readfirstlane_b32 s70, v13
+; SI-NEXT: v_readfirstlane_b32 s16, v12
; SI-NEXT: v_readfirstlane_b32 s69, v11
; SI-NEXT: v_readfirstlane_b32 s17, v10
; SI-NEXT: v_readfirstlane_b32 s67, v9
@@ -47115,505 +47118,485 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s66, v6
; SI-NEXT: v_readfirstlane_b32 s96, v5
; SI-NEXT: v_readfirstlane_b32 s64, v4
-; SI-NEXT: v_readfirstlane_b32 s87, v3
-; SI-NEXT: v_readfirstlane_b32 s98, v2
-; SI-NEXT: v_readfirstlane_b32 s97, v1
+; SI-NEXT: v_readfirstlane_b32 s97, v3
+; SI-NEXT: v_readfirstlane_b32 s87, v2
+; SI-NEXT: v_readfirstlane_b32 s51, v1
; SI-NEXT: v_readfirstlane_b32 s99, v0
-; SI-NEXT: s_lshr_b32 s79, s29, 16
-; SI-NEXT: s_lshr_b32 s90, s28, 16
-; SI-NEXT: s_lshr_b32 s31, s27, 16
-; SI-NEXT: s_lshr_b32 s88, s26, 16
-; SI-NEXT: s_lshr_b32 s95, s25, 16
-; SI-NEXT: s_lshr_b32 s78, s24, 16
-; SI-NEXT: s_lshr_b32 s93, s23, 16
-; SI-NEXT: s_lshr_b32 s76, s22, 16
-; SI-NEXT: s_lshr_b32 s91, s21, 16
-; SI-NEXT: s_lshr_b32 s51, s20, 16
-; SI-NEXT: s_lshr_b32 s89, s19, 16
-; SI-NEXT: s_lshr_b32 s77, s18, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v31, s4, 0
-; SI-NEXT: s_lshr_b32 s84, s70, 16
-; SI-NEXT: s_lshr_b32 s60, s16, 16
+; SI-NEXT: v_writelane_b32 v31, s22, 2
+; SI-NEXT: s_lshr_b32 s31, s29, 16
+; SI-NEXT: s_lshr_b32 s76, s28, 16
+; SI-NEXT: s_lshr_b32 s30, s27, 16
+; SI-NEXT: s_lshr_b32 s84, s26, 16
+; SI-NEXT: s_lshr_b32 s94, s25, 16
+; SI-NEXT: s_lshr_b32 s55, s24, 16
+; SI-NEXT: s_lshr_b32 s92, s23, 16
+; SI-NEXT: s_lshr_b32 s54, s22, 16
+; SI-NEXT: s_lshr_b32 s90, s21, 16
+; SI-NEXT: s_lshr_b32 s52, s20, 16
+; SI-NEXT: s_lshr_b32 s88, s19, 16
+; SI-NEXT: s_lshr_b32 s50, s18, 16
; SI-NEXT: s_lshr_b32 s86, s74, 16
-; SI-NEXT: s_lshr_b32 s49, s75, 16
-; SI-NEXT: s_lshr_b32 s82, s69, 16
-; SI-NEXT: s_lshr_b32 s38, s17, 16
-; SI-NEXT: s_lshr_b32 s81, s67, 16
-; SI-NEXT: s_lshr_b32 s36, s68, 16
-; SI-NEXT: s_lshr_b32 s80, s65, 16
-; SI-NEXT: s_lshr_b32 s34, s66, 16
-; SI-NEXT: s_lshr_b32 s71, s96, 16
-; SI-NEXT: s_lshr_b32 s30, s64, 16
-; SI-NEXT: s_lshr_b32 s55, s87, 16
-; SI-NEXT: s_lshr_b32 s85, s98, 16
-; SI-NEXT: s_lshr_b32 s53, s97, 16
-; SI-NEXT: s_lshr_b32 s92, s99, 16
+; SI-NEXT: s_lshr_b32 s93, s75, 16
+; SI-NEXT: s_lshr_b32 s85, s70, 16
+; SI-NEXT: s_lshr_b32 s91, s16, 16
+; SI-NEXT: s_lshr_b32 s39, s69, 16
+; SI-NEXT: s_lshr_b32 s89, s17, 16
+; SI-NEXT: s_lshr_b32 s83, s67, 16
+; SI-NEXT: s_lshr_b32 s79, s68, 16
+; SI-NEXT: s_lshr_b32 s82, s65, 16
+; SI-NEXT: s_lshr_b32 s77, s66, 16
+; SI-NEXT: s_lshr_b32 s81, s96, 16
+; SI-NEXT: s_lshr_b32 s98, s64, 16
+; SI-NEXT: s_lshr_b32 s80, s97, 16
+; SI-NEXT: s_lshr_b32 s95, s87, 16
+; SI-NEXT: s_lshr_b32 s53, s51, 16
+; SI-NEXT: s_lshr_b32 s71, s99, 16
; SI-NEXT: v_readfirstlane_b32 s4, v16
+; SI-NEXT: v_writelane_b32 v31, s24, 3
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v31, s60, 1
+; SI-NEXT: v_writelane_b32 v31, s26, 4
+; SI-NEXT: v_writelane_b32 v31, s28, 5
; SI-NEXT: s_cbranch_scc0 .LBB57_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_readlane_b32 s7, v31, 0
; SI-NEXT: s_and_b32 s5, s35, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: s_or_b32 s57, s5, s7
+; SI-NEXT: s_lshl_b32 s7, s78, 16
+; SI-NEXT: s_or_b32 s73, s5, s7
; SI-NEXT: s_and_b32 s5, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s89, 16
-; SI-NEXT: s_or_b32 s47, s5, s7
+; SI-NEXT: s_lshl_b32 s7, s88, 16
+; SI-NEXT: s_or_b32 s63, s5, s7
; SI-NEXT: s_and_b32 s5, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s91, 16
-; SI-NEXT: s_or_b32 s45, s5, s7
+; SI-NEXT: s_lshl_b32 s7, s90, 16
+; SI-NEXT: s_or_b32 s61, s5, s7
; SI-NEXT: s_and_b32 s5, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s93, 16
-; SI-NEXT: s_or_b32 s43, s5, s7
+; SI-NEXT: s_lshl_b32 s7, s92, 16
+; SI-NEXT: s_or_b32 s59, s5, s7
; SI-NEXT: s_and_b32 s5, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s95, 16
-; SI-NEXT: s_or_b32 s41, s5, s7
+; SI-NEXT: s_lshl_b32 s7, s94, 16
+; SI-NEXT: s_or_b32 s57, s5, s7
; SI-NEXT: s_and_b32 s5, s27, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s30, 16
+; SI-NEXT: s_or_b32 s47, s5, s7
+; SI-NEXT: s_and_b32 s5, s29, 0xffff
; SI-NEXT: s_lshl_b32 s7, s31, 16
+; SI-NEXT: s_or_b32 s45, s5, s7
+; SI-NEXT: s_and_b32 s5, s51, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s53, 16
+; SI-NEXT: s_or_b32 s43, s5, s7
+; SI-NEXT: s_and_b32 s5, s97, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s80, 16
+; SI-NEXT: s_or_b32 s41, s5, s7
+; SI-NEXT: s_and_b32 s5, s96, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s81, 16
; SI-NEXT: s_or_b32 s15, s5, s7
-; SI-NEXT: s_and_b32 s5, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s79, 16
+; SI-NEXT: s_and_b32 s5, s65, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s82, 16
; SI-NEXT: s_or_b32 s13, s5, s7
-; SI-NEXT: s_and_b32 s5, s97, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s53, 16
+; SI-NEXT: s_and_b32 s5, s67, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s83, 16
; SI-NEXT: s_or_b32 s11, s5, s7
-; SI-NEXT: s_and_b32 s5, s87, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s55, 16
+; SI-NEXT: s_and_b32 s5, s69, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s39, 16
; SI-NEXT: s_or_b32 s9, s5, s7
-; SI-NEXT: s_and_b32 s5, s96, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s71, 16
+; SI-NEXT: s_and_b32 s5, s70, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s85, 16
+; SI-NEXT: s_and_b32 s4, s37, 0xffff
+; SI-NEXT: s_lshl_b32 s72, s48, 16
+; SI-NEXT: s_lshl_b32 s44, s76, 16
+; SI-NEXT: s_lshl_b32 s42, s71, 16
; SI-NEXT: s_or_b32 s7, s5, s7
-; SI-NEXT: s_and_b32 s5, s65, 0xffff
-; SI-NEXT: s_lshl_b32 s58, s80, 16
-; SI-NEXT: s_or_b32 s5, s5, s58
-; SI-NEXT: s_and_b32 s58, s67, 0xffff
-; SI-NEXT: s_lshl_b32 s59, s81, 16
-; SI-NEXT: s_or_b32 vcc_hi, s58, s59
-; SI-NEXT: s_and_b32 s58, s69, 0xffff
-; SI-NEXT: s_lshl_b32 s59, s82, 16
-; SI-NEXT: s_lshl_b32 s44, s51, 16
-; SI-NEXT: s_lshl_b32 s42, s76, 16
-; SI-NEXT: s_lshl_b32 s40, s78, 16
-; SI-NEXT: s_lshl_b32 s14, s88, 16
-; SI-NEXT: s_lshl_b32 s12, s90, 16
-; SI-NEXT: s_mov_b32 s94, s82
-; SI-NEXT: s_mov_b32 s82, s71
-; SI-NEXT: s_mov_b32 s71, s90
-; SI-NEXT: s_mov_b32 s90, s88
-; SI-NEXT: s_mov_b32 s88, s78
-; SI-NEXT: s_mov_b32 s78, s76
-; SI-NEXT: s_mov_b32 s76, s51
-; SI-NEXT: s_or_b32 s51, s58, s59
-; SI-NEXT: s_and_b32 s58, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s59, s86, 16
-; SI-NEXT: s_mov_b32 s83, s80
-; SI-NEXT: s_mov_b32 s80, s53
-; SI-NEXT: s_or_b32 s53, s58, s59
-; SI-NEXT: s_and_b32 s58, s70, 0xffff
-; SI-NEXT: s_lshl_b32 s59, s84, 16
-; SI-NEXT: s_lshl_b32 s56, s48, 16
-; SI-NEXT: s_lshl_b32 s10, s92, 16
-; SI-NEXT: s_lshl_b32 s6, s30, 16
-; SI-NEXT: s_lshl_b32 s4, s34, 16
-; SI-NEXT: s_lshl_b32 vcc_lo, s36, 16
-; SI-NEXT: s_lshl_b32 s50, s38, 16
-; SI-NEXT: s_mov_b32 s39, s38
-; SI-NEXT: s_mov_b32 s38, s36
-; SI-NEXT: s_mov_b32 s36, s34
-; SI-NEXT: s_mov_b32 s34, s30
-; SI-NEXT: s_mov_b32 s30, s84
-; SI-NEXT: s_mov_b32 s84, s81
-; SI-NEXT: s_mov_b32 s81, s92
-; SI-NEXT: s_mov_b32 s92, s55
-; SI-NEXT: s_or_b32 s55, s58, s59
-; SI-NEXT: s_and_b32 s58, s37, 0xffff
-; SI-NEXT: s_lshl_b32 s54, s60, 16
-; SI-NEXT: s_or_b32 s60, s58, s56
-; SI-NEXT: s_mov_b32 s61, s57
+; SI-NEXT: s_and_b32 s5, s74, 0xffff
+; SI-NEXT: s_mov_b32 s49, s71
+; SI-NEXT: s_mov_b32 s71, s76
+; SI-NEXT: s_lshl_b32 s76, s86, 16
+; SI-NEXT: s_or_b32 s4, s4, s72
+; SI-NEXT: s_or_b32 vcc_hi, s5, s76
+; SI-NEXT: s_mov_b32 s5, s73
+; SI-NEXT: s_lshr_b64 s[72:73], s[72:73], 16
+; SI-NEXT: v_writelane_b32 v31, s72, 6
+; SI-NEXT: s_lshl_b32 s62, s50, 16
+; SI-NEXT: v_writelane_b32 v31, s73, 7
+; SI-NEXT: s_and_b32 s72, s18, 0xffff
+; SI-NEXT: s_lshl_b32 s60, s52, 16
+; SI-NEXT: s_or_b32 s72, s72, s62
+; SI-NEXT: s_mov_b32 s76, s19
+; SI-NEXT: s_lshr_b64 s[18:19], s[62:63], 16
+; SI-NEXT: s_and_b32 s62, s20, 0xffff
+; SI-NEXT: s_mov_b32 s73, s63
+; SI-NEXT: s_or_b32 s62, s62, s60
+; SI-NEXT: s_mov_b32 s63, s61
+; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
+; SI-NEXT: v_writelane_b32 v31, s60, 8
+; SI-NEXT: s_lshl_b32 s58, s54, 16
+; SI-NEXT: v_writelane_b32 v31, s61, 9
+; SI-NEXT: s_and_b32 s60, s22, 0xffff
+; SI-NEXT: s_or_b32 s60, s60, s58
+; SI-NEXT: s_mov_b32 s61, s59
+; SI-NEXT: s_lshr_b64 s[58:59], s[58:59], 16
+; SI-NEXT: v_writelane_b32 v31, s58, 10
+; SI-NEXT: s_lshl_b32 s56, s55, 16
+; SI-NEXT: v_writelane_b32 v31, s59, 11
+; SI-NEXT: s_and_b32 s58, s24, 0xffff
+; SI-NEXT: s_or_b32 s58, s58, s56
+; SI-NEXT: s_mov_b32 s59, s57
; SI-NEXT: s_lshr_b64 s[56:57], s[56:57], 16
-; SI-NEXT: v_writelane_b32 v31, s56, 2
-; SI-NEXT: s_lshl_b32 s46, s77, 16
-; SI-NEXT: v_writelane_b32 v31, s57, 3
-; SI-NEXT: s_and_b32 s56, s18, 0xffff
-; SI-NEXT: s_or_b32 s72, s56, s46
-; SI-NEXT: s_mov_b32 s73, s47
+; SI-NEXT: v_writelane_b32 v31, s56, 12
+; SI-NEXT: s_lshl_b32 s46, s84, 16
+; SI-NEXT: v_writelane_b32 v31, s57, 13
+; SI-NEXT: s_and_b32 s56, s26, 0xffff
+; SI-NEXT: s_or_b32 s56, s56, s46
+; SI-NEXT: s_mov_b32 s57, s47
; SI-NEXT: s_lshr_b64 s[46:47], s[46:47], 16
-; SI-NEXT: v_writelane_b32 v31, s46, 4
-; SI-NEXT: v_writelane_b32 v31, s47, 5
-; SI-NEXT: s_and_b32 s46, s20, 0xffff
-; SI-NEXT: s_or_b32 s62, s46, s44
-; SI-NEXT: s_mov_b32 s63, s45
+; SI-NEXT: v_writelane_b32 v31, s46, 14
+; SI-NEXT: v_writelane_b32 v31, s47, 15
+; SI-NEXT: s_and_b32 s46, s28, 0xffff
+; SI-NEXT: s_or_b32 s46, s46, s44
+; SI-NEXT: s_mov_b32 s47, s45
; SI-NEXT: s_lshr_b64 s[44:45], s[44:45], 16
-; SI-NEXT: v_writelane_b32 v31, s44, 6
-; SI-NEXT: v_writelane_b32 v31, s45, 7
-; SI-NEXT: s_and_b32 s44, s22, 0xffff
-; SI-NEXT: s_or_b32 s58, s44, s42
-; SI-NEXT: s_mov_b32 s59, s43
+; SI-NEXT: v_writelane_b32 v31, s44, 16
+; SI-NEXT: v_writelane_b32 v31, s45, 17
+; SI-NEXT: s_and_b32 s44, s99, 0xffff
+; SI-NEXT: s_or_b32 s44, s44, s42
+; SI-NEXT: s_mov_b32 s45, s43
; SI-NEXT: s_lshr_b64 s[42:43], s[42:43], 16
-; SI-NEXT: v_writelane_b32 v31, s42, 8
-; SI-NEXT: v_writelane_b32 v31, s43, 9
-; SI-NEXT: s_and_b32 s42, s24, 0xffff
-; SI-NEXT: s_or_b32 s56, s42, s40
-; SI-NEXT: s_mov_b32 s57, s41
-; SI-NEXT: s_lshr_b64 s[40:41], s[40:41], 16
-; SI-NEXT: v_writelane_b32 v31, s40, 10
-; SI-NEXT: v_writelane_b32 v31, s41, 11
-; SI-NEXT: s_and_b32 s40, s26, 0xffff
-; SI-NEXT: s_or_b32 s46, s40, s14
-; SI-NEXT: s_mov_b32 s47, s15
-; SI-NEXT: s_lshr_b64 s[14:15], s[14:15], 16
-; SI-NEXT: v_writelane_b32 v31, s14, 12
-; SI-NEXT: v_writelane_b32 v31, s15, 13
-; SI-NEXT: s_and_b32 s14, s28, 0xffff
-; SI-NEXT: s_or_b32 s44, s14, s12
-; SI-NEXT: s_mov_b32 s45, s13
+; SI-NEXT: v_writelane_b32 v31, s42, 18
+; SI-NEXT: s_lshl_b32 s40, s95, 16
+; SI-NEXT: v_writelane_b32 v31, s43, 19
+; SI-NEXT: s_and_b32 s42, s87, 0xffff
+; SI-NEXT: s_lshl_b32 s14, s98, 16
+; SI-NEXT: s_or_b32 s42, s42, s40
+; SI-NEXT: s_mov_b32 s36, s35
+; SI-NEXT: s_lshr_b64 s[34:35], s[40:41], 16
+; SI-NEXT: s_and_b32 s40, s64, 0xffff
+; SI-NEXT: s_lshl_b32 s12, s77, 16
+; SI-NEXT: s_mov_b32 s35, s36
+; SI-NEXT: s_or_b32 s40, s40, s14
+; SI-NEXT: s_mov_b32 s38, s37
+; SI-NEXT: s_lshr_b64 s[36:37], s[14:15], 16
+; SI-NEXT: s_and_b32 s14, s66, 0xffff
+; SI-NEXT: s_mov_b32 s43, s41
+; SI-NEXT: s_mov_b32 s41, s15
+; SI-NEXT: s_or_b32 s14, s14, s12
+; SI-NEXT: s_mov_b32 s15, s13
; SI-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
-; SI-NEXT: v_writelane_b32 v31, s12, 14
-; SI-NEXT: v_writelane_b32 v31, s13, 15
-; SI-NEXT: s_and_b32 s12, s99, 0xffff
-; SI-NEXT: s_or_b32 s42, s12, s10
-; SI-NEXT: s_mov_b32 s43, s11
+; SI-NEXT: v_writelane_b32 v31, s12, 20
+; SI-NEXT: s_lshl_b32 s10, s79, 16
+; SI-NEXT: v_writelane_b32 v31, s13, 21
+; SI-NEXT: s_and_b32 s12, s68, 0xffff
+; SI-NEXT: s_or_b32 s12, s12, s10
+; SI-NEXT: s_mov_b32 s13, s11
; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
-; SI-NEXT: v_writelane_b32 v31, s10, 16
-; SI-NEXT: s_lshl_b32 s8, s85, 16
-; SI-NEXT: v_writelane_b32 v31, s11, 17
-; SI-NEXT: s_and_b32 s10, s98, 0xffff
-; SI-NEXT: s_or_b32 s40, s10, s8
-; SI-NEXT: s_mov_b32 s41, s9
+; SI-NEXT: v_writelane_b32 v31, s10, 22
+; SI-NEXT: s_lshl_b32 s8, s89, 16
+; SI-NEXT: v_writelane_b32 v31, s11, 23
+; SI-NEXT: s_and_b32 s10, s17, 0xffff
+; SI-NEXT: s_or_b32 s10, s10, s8
+; SI-NEXT: s_mov_b32 s11, s9
; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
-; SI-NEXT: v_writelane_b32 v31, s8, 18
-; SI-NEXT: v_writelane_b32 v31, s9, 19
-; SI-NEXT: s_and_b32 s8, s64, 0xffff
-; SI-NEXT: s_or_b32 s14, s8, s6
-; SI-NEXT: s_mov_b32 s15, s7
+; SI-NEXT: v_writelane_b32 v31, s8, 24
+; SI-NEXT: s_lshl_b32 s6, s91, 16
+; SI-NEXT: v_writelane_b32 v31, s9, 25
+; SI-NEXT: s_and_b32 s8, s16, 0xffff
+; SI-NEXT: s_or_b32 s8, s8, s6
+; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
-; SI-NEXT: v_writelane_b32 v31, s6, 20
-; SI-NEXT: v_writelane_b32 v31, s7, 21
-; SI-NEXT: s_and_b32 s6, s66, 0xffff
-; SI-NEXT: s_or_b32 s12, s6, s4
-; SI-NEXT: s_mov_b32 s13, s5
-; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
-; SI-NEXT: v_writelane_b32 v31, s4, 22
-; SI-NEXT: v_writelane_b32 v31, s5, 23
-; SI-NEXT: s_and_b32 s4, s68, 0xffff
-; SI-NEXT: s_or_b32 s10, s4, vcc_lo
-; SI-NEXT: s_lshr_b64 s[6:7], vcc, 16
-; SI-NEXT: s_and_b32 s4, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s52, s49, 16
-; SI-NEXT: v_writelane_b32 v31, s6, 24
-; SI-NEXT: s_or_b32 s8, s4, s50
-; SI-NEXT: s_and_b32 s4, s75, 0xffff
-; SI-NEXT: v_writelane_b32 v31, s7, 25
-; SI-NEXT: s_or_b32 s6, s4, s52
-; SI-NEXT: s_and_b32 s4, s16, 0xffff
-; SI-NEXT: s_mov_b32 s9, s51
-; SI-NEXT: s_lshr_b64 s[50:51], s[50:51], 16
-; SI-NEXT: s_mov_b32 s7, s53
-; SI-NEXT: s_lshr_b64 s[52:53], s[52:53], 16
-; SI-NEXT: s_or_b32 s4, s4, s54
-; SI-NEXT: s_mov_b32 s5, s55
-; SI-NEXT: s_lshr_b64 s[54:55], s[54:55], 16
-; SI-NEXT: s_mov_b32 s11, vcc_hi
-; SI-NEXT: s_mov_b32 s51, s76
-; SI-NEXT: s_mov_b32 s76, s78
-; SI-NEXT: s_mov_b32 s78, s88
-; SI-NEXT: s_mov_b32 s88, s90
-; SI-NEXT: s_mov_b32 s90, s71
-; SI-NEXT: s_mov_b32 s71, s82
-; SI-NEXT: s_mov_b32 s82, s94
-; SI-NEXT: s_mov_b32 s53, s80
-; SI-NEXT: s_mov_b32 s80, s83
-; SI-NEXT: s_mov_b32 s55, s92
-; SI-NEXT: s_mov_b32 s92, s81
-; SI-NEXT: s_mov_b32 s81, s84
-; SI-NEXT: s_mov_b32 s84, s30
-; SI-NEXT: s_mov_b32 s30, s34
-; SI-NEXT: s_mov_b32 s34, s36
-; SI-NEXT: s_mov_b32 s36, s38
-; SI-NEXT: s_mov_b32 s38, s39
+; SI-NEXT: s_lshl_b32 vcc_lo, s93, 16
+; SI-NEXT: v_writelane_b32 v31, s6, 26
+; SI-NEXT: s_mov_b32 s19, s76
+; SI-NEXT: s_mov_b32 s37, s38
+; SI-NEXT: s_mov_b32 s76, s84
+; SI-NEXT: v_writelane_b32 v31, s7, 27
+; SI-NEXT: s_and_b32 s6, s75, 0xffff
+; SI-NEXT: s_mov_b32 s84, s39
+; SI-NEXT: s_lshr_b64 s[38:39], vcc, 16
+; SI-NEXT: s_or_b32 s6, s6, vcc_lo
+; SI-NEXT: s_mov_b32 s7, vcc_hi
+; SI-NEXT: s_mov_b32 s39, s84
+; SI-NEXT: s_mov_b32 s84, s76
+; SI-NEXT: s_mov_b32 s76, s71
+; SI-NEXT: s_mov_b32 s71, s49
; SI-NEXT: s_cbranch_execnz .LBB57_3
; SI-NEXT: .LBB57_2: ; %cmp.true
+; SI-NEXT: s_add_i32 s75, s75, 3
+; SI-NEXT: s_and_b32 s4, s75, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s93, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s74, s74, 3
+; SI-NEXT: s_add_i32 s6, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s74, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s86, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s5, v31, 1
+; SI-NEXT: s_add_i32 s7, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: s_lshl_b32 s5, s91, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s70, s70, 3
+; SI-NEXT: s_add_i32 s8, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s70, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s85, 16
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: s_and_b32 s5, s70, 0xffff
-; SI-NEXT: s_lshl_b32 s6, s84, 16
-; SI-NEXT: s_add_i32 s75, s75, 3
-; SI-NEXT: s_or_b32 s5, s6, s5
-; SI-NEXT: s_and_b32 s6, s75, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s49, 16
-; SI-NEXT: s_add_i32 s74, s74, 3
-; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: s_and_b32 s7, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s8, s86, 16
; SI-NEXT: s_add_i32 s17, s17, 3
-; SI-NEXT: s_or_b32 s7, s8, s7
-; SI-NEXT: s_and_b32 s8, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s9, s38, 16
+; SI-NEXT: s_add_i32 s9, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s17, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s89, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s69, s69, 3
-; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: s_and_b32 s9, s69, 0xffff
-; SI-NEXT: s_lshl_b32 s10, s82, 16
+; SI-NEXT: s_add_i32 s10, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s69, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s39, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s68, s68, 3
-; SI-NEXT: s_or_b32 s9, s10, s9
-; SI-NEXT: s_and_b32 s10, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s11, s36, 16
+; SI-NEXT: s_add_i32 s11, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s68, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s79, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s67, s67, 3
-; SI-NEXT: s_or_b32 s10, s11, s10
-; SI-NEXT: s_and_b32 s11, s67, 0xffff
-; SI-NEXT: s_lshl_b32 s12, s81, 16
+; SI-NEXT: s_add_i32 s12, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s67, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s83, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s66, s66, 3
-; SI-NEXT: s_or_b32 s11, s12, s11
-; SI-NEXT: s_and_b32 s12, s66, 0xffff
-; SI-NEXT: s_lshl_b32 s13, s34, 16
+; SI-NEXT: s_add_i32 s13, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s66, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s77, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s65, s65, 3
-; SI-NEXT: s_or_b32 s12, s13, s12
-; SI-NEXT: s_and_b32 s13, s65, 0xffff
-; SI-NEXT: s_lshl_b32 s14, s80, 16
+; SI-NEXT: s_add_i32 s14, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s65, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s82, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s64, s64, 3
-; SI-NEXT: s_or_b32 s13, s14, s13
-; SI-NEXT: s_and_b32 s14, s64, 0xffff
-; SI-NEXT: s_lshl_b32 s15, s30, 16
+; SI-NEXT: s_add_i32 s15, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s64, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s98, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s96, s96, 3
-; SI-NEXT: s_or_b32 s14, s15, s14
-; SI-NEXT: s_and_b32 s15, s96, 0xffff
-; SI-NEXT: s_lshl_b32 s16, s71, 16
-; SI-NEXT: s_add_i32 s98, s98, 3
-; SI-NEXT: s_or_b32 s15, s16, s15
-; SI-NEXT: s_and_b32 s16, s98, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s85, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s87, s87, 3
-; SI-NEXT: s_add_i32 s40, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s87, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s55, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s40, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s96, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s81, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s98, s87, 3
+; SI-NEXT: s_add_i32 s41, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s98, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s95, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s87, s97, 3
+; SI-NEXT: s_add_i32 s42, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s87, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s80, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s99, s99, 3
-; SI-NEXT: s_add_i32 s41, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s99, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s92, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s97, s97, 3
-; SI-NEXT: s_add_i32 s42, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s97, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s53, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s28, s28, 3
-; SI-NEXT: s_add_i32 s43, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s90, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s43, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s99, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s71, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s97, s51, 3
+; SI-NEXT: s_add_i32 s44, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s97, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s53, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s45, s4, 0x30000
+; SI-NEXT: v_readlane_b32 s4, v31, 5
+; SI-NEXT: s_add_i32 s28, s4, 3
+; SI-NEXT: s_and_b32 s4, s28, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s76, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s29, s29, 3
-; SI-NEXT: s_add_i32 s44, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s79, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s26, s26, 3
-; SI-NEXT: s_add_i32 s45, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s88, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s46, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s29, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s31, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s47, s4, 0x30000
+; SI-NEXT: v_readlane_b32 s4, v31, 4
+; SI-NEXT: s_add_i32 s26, s4, 3
+; SI-NEXT: s_and_b32 s4, s26, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s84, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s27, s27, 3
-; SI-NEXT: s_add_i32 s46, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s31, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s24, s24, 3
-; SI-NEXT: s_add_i32 s47, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s78, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s56, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s27, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s30, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s57, s4, 0x30000
+; SI-NEXT: v_readlane_b32 s4, v31, 3
+; SI-NEXT: s_add_i32 s24, s4, 3
+; SI-NEXT: s_and_b32 s4, s24, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s55, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s25, s25, 3
-; SI-NEXT: s_add_i32 s56, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s95, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s22, s22, 3
-; SI-NEXT: s_add_i32 s57, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s76, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s58, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s25, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s94, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s59, s4, 0x30000
+; SI-NEXT: v_readlane_b32 s4, v31, 2
+; SI-NEXT: s_add_i32 s22, s4, 3
+; SI-NEXT: s_and_b32 s4, s22, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s54, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s23, s23, 3
-; SI-NEXT: s_add_i32 s58, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s93, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s20, s20, 3
-; SI-NEXT: s_add_i32 s59, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s51, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s60, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s23, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s92, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s61, s4, 0x30000
+; SI-NEXT: v_readlane_b32 s4, v31, 1
+; SI-NEXT: s_add_i32 s20, s4, 3
+; SI-NEXT: s_and_b32 s4, s20, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s52, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s21, s21, 3
-; SI-NEXT: s_add_i32 s62, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s91, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s18, s18, 3
-; SI-NEXT: s_add_i32 s63, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s18, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s77, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s62, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s21, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s90, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s63, s4, 0x30000
+; SI-NEXT: v_readlane_b32 s4, v31, 0
+; SI-NEXT: s_add_i32 s18, s4, 3
+; SI-NEXT: s_and_b32 s4, s18, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s50, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: s_add_i32 s72, s16, 0x30000
-; SI-NEXT: s_and_b32 s16, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s89, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s73, s16, 0x30000
-; SI-NEXT: s_add_i32 s16, s37, 3
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s48, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s60, s16, 0x30000
-; SI-NEXT: s_add_i32 s16, s35, 3
-; SI-NEXT: v_readlane_b32 s17, v31, 0
-; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s61, s16, 0x30000
-; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
-; SI-NEXT: v_writelane_b32 v31, s16, 2
-; SI-NEXT: v_writelane_b32 v31, s17, 3
-; SI-NEXT: s_lshr_b64 s[16:17], s[72:73], 16
-; SI-NEXT: v_writelane_b32 v31, s16, 4
-; SI-NEXT: v_writelane_b32 v31, s17, 5
-; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
+; SI-NEXT: s_add_i32 s72, s4, 0x30000
+; SI-NEXT: s_and_b32 s4, s19, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s88, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s73, s4, 0x30000
+; SI-NEXT: s_add_i32 s4, s37, 3
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s48, 16
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_add_i32 s5, s35, 3
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_lshl_b32 s16, s78, 16
+; SI-NEXT: s_or_b32 s5, s16, s5
+; SI-NEXT: s_add_i32 s4, s4, 0x30000
+; SI-NEXT: s_add_i32 s5, s5, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16
; SI-NEXT: v_writelane_b32 v31, s16, 6
; SI-NEXT: v_writelane_b32 v31, s17, 7
-; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
; SI-NEXT: v_writelane_b32 v31, s16, 8
; SI-NEXT: v_writelane_b32 v31, s17, 9
-; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
; SI-NEXT: v_writelane_b32 v31, s16, 10
; SI-NEXT: v_writelane_b32 v31, s17, 11
-; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16
; SI-NEXT: v_writelane_b32 v31, s16, 12
; SI-NEXT: v_writelane_b32 v31, s17, 13
-; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
; SI-NEXT: v_writelane_b32 v31, s16, 14
; SI-NEXT: v_writelane_b32 v31, s17, 15
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
; SI-NEXT: v_writelane_b32 v31, s16, 16
; SI-NEXT: v_writelane_b32 v31, s17, 17
-; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 16
-; SI-NEXT: s_add_i32 s14, s14, 0x30000
-; SI-NEXT: s_add_i32 s15, s15, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
; SI-NEXT: v_writelane_b32 v31, s16, 18
; SI-NEXT: v_writelane_b32 v31, s17, 19
; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
-; SI-NEXT: s_add_i32 s12, s12, 0x30000
-; SI-NEXT: s_add_i32 s13, s13, 0x30000
; SI-NEXT: v_writelane_b32 v31, s16, 20
; SI-NEXT: v_writelane_b32 v31, s17, 21
; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 16
-; SI-NEXT: s_add_i32 s10, s10, 0x30000
-; SI-NEXT: s_add_i32 s11, s11, 0x30000
; SI-NEXT: v_writelane_b32 v31, s16, 22
-; SI-NEXT: s_add_i32 s4, s4, 0x30000
-; SI-NEXT: s_add_i32 s5, s5, 0x30000
-; SI-NEXT: s_add_i32 s6, s6, 0x30000
-; SI-NEXT: s_add_i32 s7, s7, 0x30000
; SI-NEXT: v_writelane_b32 v31, s17, 23
; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 16
-; SI-NEXT: s_add_i32 s8, s8, 0x30000
-; SI-NEXT: s_add_i32 s9, s9, 0x30000
; SI-NEXT: v_writelane_b32 v31, s16, 24
-; SI-NEXT: s_lshr_b64 s[52:53], s[6:7], 16
-; SI-NEXT: s_lshr_b64 s[54:55], s[4:5], 16
; SI-NEXT: v_writelane_b32 v31, s17, 25
-; SI-NEXT: s_lshr_b64 s[50:51], s[8:9], 16
-; SI-NEXT: s_lshr_b32 s16, s61, 16
-; SI-NEXT: s_lshr_b32 s89, s73, 16
-; SI-NEXT: s_lshr_b32 s91, s63, 16
-; SI-NEXT: s_lshr_b32 s93, s59, 16
-; SI-NEXT: s_lshr_b32 s95, s57, 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16
+; SI-NEXT: s_lshr_b64 s[38:39], s[6:7], 16
+; SI-NEXT: s_lshr_b64 s[18:19], s[72:73], 16
+; SI-NEXT: s_lshr_b64 s[34:35], s[42:43], 16
+; SI-NEXT: s_lshr_b64 s[36:37], s[40:41], 16
+; SI-NEXT: v_writelane_b32 v31, s16, 26
+; SI-NEXT: s_lshr_b32 s78, s5, 16
+; SI-NEXT: s_lshr_b32 s88, s73, 16
+; SI-NEXT: s_lshr_b32 s90, s63, 16
+; SI-NEXT: s_lshr_b32 s92, s61, 16
+; SI-NEXT: s_lshr_b32 s94, s59, 16
+; SI-NEXT: s_lshr_b32 s30, s57, 16
; SI-NEXT: s_lshr_b32 s31, s47, 16
-; SI-NEXT: s_lshr_b32 s79, s45, 16
-; SI-NEXT: s_lshr_b32 s53, s43, 16
-; SI-NEXT: s_lshr_b32 s55, s41, 16
-; SI-NEXT: s_lshr_b32 s71, s15, 16
-; SI-NEXT: s_lshr_b32 s80, s13, 16
-; SI-NEXT: s_lshr_b32 s81, s11, 16
-; SI-NEXT: s_lshr_b32 s82, s9, 16
+; SI-NEXT: s_lshr_b32 s53, s45, 16
+; SI-NEXT: s_lshr_b32 s80, s43, 16
+; SI-NEXT: s_lshr_b32 s81, s41, 16
+; SI-NEXT: s_lshr_b32 s82, s15, 16
+; SI-NEXT: s_lshr_b32 s83, s13, 16
+; SI-NEXT: s_lshr_b32 s39, s11, 16
+; SI-NEXT: s_lshr_b32 s85, s9, 16
; SI-NEXT: s_lshr_b32 s86, s7, 16
-; SI-NEXT: s_lshr_b32 s84, s5, 16
-; SI-NEXT: v_writelane_b32 v31, s16, 0
+; SI-NEXT: v_writelane_b32 v31, s17, 27
; SI-NEXT: .LBB57_3: ; %end
-; SI-NEXT: v_readlane_b32 s18, v31, 2
-; SI-NEXT: s_and_b32 s16, s60, 0xffff
+; SI-NEXT: v_readlane_b32 s16, v31, 6
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: v_readlane_b32 s17, v31, 7
+; SI-NEXT: s_or_b32 s4, s4, s16
+; SI-NEXT: s_and_b32 s5, s5, 0xffff
+; SI-NEXT: s_lshl_b32 s16, s78, 16
+; SI-NEXT: s_or_b32 s5, s5, s16
+; SI-NEXT: s_and_b32 s16, s72, 0xffff
; SI-NEXT: s_lshl_b32 s17, s18, 16
-; SI-NEXT: v_readlane_b32 s18, v31, 0
-; SI-NEXT: v_readlane_b32 s19, v31, 3
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s61, 0xffff
-; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: v_readlane_b32 s20, v31, 4
+; SI-NEXT: s_and_b32 s17, s73, 0xffff
+; SI-NEXT: s_lshl_b32 s18, s88, 16
+; SI-NEXT: v_readlane_b32 s20, v31, 8
; SI-NEXT: s_or_b32 s17, s17, s18
-; SI-NEXT: s_and_b32 s18, s72, 0xffff
+; SI-NEXT: s_and_b32 s18, s62, 0xffff
; SI-NEXT: s_lshl_b32 s19, s20, 16
-; SI-NEXT: v_readlane_b32 s21, v31, 5
+; SI-NEXT: v_readlane_b32 s21, v31, 9
; SI-NEXT: s_or_b32 s18, s18, s19
-; SI-NEXT: s_and_b32 s19, s73, 0xffff
-; SI-NEXT: s_lshl_b32 s20, s89, 16
-; SI-NEXT: v_readlane_b32 s22, v31, 6
+; SI-NEXT: s_and_b32 s19, s63, 0xffff
+; SI-NEXT: s_lshl_b32 s20, s90, 16
+; SI-NEXT: v_readlane_b32 s22, v31, 10
; SI-NEXT: s_or_b32 s19, s19, s20
-; SI-NEXT: s_and_b32 s20, s62, 0xffff
+; SI-NEXT: s_and_b32 s20, s60, 0xffff
; SI-NEXT: s_lshl_b32 s21, s22, 16
-; SI-NEXT: v_readlane_b32 s23, v31, 7
+; SI-NEXT: v_readlane_b32 s23, v31, 11
; SI-NEXT: s_or_b32 s20, s20, s21
-; SI-NEXT: s_and_b32 s21, s63, 0xffff
-; SI-NEXT: s_lshl_b32 s22, s91, 16
-; SI-NEXT: v_readlane_b32 s24, v31, 8
+; SI-NEXT: s_and_b32 s21, s61, 0xffff
+; SI-NEXT: s_lshl_b32 s22, s92, 16
+; SI-NEXT: v_readlane_b32 s24, v31, 12
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s58, 0xffff
; SI-NEXT: s_lshl_b32 s23, s24, 16
-; SI-NEXT: v_readlane_b32 s25, v31, 9
+; SI-NEXT: v_readlane_b32 s25, v31, 13
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s59, 0xffff
-; SI-NEXT: s_lshl_b32 s24, s93, 16
-; SI-NEXT: v_readlane_b32 s26, v31, 10
+; SI-NEXT: s_lshl_b32 s24, s94, 16
+; SI-NEXT: v_readlane_b32 s26, v31, 14
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s24, s56, 0xffff
; SI-NEXT: s_lshl_b32 s25, s26, 16
-; SI-NEXT: v_readlane_b32 s27, v31, 11
+; SI-NEXT: v_readlane_b32 s27, v31, 15
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s57, 0xffff
-; SI-NEXT: s_lshl_b32 s26, s95, 16
-; SI-NEXT: v_readlane_b32 s28, v31, 12
+; SI-NEXT: s_lshl_b32 s26, s30, 16
+; SI-NEXT: v_readlane_b32 s28, v31, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s46, 0xffff
; SI-NEXT: s_lshl_b32 s27, s28, 16
-; SI-NEXT: v_readlane_b32 s29, v31, 13
+; SI-NEXT: v_readlane_b32 s29, v31, 17
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s47, 0xffff
; SI-NEXT: s_lshl_b32 s28, s31, 16
-; SI-NEXT: v_readlane_b32 s46, v31, 14
+; SI-NEXT: v_readlane_b32 s46, v31, 18
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s44, 0xffff
; SI-NEXT: s_lshl_b32 s29, s46, 16
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s29, s45, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s79, 16
+; SI-NEXT: s_lshl_b32 s44, s53, 16
; SI-NEXT: s_or_b32 s29, s29, s44
-; SI-NEXT: v_readlane_b32 s44, v31, 16
; SI-NEXT: s_and_b32 s42, s42, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: v_readlane_b32 s45, v31, 17
+; SI-NEXT: s_lshl_b32 s44, s34, 16
; SI-NEXT: s_or_b32 s42, s42, s44
; SI-NEXT: s_and_b32 s43, s43, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s53, 16
+; SI-NEXT: s_lshl_b32 s44, s80, 16
; SI-NEXT: s_or_b32 s43, s43, s44
-; SI-NEXT: v_readlane_b32 s44, v31, 18
; SI-NEXT: s_and_b32 s40, s40, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: v_readlane_b32 s45, v31, 19
+; SI-NEXT: s_lshl_b32 s44, s36, 16
; SI-NEXT: s_or_b32 s40, s40, s44
; SI-NEXT: s_and_b32 s41, s41, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s55, 16
+; SI-NEXT: s_lshl_b32 s44, s81, 16
; SI-NEXT: s_or_b32 s41, s41, s44
; SI-NEXT: v_readlane_b32 s44, v31, 20
; SI-NEXT: s_and_b32 s14, s14, 0xffff
@@ -47621,7 +47604,7 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; SI-NEXT: v_readlane_b32 s45, v31, 21
; SI-NEXT: s_or_b32 s14, s14, s44
; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s71, 16
+; SI-NEXT: s_lshl_b32 s44, s82, 16
; SI-NEXT: s_or_b32 s15, s15, s44
; SI-NEXT: v_readlane_b32 s44, v31, 22
; SI-NEXT: s_and_b32 s12, s12, 0xffff
@@ -47629,66 +47612,62 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; SI-NEXT: v_readlane_b32 s45, v31, 23
; SI-NEXT: s_or_b32 s12, s12, s44
; SI-NEXT: s_and_b32 s13, s13, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s80, 16
+; SI-NEXT: s_lshl_b32 s44, s83, 16
; SI-NEXT: s_or_b32 s13, s13, s44
; SI-NEXT: v_readlane_b32 s44, v31, 24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_lshl_b32 s44, s44, 16
+; SI-NEXT: v_readlane_b32 s45, v31, 25
; SI-NEXT: s_or_b32 s10, s10, s44
; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s81, 16
+; SI-NEXT: s_lshl_b32 s44, s39, 16
; SI-NEXT: s_or_b32 s11, s11, s44
+; SI-NEXT: v_readlane_b32 s44, v31, 26
; SI-NEXT: s_and_b32 s8, s8, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s50, 16
+; SI-NEXT: s_lshl_b32 s44, s44, 16
; SI-NEXT: s_or_b32 s8, s8, s44
; SI-NEXT: s_and_b32 s9, s9, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s82, 16
+; SI-NEXT: s_lshl_b32 s44, s85, 16
; SI-NEXT: s_or_b32 s9, s9, s44
; SI-NEXT: s_and_b32 s6, s6, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s52, 16
+; SI-NEXT: s_lshl_b32 s44, s38, 16
; SI-NEXT: s_or_b32 s6, s6, s44
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_lshl_b32 s44, s86, 16
; SI-NEXT: s_or_b32 s7, s7, s44
-; SI-NEXT: s_and_b32 s4, s4, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s54, 16
-; SI-NEXT: s_or_b32 s4, s4, s44
-; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s84, 16
-; SI-NEXT: s_or_b32 s5, s5, s44
; SI-NEXT: v_readlane_b32 s30, v30, 34
-; SI-NEXT: v_readlane_b32 s47, v31, 15
-; SI-NEXT: v_readlane_b32 s45, v31, 25
-; SI-NEXT: v_mov_b32_e32 v0, s16
-; SI-NEXT: v_mov_b32_e32 v1, s17
-; SI-NEXT: v_mov_b32_e32 v2, s18
-; SI-NEXT: v_mov_b32_e32 v3, s19
-; SI-NEXT: v_mov_b32_e32 v4, s20
-; SI-NEXT: v_mov_b32_e32 v5, s21
-; SI-NEXT: v_mov_b32_e32 v6, s22
-; SI-NEXT: v_mov_b32_e32 v7, s23
-; SI-NEXT: v_mov_b32_e32 v8, s24
-; SI-NEXT: v_mov_b32_e32 v9, s25
-; SI-NEXT: v_mov_b32_e32 v10, s26
-; SI-NEXT: v_mov_b32_e32 v11, s27
-; SI-NEXT: v_mov_b32_e32 v12, s28
-; SI-NEXT: v_mov_b32_e32 v13, s29
-; SI-NEXT: v_mov_b32_e32 v14, s42
-; SI-NEXT: v_mov_b32_e32 v15, s43
-; SI-NEXT: v_mov_b32_e32 v16, s40
-; SI-NEXT: v_mov_b32_e32 v17, s41
-; SI-NEXT: v_mov_b32_e32 v18, s14
-; SI-NEXT: v_mov_b32_e32 v19, s15
-; SI-NEXT: v_mov_b32_e32 v20, s12
-; SI-NEXT: v_mov_b32_e32 v21, s13
-; SI-NEXT: v_mov_b32_e32 v22, s10
-; SI-NEXT: v_mov_b32_e32 v23, s11
-; SI-NEXT: v_mov_b32_e32 v24, s8
-; SI-NEXT: v_mov_b32_e32 v25, s9
-; SI-NEXT: v_mov_b32_e32 v26, s6
-; SI-NEXT: v_mov_b32_e32 v27, s7
-; SI-NEXT: v_mov_b32_e32 v28, s4
-; SI-NEXT: v_mov_b32_e32 v29, s5
+; SI-NEXT: v_readlane_b32 s47, v31, 19
+; SI-NEXT: v_readlane_b32 s45, v31, 27
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: v_mov_b32_e32 v2, s16
+; SI-NEXT: v_mov_b32_e32 v3, s17
+; SI-NEXT: v_mov_b32_e32 v4, s18
+; SI-NEXT: v_mov_b32_e32 v5, s19
+; SI-NEXT: v_mov_b32_e32 v6, s20
+; SI-NEXT: v_mov_b32_e32 v7, s21
+; SI-NEXT: v_mov_b32_e32 v8, s22
+; SI-NEXT: v_mov_b32_e32 v9, s23
+; SI-NEXT: v_mov_b32_e32 v10, s24
+; SI-NEXT: v_mov_b32_e32 v11, s25
+; SI-NEXT: v_mov_b32_e32 v12, s26
+; SI-NEXT: v_mov_b32_e32 v13, s27
+; SI-NEXT: v_mov_b32_e32 v14, s28
+; SI-NEXT: v_mov_b32_e32 v15, s29
+; SI-NEXT: v_mov_b32_e32 v16, s42
+; SI-NEXT: v_mov_b32_e32 v17, s43
+; SI-NEXT: v_mov_b32_e32 v18, s40
+; SI-NEXT: v_mov_b32_e32 v19, s41
+; SI-NEXT: v_mov_b32_e32 v20, s14
+; SI-NEXT: v_mov_b32_e32 v21, s15
+; SI-NEXT: v_mov_b32_e32 v22, s12
+; SI-NEXT: v_mov_b32_e32 v23, s13
+; SI-NEXT: v_mov_b32_e32 v24, s10
+; SI-NEXT: v_mov_b32_e32 v25, s11
+; SI-NEXT: v_mov_b32_e32 v26, s8
+; SI-NEXT: v_mov_b32_e32 v27, s9
+; SI-NEXT: v_mov_b32_e32 v28, s6
+; SI-NEXT: v_mov_b32_e32 v29, s7
; SI-NEXT: v_readlane_b32 s31, v30, 35
; SI-NEXT: v_readlane_b32 s99, v30, 33
; SI-NEXT: v_readlane_b32 s98, v30, 32
@@ -47731,60 +47710,58 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB57_4:
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 6
+; SI-NEXT: v_writelane_b32 v31, s7, 7
+; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 2
-; SI-NEXT: v_writelane_b32 v31, s5, 3
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr72
+; SI-NEXT: ; implicit-def: $sgpr18
; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr42
+; SI-NEXT: ; implicit-def: $sgpr34
; SI-NEXT: ; implicit-def: $sgpr40
+; SI-NEXT: ; implicit-def: $sgpr36
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr12
; SI-NEXT: ; implicit-def: $sgpr10
; SI-NEXT: ; implicit-def: $sgpr8
-; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: v_writelane_b32 v31, s6, 8
+; SI-NEXT: v_writelane_b32 v31, s7, 9
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 10
+; SI-NEXT: v_writelane_b32 v31, s7, 11
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 12
+; SI-NEXT: v_writelane_b32 v31, s7, 13
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 14
+; SI-NEXT: v_writelane_b32 v31, s7, 15
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 16
+; SI-NEXT: v_writelane_b32 v31, s7, 17
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 18
+; SI-NEXT: v_writelane_b32 v31, s7, 19
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 20
+; SI-NEXT: v_writelane_b32 v31, s7, 21
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 22
+; SI-NEXT: v_writelane_b32 v31, s7, 23
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 24
+; SI-NEXT: v_writelane_b32 v31, s7, 25
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: v_writelane_b32 v31, s6, 26
+; SI-NEXT: v_writelane_b32 v31, s7, 27
; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr52
-; SI-NEXT: ; implicit-def: $sgpr54
-; SI-NEXT: v_writelane_b32 v31, s4, 4
-; SI-NEXT: v_writelane_b32 v31, s5, 5
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 6
-; SI-NEXT: v_writelane_b32 v31, s5, 7
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 8
-; SI-NEXT: v_writelane_b32 v31, s5, 9
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 10
-; SI-NEXT: v_writelane_b32 v31, s5, 11
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 12
-; SI-NEXT: v_writelane_b32 v31, s5, 13
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 14
-; SI-NEXT: v_writelane_b32 v31, s5, 15
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 16
-; SI-NEXT: v_writelane_b32 v31, s5, 17
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 18
-; SI-NEXT: v_writelane_b32 v31, s5, 19
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 20
-; SI-NEXT: v_writelane_b32 v31, s5, 21
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 22
-; SI-NEXT: v_writelane_b32 v31, s5, 23
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 24
-; SI-NEXT: v_writelane_b32 v31, s5, 25
-; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_branch .LBB57_2
;
; VI-LABEL: bitcast_v60i16_to_v60f16_scalar:
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index 9e0870ad62358..13408f1d89b25 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -2721,45 +2721,45 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_and_b32 s14, s14, 0xffff
; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x70
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s0
; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x60
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s0
; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x50
+; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s34
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s33
+; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
+; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GCN-HSA-NEXT: s_add_u32 s0, s16, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s31
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s30
-; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s28
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s27
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s26
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s29
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s28
+; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s27
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s26
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: s_add_u32 s0, s16, 32
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
@@ -3182,55 +3182,55 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x70
; GCN-HSA-NEXT: s_sext_i32_i16 s20, s1
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s0
; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x60
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
-; GCN-HSA-NEXT: s_sext_i32_i16 s12, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s0
+; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x50
+; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
; GCN-HSA-NEXT: s_sext_i32_i16 s15, s15
; GCN-HSA-NEXT: s_sext_i32_i16 s14, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x50
-; GCN-HSA-NEXT: s_sext_i32_i16 s13, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s36
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
+; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: s_sext_i32_i16 s13, s13
+; GCN-HSA-NEXT: s_sext_i32_i16 s12, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GCN-HSA-NEXT: s_add_u32 s0, s16, 48
+; GCN-HSA-NEXT: s_sext_i32_i16 s11, s11
+; GCN-HSA-NEXT: s_sext_i32_i16 s10, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s34
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s33
-; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
-; GCN-HSA-NEXT: s_sext_i32_i16 s11, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: s_sext_i32_i16 s10, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s31
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s30
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: s_sext_i32_i16 s9, s9
; GCN-HSA-NEXT: s_sext_i32_i16 s8, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s28
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s30
+; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
; GCN-HSA-NEXT: s_sext_i32_i16 s6, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s29
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s28
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: s_add_u32 s0, s16, 32
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s27
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
@@ -3714,65 +3714,32 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
;
; GCN-HSA-LABEL: constant_zextload_v64i16_to_v64i32:
; GCN-HSA: ; %bb.0:
+; GCN-HSA-NEXT: s_load_dwordx4 s[36:39], s[8:9], 0x0
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
-; GCN-HSA-NEXT: s_load_dwordx4 s[16:19], s[8:9], 0x0
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
-; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_lshr_b32 s20, s1, 16
-; GCN-HSA-NEXT: s_lshr_b32 s21, s0, 16
-; GCN-HSA-NEXT: s_lshr_b32 s22, s3, 16
-; GCN-HSA-NEXT: s_lshr_b32 s23, s2, 16
-; GCN-HSA-NEXT: s_lshr_b32 s24, s5, 16
-; GCN-HSA-NEXT: s_lshr_b32 s26, s4, 16
-; GCN-HSA-NEXT: s_lshr_b32 s28, s7, 16
-; GCN-HSA-NEXT: s_lshr_b32 s30, s6, 16
-; GCN-HSA-NEXT: s_lshr_b32 s33, s9, 16
-; GCN-HSA-NEXT: s_lshr_b32 s35, s8, 16
-; GCN-HSA-NEXT: s_lshr_b32 s37, s11, 16
-; GCN-HSA-NEXT: s_lshr_b32 s39, s10, 16
-; GCN-HSA-NEXT: s_lshr_b32 s42, s13, 16
-; GCN-HSA-NEXT: s_lshr_b32 s44, s12, 16
-; GCN-HSA-NEXT: s_lshr_b32 s45, s15, 16
-; GCN-HSA-NEXT: s_lshr_b32 s46, s14, 16
-; GCN-HSA-NEXT: s_and_b32 s25, s1, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s27, s0, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s29, s3, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s31, s2, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s34, s5, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s36, s4, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s38, s7, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s40, s6, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s41, s9, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s43, s8, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s47, s11, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s48, s10, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s49, s13, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s51, s12, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s50, s15, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s52, s14, 0xffff
-; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x10
+; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GCN-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x10
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_lshr_b32 s18, s1, 16
-; GCN-HSA-NEXT: s_lshr_b32 s19, s0, 16
-; GCN-HSA-NEXT: s_lshr_b32 s53, s3, 16
-; GCN-HSA-NEXT: s_lshr_b32 s54, s2, 16
-; GCN-HSA-NEXT: s_lshr_b32 s55, s5, 16
-; GCN-HSA-NEXT: s_lshr_b32 s56, s4, 16
-; GCN-HSA-NEXT: s_lshr_b32 s57, s7, 16
-; GCN-HSA-NEXT: s_lshr_b32 s58, s6, 16
-; GCN-HSA-NEXT: s_lshr_b32 s59, s9, 16
-; GCN-HSA-NEXT: s_lshr_b32 s60, s8, 16
-; GCN-HSA-NEXT: s_lshr_b32 s61, s11, 16
-; GCN-HSA-NEXT: s_lshr_b32 s62, s10, 16
-; GCN-HSA-NEXT: s_lshr_b32 s63, s13, 16
-; GCN-HSA-NEXT: s_lshr_b32 s64, s12, 16
-; GCN-HSA-NEXT: s_lshr_b32 s65, s15, 16
-; GCN-HSA-NEXT: s_lshr_b32 s66, s14, 16
-; GCN-HSA-NEXT: s_and_b32 s67, s1, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s68, s0, 0xffff
+; GCN-HSA-NEXT: s_lshr_b32 s33, s1, 16
+; GCN-HSA-NEXT: s_lshr_b32 s34, s0, 16
+; GCN-HSA-NEXT: s_lshr_b32 s35, s3, 16
+; GCN-HSA-NEXT: s_lshr_b32 s40, s2, 16
+; GCN-HSA-NEXT: s_lshr_b32 s41, s5, 16
+; GCN-HSA-NEXT: s_lshr_b32 s42, s4, 16
+; GCN-HSA-NEXT: s_lshr_b32 s43, s7, 16
+; GCN-HSA-NEXT: s_lshr_b32 s44, s6, 16
+; GCN-HSA-NEXT: s_lshr_b32 s45, s9, 16
+; GCN-HSA-NEXT: s_lshr_b32 s46, s8, 16
+; GCN-HSA-NEXT: s_lshr_b32 s47, s11, 16
+; GCN-HSA-NEXT: s_lshr_b32 s48, s10, 16
+; GCN-HSA-NEXT: s_lshr_b32 s49, s13, 16
+; GCN-HSA-NEXT: s_lshr_b32 s50, s12, 16
+; GCN-HSA-NEXT: s_lshr_b32 s51, s15, 16
+; GCN-HSA-NEXT: s_lshr_b32 s52, s14, 16
+; GCN-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s0, s0, 0xffff
; GCN-HSA-NEXT: s_and_b32 s3, s3, 0xffff
; GCN-HSA-NEXT: s_and_b32 s2, s2, 0xffff
; GCN-HSA-NEXT: s_and_b32 s5, s5, 0xffff
@@ -3784,150 +3751,187 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_and_b32 s11, s11, 0xffff
; GCN-HSA-NEXT: s_and_b32 s10, s10, 0xffff
; GCN-HSA-NEXT: s_and_b32 s13, s13, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s12, s12, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s15, s15, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s14, s14, 0xffff
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0xf0
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0xe0
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0xd0
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0xc0
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0xb0
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0xa0
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s10
+; GCN-HSA-NEXT: s_and_b32 s38, s12, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s12, s15, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s15, s14, 0xffff
+; GCN-HSA-NEXT: s_lshr_b32 s14, s17, 16
+; GCN-HSA-NEXT: s_lshr_b32 s39, s16, 16
+; GCN-HSA-NEXT: s_lshr_b32 s53, s19, 16
+; GCN-HSA-NEXT: s_lshr_b32 s54, s18, 16
+; GCN-HSA-NEXT: s_lshr_b32 s55, s21, 16
+; GCN-HSA-NEXT: s_lshr_b32 s56, s20, 16
+; GCN-HSA-NEXT: s_lshr_b32 s57, s23, 16
+; GCN-HSA-NEXT: s_lshr_b32 s58, s22, 16
+; GCN-HSA-NEXT: s_lshr_b32 s59, s25, 16
+; GCN-HSA-NEXT: s_lshr_b32 s60, s24, 16
+; GCN-HSA-NEXT: s_lshr_b32 s61, s27, 16
+; GCN-HSA-NEXT: s_lshr_b32 s62, s26, 16
+; GCN-HSA-NEXT: s_lshr_b32 s63, s29, 16
+; GCN-HSA-NEXT: s_lshr_b32 s64, s28, 16
+; GCN-HSA-NEXT: s_lshr_b32 s65, s31, 16
+; GCN-HSA-NEXT: s_lshr_b32 s66, s30, 16
+; GCN-HSA-NEXT: s_and_b32 s67, s17, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s68, s16, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s19, s19, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s18, s18, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s21, s21, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s20, s20, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s23, s23, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s22, s22, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s25, s25, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s24, s24, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s27, s27, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s26, s26, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s29, s29, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s28, s28, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s31, s31, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s30, s30, 0xffff
+; GCN-HSA-NEXT: s_add_u32 s16, s36, 0xf0
+; GCN-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s17
+; GCN-HSA-NEXT: s_add_u32 s16, s36, 0xe0
+; GCN-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s16
+; GCN-HSA-NEXT: s_add_u32 s16, s36, 0xd0
+; GCN-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s16
+; GCN-HSA-NEXT: s_add_u32 s16, s36, 0xc0
+; GCN-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s16
+; GCN-HSA-NEXT: s_add_u32 s16, s36, 0xb0
+; GCN-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s16
+; GCN-HSA-NEXT: s_add_u32 s16, s36, 0xa0
+; GCN-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s16
+; GCN-HSA-NEXT: s_add_u32 s16, s36, 0x90
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s26
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s62
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s27
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s61
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[23:24], v[8:11]
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x90
+; GCN-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s16
+; GCN-HSA-NEXT: s_add_u32 s16, s36, 0x80
+; GCN-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s60
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s59
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[25:26], v[12:15]
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x80
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s14
+; GCN-HSA-NEXT: s_add_u32 s14, s36, 0x70
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s30
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s66
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s31
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s65
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x70
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s58
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s7
-; GCN-HSA-NEXT: flat_store_dwordx4 v[19:20], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s57
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[27:28], v[16:19]
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x60
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
+; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[12:15]
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s28
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s15
+; GCN-HSA-NEXT: s_addc_u32 s15, s37, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s64
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s29
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s63
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x50
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s2
-; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[4:7]
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s56
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s55
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s54
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s68
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s19
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s67
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s52
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s18
-; GCN-HSA-NEXT: flat_store_dwordx4 v[9:10], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s51
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s50
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s45
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s44
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s49
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s42
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[20:23]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s39
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s47
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s37
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s58
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s57
+; GCN-HSA-NEXT: s_add_u32 s12, s36, 0x60
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s20
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s56
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s55
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GCN-HSA-NEXT: s_addc_u32 s13, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s54
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s53
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s15
+; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s68
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s67
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s51
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s49
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s12
+; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GCN-HSA-NEXT: s_add_u32 s10, s36, 0x50
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GCN-HSA-NEXT: s_addc_u32 s11, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s48
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s43
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s35
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s41
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s33
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GCN-HSA-NEXT: s_add_u32 s8, s36, 64
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GCN-HSA-NEXT: s_addc_u32 s9, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s45
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s40
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s30
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s28
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GCN-HSA-NEXT: s_add_u32 s6, s36, 48
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GCN-HSA-NEXT: s_addc_u32 s7, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s26
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s24
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GCN-HSA-NEXT: s_add_u32 s4, s36, 32
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GCN-HSA-NEXT: s_addc_u32 s5, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s31
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s36, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GCN-HSA-NEXT: s_addc_u32 s3, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s40
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s27
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s21
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s25
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s33
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s37
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
;
@@ -4606,220 +4610,219 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
;
; GCN-HSA-LABEL: constant_sextload_v64i16_to_v64i32:
; GCN-HSA: ; %bb.0:
+; GCN-HSA-NEXT: s_load_dwordx4 s[36:39], s[8:9], 0x0
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
-; GCN-HSA-NEXT: s_load_dwordx4 s[16:19], s[8:9], 0x0
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
-; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_ashr_i32 s20, s1, 16
-; GCN-HSA-NEXT: s_ashr_i32 s21, s0, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s22, s1
-; GCN-HSA-NEXT: s_sext_i32_i16 s23, s0
-; GCN-HSA-NEXT: s_ashr_i32 s24, s3, 16
-; GCN-HSA-NEXT: s_ashr_i32 s25, s2, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s26, s3
-; GCN-HSA-NEXT: s_sext_i32_i16 s27, s2
-; GCN-HSA-NEXT: s_ashr_i32 s28, s5, 16
-; GCN-HSA-NEXT: s_ashr_i32 s29, s4, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s30, s5
-; GCN-HSA-NEXT: s_sext_i32_i16 s31, s4
-; GCN-HSA-NEXT: s_ashr_i32 s33, s7, 16
-; GCN-HSA-NEXT: s_ashr_i32 s34, s6, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s35, s7
-; GCN-HSA-NEXT: s_sext_i32_i16 s36, s6
-; GCN-HSA-NEXT: s_ashr_i32 s37, s9, 16
-; GCN-HSA-NEXT: s_ashr_i32 s38, s8, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s39, s9
-; GCN-HSA-NEXT: s_sext_i32_i16 s40, s8
-; GCN-HSA-NEXT: s_ashr_i32 s41, s11, 16
-; GCN-HSA-NEXT: s_ashr_i32 s42, s10, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s43, s11
-; GCN-HSA-NEXT: s_sext_i32_i16 s44, s10
-; GCN-HSA-NEXT: s_ashr_i32 s45, s13, 16
-; GCN-HSA-NEXT: s_ashr_i32 s47, s12, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s46, s13
-; GCN-HSA-NEXT: s_sext_i32_i16 s49, s12
-; GCN-HSA-NEXT: s_ashr_i32 s48, s15, 16
-; GCN-HSA-NEXT: s_ashr_i32 s50, s14, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s51, s15
-; GCN-HSA-NEXT: s_sext_i32_i16 s52, s14
-; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x10
+; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GCN-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x10
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_ashr_i32 s18, s1, 16
-; GCN-HSA-NEXT: s_ashr_i32 s19, s0, 16
-; GCN-HSA-NEXT: s_ashr_i32 s53, s3, 16
-; GCN-HSA-NEXT: s_ashr_i32 s54, s2, 16
-; GCN-HSA-NEXT: s_ashr_i32 s57, s5, 16
-; GCN-HSA-NEXT: s_ashr_i32 s58, s4, 16
-; GCN-HSA-NEXT: s_ashr_i32 s59, s7, 16
-; GCN-HSA-NEXT: s_ashr_i32 s60, s6, 16
-; GCN-HSA-NEXT: s_ashr_i32 s61, s9, 16
-; GCN-HSA-NEXT: s_ashr_i32 s62, s8, 16
-; GCN-HSA-NEXT: s_ashr_i32 s63, s11, 16
-; GCN-HSA-NEXT: s_ashr_i32 s64, s10, 16
-; GCN-HSA-NEXT: s_ashr_i32 s65, s13, 16
-; GCN-HSA-NEXT: s_ashr_i32 s66, s12, 16
-; GCN-HSA-NEXT: s_ashr_i32 s67, s15, 16
-; GCN-HSA-NEXT: s_ashr_i32 s68, s14, 16
-; GCN-HSA-NEXT: s_sext_i32_i16 s56, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s16, 0xf0
-; GCN-HSA-NEXT: s_sext_i32_i16 s55, s3
-; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s16, 0xe0
-; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s16, 0xd0
-; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s16, 0xc0
-; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s16, 0xb0
-; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s3
-; GCN-HSA-NEXT: s_sext_i32_i16 s11, s11
-; GCN-HSA-NEXT: s_sext_i32_i16 s10, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s16, 0xa0
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s10
+; GCN-HSA-NEXT: s_ashr_i32 s33, s1, 16
+; GCN-HSA-NEXT: s_ashr_i32 s34, s0, 16
+; GCN-HSA-NEXT: s_ashr_i32 s35, s3, 16
+; GCN-HSA-NEXT: s_ashr_i32 s40, s2, 16
+; GCN-HSA-NEXT: s_ashr_i32 s41, s5, 16
+; GCN-HSA-NEXT: s_ashr_i32 s42, s4, 16
+; GCN-HSA-NEXT: s_ashr_i32 s43, s7, 16
+; GCN-HSA-NEXT: s_ashr_i32 s44, s6, 16
+; GCN-HSA-NEXT: s_ashr_i32 s45, s9, 16
+; GCN-HSA-NEXT: s_ashr_i32 s46, s8, 16
+; GCN-HSA-NEXT: s_ashr_i32 s47, s11, 16
+; GCN-HSA-NEXT: s_ashr_i32 s48, s10, 16
+; GCN-HSA-NEXT: s_ashr_i32 s49, s13, 16
+; GCN-HSA-NEXT: s_ashr_i32 s50, s12, 16
+; GCN-HSA-NEXT: s_ashr_i32 s38, s15, 16
+; GCN-HSA-NEXT: s_ashr_i32 s39, s14, 16
+; GCN-HSA-NEXT: s_ashr_i32 s51, s17, 16
+; GCN-HSA-NEXT: s_ashr_i32 s52, s16, 16
+; GCN-HSA-NEXT: s_ashr_i32 s53, s19, 16
+; GCN-HSA-NEXT: s_ashr_i32 s54, s18, 16
+; GCN-HSA-NEXT: s_ashr_i32 s57, s21, 16
+; GCN-HSA-NEXT: s_ashr_i32 s58, s20, 16
+; GCN-HSA-NEXT: s_ashr_i32 s59, s23, 16
+; GCN-HSA-NEXT: s_ashr_i32 s60, s22, 16
+; GCN-HSA-NEXT: s_ashr_i32 s61, s25, 16
+; GCN-HSA-NEXT: s_ashr_i32 s62, s24, 16
+; GCN-HSA-NEXT: s_ashr_i32 s63, s27, 16
+; GCN-HSA-NEXT: s_ashr_i32 s64, s26, 16
+; GCN-HSA-NEXT: s_ashr_i32 s65, s29, 16
+; GCN-HSA-NEXT: s_ashr_i32 s66, s28, 16
+; GCN-HSA-NEXT: s_ashr_i32 s67, s31, 16
+; GCN-HSA-NEXT: s_ashr_i32 s68, s30, 16
+; GCN-HSA-NEXT: s_sext_i32_i16 s56, s18
+; GCN-HSA-NEXT: s_add_u32 s18, s36, 0xf0
+; GCN-HSA-NEXT: s_sext_i32_i16 s55, s19
+; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s19
+; GCN-HSA-NEXT: s_add_u32 s18, s36, 0xe0
+; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s19
+; GCN-HSA-NEXT: s_add_u32 s18, s36, 0xd0
+; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s18
+; GCN-HSA-NEXT: s_add_u32 s18, s36, 0xc0
+; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s18
+; GCN-HSA-NEXT: s_add_u32 s18, s36, 0xb0
+; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s18
+; GCN-HSA-NEXT: s_add_u32 s18, s36, 0xa0
+; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s19
+; GCN-HSA-NEXT: s_sext_i32_i16 s27, s27
+; GCN-HSA-NEXT: s_sext_i32_i16 s26, s26
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s18
+; GCN-HSA-NEXT: s_add_u32 s18, s36, 0x90
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s26
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s64
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s27
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s63
-; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[23:24], v[8:11]
-; GCN-HSA-NEXT: s_sext_i32_i16 s9, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s3
-; GCN-HSA-NEXT: s_sext_i32_i16 s8, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s16, 0x90
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s19
+; GCN-HSA-NEXT: s_sext_i32_i16 s25, s25
+; GCN-HSA-NEXT: s_sext_i32_i16 s24, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s18
+; GCN-HSA-NEXT: s_add_u32 s18, s36, 0x80
+; GCN-HSA-NEXT: s_sext_i32_i16 s14, s14
+; GCN-HSA-NEXT: s_sext_i32_i16 s31, s31
+; GCN-HSA-NEXT: s_sext_i32_i16 s30, s30
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s62
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s61
-; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[25:26], v[12:15]
-; GCN-HSA-NEXT: s_sext_i32_i16 s13, s13
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
-; GCN-HSA-NEXT: s_sext_i32_i16 s12, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s16, 0x80
-; GCN-HSA-NEXT: s_sext_i32_i16 s0, s0
+; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
; GCN-HSA-NEXT: s_sext_i32_i16 s15, s15
-; GCN-HSA-NEXT: s_sext_i32_i16 s14, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GCN-HSA-NEXT: s_sext_i32_i16 s23, s23
+; GCN-HSA-NEXT: s_sext_i32_i16 s22, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s30
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s68
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s67
+; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[12:15]
+; GCN-HSA-NEXT: s_sext_i32_i16 s12, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s14
+; GCN-HSA-NEXT: s_add_u32 s14, s36, 0x70
+; GCN-HSA-NEXT: s_sext_i32_i16 s29, s29
+; GCN-HSA-NEXT: s_sext_i32_i16 s28, s28
+; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s60
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s59
+; GCN-HSA-NEXT: s_addc_u32 s15, s37, 0
+; GCN-HSA-NEXT: s_sext_i32_i16 s13, s13
+; GCN-HSA-NEXT: s_sext_i32_i16 s21, s21
+; GCN-HSA-NEXT: s_sext_i32_i16 s20, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s28
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s66
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s29
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s65
-; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: s_sext_i32_i16 s1, s1
-; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GCN-HSA-NEXT: s_add_u32 s12, s36, 0x60
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s58
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s57
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GCN-HSA-NEXT: s_addc_u32 s13, s37, 0
+; GCN-HSA-NEXT: s_sext_i32_i16 s10, s10
+; GCN-HSA-NEXT: s_sext_i32_i16 s17, s17
+; GCN-HSA-NEXT: s_sext_i32_i16 s16, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s56
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s54
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s55
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s53
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s15
+; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
+; GCN-HSA-NEXT: s_sext_i32_i16 s11, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s51
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s49
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s12
+; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GCN-HSA-NEXT: s_sext_i32_i16 s8, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GCN-HSA-NEXT: s_add_u32 s10, s36, 0x50
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GCN-HSA-NEXT: s_addc_u32 s11, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s48
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GCN-HSA-NEXT: s_sext_i32_i16 s9, s9
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_sext_i32_i16 s6, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s68
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s67
-; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[4:7]
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x70
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s60
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s7
-; GCN-HSA-NEXT: flat_store_dwordx4 v[19:20], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s59
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s1
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[27:28], v[16:19]
-; GCN-HSA-NEXT: s_sext_i32_i16 s5, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x60
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GCN-HSA-NEXT: s_add_u32 s8, s36, 64
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GCN-HSA-NEXT: s_addc_u32 s9, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s45
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_sext_i32_i16 s4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 0x50
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GCN-HSA-NEXT: s_add_u32 s6, s36, 48
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GCN-HSA-NEXT: s_addc_u32 s7, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GCN-HSA-NEXT: s_sext_i32_i16 s5, s5
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: s_sext_i32_i16 s2, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s56
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s58
+; GCN-HSA-NEXT: s_add_u32 s4, s36, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s57
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s54
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s55
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s52
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s18
-; GCN-HSA-NEXT: flat_store_dwordx4 v[9:10], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s50
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s49
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s51
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s47
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s45
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[20:23]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s44
+; GCN-HSA-NEXT: s_addc_u32 s5, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s43
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s41
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCN-HSA-NEXT: s_sext_i32_i16 s3, s3
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s40
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s39
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s37
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: s_sext_i32_i16 s1, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s36, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GCN-HSA-NEXT: s_addc_u32 s3, s37, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s40
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: s_sext_i32_i16 s0, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s34
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s33
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s31
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s28
-; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s27
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s24
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s23
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s21
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s37
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
;
@@ -7139,70 +7142,69 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_mov_b32 s12, s7
+; GCN-HSA-NEXT: s_ashr_i32 s25, s1, 31
+; GCN-HSA-NEXT: s_ashr_i32 s27, s1, 16
+; GCN-HSA-NEXT: s_ashr_i32 s30, s3, 31
+; GCN-HSA-NEXT: s_ashr_i32 s31, s3, 16
; GCN-HSA-NEXT: s_mov_b32 s14, s5
; GCN-HSA-NEXT: s_mov_b32 s16, s3
; GCN-HSA-NEXT: s_mov_b32 s18, s1
-; GCN-HSA-NEXT: s_ashr_i32 s27, s1, 31
-; GCN-HSA-NEXT: s_ashr_i32 s29, s3, 31
-; GCN-HSA-NEXT: s_ashr_i32 s30, s3, 16
; GCN-HSA-NEXT: s_lshr_b32 s20, s6, 16
; GCN-HSA-NEXT: s_lshr_b32 s22, s4, 16
; GCN-HSA-NEXT: s_lshr_b32 s24, s2, 16
; GCN-HSA-NEXT: s_lshr_b32 s26, s0, 16
; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[2:3], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s28, s1, 16
-; GCN-HSA-NEXT: s_ashr_i32 s31, s5, 31
-; GCN-HSA-NEXT: s_ashr_i32 s33, s5, 16
-; GCN-HSA-NEXT: s_ashr_i32 s34, s7, 31
-; GCN-HSA-NEXT: s_ashr_i32 s35, s7, 16
+; GCN-HSA-NEXT: s_ashr_i32 s33, s5, 31
+; GCN-HSA-NEXT: s_ashr_i32 s34, s5, 16
+; GCN-HSA-NEXT: s_ashr_i32 s35, s7, 31
+; GCN-HSA-NEXT: s_ashr_i32 s36, s7, 16
; GCN-HSA-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[4:5], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[26:27], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[24:25], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[24:25], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[22:23], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
-; GCN-HSA-NEXT: s_add_u32 s24, s8, 0x70
-; GCN-HSA-NEXT: s_addc_u32 s25, s9, 0
+; GCN-HSA-NEXT: s_add_u32 s22, s8, 0x70
+; GCN-HSA-NEXT: s_addc_u32 s23, s9, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
; GCN-HSA-NEXT: s_add_u32 s14, s8, 0x50
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
; GCN-HSA-NEXT: s_addc_u32 s15, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s25
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s35
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s14
; GCN-HSA-NEXT: s_add_u32 s14, s8, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s33
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s31
-; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; GCN-HSA-NEXT: s_addc_u32 s15, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
; GCN-HSA-NEXT: s_add_u32 s14, s8, 16
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s33
+; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s15, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s28
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s27
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s30
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s27
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s15
+; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s25
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: s_add_u32 s6, s8, 0x60
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
@@ -7211,24 +7213,24 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GCN-HSA-NEXT: s_add_u32 s6, s8, 64
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: s_addc_u32 s7, s9, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GCN-HSA-NEXT: s_add_u32 s4, s8, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GCN-HSA-NEXT: s_addc_u32 s5, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s23
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s4
; GCN-HSA-NEXT: s_add_u32 s4, s8, 32
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s9, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
@@ -7613,134 +7615,136 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_lshr_b32 s20, s1, 16
-; GCN-HSA-NEXT: s_lshr_b32 s21, s3, 16
-; GCN-HSA-NEXT: s_lshr_b32 s22, s5, 16
-; GCN-HSA-NEXT: s_lshr_b32 s23, s7, 16
-; GCN-HSA-NEXT: s_lshr_b32 s24, s9, 16
-; GCN-HSA-NEXT: s_lshr_b32 s25, s11, 16
-; GCN-HSA-NEXT: s_lshr_b32 s26, s13, 16
-; GCN-HSA-NEXT: s_lshr_b32 s27, s15, 16
-; GCN-HSA-NEXT: s_lshr_b32 s28, s14, 16
-; GCN-HSA-NEXT: s_lshr_b32 s29, s12, 16
-; GCN-HSA-NEXT: s_lshr_b32 s30, s10, 16
-; GCN-HSA-NEXT: s_lshr_b32 s31, s8, 16
-; GCN-HSA-NEXT: s_lshr_b32 s33, s6, 16
-; GCN-HSA-NEXT: s_lshr_b32 s34, s4, 16
+; GCN-HSA-NEXT: s_lshr_b32 s23, s1, 16
+; GCN-HSA-NEXT: s_lshr_b32 s24, s3, 16
+; GCN-HSA-NEXT: s_lshr_b32 s25, s5, 16
+; GCN-HSA-NEXT: s_lshr_b32 s26, s7, 16
+; GCN-HSA-NEXT: s_lshr_b32 s27, s9, 16
+; GCN-HSA-NEXT: s_lshr_b32 s28, s11, 16
+; GCN-HSA-NEXT: s_lshr_b32 s29, s13, 16
+; GCN-HSA-NEXT: s_lshr_b32 s30, s15, 16
+; GCN-HSA-NEXT: s_lshr_b32 s31, s14, 16
+; GCN-HSA-NEXT: s_lshr_b32 s33, s12, 16
+; GCN-HSA-NEXT: s_lshr_b32 s34, s10, 16
+; GCN-HSA-NEXT: s_lshr_b32 s22, s8, 16
+; GCN-HSA-NEXT: s_lshr_b32 s21, s6, 16
+; GCN-HSA-NEXT: s_lshr_b32 s20, s4, 16
; GCN-HSA-NEXT: s_lshr_b32 s19, s2, 16
; GCN-HSA-NEXT: s_lshr_b32 s18, s0, 16
; GCN-HSA-NEXT: s_and_b32 s0, s0, 0xffff
; GCN-HSA-NEXT: s_and_b32 s2, s2, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s35, s4, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s4, s4, 0xffff
; GCN-HSA-NEXT: s_and_b32 s6, s6, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s8, s8, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s35, s8, 0xffff
; GCN-HSA-NEXT: s_and_b32 s10, s10, 0xffff
; GCN-HSA-NEXT: s_and_b32 s12, s12, 0xffff
; GCN-HSA-NEXT: s_and_b32 s14, s14, 0xffff
; GCN-HSA-NEXT: s_and_b32 s1, s1, 0xffff
; GCN-HSA-NEXT: s_and_b32 s3, s3, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s36, s5, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s5, s5, 0xffff
; GCN-HSA-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-HSA-NEXT: s_and_b32 s9, s9, 0xffff
+; GCN-HSA-NEXT: s_and_b32 s36, s9, 0xffff
; GCN-HSA-NEXT: s_and_b32 s11, s11, 0xffff
; GCN-HSA-NEXT: s_and_b32 s13, s13, 0xffff
; GCN-HSA-NEXT: s_and_b32 s15, s15, 0xffff
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0xf0
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0xd0
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s4
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0xb0
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s4
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0x90
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xf0
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xd0
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s9
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xb0
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s9
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0x90
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s8
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0x70
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0x50
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s8
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s27
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s13
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s29
; GCN-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0x70
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s25
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s28
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 16
; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s24
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s27
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s7
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s23
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0x50
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 48
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s25
+; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xe0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s21
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 16
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s24
+; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0xe0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s28
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0xc0
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s31
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xc0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0xa0
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s33
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xa0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0x80
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0x80
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s31
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 0x60
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s33
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 64
+; GCN-HSA-NEXT: s_add_u32 s6, s16, 0x60
+; GCN-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GCN-HSA-NEXT: s_add_u32 s4, s16, 64
; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s35
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8323,36 +8327,36 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_mov_b32 s34, s15
+; GCN-HSA-NEXT: s_mov_b32 s30, s15
; GCN-HSA-NEXT: s_ashr_i32 s41, s3, 31
-; GCN-HSA-NEXT: s_ashr_i32 s42, s3, 16
-; GCN-HSA-NEXT: s_ashr_i32 s57, s5, 16
-; GCN-HSA-NEXT: s_ashr_i32 s59, s7, 31
-; GCN-HSA-NEXT: s_ashr_i32 s61, s7, 16
-; GCN-HSA-NEXT: s_ashr_i32 s63, s9, 31
-; GCN-HSA-NEXT: s_ashr_i32 s65, s9, 16
-; GCN-HSA-NEXT: s_ashr_i32 s67, s11, 31
-; GCN-HSA-NEXT: s_ashr_i32 s69, s11, 16
-; GCN-HSA-NEXT: s_mov_b32 s44, s13
-; GCN-HSA-NEXT: s_mov_b32 s46, s11
-; GCN-HSA-NEXT: s_mov_b32 s48, s9
-; GCN-HSA-NEXT: s_mov_b32 s50, s7
-; GCN-HSA-NEXT: s_mov_b32 s52, s5
+; GCN-HSA-NEXT: s_ashr_i32 s55, s3, 16
+; GCN-HSA-NEXT: s_ashr_i32 s57, s5, 31
+; GCN-HSA-NEXT: s_ashr_i32 s59, s5, 16
+; GCN-HSA-NEXT: s_ashr_i32 s61, s7, 31
+; GCN-HSA-NEXT: s_ashr_i32 s63, s7, 16
+; GCN-HSA-NEXT: s_ashr_i32 s65, s9, 31
+; GCN-HSA-NEXT: s_ashr_i32 s67, s9, 16
+; GCN-HSA-NEXT: s_mov_b32 s42, s13
+; GCN-HSA-NEXT: s_mov_b32 s44, s11
+; GCN-HSA-NEXT: s_mov_b32 s46, s9
+; GCN-HSA-NEXT: s_mov_b32 s48, s7
+; GCN-HSA-NEXT: s_mov_b32 s50, s5
; GCN-HSA-NEXT: s_mov_b32 s38, s3
; GCN-HSA-NEXT: s_mov_b32 s36, s1
-; GCN-HSA-NEXT: s_lshr_b32 s54, s14, 16
-; GCN-HSA-NEXT: s_lshr_b32 s56, s12, 16
-; GCN-HSA-NEXT: s_lshr_b32 s58, s10, 16
-; GCN-HSA-NEXT: s_lshr_b32 s60, s8, 16
-; GCN-HSA-NEXT: s_lshr_b32 s62, s6, 16
-; GCN-HSA-NEXT: s_lshr_b32 s64, s4, 16
-; GCN-HSA-NEXT: s_lshr_b32 s66, s2, 16
-; GCN-HSA-NEXT: s_lshr_b32 s68, s0, 16
+; GCN-HSA-NEXT: s_lshr_b32 s52, s14, 16
+; GCN-HSA-NEXT: s_lshr_b32 s54, s12, 16
+; GCN-HSA-NEXT: s_lshr_b32 s56, s10, 16
+; GCN-HSA-NEXT: s_lshr_b32 s58, s8, 16
+; GCN-HSA-NEXT: s_lshr_b32 s60, s6, 16
+; GCN-HSA-NEXT: s_lshr_b32 s62, s4, 16
+; GCN-HSA-NEXT: s_lshr_b32 s64, s2, 16
+; GCN-HSA-NEXT: s_lshr_b32 s66, s0, 16
; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[2:3], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[34:35], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[30:31], 0x100000
; GCN-HSA-NEXT: s_ashr_i32 s33, s1, 31
; GCN-HSA-NEXT: s_ashr_i32 s40, s1, 16
-; GCN-HSA-NEXT: s_ashr_i32 s43, s5, 31
+; GCN-HSA-NEXT: s_ashr_i32 s68, s11, 31
+; GCN-HSA-NEXT: s_ashr_i32 s69, s11, 16
; GCN-HSA-NEXT: s_ashr_i32 s70, s13, 31
; GCN-HSA-NEXT: s_ashr_i32 s71, s13, 16
; GCN-HSA-NEXT: s_ashr_i32 s72, s15, 31
@@ -8363,112 +8367,113 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[8:9], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[10:11], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[14:15], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[68:69], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[66:67], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[64:65], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[62:63], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[60:61], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[58:59], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[56:57], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[54:55], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[14:15], 0x100000
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[66:67], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[62:63], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[60:61], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[58:59], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[56:57], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[54:55], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[52:53], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x100000
-; GCN-HSA-NEXT: s_add_u32 s54, s16, 0xf0
-; GCN-HSA-NEXT: s_addc_u32 s55, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s44
-; GCN-HSA-NEXT: s_add_u32 s44, s16, 0xd0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s45
-; GCN-HSA-NEXT: s_addc_u32 s45, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s44
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s45
-; GCN-HSA-NEXT: s_add_u32 s44, s16, 0xb0
-; GCN-HSA-NEXT: s_addc_u32 s45, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s44
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s45
-; GCN-HSA-NEXT: s_add_u32 s44, s16, 0x90
-; GCN-HSA-NEXT: s_addc_u32 s45, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s44
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s54
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s45
-; GCN-HSA-NEXT: s_add_u32 s44, s16, 0x70
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s55
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s73
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s72
-; GCN-HSA-NEXT: s_addc_u32 s45, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s71
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
-; GCN-HSA-NEXT: s_add_u32 s38, s16, 0x50
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s70
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s39
-; GCN-HSA-NEXT: s_addc_u32 s39, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s47
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s69
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s67
-; GCN-HSA-NEXT: flat_store_dwordx4 v[23:24], v[4:7]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[25:26], v[8:11]
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
+; GCN-HSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x100000
+; GCN-HSA-NEXT: s_add_u32 s52, s16, 0xf0
+; GCN-HSA-NEXT: s_addc_u32 s53, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s42
+; GCN-HSA-NEXT: s_add_u32 s42, s16, 0xd0
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s43
+; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s43
+; GCN-HSA-NEXT: s_add_u32 s42, s16, 0xb0
+; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s43
+; GCN-HSA-NEXT: s_add_u32 s42, s16, 0x90
+; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s43
+; GCN-HSA-NEXT: s_add_u32 s42, s16, 0x70
+; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s43
+; GCN-HSA-NEXT: s_add_u32 s42, s16, 0x50
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s53
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s73
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s72
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s71
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s70
+; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s45
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[2:5]
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s69
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s68
+; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[6:9]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[10:13]
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s36
; GCN-HSA-NEXT: s_add_u32 s36, s16, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s37
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s37
; GCN-HSA-NEXT: s_addc_u32 s37, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s37
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s37
; GCN-HSA-NEXT: s_add_u32 s36, s16, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s67
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s65
; GCN-HSA-NEXT: s_addc_u32 s37, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s30
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[14:17]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s48
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s30
; GCN-HSA-NEXT: s_add_u32 s30, s16, 0xe0
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s49
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s65
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s63
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s49
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s63
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s61
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s31
; GCN-HSA-NEXT: s_addc_u32 s31, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v29, s44
-; GCN-HSA-NEXT: flat_store_dwordx4 v[27:28], v[12:15]
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s50
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v28, s42
+; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
; GCN-HSA-NEXT: s_add_u32 s14, s16, 0xc0
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s51
-; GCN-HSA-NEXT: v_mov_b32_e32 v30, s45
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s61
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s59
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s51
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s59
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s57
+; GCN-HSA-NEXT: v_mov_b32_e32 v29, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
; GCN-HSA-NEXT: s_addc_u32 s15, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s52
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s57
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s43
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s39
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s41
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s36
-; GCN-HSA-NEXT: flat_store_dwordx4 v[29:30], v[16:19]
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s37
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s30
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s55
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s30
+; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[18:21]
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s37
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s40
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s33
-; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[20:23]
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s28
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s34
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s35
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s40
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s33
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s31
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s14
-; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s12
; GCN-HSA-NEXT: s_add_u32 s12, s16, 0xa0
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s13
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
index 917c690ec5e89..34828aa418bc5 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
@@ -3141,74 +3141,74 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_ashr_i32 s36, s14, 31
; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0x70
; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s18
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s19
; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0x60
; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s18
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s19
; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0x50
; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GFX7-HSA-NEXT: s_add_u32 s14, s16, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 64
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 48
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
-; GFX7-HSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s34
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s33
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX7-HSA-NEXT: s_add_u32 s6, s16, 48
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[15:16], v[3:6]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
-; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s27
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s29
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[3:6]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s27
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[6:9]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s26
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT: s_add_u32 s4, s16, 32
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
-; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[3:6]
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s19
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GFX7-HSA-NEXT: s_add_u32 s2, s16, 16
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
-; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s22
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s31
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s30
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s11
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s29
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s28
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s14
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[17:18], v[6:9]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s20
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[19:20], v[9:12]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s22
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s21
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[9:12]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[6:9]
; GFX7-HSA-NEXT: s_endpgm
;
; GFX8-NOHSA-LABEL: constant_sextload_v16i32_to_v16i64:
@@ -4069,190 +4069,187 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
;
; GFX7-HSA-LABEL: constant_sextload_v32i32_to_v32i64:
; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[36:39], s[8:9], 0x0
; GFX7-HSA-NEXT: s_add_i32 s12, s12, s17
-; GFX7-HSA-NEXT: s_load_dwordx4 s[16:19], s[8:9], 0x0
; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x10
-; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_ashr_i32 s20, s1, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s21, s0, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s22, s3, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s23, s2, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s24, s5, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s25, s4, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s28, s7, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s29, s6, 31
-; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s14
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX7-HSA-NEXT: s_ashr_i32 s36, s9, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s37, s8, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s38, s11, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s39, s10, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s40, s13, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s41, s12, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s42, s15, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s43, s14, 31
-; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s13
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s11
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s4
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s5
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s2
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s1
-; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s43
-; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s42
-; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s41
-; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s40
+; GFX7-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x10
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_ashr_i32 s18, s1, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s19, s0, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s26, s3, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s27, s2, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s30, s5, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s31, s4, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s33, s7, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s44, s6, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s45, s9, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s46, s8, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s47, s11, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s48, s10, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s49, s13, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s50, s12, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s51, s15, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s52, s14, 31
-; GFX7-HSA-NEXT: s_add_u32 s34, s16, 0xf0
-; GFX7-HSA-NEXT: s_addc_u32 s35, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v32, s35
-; GFX7-HSA-NEXT: s_add_u32 s34, s16, 0xe0
-; GFX7-HSA-NEXT: s_addc_u32 s35, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v33, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v34, s35
-; GFX7-HSA-NEXT: s_add_u32 s34, s16, 0xd0
-; GFX7-HSA-NEXT: s_addc_u32 s35, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v36, s35
-; GFX7-HSA-NEXT: v_mov_b32_e32 v35, s34
-; GFX7-HSA-NEXT: s_add_u32 s34, s16, 0xc0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[31:32], v[27:30]
-; GFX7-HSA-NEXT: s_addc_u32 s35, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s35
-; GFX7-HSA-NEXT: s_add_u32 s34, s16, 0xb0
-; GFX7-HSA-NEXT: s_addc_u32 s35, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s35
-; GFX7-HSA-NEXT: s_add_u32 s34, s16, 0xa0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[33:34], v[23:26]
-; GFX7-HSA-NEXT: s_addc_u32 s35, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s35
-; GFX7-HSA-NEXT: s_add_u32 s34, s16, 0x90
-; GFX7-HSA-NEXT: s_addc_u32 s35, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s37
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s36
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s28
-; GFX7-HSA-NEXT: s_add_u32 s28, s16, 0x80
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
-; GFX7-HSA-NEXT: s_addc_u32 s29, s17, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[27:28], v[4:7]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s28
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s29
-; GFX7-HSA-NEXT: s_add_u32 s28, s16, 0x70
-; GFX7-HSA-NEXT: s_addc_u32 s29, s17, 0
-; GFX7-HSA-NEXT: s_add_u32 s24, s16, 0x60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s25
-; GFX7-HSA-NEXT: s_addc_u32 s25, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s39
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s38
+; GFX7-HSA-NEXT: s_ashr_i32 s33, s17, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s34, s16, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s35, s19, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s40, s18, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s41, s21, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s42, s20, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s43, s23, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s44, s22, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s22
+; GFX7-HSA-NEXT: s_ashr_i32 s45, s25, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s46, s24, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s47, s27, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s26, s26, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s48, s29, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s28, s28, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s24, s31, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s30, s30, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s17
+; GFX7-HSA-NEXT: s_ashr_i32 s16, s1, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s17, s0, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s18, s3, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s19, s2, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s20, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s21, s4, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s22, s7, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s23, s6, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s27, s9, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s29, s8, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s31, s11, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s38, s10, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s39, s13, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s49, s12, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s50, s15, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s51, s14, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xf0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xe0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s30
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[29:30], v[25:28]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xd0
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s25
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s34
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[35:36], v[8:11]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s48
; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s28
-; GFX7-HSA-NEXT: s_add_u32 s24, s16, 0x50
-; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s35
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s29
-; GFX7-HSA-NEXT: s_addc_u32 s25, s17, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[29:30], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s23
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s22
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s21
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[23:24], v[16:19]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[25:26], v[12:15]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s52
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s20
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s51
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xc0
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[25:26], v[18:21]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s25
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xb0
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s25
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xa0
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x90
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[27:28], v[7:10]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s46
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s25
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x80
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x70
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v32, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x60
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v34, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v33, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s43
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s51
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s50
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s25
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s50
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[20:23]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s49
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GFX7-HSA-NEXT: s_add_u32 s14, s16, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v36, s25
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[31:32], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s49
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s39
+; GFX7-HSA-NEXT: s_add_u32 s14, s36, 64
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
-; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s47
-; GFX7-HSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v35, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s40
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s35
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[29:30], v[11:14]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[22:25]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s31
+; GFX7-HSA-NEXT: s_addc_u32 s15, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[27:28], v[3:6]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[33:34], v[3:6]
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s46
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s27
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[29:30], v[6:9]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[35:36], v[6:9]
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s8
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[9:12]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX7-HSA-NEXT: s_add_u32 s6, s16, 48
+; GFX7-HSA-NEXT: s_add_u32 s6, s36, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
-; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: s_addc_u32 s7, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s44
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s22
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s34
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT: s_add_u32 s4, s16, 32
+; GFX7-HSA-NEXT: s_add_u32 s4, s36, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
-; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: s_addc_u32 s5, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s31
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s20
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s33
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GFX7-HSA-NEXT: s_add_u32 s2, s16, 16
+; GFX7-HSA-NEXT: s_add_u32 s2, s36, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
-; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: s_addc_u32 s3, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s27
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s37
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[15:18]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_endpgm
;
@@ -5079,67 +5076,61 @@ define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_addc_u32 s17, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: s_add_u32 s16, s36, 0x70
+; GFX7-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s17
+; GFX7-HSA-NEXT: s_add_u32 s16, s36, 0x60
+; GFX7-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s17
+; GFX7-HSA-NEXT: s_add_u32 s16, s36, 0x50
+; GFX7-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s17
+; GFX7-HSA-NEXT: s_add_u32 s16, s36, 64
+; GFX7-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s17
+; GFX7-HSA-NEXT: s_add_u32 s16, s36, 48
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s17, s37, 0
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GFX7-HSA-NEXT: s_add_u32 s14, s36, 0x70
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
-; GFX7-HSA-NEXT: s_addc_u32 s15, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX7-HSA-NEXT: s_add_u32 s14, s36, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
-; GFX7-HSA-NEXT: s_add_u32 s12, s36, 0x60
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
-; GFX7-HSA-NEXT: s_addc_u32 s13, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GFX7-HSA-NEXT: s_add_u32 s10, s36, 0x50
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
-; GFX7-HSA-NEXT: s_addc_u32 s11, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: s_addc_u32 s15, s37, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s17
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
-; GFX7-HSA-NEXT: s_add_u32 s8, s36, 64
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
-; GFX7-HSA-NEXT: s_addc_u32 s9, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX7-HSA-NEXT: s_add_u32 s12, s36, 16
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX7-HSA-NEXT: s_add_u32 s6, s36, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
-; GFX7-HSA-NEXT: s_addc_u32 s7, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: s_addc_u32 s13, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT: s_add_u32 s4, s36, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
-; GFX7-HSA-NEXT: s_addc_u32 s5, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GFX7-HSA-NEXT: s_add_u32 s2, s36, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
-; GFX7-HSA-NEXT: s_addc_u32 s3, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s36
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s37
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s37
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 6584a1e2b760e..2ed6a9cff42bc 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -2491,45 +2491,45 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_bfe_u32 s11, s11, 0x80010
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x60
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x50
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s27
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s25
-; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s24
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s22
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s33
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s20
-; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s22
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s20
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s31
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
@@ -2957,50 +2957,50 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_bfe_i32 s36, s11, 0x80008
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x60
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s3
-; GFX7-HSA-NEXT: s_sext_i32_i8 s10, s10
-; GFX7-HSA-NEXT: s_sext_i32_i8 s11, s11
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x50
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s11, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s34
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_sext_i32_i8 s10, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: s_sext_i32_i8 s9, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s33
-; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s31
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s30
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
-; GFX7-HSA-NEXT: s_sext_i32_i8 s9, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s28
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s27
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: s_sext_i32_i8 s8, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s26
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s24
-; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s27
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s24
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
@@ -3524,19 +3524,19 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_lshr_b32 s41, s8, 24
; GFX7-HSA-NEXT: s_bfe_u32 s43, s8, 0x80008
; GFX7-HSA-NEXT: s_lshr_b32 s44, s9, 24
-; GFX7-HSA-NEXT: s_bfe_u32 s46, s9, 0x80008
-; GFX7-HSA-NEXT: s_lshr_b32 s47, s10, 24
-; GFX7-HSA-NEXT: s_bfe_u32 s48, s10, 0x80008
-; GFX7-HSA-NEXT: s_lshr_b32 s49, s11, 24
-; GFX7-HSA-NEXT: s_bfe_u32 s50, s11, 0x80008
-; GFX7-HSA-NEXT: s_lshr_b32 s51, s12, 24
-; GFX7-HSA-NEXT: s_bfe_u32 s52, s12, 0x80008
-; GFX7-HSA-NEXT: s_lshr_b32 s53, s13, 24
-; GFX7-HSA-NEXT: s_bfe_u32 s54, s13, 0x80008
-; GFX7-HSA-NEXT: s_lshr_b32 s55, s14, 24
-; GFX7-HSA-NEXT: s_bfe_u32 s56, s14, 0x80008
-; GFX7-HSA-NEXT: s_lshr_b32 s57, s15, 24
-; GFX7-HSA-NEXT: s_bfe_u32 s58, s15, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s45, s9, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s46, s10, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s47, s10, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s48, s11, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s49, s11, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s50, s12, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s51, s12, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s52, s13, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s53, s13, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s54, s14, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s55, s14, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s56, s15, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s57, s15, 0x80008
; GFX7-HSA-NEXT: s_and_b32 s24, s0, 0xff
; GFX7-HSA-NEXT: s_bfe_u32 s0, s0, 0x80010
; GFX7-HSA-NEXT: s_and_b32 s27, s1, 0xff
@@ -3551,7 +3551,7 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_bfe_u32 s5, s5, 0x80010
; GFX7-HSA-NEXT: s_and_b32 s42, s6, 0xff
; GFX7-HSA-NEXT: s_bfe_u32 s6, s6, 0x80010
-; GFX7-HSA-NEXT: s_and_b32 s45, s7, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s58, s7, 0xff
; GFX7-HSA-NEXT: s_bfe_u32 s7, s7, 0x80010
; GFX7-HSA-NEXT: s_and_b32 s59, s8, 0xff
; GFX7-HSA-NEXT: s_bfe_u32 s60, s8, 0x80010
@@ -3571,95 +3571,95 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_bfe_u32 s15, s15, 0x80010
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xf0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xe0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xd0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xc0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xb0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xa0
+; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x90
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s66
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s54
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s53
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s13
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s53
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s52
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[23:24], v[8:11]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x80
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s65
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s8
-; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x90
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s52
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s51
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s51
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s50
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[25:26], v[12:15]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[12:15]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s68
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s8
-; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x80
-; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s58
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s57
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s57
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s56
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x70
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[19:20], v[0:3]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s63
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s47
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[9:10], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s49
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s67
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s55
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s54
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s63
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s50
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s11
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s49
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s46
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s7
; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s67
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s56
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s14
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s55
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[27:28], v[16:19]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s61
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s7
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[21:22], v[4:7]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s46
-; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s62
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s59
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s44
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s43
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s6
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s61
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s62
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s6
; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x50
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s45
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s59
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s43
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s58
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s41
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s42
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s39
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s39
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s38
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s37
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s35
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[20:23]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s40
@@ -4458,103 +4458,103 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xf0
; GFX7-HSA-NEXT: s_sext_i32_i8 s50, s9
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xe0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xd0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xc0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xb0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s9
-; GFX7-HSA-NEXT: s_sext_i32_i8 s13, s13
-; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xa0
+; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s9
+; GFX7-HSA-NEXT: s_sext_i32_i8 s13, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x90
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s62
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s61
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s60
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[23:24], v[8:11]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s9
; GFX7-HSA-NEXT: s_sext_i32_i8 s12, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s8
-; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x90
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x80
+; GFX7-HSA-NEXT: s_sext_i32_i8 s15, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s59
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s58
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s57
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[25:26], v[12:15]
-; GFX7-HSA-NEXT: s_sext_i32_i8 s15, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s8
-; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x80
-; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
; GFX7-HSA-NEXT: s_sext_i32_i8 s11, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s68
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s67
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s66
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s6
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[12:15]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s6
; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x70
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s11
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s56
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s55
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[19:20], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s54
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s56
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s55
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s54
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s7
; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[27:28], v[16:19]
; GFX7-HSA-NEXT: s_sext_i32_i8 s14, s14
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s7
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s6
-; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x60
-; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s7
; GFX7-HSA-NEXT: s_sext_i32_i8 s10, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s65
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s64
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s63
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s7
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s50
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[21:22], v[4:7]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s53
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s52
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s51
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s49
-; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s46
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s47
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s45
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s10
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s53
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s52
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s51
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s49
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s6
; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x50
; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s44
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s43
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[9:10], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s46
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s43
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s40
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s41
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s39
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s38
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s37
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[20:23]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
@@ -7039,11 +7039,11 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_mov_b32 s12, s7
; GFX7-HSA-NEXT: s_lshr_b32 s14, s6, 16
; GFX7-HSA-NEXT: s_lshr_b32 s16, s6, 24
+; GFX7-HSA-NEXT: s_ashr_i32 s29, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s31, s5, 24
; GFX7-HSA-NEXT: s_lshr_b32 s18, s6, 8
; GFX7-HSA-NEXT: s_lshr_b32 s20, s5, 16
; GFX7-HSA-NEXT: s_lshr_b32 s22, s5, 8
-; GFX7-HSA-NEXT: s_ashr_i32 s29, s5, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s31, s5, 24
; GFX7-HSA-NEXT: s_mov_b32 s24, s5
; GFX7-HSA-NEXT: s_lshr_b32 s26, s4, 16
; GFX7-HSA-NEXT: s_lshr_b32 s28, s4, 24
@@ -7070,37 +7070,37 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_addc_u32 s27, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s26
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s11
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s27
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s27
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s10
; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x50
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s16
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s17
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s11
; GFX7-HSA-NEXT: s_add_u32 s10, s0, 64
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s35
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s19
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
; GFX7-HSA-NEXT: s_add_u32 s10, s0, 48
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s19
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[2:3], v[12:15]
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s20
@@ -7526,137 +7526,140 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_load_dwordx8 s[12:19], s[2:3], 0x0
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_lshr_b32 s16, s8, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s17, s9, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s18, s10, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s19, s11, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s20, s12, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s21, s13, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s22, s14, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s23, s15, 24
-; GFX7-HSA-NEXT: s_bfe_u32 s24, s15, 0x80008
-; GFX7-HSA-NEXT: s_bfe_u32 s25, s14, 0x80008
-; GFX7-HSA-NEXT: s_bfe_u32 s26, s13, 0x80008
-; GFX7-HSA-NEXT: s_bfe_u32 s27, s12, 0x80008
-; GFX7-HSA-NEXT: s_bfe_u32 s28, s11, 0x80008
-; GFX7-HSA-NEXT: s_bfe_u32 s29, s10, 0x80008
-; GFX7-HSA-NEXT: s_bfe_u32 s4, s9, 0x80008
-; GFX7-HSA-NEXT: s_bfe_u32 s2, s8, 0x80008
-; GFX7-HSA-NEXT: s_and_b32 s3, s8, 0xff
-; GFX7-HSA-NEXT: s_and_b32 s5, s9, 0xff
-; GFX7-HSA-NEXT: s_and_b32 s30, s10, 0xff
-; GFX7-HSA-NEXT: s_and_b32 s31, s11, 0xff
-; GFX7-HSA-NEXT: s_and_b32 s33, s12, 0xff
-; GFX7-HSA-NEXT: s_and_b32 s34, s13, 0xff
-; GFX7-HSA-NEXT: s_and_b32 s35, s14, 0xff
-; GFX7-HSA-NEXT: s_and_b32 s36, s15, 0xff
-; GFX7-HSA-NEXT: s_bfe_u32 s8, s8, 0x80010
-; GFX7-HSA-NEXT: s_bfe_u32 s9, s9, 0x80010
-; GFX7-HSA-NEXT: s_bfe_u32 s10, s10, 0x80010
-; GFX7-HSA-NEXT: s_bfe_u32 s11, s11, 0x80010
-; GFX7-HSA-NEXT: s_bfe_u32 s12, s12, 0x80010
-; GFX7-HSA-NEXT: s_bfe_u32 s13, s13, 0x80010
+; GFX7-HSA-NEXT: s_lshr_b32 s11, s12, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s20, s13, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s21, s14, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s22, s15, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s23, s16, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s24, s17, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s25, s18, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s26, s19, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s27, s19, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s28, s18, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s29, s17, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s10, s16, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s8, s15, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s6, s14, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s4, s13, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s2, s12, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s3, s12, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s5, s13, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s7, s14, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s9, s15, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s30, s16, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s31, s17, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s33, s18, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s34, s19, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s35, s12, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s36, s13, 0x80010
; GFX7-HSA-NEXT: s_bfe_u32 s14, s14, 0x80010
; GFX7-HSA-NEXT: s_bfe_u32 s15, s15, 0x80010
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0xf0
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0xd0
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0xb0
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s7
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s6
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0x90
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s23
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s7
+; GFX7-HSA-NEXT: s_bfe_u32 s16, s16, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s17, s17, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s18, s18, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s19, s19, 0x80010
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xf0
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xd0
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xb0
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0x90
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0x70
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0x50
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s26
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0x70
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s13
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s24
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 16
; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s23
; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s11
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s19
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0x50
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 48
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s17
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 16
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s16
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0xe0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xe0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s36
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0xc0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s35
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0xa0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s26
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0x80
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s27
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xc0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s33
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s27
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xa0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s31
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s28
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX7-HSA-NEXT: s_add_u32 s6, s0, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x80
+; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s0, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX7-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s0, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s30
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s29
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -8264,27 +8267,27 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; GFX7-HSA-NEXT: s_mov_b32 s11, 0
-; GFX7-HSA-NEXT: s_mov_b32 s41, s11
-; GFX7-HSA-NEXT: s_mov_b32 s55, s11
+; GFX7-HSA-NEXT: s_mov_b32 s37, s11
+; GFX7-HSA-NEXT: s_mov_b32 s57, s11
; GFX7-HSA-NEXT: s_mov_b32 s47, s11
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_lshr_b32 s10, s7, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s40, s7, 8
-; GFX7-HSA-NEXT: s_mov_b32 s42, s7
-; GFX7-HSA-NEXT: s_lshr_b32 s44, s6, 16
-; GFX7-HSA-NEXT: s_ashr_i32 s43, s1, 24
-; GFX7-HSA-NEXT: s_ashr_i32 s45, s3, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s48, s3, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s36, s7, 8
+; GFX7-HSA-NEXT: s_mov_b32 s38, s7
+; GFX7-HSA-NEXT: s_lshr_b32 s40, s6, 16
+; GFX7-HSA-NEXT: s_ashr_i32 s39, s1, 24
+; GFX7-HSA-NEXT: s_ashr_i32 s41, s3, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s50, s3, 24
; GFX7-HSA-NEXT: s_ashr_i32 s65, s5, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s50, s6, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s52, s6, 8
-; GFX7-HSA-NEXT: s_lshr_b32 s54, s5, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s52, s6, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s54, s6, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s56, s5, 16
; GFX7-HSA-NEXT: s_lshr_b32 s46, s5, 8
-; GFX7-HSA-NEXT: s_mov_b32 s56, s5
-; GFX7-HSA-NEXT: s_lshr_b32 s38, s4, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s36, s4, 24
+; GFX7-HSA-NEXT: s_mov_b32 s48, s5
+; GFX7-HSA-NEXT: s_lshr_b32 s44, s4, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s42, s4, 24
; GFX7-HSA-NEXT: s_lshr_b32 s34, s4, 8
-; GFX7-HSA-NEXT: s_lshr_b32 s28, s3, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s30, s3, 16
; GFX7-HSA-NEXT: s_lshr_b32 s24, s3, 8
; GFX7-HSA-NEXT: s_mov_b32 s26, s3
; GFX7-HSA-NEXT: s_lshr_b32 s22, s2, 16
@@ -8297,17 +8300,17 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_lshr_b32 s62, s0, 24
; GFX7-HSA-NEXT: s_lshr_b32 s64, s0, 8
; GFX7-HSA-NEXT: s_bfe_i64 s[14:15], s[2:3], 0x80000
-; GFX7-HSA-NEXT: s_mov_b32 s29, s11
+; GFX7-HSA-NEXT: s_mov_b32 s31, s11
; GFX7-HSA-NEXT: s_mov_b32 s25, s11
; GFX7-HSA-NEXT: s_mov_b32 s17, s11
; GFX7-HSA-NEXT: s_mov_b32 s59, s11
; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[10:11], 0x80000
; GFX7-HSA-NEXT: s_ashr_i32 s33, s1, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s49, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s51, s5, 31
; GFX7-HSA-NEXT: s_ashr_i32 s68, s7, 31
; GFX7-HSA-NEXT: s_ashr_i32 s69, s7, 24
; GFX7-HSA-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[30:31], s[4:5], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[28:29], s[4:5], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[66:67], s[6:7], 0x80000
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
@@ -8322,108 +8325,108 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[58:59], s[44:45], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[60:61], s[42:43], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[58:59], s[40:41], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[60:61], s[38:39], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
; GFX7-HSA-NEXT: s_add_u32 s62, s8, 0xf0
; GFX7-HSA-NEXT: s_addc_u32 s63, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s40
-; GFX7-HSA-NEXT: s_add_u32 s40, s8, 0xe0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s41
-; GFX7-HSA-NEXT: s_addc_u32 s41, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s40
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s41
-; GFX7-HSA-NEXT: s_add_u32 s40, s8, 0xd0
-; GFX7-HSA-NEXT: s_addc_u32 s41, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s40
-; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s41
-; GFX7-HSA-NEXT: s_add_u32 s40, s8, 0xc0
-; GFX7-HSA-NEXT: s_addc_u32 s41, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s40
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s62
-; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s41
-; GFX7-HSA-NEXT: s_add_u32 s40, s8, 0xb0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s63
-; GFX7-HSA-NEXT: s_addc_u32 s41, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s69
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s68
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s38
-; GFX7-HSA-NEXT: s_add_u32 s38, s8, 0xa0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s61
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s39
-; GFX7-HSA-NEXT: s_addc_u32 s39, s9, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s36
+; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xe0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s37
+; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s37
+; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xd0
+; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s37
+; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xc0
+; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s37
+; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xb0
+; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s37
+; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xa0
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s58
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s30
-; GFX7-HSA-NEXT: s_add_u32 s30, s8, 0x90
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s31
-; GFX7-HSA-NEXT: s_addc_u32 s31, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s30
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s31
-; GFX7-HSA-NEXT: s_add_u32 s30, s8, 0x80
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s59
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s50
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s51
-; GFX7-HSA-NEXT: s_addc_u32 s31, s9, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s52
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s53
+; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s66
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s28
-; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x70
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s67
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s52
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s53
-; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s40
+; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x90
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s29
; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s54
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s55
-; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s67
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s54
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s55
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s29
+; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x80
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s62
+; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s63
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s69
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s68
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s29
+; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s61
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s56
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s57
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s65
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s49
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s38
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[28:29], v[12:15]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s56
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s24
-; GFX7-HSA-NEXT: s_add_u32 s24, s8, 0x60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s57
-; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s46
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s47
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s39
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s36
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s37
-; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s30
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[30:31], v[16:19]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s25
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s28
-; GFX7-HSA-NEXT: s_addc_u32 s25, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s51
+; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s36
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s48
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s31
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s35
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[20:23]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s26
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s45
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s27
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s29
+; GFX7-HSA-NEXT: s_add_u32 s24, s8, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s49
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s46
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s37
; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s25
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[4:7]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
+; GFX7-HSA-NEXT: s_addc_u32 s25, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s43
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s28
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
; GFX7-HSA-NEXT: s_add_u32 s20, s8, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[8:11]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[12:15]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
; GFX7-HSA-NEXT: s_addc_u32 s21, s9, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s20
@@ -8446,7 +8449,7 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s43
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s39
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s33
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
index 33defc2ecf6a9..73e0f6d4f1cf3 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
@@ -8093,182 +8093,196 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s4, s2, 48
-; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCN-HSA-NEXT: flat_load_dwordx4 v[14:17], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[16:19], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
-; GCN-HSA-NEXT: flat_load_dwordx4 v[10:13], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[2:5], v[0:1]
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s7, v5
-; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v6
-; GCN-HSA-NEXT: v_readfirstlane_b32 s9, v7
-; GCN-HSA-NEXT: v_readfirstlane_b32 s6, v4
+; GCN-HSA-NEXT: v_readfirstlane_b32 s7, v13
+; GCN-HSA-NEXT: v_readfirstlane_b32 s9, v15
+; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v14
; GCN-HSA-NEXT: s_mov_b32 s10, s9
; GCN-HSA-NEXT: s_mov_b32 s12, s7
-; GCN-HSA-NEXT: s_lshr_b32 s14, s8, 16
; GCN-HSA-NEXT: s_waitcnt vmcnt(2)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s23, v17
-; GCN-HSA-NEXT: s_lshr_b32 s16, s6, 16
-; GCN-HSA-NEXT: v_readfirstlane_b32 s18, v14
-; GCN-HSA-NEXT: v_readfirstlane_b32 s19, v15
-; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[14:15], 0x100000
+; GCN-HSA-NEXT: v_readfirstlane_b32 s19, v19
+; GCN-HSA-NEXT: v_readfirstlane_b32 s6, v12
+; GCN-HSA-NEXT: s_lshr_b32 s16, s8, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[8:9], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s49, s9, 31
+; GCN-HSA-NEXT: s_ashr_i32 s50, s9, 16
+; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v16
+; GCN-HSA-NEXT: v_readfirstlane_b32 s9, v17
+; GCN-HSA-NEXT: v_readfirstlane_b32 s18, v18
; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[10:11], 0x100000
-; GCN-HSA-NEXT: s_mov_b32 s24, s23
+; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
+; GCN-HSA-NEXT: s_mov_b32 s20, s19
+; GCN-HSA-NEXT: s_lshr_b32 s14, s6, 16
; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[8:9], 0x100000
; GCN-HSA-NEXT: s_ashr_i32 s33, s7, 31
-; GCN-HSA-NEXT: s_ashr_i32 s49, s7, 16
-; GCN-HSA-NEXT: s_ashr_i32 s50, s9, 31
-; GCN-HSA-NEXT: s_ashr_i32 s51, s9, 16
-; GCN-HSA-NEXT: v_readfirstlane_b32 s22, v16
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[16:17], 0x100000
-; GCN-HSA-NEXT: s_mov_b32 s26, s19
-; GCN-HSA-NEXT: s_lshr_b32 s16, s18, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[18:19], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s52, s19, 31
-; GCN-HSA-NEXT: s_ashr_i32 s53, s19, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s13
+; GCN-HSA-NEXT: s_ashr_i32 s48, s7, 16
+; GCN-HSA-NEXT: s_mov_b32 s22, s9
+; GCN-HSA-NEXT: s_lshr_b32 s24, s18, 16
+; GCN-HSA-NEXT: s_lshr_b32 s28, s8, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s51, s9, 31
+; GCN-HSA-NEXT: s_ashr_i32 s52, s9, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s13
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s12, v10
-; GCN-HSA-NEXT: v_readfirstlane_b32 s13, v11
-; GCN-HSA-NEXT: v_readfirstlane_b32 s14, v12
-; GCN-HSA-NEXT: v_readfirstlane_b32 s15, v13
-; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[24:25], 0x100000
-; GCN-HSA-NEXT: s_lshr_b32 s28, s22, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[22:23], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[26:27], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s19
-; GCN-HSA-NEXT: s_lshr_b32 s22, s12, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s58, s15, 31
-; GCN-HSA-NEXT: s_ashr_i32 s59, s15, 16
-; GCN-HSA-NEXT: s_mov_b32 s12, s15
-; GCN-HSA-NEXT: s_lshr_b32 s26, s14, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[14:15], 0x100000
+; GCN-HSA-NEXT: v_readfirstlane_b32 s9, v9
+; GCN-HSA-NEXT: v_readfirstlane_b32 s10, v10
+; GCN-HSA-NEXT: v_readfirstlane_b32 s11, v11
+; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[20:21], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[16:17], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[18:19], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s53, s19, 31
+; GCN-HSA-NEXT: s_ashr_i32 s54, s19, 16
+; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v8
+; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[28:29], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[24:25], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[40:41], s[22:23], 0x100000
+; GCN-HSA-NEXT: s_mov_b32 s22, s11
+; GCN-HSA-NEXT: s_mov_b32 s24, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s12
+; GCN-HSA-NEXT: s_ashr_i32 s57, s11, 31
+; GCN-HSA-NEXT: s_ashr_i32 s58, s11, 16
+; GCN-HSA-NEXT: s_lshr_b32 s12, s10, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[10:11], 0x100000
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s14, v0
-; GCN-HSA-NEXT: v_readfirstlane_b32 s15, v1
-; GCN-HSA-NEXT: v_readfirstlane_b32 s36, v2
-; GCN-HSA-NEXT: v_readfirstlane_b32 s37, v3
-; GCN-HSA-NEXT: s_mov_b32 s24, s13
-; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[26:27], 0x100000
-; GCN-HSA-NEXT: s_mov_b32 s44, s15
-; GCN-HSA-NEXT: s_lshr_b32 s26, s14, 16
+; GCN-HSA-NEXT: v_readfirstlane_b32 s10, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s11, v3
+; GCN-HSA-NEXT: v_readfirstlane_b32 s36, v4
+; GCN-HSA-NEXT: v_readfirstlane_b32 s37, v5
+; GCN-HSA-NEXT: s_lshr_b32 s20, s8, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[12:13], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[24:25], 0x100000
+; GCN-HSA-NEXT: s_mov_b32 s44, s11
+; GCN-HSA-NEXT: s_lshr_b32 s12, s10, 16
; GCN-HSA-NEXT: s_mov_b32 s46, s37
-; GCN-HSA-NEXT: s_lshr_b32 s48, s36, 16
-; GCN-HSA-NEXT: s_ashr_i32 s54, s23, 31
-; GCN-HSA-NEXT: s_ashr_i32 s55, s23, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s56, s13, 31
-; GCN-HSA-NEXT: s_ashr_i32 s57, s13, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[40:41], s[24:25], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[42:43], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s60, s15, 31
-; GCN-HSA-NEXT: s_ashr_i32 s61, s15, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[14:15], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s62, s37, 31
-; GCN-HSA-NEXT: s_ashr_i32 s63, s37, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[36:37], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[26:27], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[48:49], 0x100000
+; GCN-HSA-NEXT: s_lshr_b32 s24, s36, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s55, s9, 31
+; GCN-HSA-NEXT: s_ashr_i32 s56, s9, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s13
+; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[42:43], s[22:23], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s59, s11, 31
+; GCN-HSA-NEXT: s_ashr_i32 s60, s11, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s61, s37, 31
+; GCN-HSA-NEXT: s_ashr_i32 s62, s37, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[36:37], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[36:37], s[44:45], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[44:45], s[46:47], 0x100000
; GCN-HSA-NEXT: s_add_u32 s46, s0, 48
; GCN-HSA-NEXT: s_addc_u32 s47, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s47
; GCN-HSA-NEXT: s_add_u32 s46, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s47, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s47
; GCN-HSA-NEXT: s_add_u32 s46, s0, 0xf0
; GCN-HSA-NEXT: s_addc_u32 s47, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
-; GCN-HSA-NEXT: s_add_u32 s38, s0, 0xd0
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s39
-; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v29, s39
-; GCN-HSA-NEXT: s_add_u32 s38, s0, 0xb0
-; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v30, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v31, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s40
+; GCN-HSA-NEXT: s_add_u32 s40, s0, 0xd0
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s41
+; GCN-HSA-NEXT: s_addc_u32 s41, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v29, s40
+; GCN-HSA-NEXT: v_mov_b32_e32 v30, s41
+; GCN-HSA-NEXT: s_add_u32 s40, s0, 0xb0
+; GCN-HSA-NEXT: s_addc_u32 s41, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s49
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s38
; GCN-HSA-NEXT: s_add_u32 s38, s0, 0x90
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s39
; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v32, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s49
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s33
-; GCN-HSA-NEXT: v_mov_b32_e32 v33, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s39
; GCN-HSA-NEXT: s_add_u32 s38, s0, 0x70
-; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[8:11]
-; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s39
-; GCN-HSA-NEXT: s_add_u32 s38, s0, 0x50
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s51
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s50
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v28, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v31, s40
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s48
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s33
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s54
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s53
; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s43
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s59
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s58
-; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s44
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s45
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v32, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s51
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s58
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s57
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s56
+; GCN-HSA-NEXT: flat_store_dwordx4 v[25:26], v[6:9]
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s55
+; GCN-HSA-NEXT: flat_store_dwordx4 v[27:28], v[10:13]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[29:30], v[14:17]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[31:32], v[18:21]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[22:25]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s45
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s62
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s61
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s39
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s36
+; GCN-HSA-NEXT: s_add_u32 s36, s0, 0x50
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s37
+; GCN-HSA-NEXT: s_addc_u32 s37, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s60
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s59
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s37
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: s_add_u32 s4, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s40
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s41
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s57
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s56
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s63
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s62
-; GCN-HSA-NEXT: flat_store_dwordx4 v[30:31], v[16:19]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[32:33], v[20:23]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s27
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xe0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xc0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s28
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s29
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s31
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
@@ -8276,15 +8290,15 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xa0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s19
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s30
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
@@ -8292,39 +8306,27 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s24
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s27
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v34, s38
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s47
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s55
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s54
-; GCN-HSA-NEXT: v_mov_b32_e32 v35, s39
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s37
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s61
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s60
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[12:15]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[34:35], v[8:11]
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
index 7978ac89c163b..2c79134f785bc 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
@@ -8104,7 +8104,7 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_mov_b32 s9, s5
; GCN-HSA-NEXT: s_mov_b32 s3, s5
; GCN-HSA-NEXT: s_mov_b32 s7, s5
-; GCN-HSA-NEXT: s_mov_b32 s35, s5
+; GCN-HSA-NEXT: s_mov_b32 s31, s5
; GCN-HSA-NEXT: s_mov_b32 s27, s5
; GCN-HSA-NEXT: s_mov_b32 s15, s5
; GCN-HSA-NEXT: s_mov_b32 s11, s5
@@ -8125,7 +8125,7 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[12:13], 0x80000
; GCN-HSA-NEXT: s_lshr_b32 s12, s16, 16
; GCN-HSA-NEXT: s_lshr_b32 s26, s16, 24
-; GCN-HSA-NEXT: s_lshr_b32 s34, s16, 8
+; GCN-HSA-NEXT: s_lshr_b32 s30, s16, 8
; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
@@ -8138,17 +8138,17 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_bfe_i64 s[46:47], s[16:17], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[14:15], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[24:25], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[22:23], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[22:23], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[36:37], s[18:19], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[42:43], s[10:11], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[40:41], s[6:7], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[50:51], s[2:3], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[52:53], s[34:35], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[52:53], s[30:31], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[54:55], s[26:27], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[56:57], s[12:13], 0x80000
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s8
-; GCN-HSA-NEXT: s_lshr_b32 s34, s49, 16
+; GCN-HSA-NEXT: s_lshr_b32 s30, s49, 16
; GCN-HSA-NEXT: s_lshr_b32 s26, s49, 8
; GCN-HSA-NEXT: s_lshr_b32 s14, s39, 16
; GCN-HSA-NEXT: s_lshr_b32 s10, s39, 8
@@ -8183,7 +8183,7 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
; GCN-HSA-NEXT: s_add_u32 s48, s0, 0x70
; GCN-HSA-NEXT: s_addc_u32 s49, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s48
@@ -8212,8 +8212,8 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_addc_u32 s37, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s50
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s51
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v31, s43
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s58
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s45
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s20
@@ -8230,8 +8230,8 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s41
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s37
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s21
; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xe0
; GCN-HSA-NEXT: v_mov_b32_e32 v26, s48
@@ -8256,8 +8256,8 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xd0
; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11]
; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[12:15]
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s34
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s30
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s31
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s62
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s61
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s38
diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
index 979307509d3ae..b421f07b05877 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
@@ -2480,18 +2480,19 @@ body: |
; GFX908-NEXT: [[S_MOV_B32_62:%[0-9]+]]:sgpr_32 = S_MOV_B32 69
; GFX908-NEXT: [[S_MOV_B32_63:%[0-9]+]]:sgpr_32 = S_MOV_B32 70
; GFX908-NEXT: [[S_MOV_B32_64:%[0-9]+]]:sgpr_32 = S_MOV_B32 71
+ ; GFX908-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: [[S_MOV_B32_65:%[0-9]+]]:sgpr_32 = S_MOV_B32 72
+ ; GFX908-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: [[S_MOV_B32_66:%[0-9]+]]:sgpr_32 = S_MOV_B32 73
+ ; GFX908-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: [[S_MOV_B32_67:%[0-9]+]]:sgpr_32 = S_MOV_B32 74
+ ; GFX908-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode
; GFX908-NEXT: [[S_MOV_B32_68:%[0-9]+]]:sgpr_32 = S_MOV_B32 75
; GFX908-NEXT: [[S_MOV_B32_69:%[0-9]+]]:sgpr_32 = S_MOV_B32 76
; GFX908-NEXT: [[S_MOV_B32_70:%[0-9]+]]:sgpr_32 = S_MOV_B32 77
; GFX908-NEXT: [[S_MOV_B32_71:%[0-9]+]]:sgpr_32 = S_MOV_B32 78
; GFX908-NEXT: [[S_MOV_B32_72:%[0-9]+]]:sgpr_32 = S_MOV_B32 79
- ; GFX908-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: [[S_MOV_B32_73:%[0-9]+]]:sgpr_32 = S_MOV_B32 80
- ; GFX908-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
- ; GFX908-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
@@ -2511,7 +2512,6 @@ body: |
; GFX908-NEXT: bb.3:
; GFX908-NEXT: successors: %bb.5(0x04000000), %bb.4(0x7c000000)
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_23]]
; GFX908-NEXT: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
; GFX908-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64 = S_ADD_I32 [[S_MOV_B32_]].sub0, -1, implicit-def dead $scc
@@ -2682,18 +2682,19 @@ body: |
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_64:%[0-9]+]]:sgpr_32 = S_MOV_B32 71
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_65:%[0-9]+]]:sgpr_32 = S_MOV_B32 72
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_66:%[0-9]+]]:sgpr_32 = S_MOV_B32 73
- ; GFX908-GCNTRACKERS-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_U32_e64 [[S_LOAD_DWORDX2_IMM]].sub0, [[COPY1]](s32), implicit $exec
; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_67:%[0-9]+]]:sgpr_32 = S_MOV_B32 74
+ ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_68:%[0-9]+]]:sgpr_32 = S_MOV_B32 75
+ ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_69:%[0-9]+]]:sgpr_32 = S_MOV_B32 76
+ ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_70:%[0-9]+]]:sgpr_32 = S_MOV_B32 77
+ ; GFX908-GCNTRACKERS-NEXT: [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_U32_e64 [[S_LOAD_DWORDX2_IMM]].sub0, [[COPY1]](s32), implicit $exec
+ ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_71:%[0-9]+]]:sgpr_32 = S_MOV_B32 78
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_72:%[0-9]+]]:sgpr_32 = S_MOV_B32 79
; GFX908-GCNTRACKERS-NEXT: [[S_MOV_B32_73:%[0-9]+]]:sgpr_32 = S_MOV_B32 80
- ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
- ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
- ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-GCNTRACKERS-NEXT: {{ $}}
; GFX908-GCNTRACKERS-NEXT: bb.1:
; GFX908-GCNTRACKERS-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
@@ -2713,7 +2714,6 @@ body: |
; GFX908-GCNTRACKERS-NEXT: bb.3:
; GFX908-GCNTRACKERS-NEXT: successors: %bb.5(0x04000000), %bb.4(0x7c000000)
; GFX908-GCNTRACKERS-NEXT: {{ $}}
- ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode
; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_23]]
; GFX908-GCNTRACKERS-NEXT: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
; GFX908-GCNTRACKERS-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64 = S_ADD_I32 [[S_MOV_B32_]].sub0, -1, implicit-def dead $scc
diff --git a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
index fcfeb099c698f..2ede4248508ed 100644
--- a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
+++ b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
@@ -1,5 +1,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-xnack < %s | FileCheck --check-prefixes=GCN,GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -mattr=-xnack < %s | FileCheck --check-prefixes=GCN,GFX950 %s
+; The amdhsa OS implicitly enables the trap handler, which reserves 16 SGPRs per
+; wave. The reported occupancy of SGPR-limited kernels must account for that, so
+; the same kernels reach a lower occupancy than on the non-amdhsa runs above.
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-xnack < %s | FileCheck --check-prefixes=GCN,GFX9TRAP %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -mattr=-xnack < %s | FileCheck --check-prefixes=GCN,GFX950TRAP %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-xnack < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10W32,GFX1010,GFX1010W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-xnack -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10W64,GFX1010,GFX1010W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10W32,GFX1030,GFX1030W32 %s
@@ -353,6 +358,8 @@ define amdgpu_kernel void @used_256_vgprs() #10 {
; GCN-LABEL: {{^}}used_80_sgprs:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
+; GFX9TRAP: ; Occupancy: 8
+; GFX950TRAP: ; Occupancy: 7
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
@@ -363,8 +370,10 @@ define amdgpu_kernel void @used_80_sgprs() #10 {
}
; GCN-LABEL: {{^}}used_88_sgprs:
-; GFX9: ; Occupancy: 9
+; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
+; GFX9TRAP: ; Occupancy: 7
+; GFX950TRAP: ; Occupancy: 7
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
@@ -375,8 +384,10 @@ define amdgpu_kernel void @used_88_sgprs() #10 {
}
; GCN-LABEL: {{^}}used_100_sgprs:
-; GFX9: ; Occupancy: 8
+; GFX9: ; Occupancy: 7
; GFX950: ; Occupancy: 7
+; GFX9TRAP: ; Occupancy: 6
+; GFX950TRAP: ; Occupancy: 6
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
@@ -389,6 +400,8 @@ define amdgpu_kernel void @used_100_sgprs() #10 {
; GCN-LABEL: {{^}}used_101_sgprs:
; GFX9: ; Occupancy: 7
; GFX950: ; Occupancy: 7
+; GFX9TRAP: ; Occupancy: 6
+; GFX950TRAP: ; Occupancy: 6
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
diff --git a/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll b/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
index 56ba2d1ea7027..2213ace3045d9 100644
--- a/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
+++ b/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
@@ -146,7 +146,7 @@ define void @empty_func() !dbg !8 {
; STDERR-NEXT: remark: foo.cl:64:0: AGPRs: .Ltest_indirect_call.num_agpr
; STDERR-NEXT: remark: foo.cl:64:0: ScratchSize [bytes/lane]: 0
; STDERR-NEXT: remark: foo.cl:64:0: Dynamic Stack: True
-; STDERR-NEXT: remark: foo.cl:64:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 8, 10, max(.Ltest_indirect_call.numbered_sgpr+extrasgprs(.Ltest_indirect_call.uses_vcc, .Ltest_indirect_call.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_call.num_agpr, .Ltest_indirect_call.num_vgpr), 1, 0))
+; STDERR-NEXT: remark: foo.cl:64:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 8, 10, max(.Ltest_indirect_call.numbered_sgpr+extrasgprs(.Ltest_indirect_call.uses_vcc, .Ltest_indirect_call.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_call.num_agpr, .Ltest_indirect_call.num_vgpr), 1, 0), 800, 16, 16)
; STDERR-NEXT: remark: foo.cl:64:0: SGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:64:0: VGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:64:0: LDS Size [bytes/block]: 0
@@ -164,7 +164,7 @@ define amdgpu_kernel void @test_indirect_call() !dbg !9 {
; STDERR-NEXT: remark: foo.cl:74:0: AGPRs: .Ltest_indirect_w_static_stack.num_agpr
; STDERR-NEXT: remark: foo.cl:74:0: ScratchSize [bytes/lane]: 144
; STDERR-NEXT: remark: foo.cl:74:0: Dynamic Stack: True
-; STDERR-NEXT: remark: foo.cl:74:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 8, 10, max(.Ltest_indirect_w_static_stack.numbered_sgpr+extrasgprs(.Ltest_indirect_w_static_stack.uses_vcc, .Ltest_indirect_w_static_stack.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_w_static_stack.num_agpr, .Ltest_indirect_w_static_stack.num_vgpr), 1, 0))
+; STDERR-NEXT: remark: foo.cl:74:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 8, 10, max(.Ltest_indirect_w_static_stack.numbered_sgpr+extrasgprs(.Ltest_indirect_w_static_stack.uses_vcc, .Ltest_indirect_w_static_stack.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_w_static_stack.num_agpr, .Ltest_indirect_w_static_stack.num_vgpr), 1, 0), 800, 16, 16)
; STDERR-NEXT: remark: foo.cl:74:0: SGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:74:0: VGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:74:0: LDS Size [bytes/block]: 0
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll b/llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
index 0d25bc97ff775..d1c972758692f 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
@@ -8,8 +8,8 @@
; GCN-GCNTRACKERS: NumVgprs: 2
; GCN: ScratchSize: 0
; GCN-GCNTRACKERS: ScratchSize: 0
-; GCN: Occupancy: 5
-; GCN-GCNTRACKERS: Occupancy: 5
+; GCN: Occupancy: 4
+; GCN-GCNTRACKERS: Occupancy: 4
; FIXME: GCN Trackers do not track pressure from PhysRegs, so scheduling is actually worse
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
index 8e92cfb9dfab7..d608fa63bd668 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
@@ -39,7 +39,7 @@
; CHECK-NEXT: fp64-fp16-input-denormals: true
; CHECK-NEXT: fp64-fp16-output-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
-; CHECK-NEXT: occupancy: 5
+; CHECK-NEXT: occupancy: 4
; CHECK-NEXT: scavengeFI: '%stack.0'
; CHECK-NEXT: vgprForAGPRCopy: ''
; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
@@ -312,7 +312,7 @@
; CHECK-NEXT: fp64-fp16-input-denormals: true
; CHECK-NEXT: fp64-fp16-output-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
-; CHECK-NEXT: occupancy: 5
+; CHECK-NEXT: occupancy: 4
; CHECK-NEXT: scavengeFI: '%stack.0'
; CHECK-NEXT: vgprForAGPRCopy: ''
; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
index 778c0d6d29690..d06c8413fd6cc 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
@@ -39,7 +39,7 @@
; AFTER-PEI-NEXT: fp64-fp16-input-denormals: true
; AFTER-PEI-NEXT: fp64-fp16-output-denormals: true
; AFTER-PEI-NEXT: highBitsOf32BitAddress: 0
-; AFTER-PEI-NEXT: occupancy: 5
+; AFTER-PEI-NEXT: occupancy: 4
; AFTER-PEI-NEXT: scavengeFI: '%stack.3'
; AFTER-PEI-NEXT: vgprForAGPRCopy: ''
; AFTER-PEI-NEXT: sgprForEXECCopy: ''
diff --git a/llvm/test/MC/AMDGPU/occupancy_mcexpr.s b/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
index 06bec8c538dae..fca27b6ca3094 100644
--- a/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
+++ b/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
@@ -1,12 +1,19 @@
// RUN: llvm-mc -triple amdgcn-amd-amdhsa < %s | FileCheck --check-prefix=ASM %s
+// The occupancy() MCExpr arguments are:
+// occupancy(MaxWaves, VGPRGranule, TotalVGPRs, Generation, InitOcc,
+// NumSGPRs, NumVGPRs, SGPRTotal, SGPRGranule, SGPRTrapReserve)
+// The SGPR budget (SGPRTotal/SGPRGranule/SGPRTrapReserve) is passed explicitly
+// so the SGPR-limited occupancy matches the code generator, including the
+// trap-handler reservation, independent of the assembler's subtarget.
+
// ASM: .set occupancy_init_one, 1
// ASM: .set occupancy_init_seven, 7
// ASM: .set occupancy_init_eight, 8
-.set occupancy_init_one, occupancy(0, 0, 0, 0, 1, 0, 0)
-.set occupancy_init_seven, occupancy(0, 0, 0, 0, 7, 0, 0)
-.set occupancy_init_eight, occupancy(0, 0, 0, 0, 8, 0, 0)
+.set occupancy_init_one, occupancy(0, 0, 0, 0, 1, 0, 0, 0, 0, 0)
+.set occupancy_init_seven, occupancy(0, 0, 0, 0, 7, 0, 0, 0, 0, 0)
+.set occupancy_init_eight, occupancy(0, 0, 0, 0, 8, 0, 0, 0, 0, 0)
// ASM: .set occupancy_numsgpr_seaisle_ten, 10
// ASM: .set occupancy_numsgpr_seaisle_nine, 9
@@ -15,38 +22,54 @@
// ASM: .set occupancy_numsgpr_seaisle_six, 6
// ASM: .set occupancy_numsgpr_seaisle_five, 5
-.set occupancy_numsgpr_seaisle_ten, occupancy(0, 0, 0, 6, 11, 1, 0)
-.set occupancy_numsgpr_seaisle_nine, occupancy(0, 0, 0, 6, 11, 49, 0)
-.set occupancy_numsgpr_seaisle_eight, occupancy(0, 0, 0, 6, 11, 57, 0)
-.set occupancy_numsgpr_seaisle_seven, occupancy(0, 0, 0, 6, 11, 65, 0)
-.set occupancy_numsgpr_seaisle_six, occupancy(0, 0, 0, 6, 11, 73, 0)
-.set occupancy_numsgpr_seaisle_five, occupancy(0, 0, 0, 6, 11, 81, 0)
+.set occupancy_numsgpr_seaisle_ten, occupancy(10, 0, 0, 6, 10, 1, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_nine, occupancy(10, 0, 0, 6, 10, 49, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_eight, occupancy(10, 0, 0, 6, 10, 57, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_seven, occupancy(10, 0, 0, 6, 10, 65, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_six, occupancy(10, 0, 0, 6, 10, 73, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_five, occupancy(10, 0, 0, 6, 10, 81, 0, 512, 8, 0)
// ASM: .set occupancy_numsgpr_gfx9_ten, 10
-// ASM: .set occupancy_numsgpr_gfx9_nine, 9
// ASM: .set occupancy_numsgpr_gfx9_eight, 8
+// ASM: .set occupancy_numsgpr_gfx9_eight_b, 8
// ASM: .set occupancy_numsgpr_gfx9_seven, 7
-.set occupancy_numsgpr_gfx9_ten, occupancy(0, 0, 0, 8, 11, 1, 0)
-.set occupancy_numsgpr_gfx9_nine, occupancy(0, 0, 0, 8, 11, 81, 0)
-.set occupancy_numsgpr_gfx9_eight, occupancy(0, 0, 0, 8, 11, 89, 0)
-.set occupancy_numsgpr_gfx9_seven, occupancy(0, 0, 0, 8, 11, 101, 0)
+.set occupancy_numsgpr_gfx9_ten, occupancy(10, 0, 0, 8, 10, 1, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx9_eight, occupancy(10, 0, 0, 8, 10, 81, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx9_eight_b, occupancy(10, 0, 0, 8, 10, 89, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx9_seven, occupancy(10, 0, 0, 8, 10, 101, 0, 800, 16, 0)
+
+// Same SGPR budget as gfx9 above, but with the trap handler enabled the 16
+// reserved SGPRs per wave lower the achievable occupancy.
+
+// ASM: .set occupancy_numsgpr_gfx9_trap_ten, 10
+// ASM: .set occupancy_numsgpr_gfx9_trap_eight, 8
+// ASM: .set occupancy_numsgpr_gfx9_trap_seven, 7
+// ASM: .set occupancy_numsgpr_gfx9_trap_six, 6
+
+.set occupancy_numsgpr_gfx9_trap_ten, occupancy(10, 0, 0, 8, 10, 1, 0, 800, 16, 16)
+.set occupancy_numsgpr_gfx9_trap_eight, occupancy(10, 0, 0, 8, 10, 65, 0, 800, 16, 16)
+.set occupancy_numsgpr_gfx9_trap_seven, occupancy(10, 0, 0, 8, 10, 81, 0, 800, 16, 16)
+.set occupancy_numsgpr_gfx9_trap_six, occupancy(10, 0, 0, 8, 10, 97, 0, 800, 16, 16)
+
+// On GFX10+ (Generation 9) the SGPR file is large enough that SGPRs never
+// limit occupancy, so the result is just the init occupancy.
// ASM: .set occupancy_numsgpr_gfx10_one, 1
// ASM: .set occupancy_numsgpr_gfx10_seven, 7
// ASM: .set occupancy_numsgpr_gfx10_eight, 8
-.set occupancy_numsgpr_gfx10_one, occupancy(1, 0, 0, 9, 11, 1, 0)
-.set occupancy_numsgpr_gfx10_seven, occupancy(7, 0, 0, 9, 11, 1, 0)
-.set occupancy_numsgpr_gfx10_eight, occupancy(8, 0, 0, 9, 11, 1, 0)
+.set occupancy_numsgpr_gfx10_one, occupancy(10, 0, 0, 9, 1, 200, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx10_seven, occupancy(10, 0, 0, 9, 7, 200, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx10_eight, occupancy(10, 0, 0, 9, 8, 200, 0, 800, 16, 0)
// ASM: .set occupancy_numvgpr_high_granule_one, 1
// ASM: .set occupancy_numvgpr_high_granule_seven, 7
// ASM: .set occupancy_numvgpr_high_granule_eight, 8
-.set occupancy_numvgpr_high_granule_one, occupancy(1, 2, 0, 0, 11, 0, 1)
-.set occupancy_numvgpr_high_granule_seven, occupancy(7, 2, 0, 0, 11, 0, 1)
-.set occupancy_numvgpr_high_granule_eight, occupancy(8, 2, 0, 0, 11, 0, 1)
+.set occupancy_numvgpr_high_granule_one, occupancy(1, 2, 0, 0, 11, 0, 1, 0, 0, 0)
+.set occupancy_numvgpr_high_granule_seven, occupancy(7, 2, 0, 0, 11, 0, 1, 0, 0, 0)
+.set occupancy_numvgpr_high_granule_eight, occupancy(8, 2, 0, 0, 11, 0, 1, 0, 0, 0)
// ASM: .set occupancy_numvgpr_low_total_one, 1
// ASM: .set occupancy_numvgpr_one, 1
@@ -54,8 +77,8 @@
// ASM: .set occupancy_numvgpr_eight, 8
// ASM: .set occupancy_numvgpr_ten, 10
-.set occupancy_numvgpr_low_total_one, occupancy(11, 4, 2, 0, 11, 0, 4)
-.set occupancy_numvgpr_one, occupancy(11, 4, 4, 0, 11, 0, 4)
-.set occupancy_numvgpr_seven, occupancy(11, 4, 28, 0, 11, 0, 4)
-.set occupancy_numvgpr_eight, occupancy(11, 4, 32, 0, 11, 0, 4)
-.set occupancy_numvgpr_ten, occupancy(11, 4, 40, 0, 11, 0, 4)
+.set occupancy_numvgpr_low_total_one, occupancy(11, 4, 2, 0, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_one, occupancy(11, 4, 4, 0, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_seven, occupancy(11, 4, 28, 0, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_eight, occupancy(11, 4, 32, 0, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_ten, occupancy(11, 4, 40, 0, 11, 0, 4, 0, 0, 0)
>From efd36cdbca4979074a855dfe922ff649d85b988f Mon Sep 17 00:00:00 2001
From: mselehov <mselehov at amd.com>
Date: Wed, 3 Jun 2026 09:42:37 -0500
Subject: [PATCH 2/5] [AMDGPU] Simplify occupancy MCExpr: capability predicate,
parse-time arity, closed form
Assisted-by: Claude Opus
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 30 +++++---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 6 ++
.../AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp | 64 ++++++++++------
.../Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h | 6 ++
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 37 ++++++----
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 10 ++-
.../CodeGen/AMDGPU/agpr-register-count.ll | 4 +-
.../AMDGPU/resource-optimization-remarks.ll | 4 +-
llvm/test/MC/AMDGPU/mcexpr_amd_err.s | 16 ++++
llvm/test/MC/AMDGPU/occupancy_mcexpr.s | 73 ++++++++++---------
10 files changed, 161 insertions(+), 89 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 45036661fbf2c..b2ce55587ab77 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -434,12 +434,12 @@ const AMDGPUMCExpr *createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
unsigned MaxWaves = IsaInfo::getMaxWavesPerEU(STM);
unsigned Granule = IsaInfo::getVGPRAllocGranule(STM, DynamicVGPRBlockSize);
unsigned TargetTotalNumVGPRs = IsaInfo::getTotalNumVGPRs(STM);
- unsigned Generation = STM.getGeneration();
- // SGPR budget of the code generator's subtarget, so the printed occupancy
- // matches what codegen assumed. In particular STM carries the implicit
- // amdhsa trap-handler feature, which the asm printer's MCSubtargetInfo does
- // not, so the reservation has to be threaded through explicitly here.
+ // All subtarget-dependent decisions are taken here from the per-function
+ // subtarget STM and baked into the operands; the MCExpr itself stays purely
+ // arithmetic because it is evaluated late, when NumSGPRs/NumVGPRs are still
+ // symbolic. STM carries the implicit amdhsa trap-handler feature, so the trap
+ // reservation has to be threaded through explicitly.
unsigned SGPRTotal = IsaInfo::getTotalNumSGPRs(STM);
unsigned SGPRGranule = IsaInfo::getSGPRAllocGranule(STM);
unsigned SGPRTrapReserve = STM.hasTrapHandler() ? IsaInfo::TRAP_NUM_SGPRS : 0;
@@ -448,13 +448,19 @@ const AMDGPUMCExpr *createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
return MCConstantExpr::create(Value, Ctx);
};
- return AMDGPUMCExpr::create(
- AMDGPUMCExpr::AGVK_Occupancy,
- {CreateExpr(MaxWaves), CreateExpr(Granule),
- CreateExpr(TargetTotalNumVGPRs), CreateExpr(Generation),
- CreateExpr(InitOcc), NumSGPRs, NumVGPRs, CreateExpr(SGPRTotal),
- CreateExpr(SGPRGranule), CreateExpr(SGPRTrapReserve)},
- Ctx);
+ // On targets where SGPRs do not limit occupancy, pass a zero SGPR count so
+ // the SGPR term is skipped during evaluation, instead of testing the target
+ // generation inside the MCExpr.
+ const MCExpr *SGPRArg =
+ IsaInfo::isSGPROccupancyLimited(STM) ? NumSGPRs : CreateExpr(0);
+
+ return AMDGPUMCExpr::create(AMDGPUMCExpr::AGVK_Occupancy,
+ {CreateExpr(MaxWaves), CreateExpr(Granule),
+ CreateExpr(TargetTotalNumVGPRs),
+ CreateExpr(InitOcc), SGPRArg, NumVGPRs,
+ CreateExpr(SGPRTotal), CreateExpr(SGPRGranule),
+ CreateExpr(SGPRTrapReserve)},
+ Ctx);
}
void AMDGPUAsmPrinter::validateMCResourceInfo(Function &F) {
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 2a9a31e732a6e..c64c31f712f10 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -9408,6 +9408,12 @@ bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
"mismatch of commas in " + Twine(TokenId) + " expression");
return true;
}
+ if (unsigned Expected = AMDGPUMCExpr::getNumExpectedArgs(VK);
+ Expected && Exprs.size() != Expected) {
+ Error(getToken().getLoc(), Twine(TokenId) + " expression expects " +
+ Twine(Expected) + " operands");
+ return true;
+ }
Res = AMDGPUMCExpr::create(VK, Exprs, getContext());
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
index 86501cab0d479..e6eb3d80e4df7 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
@@ -30,6 +30,9 @@ AMDGPUMCExpr::AMDGPUMCExpr(VariantKind Kind, ArrayRef<const MCExpr *> Args,
: Kind(Kind), Ctx(Ctx) {
assert(Args.size() >= 1 && "Needs a minimum of one expression.");
assert(Kind != AGVK_None && "Cannot construct AMDGPUMCExpr of kind none.");
+ assert((getNumExpectedArgs(Kind) == 0 ||
+ Args.size() == getNumExpectedArgs(Kind)) &&
+ "Wrong number of operands for AMDGPUMCExpr kind.");
// Allocating the variadic arguments through the same allocation mechanism
// that the object itself is allocated with so they end up in the same memory.
@@ -50,6 +53,29 @@ const AMDGPUMCExpr *AMDGPUMCExpr::create(VariantKind Kind,
return new (Ctx) AMDGPUMCExpr(Kind, Args, Ctx);
}
+unsigned AMDGPUMCExpr::getNumExpectedArgs(VariantKind Kind) {
+ switch (Kind) {
+ case AGVK_None:
+ case AGVK_Or:
+ case AGVK_Max:
+ case AGVK_Min:
+ // Variadic: any number of operands (the parser already requires >= 1).
+ return 0;
+ case AGVK_Lit:
+ case AGVK_Lit64:
+ case AGVK_InstPrefSize:
+ return 1;
+ case AGVK_TotalNumVGPRs:
+ case AGVK_AlignTo:
+ return 2;
+ case AGVK_ExtraSGPRs:
+ return 3;
+ case AGVK_Occupancy:
+ return 9;
+ }
+ llvm_unreachable("Unknown AMDGPUMCExpr kind.");
+}
+
const MCExpr *AMDGPUMCExpr::getSubExpr(size_t Index) const {
assert(Index < Args.size() && "Indexing out of bounds AMDGPUMCExpr sub-expr");
return Args[Index];
@@ -166,38 +192,30 @@ bool AMDGPUMCExpr::evaluateAlignTo(MCValue &Res, const MCAssembler *Asm) const {
bool AMDGPUMCExpr::evaluateOccupancy(MCValue &Res,
const MCAssembler *Asm) const {
- uint64_t InitOccupancy, MaxWaves, Granule, TargetTotalNumVGPRs, Generation,
- NumSGPRs, NumVGPRs, SGPRTotal, SGPRGranule, SGPRTrapReserve;
-
- // createOccupancy() always emits exactly these ten operands; bail out rather
- // than read out of bounds if a hand-written expression has a different arity.
- if (Args.size() != 10)
- return false;
+ uint64_t InitOccupancy, MaxWaves, Granule, TargetTotalNumVGPRs, NumSGPRs,
+ NumVGPRs, SGPRTotal, SGPRGranule, SGPRTrapReserve;
- bool Success = evaluateMCExprs(
- Args.slice(0, 5), Asm,
- {MaxWaves, Granule, TargetTotalNumVGPRs, Generation, InitOccupancy});
+ bool Success =
+ evaluateMCExprs(Args.slice(0, 4), Asm,
+ {MaxWaves, Granule, TargetTotalNumVGPRs, InitOccupancy});
- assert(Success && "Arguments 1 to 5 for Occupancy should be known constants");
+ assert(Success && "Arguments 1 to 4 for Occupancy should be known constants");
- if (!Success || !evaluateMCExprs(Args.slice(5, 2), Asm, {NumSGPRs, NumVGPRs}))
+ if (!Success || !evaluateMCExprs(Args.slice(4, 2), Asm, {NumSGPRs, NumVGPRs}))
return false;
- // Arguments 8 to 10 carry the SGPR budget of the code-generator's subtarget
- // (total SGPRs, allocation granule, and the trap-handler reservation). They
- // let the SGPR-limited occupancy be computed exactly as the code generator
- // does (in particular trap-handler aware), instead of from the asm printer's
- // MCSubtargetInfo which does not carry the implicit amdhsa features.
- if (!evaluateMCExprs(Args.slice(7, 3), Asm,
+ // The trailing operands carry the SGPR budget of the code generator's
+ // subtarget (total SGPRs, allocation granule, and the trap-handler
+ // reservation), so the SGPR-limited occupancy is computed exactly as the code
+ // generator does (trap-handler aware). createOccupancy() passes a zero SGPR
+ // count on targets where SGPRs do not limit occupancy, so the SGPR term below
+ // is skipped without this expression having to know the target generation.
+ if (!evaluateMCExprs(Args.slice(6, 3), Asm,
{SGPRTotal, SGPRGranule, SGPRTrapReserve}))
return false;
unsigned Occupancy = InitOccupancy;
- // Mirror the GFX10+ rule of the getOccupancyWithNumSGPRs(MCSubtargetInfo)
- // overload: on GFX10+ the SGPR file is large enough that SGPRs never limit
- // occupancy. The MC layer only has the decoded Generation here, so it tests
- // that rather than an MCSubtargetInfo.
- if (NumSGPRs && Generation < AMDGPUSubtarget::GFX10)
+ if (NumSGPRs)
Occupancy = std::min(Occupancy, IsaInfo::getOccupancyWithNumSGPRs(
NumSGPRs, MaxWaves, SGPRTotal,
SGPRGranule, SGPRTrapReserve));
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
index 369545fa79cea..068310cebd180 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
@@ -79,6 +79,12 @@ class AMDGPUMCExpr : public MCTargetExpr {
static const AMDGPUMCExpr *
create(VariantKind Kind, ArrayRef<const MCExpr *> Args, MCContext &Ctx);
+ /// \returns the exact number of operands a well-formed expression of \p Kind
+ /// must have, or 0 for the variadic kinds (or/max/min) that accept any number
+ /// of operands. Used to validate hand-written expressions at parse time and
+ /// to assert printer-built ones in create().
+ static unsigned getNumExpectedArgs(VariantKind Kind);
+
static const AMDGPUMCExpr *createOr(ArrayRef<const MCExpr *> Args,
MCContext &Ctx) {
return create(VariantKind::AGVK_Or, Args, Ctx);
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 23254f0ffc5e1..139cc80ef70c9 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1389,6 +1389,18 @@ unsigned getMaxNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
return std::min(MaxNumSGPRs, AddressableNumSGPRs);
}
+bool isSGPROccupancyLimited(const MCSubtargetInfo &STI) {
+ // Whether the SGPR file is a limiting resource for occupancy. This is a
+ // target capability rather than a generation per se, but it currently has a
+ // single determinant: from GFX10 on, the SGPR file is large enough that the
+ // SGPR count never reduces occupancy. The test lives here, next to the SGPR
+ // model that already keys on the ISA version
+ // (getMaxNumSGPRs/getAddressableNumSGPRs), so there is one place to update --
+ // or to back by a subtarget feature -- if a future target reintroduces an
+ // SGPR-limited regime.
+ return getIsaVersion(STI.getCPU()).Major < 10;
+}
+
unsigned getNumExtraSGPRs(const MCSubtargetInfo &STI, bool VCCUsed,
bool FlatScrUsed, bool XNACKUsed) {
unsigned ExtraSGPRs = 0;
@@ -1522,24 +1534,23 @@ unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
unsigned TotalNumSGPRs, unsigned Granule,
unsigned TrapReserve) {
- // Invert getMaxNumSGPRs(): find the largest number of waves W whose per-wave
- // SGPR budget still accommodates \p SGPRs. Higher occupancy means a smaller
- // budget, so search from the maximum downwards and return the first fit. The
- // budget is computed by the same helper getMaxNumSGPRs() uses, so the two
- // stay exact inverses (modulo the addressable clamp, which is intentionally
- // not applied here - see the header).
- for (unsigned Waves = MaxWaves; Waves > 1; --Waves)
- if (SGPRs <=
- getSGPRBudgetPerWave(TotalNumSGPRs, Waves, TrapReserve, Granule))
- return Waves;
- return 1;
+ // Closed-form inverse of getMaxNumSGPRs(): the largest number of waves W
+ // whose per-wave SGPR budget still accommodates \p SGPRs. The budget
+ // condition
+ // SGPRs <= alignDown(TotalNumSGPRs / W - TrapReserve, Granule)
+ // is equivalent to TotalNumSGPRs / W - TrapReserve >= alignTo(SGPRs,
+ // Granule), i.e. W <= TotalNumSGPRs / (alignTo(SGPRs, Granule) +
+ // TrapReserve), so no search is needed. This uses the same per-wave budget as
+ // getMaxNumSGPRs(), so the two stay exact inverses (modulo the addressable
+ // clamp, which is intentionally not applied here - see the header).
+ unsigned PerWave = alignTo(SGPRs, Granule) + TrapReserve;
+ return PerWave ? std::clamp(TotalNumSGPRs / PerWave, 1u, MaxWaves) : MaxWaves;
}
unsigned getOccupancyWithNumSGPRs(const MCSubtargetInfo &STI, unsigned SGPRs) {
unsigned MaxWaves = getMaxWavesPerEU(STI);
- // On GFX10+ the SGPR file is large enough that SGPRs never limit occupancy.
- if (getIsaVersion(STI.getCPU()).Major >= 10)
+ if (!isSGPROccupancyLimited(STI))
return MaxWaves;
return getOccupancyWithNumSGPRs(SGPRs, MaxWaves, getTotalNumSGPRs(STI),
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index f73e1c995e49f..35e692da75052 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -375,6 +375,12 @@ unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
unsigned MaxWaves,
unsigned TotalNumVGPRs);
+/// \returns Whether the number of allocated SGPRs can reduce occupancy on
+/// subtarget \p STI, i.e. whether the SGPR file is a limiting resource. This is
+/// a single, named capability so that callers (the occupancy query and the asm
+/// printer's occupancy MCExpr) do not each test the ISA version themselves.
+bool isSGPROccupancyLimited(const MCSubtargetInfo &STI);
+
/// \returns Occupancy (waves per EU) limited by \p SGPRs usage for subtarget
/// \p STI. This is the inverse of getMaxNumSGPRs(): it returns the largest
/// number of waves W for which \p SGPRs still fits the per-wave SGPR budget
@@ -390,8 +396,8 @@ unsigned getOccupancyWithNumSGPRs(const MCSubtargetInfo &STI, unsigned SGPRs);
/// trap-handler \p TrapReserve (0 when the trap handler is disabled). This is
/// the subtarget-free core shared by the MCSubtargetInfo overload and the
/// occupancy MCExpr, so that the asm printer reports the same trap-aware
-/// occupancy the code generator assumes. Callers must apply the GFX10+ "SGPRs
-/// never limit occupancy" rule themselves before calling this.
+/// occupancy the code generator assumes. Callers must check
+/// isSGPROccupancyLimited() first; this assumes SGPRs are a limiting resource.
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
unsigned TotalNumSGPRs, unsigned Granule,
unsigned TrapReserve);
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
index ea8c9406b2e11..1bdb8a7bffb18 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
@@ -165,8 +165,8 @@ declare void @undef_func()
; GFX90A: VGPRBlocks: (alignto(max(max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 1), 8)/8)-1
; GCN: NumVGPRsForWavesPerEU: max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0)
; GFX90A: AccumOffset: ((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1+1)*4
-; GFX908: Occupancy: occupancy(10, 4, 256, 8, 10, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 800, 16, 16)
-; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 8, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 800, 16, 16)
+; GFX908: Occupancy: occupancy(10, 4, 256, 10, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 800, 16, 16)
+; GFX90A: Occupancy: occupancy(8, 8, 512, 8, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 800, 16, 16)
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: (((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1)&~65536)&63
define amdgpu_kernel void @kernel_call_undef_func() #0 {
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll b/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
index 2213ace3045d9..203c4fb9c6267 100644
--- a/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
+++ b/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
@@ -146,7 +146,7 @@ define void @empty_func() !dbg !8 {
; STDERR-NEXT: remark: foo.cl:64:0: AGPRs: .Ltest_indirect_call.num_agpr
; STDERR-NEXT: remark: foo.cl:64:0: ScratchSize [bytes/lane]: 0
; STDERR-NEXT: remark: foo.cl:64:0: Dynamic Stack: True
-; STDERR-NEXT: remark: foo.cl:64:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 8, 10, max(.Ltest_indirect_call.numbered_sgpr+extrasgprs(.Ltest_indirect_call.uses_vcc, .Ltest_indirect_call.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_call.num_agpr, .Ltest_indirect_call.num_vgpr), 1, 0), 800, 16, 16)
+; STDERR-NEXT: remark: foo.cl:64:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 10, max(.Ltest_indirect_call.numbered_sgpr+extrasgprs(.Ltest_indirect_call.uses_vcc, .Ltest_indirect_call.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_call.num_agpr, .Ltest_indirect_call.num_vgpr), 1, 0), 800, 16, 16)
; STDERR-NEXT: remark: foo.cl:64:0: SGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:64:0: VGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:64:0: LDS Size [bytes/block]: 0
@@ -164,7 +164,7 @@ define amdgpu_kernel void @test_indirect_call() !dbg !9 {
; STDERR-NEXT: remark: foo.cl:74:0: AGPRs: .Ltest_indirect_w_static_stack.num_agpr
; STDERR-NEXT: remark: foo.cl:74:0: ScratchSize [bytes/lane]: 144
; STDERR-NEXT: remark: foo.cl:74:0: Dynamic Stack: True
-; STDERR-NEXT: remark: foo.cl:74:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 8, 10, max(.Ltest_indirect_w_static_stack.numbered_sgpr+extrasgprs(.Ltest_indirect_w_static_stack.uses_vcc, .Ltest_indirect_w_static_stack.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_w_static_stack.num_agpr, .Ltest_indirect_w_static_stack.num_vgpr), 1, 0), 800, 16, 16)
+; STDERR-NEXT: remark: foo.cl:74:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 10, max(.Ltest_indirect_w_static_stack.numbered_sgpr+extrasgprs(.Ltest_indirect_w_static_stack.uses_vcc, .Ltest_indirect_w_static_stack.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_w_static_stack.num_agpr, .Ltest_indirect_w_static_stack.num_vgpr), 1, 0), 800, 16, 16)
; STDERR-NEXT: remark: foo.cl:74:0: SGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:74:0: VGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:74:0: LDS Size [bytes/block]: 0
diff --git a/llvm/test/MC/AMDGPU/mcexpr_amd_err.s b/llvm/test/MC/AMDGPU/mcexpr_amd_err.s
index e97479688c5fe..80b739459050e 100644
--- a/llvm/test/MC/AMDGPU/mcexpr_amd_err.s
+++ b/llvm/test/MC/AMDGPU/mcexpr_amd_err.s
@@ -60,5 +60,21 @@
.set min_no_lparen, min four, five)
// ASM: :[[@LINE-1]]:{{[0-9]+}}: error: expected newline
+.set occupancy_wrong_arity, occupancy(one, two, three)
+// ASM: :[[@LINE-1]]:{{[0-9]+}}: error: occupancy expression expects 9 operands
+// ASM: :[[@LINE-2]]:{{[0-9]+}}: error: missing expression
+
+.set alignto_wrong_arity, alignto(one)
+// ASM: :[[@LINE-1]]:{{[0-9]+}}: error: alignto expression expects 2 operands
+// ASM: :[[@LINE-2]]:{{[0-9]+}}: error: missing expression
+
+.set totalnumvgprs_wrong_arity, totalnumvgprs(one)
+// ASM: :[[@LINE-1]]:{{[0-9]+}}: error: totalnumvgprs expression expects 2 operands
+// ASM: :[[@LINE-2]]:{{[0-9]+}}: error: missing expression
+
+.set extrasgprs_wrong_arity, extrasgprs(one, two, three, one)
+// ASM: :[[@LINE-1]]:{{[0-9]+}}: error: extrasgprs expression expects 3 operands
+// ASM: :[[@LINE-2]]:{{[0-9]+}}: error: missing expression
+
.set four, 4
.set five, 5
diff --git a/llvm/test/MC/AMDGPU/occupancy_mcexpr.s b/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
index fca27b6ca3094..d8f2406c9af70 100644
--- a/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
+++ b/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
@@ -1,19 +1,21 @@
// RUN: llvm-mc -triple amdgcn-amd-amdhsa < %s | FileCheck --check-prefix=ASM %s
// The occupancy() MCExpr arguments are:
-// occupancy(MaxWaves, VGPRGranule, TotalVGPRs, Generation, InitOcc,
+// occupancy(MaxWaves, VGPRGranule, TotalVGPRs, InitOcc,
// NumSGPRs, NumVGPRs, SGPRTotal, SGPRGranule, SGPRTrapReserve)
// The SGPR budget (SGPRTotal/SGPRGranule/SGPRTrapReserve) is passed explicitly
// so the SGPR-limited occupancy matches the code generator, including the
-// trap-handler reservation, independent of the assembler's subtarget.
+// trap-handler reservation, independent of the assembler's subtarget. On
+// targets where SGPRs do not limit occupancy the asm printer passes a zero
+// NumSGPRs (see createOccupancy), so the expression never tests the generation.
// ASM: .set occupancy_init_one, 1
// ASM: .set occupancy_init_seven, 7
// ASM: .set occupancy_init_eight, 8
-.set occupancy_init_one, occupancy(0, 0, 0, 0, 1, 0, 0, 0, 0, 0)
-.set occupancy_init_seven, occupancy(0, 0, 0, 0, 7, 0, 0, 0, 0, 0)
-.set occupancy_init_eight, occupancy(0, 0, 0, 0, 8, 0, 0, 0, 0, 0)
+.set occupancy_init_one, occupancy(0, 0, 0, 1, 0, 0, 0, 0, 0)
+.set occupancy_init_seven, occupancy(0, 0, 0, 7, 0, 0, 0, 0, 0)
+.set occupancy_init_eight, occupancy(0, 0, 0, 8, 0, 0, 0, 0, 0)
// ASM: .set occupancy_numsgpr_seaisle_ten, 10
// ASM: .set occupancy_numsgpr_seaisle_nine, 9
@@ -22,22 +24,22 @@
// ASM: .set occupancy_numsgpr_seaisle_six, 6
// ASM: .set occupancy_numsgpr_seaisle_five, 5
-.set occupancy_numsgpr_seaisle_ten, occupancy(10, 0, 0, 6, 10, 1, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_nine, occupancy(10, 0, 0, 6, 10, 49, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_eight, occupancy(10, 0, 0, 6, 10, 57, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_seven, occupancy(10, 0, 0, 6, 10, 65, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_six, occupancy(10, 0, 0, 6, 10, 73, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_five, occupancy(10, 0, 0, 6, 10, 81, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_ten, occupancy(10, 0, 0, 10, 1, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_nine, occupancy(10, 0, 0, 10, 49, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_eight, occupancy(10, 0, 0, 10, 57, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_seven, occupancy(10, 0, 0, 10, 65, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_six, occupancy(10, 0, 0, 10, 73, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_five, occupancy(10, 0, 0, 10, 81, 0, 512, 8, 0)
// ASM: .set occupancy_numsgpr_gfx9_ten, 10
// ASM: .set occupancy_numsgpr_gfx9_eight, 8
// ASM: .set occupancy_numsgpr_gfx9_eight_b, 8
// ASM: .set occupancy_numsgpr_gfx9_seven, 7
-.set occupancy_numsgpr_gfx9_ten, occupancy(10, 0, 0, 8, 10, 1, 0, 800, 16, 0)
-.set occupancy_numsgpr_gfx9_eight, occupancy(10, 0, 0, 8, 10, 81, 0, 800, 16, 0)
-.set occupancy_numsgpr_gfx9_eight_b, occupancy(10, 0, 0, 8, 10, 89, 0, 800, 16, 0)
-.set occupancy_numsgpr_gfx9_seven, occupancy(10, 0, 0, 8, 10, 101, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx9_ten, occupancy(10, 0, 0, 10, 1, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx9_eight, occupancy(10, 0, 0, 10, 81, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx9_eight_b, occupancy(10, 0, 0, 10, 89, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx9_seven, occupancy(10, 0, 0, 10, 101, 0, 800, 16, 0)
// Same SGPR budget as gfx9 above, but with the trap handler enabled the 16
// reserved SGPRs per wave lower the achievable occupancy.
@@ -47,29 +49,30 @@
// ASM: .set occupancy_numsgpr_gfx9_trap_seven, 7
// ASM: .set occupancy_numsgpr_gfx9_trap_six, 6
-.set occupancy_numsgpr_gfx9_trap_ten, occupancy(10, 0, 0, 8, 10, 1, 0, 800, 16, 16)
-.set occupancy_numsgpr_gfx9_trap_eight, occupancy(10, 0, 0, 8, 10, 65, 0, 800, 16, 16)
-.set occupancy_numsgpr_gfx9_trap_seven, occupancy(10, 0, 0, 8, 10, 81, 0, 800, 16, 16)
-.set occupancy_numsgpr_gfx9_trap_six, occupancy(10, 0, 0, 8, 10, 97, 0, 800, 16, 16)
+.set occupancy_numsgpr_gfx9_trap_ten, occupancy(10, 0, 0, 10, 1, 0, 800, 16, 16)
+.set occupancy_numsgpr_gfx9_trap_eight, occupancy(10, 0, 0, 10, 65, 0, 800, 16, 16)
+.set occupancy_numsgpr_gfx9_trap_seven, occupancy(10, 0, 0, 10, 81, 0, 800, 16, 16)
+.set occupancy_numsgpr_gfx9_trap_six, occupancy(10, 0, 0, 10, 97, 0, 800, 16, 16)
-// On GFX10+ (Generation 9) the SGPR file is large enough that SGPRs never
-// limit occupancy, so the result is just the init occupancy.
+// On a target where SGPRs do not limit occupancy the asm printer passes a zero
+// NumSGPRs, so the SGPR term is skipped and the result is the init occupancy --
+// the expression no longer needs to know the target generation.
-// ASM: .set occupancy_numsgpr_gfx10_one, 1
-// ASM: .set occupancy_numsgpr_gfx10_seven, 7
-// ASM: .set occupancy_numsgpr_gfx10_eight, 8
+// ASM: .set occupancy_numsgpr_unlimited_one, 1
+// ASM: .set occupancy_numsgpr_unlimited_seven, 7
+// ASM: .set occupancy_numsgpr_unlimited_eight, 8
-.set occupancy_numsgpr_gfx10_one, occupancy(10, 0, 0, 9, 1, 200, 0, 800, 16, 0)
-.set occupancy_numsgpr_gfx10_seven, occupancy(10, 0, 0, 9, 7, 200, 0, 800, 16, 0)
-.set occupancy_numsgpr_gfx10_eight, occupancy(10, 0, 0, 9, 8, 200, 0, 800, 16, 0)
+.set occupancy_numsgpr_unlimited_one, occupancy(10, 0, 0, 1, 0, 0, 800, 16, 0)
+.set occupancy_numsgpr_unlimited_seven, occupancy(10, 0, 0, 7, 0, 0, 800, 16, 0)
+.set occupancy_numsgpr_unlimited_eight, occupancy(10, 0, 0, 8, 0, 0, 800, 16, 0)
// ASM: .set occupancy_numvgpr_high_granule_one, 1
// ASM: .set occupancy_numvgpr_high_granule_seven, 7
// ASM: .set occupancy_numvgpr_high_granule_eight, 8
-.set occupancy_numvgpr_high_granule_one, occupancy(1, 2, 0, 0, 11, 0, 1, 0, 0, 0)
-.set occupancy_numvgpr_high_granule_seven, occupancy(7, 2, 0, 0, 11, 0, 1, 0, 0, 0)
-.set occupancy_numvgpr_high_granule_eight, occupancy(8, 2, 0, 0, 11, 0, 1, 0, 0, 0)
+.set occupancy_numvgpr_high_granule_one, occupancy(1, 2, 0, 11, 0, 1, 0, 0, 0)
+.set occupancy_numvgpr_high_granule_seven, occupancy(7, 2, 0, 11, 0, 1, 0, 0, 0)
+.set occupancy_numvgpr_high_granule_eight, occupancy(8, 2, 0, 11, 0, 1, 0, 0, 0)
// ASM: .set occupancy_numvgpr_low_total_one, 1
// ASM: .set occupancy_numvgpr_one, 1
@@ -77,8 +80,8 @@
// ASM: .set occupancy_numvgpr_eight, 8
// ASM: .set occupancy_numvgpr_ten, 10
-.set occupancy_numvgpr_low_total_one, occupancy(11, 4, 2, 0, 11, 0, 4, 0, 0, 0)
-.set occupancy_numvgpr_one, occupancy(11, 4, 4, 0, 11, 0, 4, 0, 0, 0)
-.set occupancy_numvgpr_seven, occupancy(11, 4, 28, 0, 11, 0, 4, 0, 0, 0)
-.set occupancy_numvgpr_eight, occupancy(11, 4, 32, 0, 11, 0, 4, 0, 0, 0)
-.set occupancy_numvgpr_ten, occupancy(11, 4, 40, 0, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_low_total_one, occupancy(11, 4, 2, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_one, occupancy(11, 4, 4, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_seven, occupancy(11, 4, 28, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_eight, occupancy(11, 4, 32, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_ten, occupancy(11, 4, 40, 11, 0, 4, 0, 0, 0)
>From f33d9c971a714744af47607b0961b4f39e6b81da Mon Sep 17 00:00:00 2001
From: mselehov <mselehov at amd.com>
Date: Wed, 3 Jun 2026 10:43:13 -0500
Subject: [PATCH 3/5] [AMDGPU] Address review: trim occupancy comments,
lowercase MCExpr diags
Trim the comments this PR added down to the non-obvious intent (asm printer,
occupancy MCExpr, IsaInfo SGPR budget/inverse, and the headers), and lowercase
the two AMDGPUMCExpr diagnostic strings flagged in review (the getNumExpectedArgs
unreachable and the arity assert). No functional change.
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 13 +++-----
.../AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp | 14 +++-----
.../Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h | 6 ++--
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 33 +++++--------------
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 29 ++++++----------
5 files changed, 31 insertions(+), 64 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index b2ce55587ab77..78970454ae0e5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -435,11 +435,9 @@ const AMDGPUMCExpr *createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
unsigned Granule = IsaInfo::getVGPRAllocGranule(STM, DynamicVGPRBlockSize);
unsigned TargetTotalNumVGPRs = IsaInfo::getTotalNumVGPRs(STM);
- // All subtarget-dependent decisions are taken here from the per-function
- // subtarget STM and baked into the operands; the MCExpr itself stays purely
- // arithmetic because it is evaluated late, when NumSGPRs/NumVGPRs are still
- // symbolic. STM carries the implicit amdhsa trap-handler feature, so the trap
- // reservation has to be threaded through explicitly.
+ // Bake the per-function SGPR budget into the operands so the late-evaluated
+ // MCExpr stays arithmetic. The trap reservation in particular is implicit on
+ // amdhsa and lives on STM, not on the assembler's MCSubtargetInfo.
unsigned SGPRTotal = IsaInfo::getTotalNumSGPRs(STM);
unsigned SGPRGranule = IsaInfo::getSGPRAllocGranule(STM);
unsigned SGPRTrapReserve = STM.hasTrapHandler() ? IsaInfo::TRAP_NUM_SGPRS : 0;
@@ -448,9 +446,8 @@ const AMDGPUMCExpr *createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
return MCConstantExpr::create(Value, Ctx);
};
- // On targets where SGPRs do not limit occupancy, pass a zero SGPR count so
- // the SGPR term is skipped during evaluation, instead of testing the target
- // generation inside the MCExpr.
+ // Zero SGPR count when SGPRs don't limit occupancy, so the MCExpr skips the
+ // SGPR term without having to test the generation itself.
const MCExpr *SGPRArg =
IsaInfo::isSGPROccupancyLimited(STM) ? NumSGPRs : CreateExpr(0);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
index e6eb3d80e4df7..2807dcaaca465 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
@@ -32,7 +32,7 @@ AMDGPUMCExpr::AMDGPUMCExpr(VariantKind Kind, ArrayRef<const MCExpr *> Args,
assert(Kind != AGVK_None && "Cannot construct AMDGPUMCExpr of kind none.");
assert((getNumExpectedArgs(Kind) == 0 ||
Args.size() == getNumExpectedArgs(Kind)) &&
- "Wrong number of operands for AMDGPUMCExpr kind.");
+ "wrong number of operands for AMDGPUMCExpr kind.");
// Allocating the variadic arguments through the same allocation mechanism
// that the object itself is allocated with so they end up in the same memory.
@@ -59,7 +59,7 @@ unsigned AMDGPUMCExpr::getNumExpectedArgs(VariantKind Kind) {
case AGVK_Or:
case AGVK_Max:
case AGVK_Min:
- // Variadic: any number of operands (the parser already requires >= 1).
+ // Variadic (parser requires >= 1).
return 0;
case AGVK_Lit:
case AGVK_Lit64:
@@ -73,7 +73,7 @@ unsigned AMDGPUMCExpr::getNumExpectedArgs(VariantKind Kind) {
case AGVK_Occupancy:
return 9;
}
- llvm_unreachable("Unknown AMDGPUMCExpr kind.");
+ llvm_unreachable("unknown AMDGPUMCExpr kind.");
}
const MCExpr *AMDGPUMCExpr::getSubExpr(size_t Index) const {
@@ -204,12 +204,8 @@ bool AMDGPUMCExpr::evaluateOccupancy(MCValue &Res,
if (!Success || !evaluateMCExprs(Args.slice(4, 2), Asm, {NumSGPRs, NumVGPRs}))
return false;
- // The trailing operands carry the SGPR budget of the code generator's
- // subtarget (total SGPRs, allocation granule, and the trap-handler
- // reservation), so the SGPR-limited occupancy is computed exactly as the code
- // generator does (trap-handler aware). createOccupancy() passes a zero SGPR
- // count on targets where SGPRs do not limit occupancy, so the SGPR term below
- // is skipped without this expression having to know the target generation.
+ // Trailing operands carry the codegen SGPR budget (total, granule, trap
+ // reserve) so the SGPR-limited occupancy matches getMaxNumSGPRs().
if (!evaluateMCExprs(Args.slice(6, 3), Asm,
{SGPRTotal, SGPRGranule, SGPRTrapReserve}))
return false;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
index 068310cebd180..96003711faf88 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
@@ -79,10 +79,8 @@ class AMDGPUMCExpr : public MCTargetExpr {
static const AMDGPUMCExpr *
create(VariantKind Kind, ArrayRef<const MCExpr *> Args, MCContext &Ctx);
- /// \returns the exact number of operands a well-formed expression of \p Kind
- /// must have, or 0 for the variadic kinds (or/max/min) that accept any number
- /// of operands. Used to validate hand-written expressions at parse time and
- /// to assert printer-built ones in create().
+ /// \returns the required operand count for \p Kind, or 0 for the variadic
+ /// kinds (or/max/min). Used at parse time and by the create() assert.
static unsigned getNumExpectedArgs(VariantKind Kind);
static const AMDGPUMCExpr *createOr(ArrayRef<const MCExpr *> Args,
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 139cc80ef70c9..9dd879410e872 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1334,18 +1334,15 @@ unsigned getAddressableNumSGPRs(const MCSubtargetInfo &STI) {
return 104;
}
-// Per-wave SGPRs reserved for the trap handler when it is enabled, in the same
-// units as the budget computations below.
+// Per-wave SGPRs reserved for the trap handler when enabled.
static unsigned getSGPRTrapHandlerReserve(const MCSubtargetInfo &STI) {
return STI.getFeatureBits().test(FeatureTrapHandler) ? TRAP_NUM_SGPRS : 0;
}
-// SGPRs usable per wave when \p WavesPerEU waves share the register file,
-// before any addressable clamp: the trap-handler reservation is taken off the
-// top and the remainder is rounded down to the allocation \p Granule. This is
-// the single source of truth shared by getMinNumSGPRs(), getMaxNumSGPRs() and
-// the occupancy inverse getOccupancyWithNumSGPRs(), so the budget and its
-// inverse cannot drift apart.
+// Per-wave SGPR budget (before the addressable clamp): take off the trap
+// reserve, round down to \p Granule. Single source of truth shared by
+// getMinNumSGPRs()/getMaxNumSGPRs() and the occupancy inverse, so they cannot
+// drift apart.
static unsigned getSGPRBudgetPerWave(unsigned TotalNumSGPRs,
unsigned WavesPerEU, unsigned TrapReserve,
unsigned Granule) {
@@ -1390,14 +1387,8 @@ unsigned getMaxNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
}
bool isSGPROccupancyLimited(const MCSubtargetInfo &STI) {
- // Whether the SGPR file is a limiting resource for occupancy. This is a
- // target capability rather than a generation per se, but it currently has a
- // single determinant: from GFX10 on, the SGPR file is large enough that the
- // SGPR count never reduces occupancy. The test lives here, next to the SGPR
- // model that already keys on the ISA version
- // (getMaxNumSGPRs/getAddressableNumSGPRs), so there is one place to update --
- // or to back by a subtarget feature -- if a future target reintroduces an
- // SGPR-limited regime.
+ // From GFX10 on the SGPR file is large enough that SGPRs never limit
+ // occupancy. Kept as one capability so callers don't each test the version.
return getIsaVersion(STI.getCPU()).Major < 10;
}
@@ -1534,15 +1525,9 @@ unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
unsigned TotalNumSGPRs, unsigned Granule,
unsigned TrapReserve) {
- // Closed-form inverse of getMaxNumSGPRs(): the largest number of waves W
- // whose per-wave SGPR budget still accommodates \p SGPRs. The budget
- // condition
+ // Closed-form inverse of getMaxNumSGPRs(): the budget condition
// SGPRs <= alignDown(TotalNumSGPRs / W - TrapReserve, Granule)
- // is equivalent to TotalNumSGPRs / W - TrapReserve >= alignTo(SGPRs,
- // Granule), i.e. W <= TotalNumSGPRs / (alignTo(SGPRs, Granule) +
- // TrapReserve), so no search is needed. This uses the same per-wave budget as
- // getMaxNumSGPRs(), so the two stay exact inverses (modulo the addressable
- // clamp, which is intentionally not applied here - see the header).
+ // solves to W <= TotalNumSGPRs / (alignTo(SGPRs, Granule) + TrapReserve).
unsigned PerWave = alignTo(SGPRs, Granule) + TrapReserve;
return PerWave ? std::clamp(TotalNumSGPRs / PerWave, 1u, MaxWaves) : MaxWaves;
}
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 35e692da75052..a6088136b4851 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -375,29 +375,20 @@ unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
unsigned MaxWaves,
unsigned TotalNumVGPRs);
-/// \returns Whether the number of allocated SGPRs can reduce occupancy on
-/// subtarget \p STI, i.e. whether the SGPR file is a limiting resource. This is
-/// a single, named capability so that callers (the occupancy query and the asm
-/// printer's occupancy MCExpr) do not each test the ISA version themselves.
+/// \returns Whether allocated SGPRs can reduce occupancy on subtarget \p STI
+/// (true pre-GFX10). One named capability so callers don't test the version.
bool isSGPROccupancyLimited(const MCSubtargetInfo &STI);
-/// \returns Occupancy (waves per EU) limited by \p SGPRs usage for subtarget
-/// \p STI. This is the inverse of getMaxNumSGPRs(): it returns the largest
-/// number of waves W for which \p SGPRs still fits the per-wave SGPR budget
-/// (total SGPRs / W, minus the trap-handler reservation when enabled, rounded
-/// down to the allocation granule). Unlike getMaxNumSGPRs() the budget is not
-/// clamped to the addressable SGPR count, because the reported allocated SGPR
-/// count (which is what callers pass in) can legitimately exceed it.
+/// \returns SGPR-limited occupancy (waves per EU) for subtarget \p STI: the
+/// inverse of getMaxNumSGPRs(). Unlike getMaxNumSGPRs() the budget is not
+/// clamped to the addressable count, since the allocated count callers pass in
+/// can exceed it.
unsigned getOccupancyWithNumSGPRs(const MCSubtargetInfo &STI, unsigned SGPRs);
-/// \returns Occupancy (waves per EU) limited by \p SGPRs usage, computed from
-/// explicit budget parameters rather than a subtarget: the \p MaxWaves cap, the
-/// \p TotalNumSGPRs in the file, the allocation \p Granule, and the
-/// trap-handler \p TrapReserve (0 when the trap handler is disabled). This is
-/// the subtarget-free core shared by the MCSubtargetInfo overload and the
-/// occupancy MCExpr, so that the asm printer reports the same trap-aware
-/// occupancy the code generator assumes. Callers must check
-/// isSGPROccupancyLimited() first; this assumes SGPRs are a limiting resource.
+/// \returns SGPR-limited occupancy computed from explicit budget parameters
+/// (\p MaxWaves, \p TotalNumSGPRs, \p Granule, \p TrapReserve). Subtarget-free
+/// core shared by the overload above and the occupancy MCExpr. Callers must
+/// check isSGPROccupancyLimited() first.
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
unsigned TotalNumSGPRs, unsigned Granule,
unsigned TrapReserve);
>From 1b7052db5d229b6d7302e6d9a262b1133494dd37 Mon Sep 17 00:00:00 2001
From: mselehov <mselehov at amd.com>
Date: Thu, 4 Jun 2026 03:40:49 -0500
Subject: [PATCH 4/5] [AMDGPU] Occupancy review nits: group known operands
first, bail on AGVK_None
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 6 +-
.../AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp | 20 +++----
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 7 ++-
.../CodeGen/AMDGPU/agpr-register-count.ll | 4 +-
.../AMDGPU/resource-optimization-remarks.ll | 4 +-
llvm/test/MC/AMDGPU/occupancy_mcexpr.s | 57 ++++++++++---------
6 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 78970454ae0e5..9f29934f5a4a5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -454,9 +454,9 @@ const AMDGPUMCExpr *createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
return AMDGPUMCExpr::create(AMDGPUMCExpr::AGVK_Occupancy,
{CreateExpr(MaxWaves), CreateExpr(Granule),
CreateExpr(TargetTotalNumVGPRs),
- CreateExpr(InitOcc), SGPRArg, NumVGPRs,
- CreateExpr(SGPRTotal), CreateExpr(SGPRGranule),
- CreateExpr(SGPRTrapReserve)},
+ CreateExpr(InitOcc), CreateExpr(SGPRTotal),
+ CreateExpr(SGPRGranule),
+ CreateExpr(SGPRTrapReserve), SGPRArg, NumVGPRs},
Ctx);
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
index 2807dcaaca465..745647e235f6e 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
@@ -56,6 +56,7 @@ const AMDGPUMCExpr *AMDGPUMCExpr::create(VariantKind Kind,
unsigned AMDGPUMCExpr::getNumExpectedArgs(VariantKind Kind) {
switch (Kind) {
case AGVK_None:
+ llvm_unreachable("AGVK_None is not a valid AMDGPUMCExpr kind.");
case AGVK_Or:
case AGVK_Max:
case AGVK_Min:
@@ -195,19 +196,18 @@ bool AMDGPUMCExpr::evaluateOccupancy(MCValue &Res,
uint64_t InitOccupancy, MaxWaves, Granule, TargetTotalNumVGPRs, NumSGPRs,
NumVGPRs, SGPRTotal, SGPRGranule, SGPRTrapReserve;
+ // Leading operands are known constants (wave/VGPR caps + the SGPR budget
+ // total/granule/trap reserve baked in by createOccupancy); only NumSGPRs and
+ // NumVGPRs can still be symbolic. The SGPR budget makes the SGPR-limited
+ // occupancy match getMaxNumSGPRs().
bool Success =
- evaluateMCExprs(Args.slice(0, 4), Asm,
- {MaxWaves, Granule, TargetTotalNumVGPRs, InitOccupancy});
+ evaluateMCExprs(Args.slice(0, 7), Asm,
+ {MaxWaves, Granule, TargetTotalNumVGPRs, InitOccupancy,
+ SGPRTotal, SGPRGranule, SGPRTrapReserve});
- assert(Success && "Arguments 1 to 4 for Occupancy should be known constants");
+ assert(Success && "Arguments 1 to 7 for Occupancy should be known constants");
- if (!Success || !evaluateMCExprs(Args.slice(4, 2), Asm, {NumSGPRs, NumVGPRs}))
- return false;
-
- // Trailing operands carry the codegen SGPR budget (total, granule, trap
- // reserve) so the SGPR-limited occupancy matches getMaxNumSGPRs().
- if (!evaluateMCExprs(Args.slice(6, 3), Asm,
- {SGPRTotal, SGPRGranule, SGPRTrapReserve}))
+ if (!Success || !evaluateMCExprs(Args.slice(7, 2), Asm, {NumSGPRs, NumVGPRs}))
return false;
unsigned Occupancy = InitOccupancy;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 9dd879410e872..500f01b9c8dda 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1340,9 +1340,10 @@ static unsigned getSGPRTrapHandlerReserve(const MCSubtargetInfo &STI) {
}
// Per-wave SGPR budget (before the addressable clamp): take off the trap
-// reserve, round down to \p Granule. Single source of truth shared by
-// getMinNumSGPRs()/getMaxNumSGPRs() and the occupancy inverse, so they cannot
-// drift apart.
+// reserve, round down to \p Granule. Shared by getMinNumSGPRs() and
+// getMaxNumSGPRs(); getOccupancyWithNumSGPRs() is the closed-form algebraic
+// inverse of this same budget (it does not call this helper), so the two encode
+// one model.
static unsigned getSGPRBudgetPerWave(unsigned TotalNumSGPRs,
unsigned WavesPerEU, unsigned TrapReserve,
unsigned Granule) {
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
index 1bdb8a7bffb18..e0a65f43bdc9a 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
@@ -165,8 +165,8 @@ declare void @undef_func()
; GFX90A: VGPRBlocks: (alignto(max(max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 1), 8)/8)-1
; GCN: NumVGPRsForWavesPerEU: max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0)
; GFX90A: AccumOffset: ((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1+1)*4
-; GFX908: Occupancy: occupancy(10, 4, 256, 10, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 800, 16, 16)
-; GFX90A: Occupancy: occupancy(8, 8, 512, 8, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 800, 16, 16)
+; GFX908: Occupancy: occupancy(10, 4, 256, 10, 800, 16, 16, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0))
+; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 800, 16, 16, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0))
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: (((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1)&~65536)&63
define amdgpu_kernel void @kernel_call_undef_func() #0 {
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll b/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
index 203c4fb9c6267..3a008e90d60d4 100644
--- a/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
+++ b/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
@@ -146,7 +146,7 @@ define void @empty_func() !dbg !8 {
; STDERR-NEXT: remark: foo.cl:64:0: AGPRs: .Ltest_indirect_call.num_agpr
; STDERR-NEXT: remark: foo.cl:64:0: ScratchSize [bytes/lane]: 0
; STDERR-NEXT: remark: foo.cl:64:0: Dynamic Stack: True
-; STDERR-NEXT: remark: foo.cl:64:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 10, max(.Ltest_indirect_call.numbered_sgpr+extrasgprs(.Ltest_indirect_call.uses_vcc, .Ltest_indirect_call.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_call.num_agpr, .Ltest_indirect_call.num_vgpr), 1, 0), 800, 16, 16)
+; STDERR-NEXT: remark: foo.cl:64:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 10, 800, 16, 16, max(.Ltest_indirect_call.numbered_sgpr+extrasgprs(.Ltest_indirect_call.uses_vcc, .Ltest_indirect_call.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_call.num_agpr, .Ltest_indirect_call.num_vgpr), 1, 0))
; STDERR-NEXT: remark: foo.cl:64:0: SGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:64:0: VGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:64:0: LDS Size [bytes/block]: 0
@@ -164,7 +164,7 @@ define amdgpu_kernel void @test_indirect_call() !dbg !9 {
; STDERR-NEXT: remark: foo.cl:74:0: AGPRs: .Ltest_indirect_w_static_stack.num_agpr
; STDERR-NEXT: remark: foo.cl:74:0: ScratchSize [bytes/lane]: 144
; STDERR-NEXT: remark: foo.cl:74:0: Dynamic Stack: True
-; STDERR-NEXT: remark: foo.cl:74:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 10, max(.Ltest_indirect_w_static_stack.numbered_sgpr+extrasgprs(.Ltest_indirect_w_static_stack.uses_vcc, .Ltest_indirect_w_static_stack.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_w_static_stack.num_agpr, .Ltest_indirect_w_static_stack.num_vgpr), 1, 0), 800, 16, 16)
+; STDERR-NEXT: remark: foo.cl:74:0: Occupancy [waves/SIMD]: occupancy(10, 4, 256, 10, 800, 16, 16, max(.Ltest_indirect_w_static_stack.numbered_sgpr+extrasgprs(.Ltest_indirect_w_static_stack.uses_vcc, .Ltest_indirect_w_static_stack.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Ltest_indirect_w_static_stack.num_agpr, .Ltest_indirect_w_static_stack.num_vgpr), 1, 0))
; STDERR-NEXT: remark: foo.cl:74:0: SGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:74:0: VGPRs Spill: 0
; STDERR-NEXT: remark: foo.cl:74:0: LDS Size [bytes/block]: 0
diff --git a/llvm/test/MC/AMDGPU/occupancy_mcexpr.s b/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
index d8f2406c9af70..69c22f5612c37 100644
--- a/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
+++ b/llvm/test/MC/AMDGPU/occupancy_mcexpr.s
@@ -2,9 +2,10 @@
// The occupancy() MCExpr arguments are:
// occupancy(MaxWaves, VGPRGranule, TotalVGPRs, InitOcc,
-// NumSGPRs, NumVGPRs, SGPRTotal, SGPRGranule, SGPRTrapReserve)
-// The SGPR budget (SGPRTotal/SGPRGranule/SGPRTrapReserve) is passed explicitly
-// so the SGPR-limited occupancy matches the code generator, including the
+// SGPRTotal, SGPRGranule, SGPRTrapReserve, NumSGPRs, NumVGPRs)
+// The known constants (the wave/VGPR caps and the SGPR budget) come first; only
+// NumSGPRs/NumVGPRs may be symbolic. The SGPR budget is passed explicitly so
+// the SGPR-limited occupancy matches the code generator, including the
// trap-handler reservation, independent of the assembler's subtarget. On
// targets where SGPRs do not limit occupancy the asm printer passes a zero
// NumSGPRs (see createOccupancy), so the expression never tests the generation.
@@ -24,22 +25,22 @@
// ASM: .set occupancy_numsgpr_seaisle_six, 6
// ASM: .set occupancy_numsgpr_seaisle_five, 5
-.set occupancy_numsgpr_seaisle_ten, occupancy(10, 0, 0, 10, 1, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_nine, occupancy(10, 0, 0, 10, 49, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_eight, occupancy(10, 0, 0, 10, 57, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_seven, occupancy(10, 0, 0, 10, 65, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_six, occupancy(10, 0, 0, 10, 73, 0, 512, 8, 0)
-.set occupancy_numsgpr_seaisle_five, occupancy(10, 0, 0, 10, 81, 0, 512, 8, 0)
+.set occupancy_numsgpr_seaisle_ten, occupancy(10, 0, 0, 10, 512, 8, 0, 1, 0)
+.set occupancy_numsgpr_seaisle_nine, occupancy(10, 0, 0, 10, 512, 8, 0, 49, 0)
+.set occupancy_numsgpr_seaisle_eight, occupancy(10, 0, 0, 10, 512, 8, 0, 57, 0)
+.set occupancy_numsgpr_seaisle_seven, occupancy(10, 0, 0, 10, 512, 8, 0, 65, 0)
+.set occupancy_numsgpr_seaisle_six, occupancy(10, 0, 0, 10, 512, 8, 0, 73, 0)
+.set occupancy_numsgpr_seaisle_five, occupancy(10, 0, 0, 10, 512, 8, 0, 81, 0)
// ASM: .set occupancy_numsgpr_gfx9_ten, 10
// ASM: .set occupancy_numsgpr_gfx9_eight, 8
// ASM: .set occupancy_numsgpr_gfx9_eight_b, 8
// ASM: .set occupancy_numsgpr_gfx9_seven, 7
-.set occupancy_numsgpr_gfx9_ten, occupancy(10, 0, 0, 10, 1, 0, 800, 16, 0)
-.set occupancy_numsgpr_gfx9_eight, occupancy(10, 0, 0, 10, 81, 0, 800, 16, 0)
-.set occupancy_numsgpr_gfx9_eight_b, occupancy(10, 0, 0, 10, 89, 0, 800, 16, 0)
-.set occupancy_numsgpr_gfx9_seven, occupancy(10, 0, 0, 10, 101, 0, 800, 16, 0)
+.set occupancy_numsgpr_gfx9_ten, occupancy(10, 0, 0, 10, 800, 16, 0, 1, 0)
+.set occupancy_numsgpr_gfx9_eight, occupancy(10, 0, 0, 10, 800, 16, 0, 81, 0)
+.set occupancy_numsgpr_gfx9_eight_b, occupancy(10, 0, 0, 10, 800, 16, 0, 89, 0)
+.set occupancy_numsgpr_gfx9_seven, occupancy(10, 0, 0, 10, 800, 16, 0, 101, 0)
// Same SGPR budget as gfx9 above, but with the trap handler enabled the 16
// reserved SGPRs per wave lower the achievable occupancy.
@@ -49,10 +50,10 @@
// ASM: .set occupancy_numsgpr_gfx9_trap_seven, 7
// ASM: .set occupancy_numsgpr_gfx9_trap_six, 6
-.set occupancy_numsgpr_gfx9_trap_ten, occupancy(10, 0, 0, 10, 1, 0, 800, 16, 16)
-.set occupancy_numsgpr_gfx9_trap_eight, occupancy(10, 0, 0, 10, 65, 0, 800, 16, 16)
-.set occupancy_numsgpr_gfx9_trap_seven, occupancy(10, 0, 0, 10, 81, 0, 800, 16, 16)
-.set occupancy_numsgpr_gfx9_trap_six, occupancy(10, 0, 0, 10, 97, 0, 800, 16, 16)
+.set occupancy_numsgpr_gfx9_trap_ten, occupancy(10, 0, 0, 10, 800, 16, 16, 1, 0)
+.set occupancy_numsgpr_gfx9_trap_eight, occupancy(10, 0, 0, 10, 800, 16, 16, 65, 0)
+.set occupancy_numsgpr_gfx9_trap_seven, occupancy(10, 0, 0, 10, 800, 16, 16, 81, 0)
+.set occupancy_numsgpr_gfx9_trap_six, occupancy(10, 0, 0, 10, 800, 16, 16, 97, 0)
// On a target where SGPRs do not limit occupancy the asm printer passes a zero
// NumSGPRs, so the SGPR term is skipped and the result is the init occupancy --
@@ -62,17 +63,17 @@
// ASM: .set occupancy_numsgpr_unlimited_seven, 7
// ASM: .set occupancy_numsgpr_unlimited_eight, 8
-.set occupancy_numsgpr_unlimited_one, occupancy(10, 0, 0, 1, 0, 0, 800, 16, 0)
-.set occupancy_numsgpr_unlimited_seven, occupancy(10, 0, 0, 7, 0, 0, 800, 16, 0)
-.set occupancy_numsgpr_unlimited_eight, occupancy(10, 0, 0, 8, 0, 0, 800, 16, 0)
+.set occupancy_numsgpr_unlimited_one, occupancy(10, 0, 0, 1, 800, 16, 0, 0, 0)
+.set occupancy_numsgpr_unlimited_seven, occupancy(10, 0, 0, 7, 800, 16, 0, 0, 0)
+.set occupancy_numsgpr_unlimited_eight, occupancy(10, 0, 0, 8, 800, 16, 0, 0, 0)
// ASM: .set occupancy_numvgpr_high_granule_one, 1
// ASM: .set occupancy_numvgpr_high_granule_seven, 7
// ASM: .set occupancy_numvgpr_high_granule_eight, 8
-.set occupancy_numvgpr_high_granule_one, occupancy(1, 2, 0, 11, 0, 1, 0, 0, 0)
-.set occupancy_numvgpr_high_granule_seven, occupancy(7, 2, 0, 11, 0, 1, 0, 0, 0)
-.set occupancy_numvgpr_high_granule_eight, occupancy(8, 2, 0, 11, 0, 1, 0, 0, 0)
+.set occupancy_numvgpr_high_granule_one, occupancy(1, 2, 0, 11, 0, 0, 0, 0, 1)
+.set occupancy_numvgpr_high_granule_seven, occupancy(7, 2, 0, 11, 0, 0, 0, 0, 1)
+.set occupancy_numvgpr_high_granule_eight, occupancy(8, 2, 0, 11, 0, 0, 0, 0, 1)
// ASM: .set occupancy_numvgpr_low_total_one, 1
// ASM: .set occupancy_numvgpr_one, 1
@@ -80,8 +81,8 @@
// ASM: .set occupancy_numvgpr_eight, 8
// ASM: .set occupancy_numvgpr_ten, 10
-.set occupancy_numvgpr_low_total_one, occupancy(11, 4, 2, 11, 0, 4, 0, 0, 0)
-.set occupancy_numvgpr_one, occupancy(11, 4, 4, 11, 0, 4, 0, 0, 0)
-.set occupancy_numvgpr_seven, occupancy(11, 4, 28, 11, 0, 4, 0, 0, 0)
-.set occupancy_numvgpr_eight, occupancy(11, 4, 32, 11, 0, 4, 0, 0, 0)
-.set occupancy_numvgpr_ten, occupancy(11, 4, 40, 11, 0, 4, 0, 0, 0)
+.set occupancy_numvgpr_low_total_one, occupancy(11, 4, 2, 11, 0, 0, 0, 0, 4)
+.set occupancy_numvgpr_one, occupancy(11, 4, 4, 11, 0, 0, 0, 0, 4)
+.set occupancy_numvgpr_seven, occupancy(11, 4, 28, 11, 0, 0, 0, 0, 4)
+.set occupancy_numvgpr_eight, occupancy(11, 4, 32, 11, 0, 0, 0, 0, 4)
+.set occupancy_numvgpr_ten, occupancy(11, 4, 40, 11, 0, 0, 0, 0, 4)
>From 4e3d3d7fc90bc09574032f26a495dfb810fbad73 Mon Sep 17 00:00:00 2001
From: mselehov <mselehov at amd.com>
Date: Thu, 4 Jun 2026 10:15:12 -0500
Subject: [PATCH 5/5] [AMDGPU] Add SGPR occupancy round-trip unit test (inverse
of getMaxNumSGPRs)
---
.../Target/AMDGPU/AMDGPUUnitTests.cpp | 29 +++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
index 103891bbedecd..d1570e3986188 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
@@ -49,13 +49,15 @@ static bool checkMinMax(std::stringstream &OS, unsigned Occ, unsigned MinOcc,
unsigned MaxOcc,
std::function<unsigned(unsigned)> GetOcc,
std::function<unsigned(unsigned)> GetMinGPRs,
- std::function<unsigned(unsigned)> GetMaxGPRs) {
+ std::function<unsigned(unsigned)> GetMaxGPRs,
+ bool AllowUnreachable = false) {
bool MinValid = true, MaxValid = true, RangeValid = true;
unsigned MinGPRs = GetMinGPRs(Occ);
unsigned MaxGPRs = GetMaxGPRs(Occ);
unsigned RealOcc;
- if (MinGPRs >= MaxGPRs)
+ bool Unreachable = MinGPRs >= MaxGPRs;
+ if (Unreachable)
RangeValid = false;
else {
RealOcc = GetOcc(MinGPRs);
@@ -82,6 +84,12 @@ static bool checkMinMax(std::stringstream &OS, unsigned Occ, unsigned MinOcc,
OS << std::left << std::setw(15) << MinStr.str() << std::setw(3) << MaxGPRs
<< " (O" << GetOcc(MaxGPRs) << ')' << (MaxValid ? "" : " >");
+ // A coarse resource (SGPRs before GFX10) cannot realize every occupancy
+ // level: an empty [min, max] window just means this level is unreachable,
+ // which is not a min/max inconsistency.
+ if (Unreachable && AllowUnreachable)
+ return true;
+
return MinValid && MaxValid && RangeValid;
}
@@ -201,6 +209,23 @@ TEST_F(AMDGPUTestBase, TestVGPRLimitsPerOccupancy) {
testDynamicVGPRLimits("gfx1200", "+wavefrontsize32", test);
}
+TEST_F(AMDGPUTestBase, TestSGPRLimitsPerOccupancy) {
+ auto test = [](std::stringstream &OS, unsigned Occ, const GCNSubtarget &ST,
+ unsigned /*DynamicVGPRBlockSize*/) {
+ unsigned MaxSGPRNum = ST.getAddressableNumSGPRs();
+ return checkMinMax(
+ OS, Occ, ST.getOccupancyWithNumSGPRs(MaxSGPRNum), ST.getMaxWavesPerEU(),
+ [&](unsigned NumGPRs) { return ST.getOccupancyWithNumSGPRs(NumGPRs); },
+ [&](unsigned Occ) { return ST.getMinNumSGPRs(Occ); },
+ [&](unsigned Occ) {
+ return ST.getMaxNumSGPRs(Occ, /*Addressable=*/true);
+ },
+ /*AllowUnreachable=*/true);
+ };
+
+ testGPRLimits("SGPR", false, test);
+}
+
static void testAbsoluteLimits(StringRef CPUName, StringRef FS,
unsigned DynamicVGPRBlockSize,
unsigned ExpectedMinOcc, unsigned ExpectedMaxOcc,
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