[llvm] 9f53175 - [RISCV][P-ext] Support packed bswap/bitreverse. (#200448)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 4 08:03:15 PDT 2026
Author: Craig Topper
Date: 2026-06-04T08:03:10-07:00
New Revision: 9f531751bbba6b1493ef4c73c6c97f0adb029976
URL: https://github.com/llvm/llvm-project/commit/9f531751bbba6b1493ef4c73c6c97f0adb029976
DIFF: https://github.com/llvm/llvm-project/commit/9f531751bbba6b1493ef4c73c6c97f0adb029976.diff
LOG: [RISCV][P-ext] Support packed bswap/bitreverse. (#200448)
We can implement these using combinations of rev, rev8, and ppairoe.*.
Rename REV16->REV16_RV64. A hypothetical REV16 on RV32 would have a
different encoding like REV and REV8.
Long term we should probably custom lower these instead of having
complex isel patterns. That would allow additional optimizations. But I
think the isel patterns are fine as a starting point.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoP.td
llvm/test/CodeGen/RISCV/rvp-simd-32.ll
llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8931cf03b7a4f..be98a3e1db5f3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -580,11 +580,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::USUBSAT, VTs, Legal);
setOperationAction(ISD::SSUBSAT, VTs, Legal);
setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VTs, Legal);
+ setOperationAction(ISD::BITREVERSE, VTs, Legal);
for (MVT VT : VTs) {
if (VT != MVT::v2i32)
setOperationAction({ISD::ABS, ISD::ABDS, ISD::ABDU}, VT, Legal);
- if (VT.getVectorElementType() != MVT::i8)
+ if (VT.getVectorElementType() != MVT::i8) {
setOperationAction(ISD::SSHLSAT, VT, Custom);
+ setOperationAction(ISD::BSWAP, VT, Legal);
+ }
}
setOperationAction(ISD::SPLAT_VECTOR, VTs, Legal);
setOperationAction(ISD::BUILD_VECTOR, VTs, Legal);
@@ -637,6 +640,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
{MVT::v4i16, MVT::v8i8}, Legal);
setOperationAction({ISD::SHL, ISD::SRL, ISD::SRA}, P64VecVTs, Custom);
setOperationAction(ISD::SSHLSAT, {MVT::v2i32, MVT::v4i16}, Custom);
+ setOperationAction(ISD::BSWAP, MVT::v4i16, Legal);
+ setOperationAction(ISD::BITREVERSE, {MVT::v4i16, MVT::v8i8}, Legal);
setOperationAction(ISD::SPLAT_VECTOR, P64VecVTs, Legal);
setOperationAction(ISD::BUILD_VECTOR, P64VecVTs, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 4c07d054c2983..1601fa81e791e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -561,7 +561,7 @@ let append Predicates = [IsRV32] in {
} // Predicates = [IsRV32]
let append Predicates = [IsRV64] in {
- def REV16 : Unary_r<0b011010110000, 0b101, "rev16">;
+ def REV16_RV64 : Unary_r<0b011010110000, 0b101, "rev16">;
def REV_RV64 : Unary_r<0b011010111111, 0b101, "rev">;
let IsSignExtendingOpW = 1 in {
@@ -2055,6 +2055,10 @@ let Predicates = [HasStdExtP] in {
def : Pat<(XLenVecI16VT (vselect (XLenVecI16VT GPR:$mask), GPR:$true_v, GPR:$false_v)),
(MERGE GPR:$mask, GPR:$false_v, GPR:$true_v)>;
+ // 16-bit bswap patterns
+ def : Pat<(XLenVecI16VT (bswap GPR:$rs)),
+ (PPAIROE_B GPR:$rs, GPR:$rs)>;
+
let append Predicates = [IsRV32] in {
def : PatGpr<bitreverse, REV_RV32>;
@@ -2130,6 +2134,13 @@ let append Predicates = [IsRV32] in {
def : Pat<(v2i16 (mul GPR:$rs1, GPR:$rs2)),
(PNSRLI_H (PWMUL_H GPR:$rs1, GPR:$rs2), 0)>;
+ // 8/16-bit bitrevers patterns
+ // FIXME: Use BREV8 with Zbkb.
+ def : Pat<(v4i8 (bitreverse GPR:$rs)),
+ (REV8_RV32 (REV_RV32 GPR:$rs))>;
+ def : Pat<(v2i16 (bitreverse GPR:$rs)),
+ (PPAIROE_H (REV_RV32 GPR:$rs), (REV_RV32 GPR:$rs))>;
+
// Load/Store patterns
def : StPat<store, SW, GPR, v4i8>;
def : StPat<store, SW, GPR, v2i16>;
@@ -2278,6 +2289,21 @@ let append Predicates = [IsRV32] in {
def : PatGprPairGprPair<smax, PMAX_DW, v2i32>;
def : PatGprPairGprPair<umax, PMAXU_DW, v2i32>;
+ // 16-bit bswap patterns
+ def : Pat<(v4i16 (bswap GPRPair:$rs)),
+ (PPAIROE_DB GPRPair:$rs, GPRPair:$rs)>;
+
+ // 8/16-bit bitreverse patterns
+ // FIXME: Custom lower?
+ def : Pat<(v8i8 (bitreverse GPRPair:$rs)),
+ (BuildGPRPair (REV8_RV32 (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even))),
+ (REV8_RV32 (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd))))>;
+ def : Pat<(v4i16 (bitreverse GPRPair:$rs)),
+ (PPAIROE_DH (BuildGPRPair (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)),
+ (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd))),
+ (BuildGPRPair (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)),
+ (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd))))>;
+
// splat pattern
def : Pat<(v8i8 (splat_vector (XLenVT GPR:$rs2))),
(PADD_DBS (v8i8 X0_Pair), GPR:$rs2)>;
@@ -2441,6 +2467,18 @@ let append Predicates = [IsRV64] in {
def : Pat<(v2i32 (vselect (v2i32 GPR:$mask), GPR:$true_v, GPR:$false_v)),
(MERGE GPR:$mask, GPR:$false_v, GPR:$true_v)>;
+ // 32-bit bswap patterns
+ def : Pat<(v2i32 (bswap GPR:$rs)),
+ (PPAIROE_W (REV8_RV64 GPR:$rs), (REV8_RV64 GPR:$rs))>;
+
+ // 8/16/32-bit bitreverse patterns
+ def : Pat<(v8i8 (bitreverse GPR:$rs)),
+ (REV8_RV64 (REV_RV64 GPR:$rs))>;
+ def : Pat<(v4i16 (bitreverse GPR:$rs)),
+ (REV16_RV64 (REV_RV64 GPR:$rs))>;
+ def : Pat<(v2i32 (bitreverse GPR:$rs)),
+ (PPAIROE_W (REV_RV64 GPR:$rs), (REV_RV64 GPR:$rs))>;
+
// Load/Store patterns
def : StPat<store, SD, GPR, v8i8>;
def : StPat<store, SD, GPR, v4i16>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index f7078dad860f5..1b0ecb8f151de 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -2061,9 +2061,7 @@ define <4 x i8> @test_vselect_v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c) {
define <2 x i16> @test_bswap_v2i16(<2 x i16> %a) {
; CHECK-LABEL: test_bswap_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: psrli.h a1, a0, 8
-; CHECK-NEXT: pslli.h a0, a0, 8
-; CHECK-NEXT: or a0, a0, a1
+; CHECK-NEXT: ppairoe.b a0, a0, a0
; CHECK-NEXT: ret
%res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
ret <2 x i16> %res
@@ -2072,54 +2070,25 @@ define <2 x i16> @test_bswap_v2i16(<2 x i16> %a) {
define <4 x i8> @test_bitreverse_v4i8(<4 x i8> %a) {
; CHECK-LABEL: test_bitreverse_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: psrli.b a1, a0, 4
-; CHECK-NEXT: pli.b a2, 15
-; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: pli.b a2, 51
-; CHECK-NEXT: pslli.b a0, a0, 4
-; CHECK-NEXT: or a0, a1, a0
-; CHECK-NEXT: psrli.b a1, a0, 2
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: pli.b a2, 85
-; CHECK-NEXT: pslli.b a0, a0, 2
-; CHECK-NEXT: or a0, a1, a0
-; CHECK-NEXT: psrli.b a1, a0, 1
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: pslli.b a0, a0, 1
-; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: rev a0, a0
+; CHECK-NEXT: rev8 a0, a0
; CHECK-NEXT: ret
%res = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %a)
ret <4 x i8> %res
}
define <2 x i16> @test_bitreverse_v2i16(<2 x i16> %a) {
-; CHECK-LABEL: test_bitreverse_v2i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: psrli.h a1, a0, 8
-; CHECK-NEXT: pslli.h a0, a0, 8
-; CHECK-NEXT: pli.b a2, 15
-; CHECK-NEXT: or a0, a0, a1
-; CHECK-NEXT: psrli.h a1, a0, 4
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: pli.b a2, 51
-; CHECK-NEXT: pslli.h a0, a0, 4
-; CHECK-NEXT: or a0, a1, a0
-; CHECK-NEXT: psrli.h a1, a0, 2
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: pli.b a2, 85
-; CHECK-NEXT: pslli.h a0, a0, 2
-; CHECK-NEXT: or a0, a1, a0
-; CHECK-NEXT: psrli.h a1, a0, 1
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: pslli.h a0, a0, 1
-; CHECK-NEXT: or a0, a1, a0
-; CHECK-NEXT: ret
+; RV32-LABEL: test_bitreverse_v2i16:
+; RV32: # %bb.0:
+; RV32-NEXT: rev a0, a0
+; RV32-NEXT: ppairoe.h a0, a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_bitreverse_v2i16:
+; RV64: # %bb.0:
+; RV64-NEXT: rev a0, a0
+; RV64-NEXT: rev16 a0, a0
+; RV64-NEXT: ret
%res = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
ret <2 x i16> %res
}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 8d2d0f278e8c9..4cdb607b44733 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -4134,17 +4134,12 @@ define <2 x i32> @test_vselect_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
define <4 x i16> @test_bswap_v4i16(<4 x i16> %a) {
; RV32-LABEL: test_bswap_v4i16:
; RV32: # %bb.0:
-; RV32-NEXT: psrli.dh a2, a0, 8
-; RV32-NEXT: pslli.dh a0, a0, 8
-; RV32-NEXT: or a1, a1, a3
-; RV32-NEXT: or a0, a0, a2
+; RV32-NEXT: ppairoe.db a0, a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: test_bswap_v4i16:
; RV64: # %bb.0:
-; RV64-NEXT: psrli.h a1, a0, 8
-; RV64-NEXT: pslli.h a0, a0, 8
-; RV64-NEXT: or a0, a0, a1
+; RV64-NEXT: ppairoe.b a0, a0, a0
; RV64-NEXT: ret
%res = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %a)
ret <4 x i16> %res
@@ -4159,18 +4154,8 @@ define <2 x i32> @test_bswap_v2i32(<2 x i32> %a) {
;
; RV64-LABEL: test_bswap_v2i32:
; RV64: # %bb.0:
-; RV64-NEXT: psrli.w a1, a0, 8
-; RV64-NEXT: lui a2, 16
-; RV64-NEXT: psrli.w a3, a0, 24
-; RV64-NEXT: addi a2, a2, -256
-; RV64-NEXT: pmv.ws a2, a2
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: and a2, a0, a2
-; RV64-NEXT: or a1, a1, a3
-; RV64-NEXT: pslli.w a2, a2, 8
-; RV64-NEXT: pslli.w a0, a0, 24
-; RV64-NEXT: or a0, a0, a2
-; RV64-NEXT: or a0, a0, a1
+; RV64-NEXT: rev8 a0, a0
+; RV64-NEXT: ppairoe.w a0, a0, a0
; RV64-NEXT: ret
%res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a)
ret <2 x i32> %res
@@ -4179,55 +4164,16 @@ define <2 x i32> @test_bswap_v2i32(<2 x i32> %a) {
define <8 x i8> @test_bitreverse_v8i8(<8 x i8> %a) {
; RV32-LABEL: test_bitreverse_v8i8:
; RV32: # %bb.0:
-; RV32-NEXT: pli.b a2, 15
-; RV32-NEXT: pli.b a3, 51
-; RV32-NEXT: pli.b a4, 85
-; RV32-NEXT: and a7, a1, a2
-; RV32-NEXT: and a6, a0, a2
-; RV32-NEXT: psrli.db a0, a0, 4
-; RV32-NEXT: and a1, a1, a2
-; RV32-NEXT: and a0, a0, a2
-; RV32-NEXT: pslli.db a6, a6, 4
-; RV32-NEXT: or a1, a1, a7
-; RV32-NEXT: or a0, a0, a6
-; RV32-NEXT: psrli.db a6, a0, 2
-; RV32-NEXT: and a1, a1, a3
-; RV32-NEXT: and a0, a0, a3
-; RV32-NEXT: and a2, a7, a3
-; RV32-NEXT: and a3, a6, a3
-; RV32-NEXT: pslli.db a0, a0, 2
-; RV32-NEXT: or a1, a2, a1
-; RV32-NEXT: or a0, a3, a0
-; RV32-NEXT: psrli.db a2, a0, 1
-; RV32-NEXT: and a1, a1, a4
-; RV32-NEXT: and a3, a3, a4
-; RV32-NEXT: and a0, a0, a4
-; RV32-NEXT: and a2, a2, a4
-; RV32-NEXT: pslli.db a0, a0, 1
-; RV32-NEXT: or a1, a3, a1
-; RV32-NEXT: or a0, a2, a0
+; RV32-NEXT: rev a1, a1
+; RV32-NEXT: rev a0, a0
+; RV32-NEXT: rev8 a1, a1
+; RV32-NEXT: rev8 a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: test_bitreverse_v8i8:
; RV64: # %bb.0:
-; RV64-NEXT: psrli.b a1, a0, 4
-; RV64-NEXT: pli.b a2, 15
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: pli.b a2, 51
-; RV64-NEXT: pslli.b a0, a0, 4
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: psrli.b a1, a0, 2
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: pli.b a2, 85
-; RV64-NEXT: pslli.b a0, a0, 2
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: psrli.b a1, a0, 1
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: pslli.b a0, a0, 1
-; RV64-NEXT: or a0, a1, a0
+; RV64-NEXT: rev a0, a0
+; RV64-NEXT: rev8 a0, a0
; RV64-NEXT: ret
%res = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a)
ret <8 x i8> %res
@@ -4236,62 +4182,15 @@ define <8 x i8> @test_bitreverse_v8i8(<8 x i8> %a) {
define <4 x i16> @test_bitreverse_v4i16(<4 x i16> %a) {
; RV32-LABEL: test_bitreverse_v4i16:
; RV32: # %bb.0:
-; RV32-NEXT: pli.b a2, 15
-; RV32-NEXT: pli.b a3, 51
-; RV32-NEXT: psrli.dh a4, a0, 8
-; RV32-NEXT: pslli.dh a0, a0, 8
-; RV32-NEXT: or a1, a1, a5
-; RV32-NEXT: or a0, a0, a4
-; RV32-NEXT: pli.b a4, 85
-; RV32-NEXT: and a7, a1, a2
-; RV32-NEXT: and a6, a0, a2
-; RV32-NEXT: psrli.dh a0, a0, 4
-; RV32-NEXT: and a1, a1, a2
-; RV32-NEXT: and a0, a0, a2
-; RV32-NEXT: pslli.dh a6, a6, 4
-; RV32-NEXT: or a1, a1, a7
-; RV32-NEXT: or a0, a0, a6
-; RV32-NEXT: psrli.dh a6, a0, 2
-; RV32-NEXT: and a1, a1, a3
-; RV32-NEXT: and a0, a0, a3
-; RV32-NEXT: and a2, a7, a3
-; RV32-NEXT: and a3, a6, a3
-; RV32-NEXT: pslli.dh a0, a0, 2
-; RV32-NEXT: or a1, a2, a1
-; RV32-NEXT: or a0, a3, a0
-; RV32-NEXT: psrli.dh a2, a0, 1
-; RV32-NEXT: and a1, a1, a4
-; RV32-NEXT: and a3, a3, a4
-; RV32-NEXT: and a0, a0, a4
-; RV32-NEXT: and a2, a2, a4
-; RV32-NEXT: pslli.dh a0, a0, 1
-; RV32-NEXT: or a1, a3, a1
-; RV32-NEXT: or a0, a2, a0
+; RV32-NEXT: rev a1, a1
+; RV32-NEXT: rev a0, a0
+; RV32-NEXT: ppairoe.dh a0, a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: test_bitreverse_v4i16:
; RV64: # %bb.0:
-; RV64-NEXT: psrli.h a1, a0, 8
-; RV64-NEXT: pslli.h a0, a0, 8
-; RV64-NEXT: pli.b a2, 15
-; RV64-NEXT: or a0, a0, a1
-; RV64-NEXT: psrli.h a1, a0, 4
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: pli.b a2, 51
-; RV64-NEXT: pslli.h a0, a0, 4
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: psrli.h a1, a0, 2
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: pli.b a2, 85
-; RV64-NEXT: pslli.h a0, a0, 2
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: psrli.h a1, a0, 1
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: pslli.h a0, a0, 1
-; RV64-NEXT: or a0, a1, a0
+; RV64-NEXT: rev a0, a0
+; RV64-NEXT: rev16 a0, a0
; RV64-NEXT: ret
%res = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %a)
ret <4 x i16> %res
@@ -4306,36 +4205,8 @@ define <2 x i32> @test_bitreverse_v2i32(<2 x i32> %a) {
;
; RV64-LABEL: test_bitreverse_v2i32:
; RV64: # %bb.0:
-; RV64-NEXT: psrli.w a1, a0, 8
-; RV64-NEXT: lui a2, 16
-; RV64-NEXT: psrli.w a3, a0, 24
-; RV64-NEXT: addi a2, a2, -256
-; RV64-NEXT: pmv.ws a2, a2
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: and a2, a0, a2
-; RV64-NEXT: pslli.w a0, a0, 24
-; RV64-NEXT: or a1, a1, a3
-; RV64-NEXT: pli.b a3, 15
-; RV64-NEXT: pslli.w a2, a2, 8
-; RV64-NEXT: or a0, a0, a2
-; RV64-NEXT: pli.b a2, 51
-; RV64-NEXT: or a0, a0, a1
-; RV64-NEXT: psrli.w a1, a0, 4
-; RV64-NEXT: and a0, a0, a3
-; RV64-NEXT: and a1, a1, a3
-; RV64-NEXT: pli.b a3, 85
-; RV64-NEXT: pslli.w a0, a0, 4
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: psrli.w a1, a0, 2
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: pslli.w a0, a0, 2
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: psrli.w a1, a0, 1
-; RV64-NEXT: and a0, a0, a3
-; RV64-NEXT: and a1, a1, a3
-; RV64-NEXT: pslli.w a0, a0, 1
-; RV64-NEXT: or a0, a1, a0
+; RV64-NEXT: rev a0, a0
+; RV64-NEXT: ppairoe.w a0, a0, a0
; RV64-NEXT: ret
%res = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
ret <2 x i32> %res
More information about the llvm-commits
mailing list