[llvm] [AMDGPU][GISel] Fold 'min(min(x,y),z)' and 'max(max(x,y),z)' into min3 and max3 (PR #200410)
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llvm-commits at lists.llvm.org
Thu Jun 4 07:41:33 PDT 2026
https://github.com/xiongzile updated https://github.com/llvm/llvm-project/pull/200410
>From 51b8b64dcacd1ea3ebfe73aec6d6388f8af8737e Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Fri, 29 May 2026 21:48:04 +0800
Subject: [PATCH 01/13] [AMDGPU][GISel] Fold 'min(min(x,y),z)' and
'max(max(x,y),z)' into min3 and max3.
---
llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 21 ++-
llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 6 +
.../AMDGPU/AMDGPUPreLegalizerCombiner.cpp | 59 ++++++
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 20 ++
llvm/lib/Target/AMDGPU/SIInstructions.td | 36 ++++
.../AMDGPU/GlobalISel/fmin3-fmax3-combine.ll | 71 ++++++++
.../AMDGPU/GlobalISel/min3-max3-combine.ll | 171 ++++++++++++++++++
7 files changed, 383 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index a2e6e6f448e8f..a20ed2a89029b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -157,6 +157,23 @@ def zext_of_shift_amount_combines : GICombineGroup<[
canonicalize_zext_lshr, canonicalize_zext_ashr, canonicalize_zext_shl
]>;
+def minmax3_matchdata : GIDefMatchData<"MinMaxToMinMax3MatchInfo">;
+
+class minmax_to_minmax3_opcodes<Instruction minmaxOpcode> : GICombineRule<
+ (defs root:$min_or_max, minmax3_matchdata:$matchinfo),
+ (match (minmaxOpcode $dst, $lhs, $rhs):$min_or_max,
+ [{ return matchMinMaxToMinMax3(*${min_or_max}, ${matchinfo}); }]),
+ (apply [{ applyMinMaxToMinMax3(*${min_or_max}, ${matchinfo}); }])>;
+
+def smax_to_minmax3 : minmax_to_minmax3_opcodes<G_SMAX>;
+def smin_to_minmax3 : minmax_to_minmax3_opcodes<G_SMIN>;
+def umax_to_minmax3 : minmax_to_minmax3_opcodes<G_UMAX>;
+def umin_to_minmax3 : minmax_to_minmax3_opcodes<G_UMIN>;
+def fmax_to_minmax3 : minmax_to_minmax3_opcodes<G_FMAXNUM>;
+def fmin_to_minmax3 : minmax_to_minmax3_opcodes<G_FMINNUM>;
+def fmax_ieee_to_minmax3 : minmax_to_minmax3_opcodes<G_FMAXNUM_IEEE>;
+def fmin_ieee_to_minmax3 : minmax_to_minmax3_opcodes<G_FMINNUM_IEEE>;
+
// (and/or i64:x, i64:y) -> i64:(merge (and/or lo_32(x), lo_32(y)), (and/or hi_32(x), hi_32(y)))
// when either x or y is all ones in low or high parts
class combine_binop_s64_with_s32_mask<Instruction opcode> : GICombineRule<
@@ -219,7 +236,9 @@ def AMDGPUPreLegalizerCombiner: GICombiner<
"AMDGPUPreLegalizerCombinerImpl",
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
foldable_fneg, combine_shuffle_vector, combine_shuffle_vector_to_build_vector,
- binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
+ binop_s64_with_s32_mask_combines, combine_or_s64_s32, smax_to_minmax3,
+ smin_to_minmax3, umax_to_minmax3, umin_to_minmax3, fmax_to_minmax3,
+ fmin_to_minmax3, fmax_ieee_to_minmax3, fmin_ieee_to_minmax3]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
index 51a8a476bbf7e..97957f5100067 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -271,6 +271,12 @@ def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>;
def : GINodeEquiv<G_AMDGPU_SMED3, AMDGPUsmed3>;
def : GINodeEquiv<G_AMDGPU_UMED3, AMDGPUumed3>;
def : GINodeEquiv<G_AMDGPU_FMED3, AMDGPUfmed3_impl>;
+def : GINodeEquiv<G_AMDGPU_SMAX3, AMDGPUsmax3>;
+def : GINodeEquiv<G_AMDGPU_UMAX3, AMDGPUumax3>;
+def : GINodeEquiv<G_AMDGPU_FMAX3, AMDGPUfmax3>;
+def : GINodeEquiv<G_AMDGPU_SMIN3, AMDGPUsmin3>;
+def : GINodeEquiv<G_AMDGPU_UMIN3, AMDGPUumin3>;
+def : GINodeEquiv<G_AMDGPU_FMIN3, AMDGPUfmin3>;
def : GINodeEquiv<G_AMDGPU_CLAMP, AMDGPUclamp>;
def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index 67c0bdd35f367..d1966893e18a2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -16,6 +16,7 @@
#include "AMDGPULegalizerInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
@@ -66,6 +67,11 @@ class AMDGPUPreLegalizerCombinerImpl : public Combiner {
Register Origin;
};
+ struct MinMaxToMinMax3MatchInfo {
+ unsigned Opc;
+ Register Val0, Val1, Val2;
+ };
+
bool matchClampI64ToI16(MachineInstr &MI, const MachineRegisterInfo &MRI,
const MachineFunction &MF,
ClampI64ToI16MatchInfo &MatchInfo) const;
@@ -73,6 +79,10 @@ class AMDGPUPreLegalizerCombinerImpl : public Combiner {
void applyClampI64ToI16(MachineInstr &MI,
const ClampI64ToI16MatchInfo &MatchInfo) const;
+ bool matchMinMaxToMinMax3(MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const;
+
+ void applyMinMaxToMinMax3(MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const;
+
private:
#define GET_GICOMBINER_CLASS_MEMBERS
#define AMDGPUSubtarget GCNSubtarget
@@ -106,6 +116,55 @@ bool AMDGPUPreLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
return false;
}
+void AMDGPUPreLegalizerCombinerImpl::applyMinMaxToMinMax3(
+ MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const {
+ B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
+ {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2}, MI.getFlags());
+ MI.eraseFromParent();
+ return;
+}
+
+bool AMDGPUPreLegalizerCombinerImpl::matchMinMaxToMinMax3(
+ MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const {
+ Register dst = MI.getOperand(0).getReg();
+ LLT t = MRI.getType(dst);
+ if (t == LLT::scalar(16)) {
+ if (!STI.hasMin3Max3_16()) {
+ return false;
+ }
+ } else if (t != LLT::scalar(32)) {
+ if (!(t.isVector() && t.getScalarSizeInBits() == 32))
+ return false;
+ }
+
+ Register R0, R1, R2;
+ unsigned opc = MI.getOpcode();
+ auto matchVOP3 = [&](MachineInstr &MI, MachineRegisterInfo &MRI, unsigned op,
+ Register &r0, Register &r1, Register &r2) {
+ auto p1 = m_BinOp(op, m_OneNonDBGUse(m_BinOp(op, m_Reg(r0), m_Reg(r1))),
+ m_Reg(r2));
+ auto p2 = m_BinOp(op, m_Reg(r0),
+ m_OneNonDBGUse(m_BinOp(op, m_Reg(r1), m_Reg(r2))));
+
+ return mi_match(MI, MRI, m_any_of(p1, p2));
+ };
+ if (!matchVOP3(MI, MRI, opc, R0, R1, R2)) {
+ return false;
+ }
+
+ llvm::SmallDenseMap<uint16_t, uint16_t, 8> mp = {
+ {AMDGPU::G_SMAX, AMDGPU::G_AMDGPU_SMAX3},
+ {AMDGPU::G_SMIN, AMDGPU::G_AMDGPU_SMIN3},
+ {AMDGPU::G_UMAX, AMDGPU::G_AMDGPU_UMAX3},
+ {AMDGPU::G_UMIN, AMDGPU::G_AMDGPU_UMIN3},
+ {AMDGPU::G_FMAXNUM, AMDGPU::G_AMDGPU_FMAX3},
+ {AMDGPU::G_FMAXNUM_IEEE, AMDGPU::G_AMDGPU_FMAX3},
+ {AMDGPU::G_FMINNUM, AMDGPU::G_AMDGPU_FMIN3},
+ {AMDGPU::G_FMINNUM_IEEE, AMDGPU::G_AMDGPU_FMIN3}};
+ MatchInfo = {mp.at(opc), R0, R1, R2};
+ return true;
+}
+
bool AMDGPUPreLegalizerCombinerImpl::matchClampI64ToI16(
MachineInstr &MI, const MachineRegisterInfo &MRI, const MachineFunction &MF,
ClampI64ToI16MatchInfo &MatchInfo) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index b7a4c6c9bd9ec..d67dab6e7cd1c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3972,6 +3972,26 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
return getInvalidInstructionMapping();
+ case AMDGPU::G_AMDGPU_SMAX3:
+ case AMDGPU::G_AMDGPU_SMIN3:
+ case AMDGPU::G_AMDGPU_UMAX3:
+ case AMDGPU::G_AMDGPU_UMIN3:
+ case AMDGPU::G_AMDGPU_FMAX3:
+ case AMDGPU::G_AMDGPU_FMIN3: {
+ unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+ assert(Size == 32);
+ auto op1 = getRegBankID(MI.getOperand(1).getReg(), MRI,
+ AMDGPU::VCCRegBankID);
+ auto op2 = getRegBankID(MI.getOperand(2).getReg(), MRI,
+ AMDGPU::VCCRegBankID);
+ auto op3 = getRegBankID(MI.getOperand(3).getReg(), MRI,
+ AMDGPU::VCCRegBankID);
+ OpdsMapping[0] = AMDGPU::getValueMapping(op1, Size);
+ OpdsMapping[1] = AMDGPU::getValueMapping(op1, Size);
+ OpdsMapping[2] = AMDGPU::getValueMapping(op2, Size);
+ OpdsMapping[3] = AMDGPU::getValueMapping(op3, Size);
+ break;
+ }
case AMDGPU::G_AND:
case AMDGPU::G_OR:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 4c351580ca5b6..96068037197d1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4720,6 +4720,42 @@ def G_AMDGPU_FMED3 : AMDGPUGenericInstruction {
let hasSideEffects = 0;
}
+def G_AMDGPU_SMIN3 : AMDGPUGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+def G_AMDGPU_UMIN3 : AMDGPUGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+def G_AMDGPU_FMIN3 : AMDGPUGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+def G_AMDGPU_SMAX3 : AMDGPUGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+def G_AMDGPU_UMAX3 : AMDGPUGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+def G_AMDGPU_FMAX3 : AMDGPUGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
def G_AMDGPU_CLAMP : AMDGPUGenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
new file mode 100644
index 0000000000000..0a6a63e5289c1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
+
+define float @test_fmin3(float %a, float %b, float %c) {
+; GFX10-LABEL: test_fmin3:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call float @llvm.minnum.f32(float %a, float %b)
+ %min2 = call float @llvm.minnum.f32(float %min1, float %c)
+ ret float %min2
+}
+
+define float @test_fmin3_nnan(float %a, float %b, float %c) {
+; GFX10-LABEL: test_fmin3_nnan:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call nnan float @llvm.minnum.f32(float %a, float %b)
+ %min2 = call nnan float @llvm.minnum.f32(float %min1, float %c)
+ ret float %min2
+}
+
+define float @test_fmin3_with_constants_nnan(float %a, float %b) {
+; GFX10-LABEL: test_fmin3_with_constants_nnan:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_f32 v0, v0, v1, 0x40e00000
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call nnan float @llvm.minnum.f32(float %a, float %b)
+ %min2 = call nnan float @llvm.minnum.f32(float %min1, float 7.0)
+ ret float %min2
+}
+
+define float @test_fmax3(float %a, float %b, float %c) {
+; GFX10-LABEL: test_fmax3:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call float @llvm.maxnum.f32(float %a, float %b)
+ %max2 = call float @llvm.maxnum.f32(float %max1, float %c)
+ ret float %max2
+}
+
+define float @test_fmax3_nnan(float %a, float %b, float %c) {
+; GFX10-LABEL: test_fmax3_nnan:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call nnan float @llvm.maxnum.f32(float %a, float %b)
+ %max2 = call nnan float @llvm.maxnum.f32(float %max1, float %c)
+ ret float %max2
+}
+
+define float @test_fmax3_with_constants_nnan(float %a, float %b) {
+; GFX10-LABEL: test_fmax3_with_constants_nnan:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_f32 v0, v0, v1, 0x40e00000
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call nnan float @llvm.maxnum.f32(float %a, float %b)
+ %max2 = call nnan float @llvm.maxnum.f32(float %max1, float 7.0)
+ ret float %max2
+}
+
+declare float @llvm.minnum.f32(float, float)
+declare float @llvm.maxnum.f32(float, float)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
new file mode 100644
index 0000000000000..e4165c090c399
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
@@ -0,0 +1,171 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
+
+define i32 @test_smin3(i32 %a, i32 %b, i32 %c) {
+; GFX10-LABEL: test_smin3:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_i32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ %min2 = call i32 @llvm.smin.i32(i32 %min1, i32 %c)
+ ret i32 %min2
+}
+
+define i32 @test_smin3_with_constants(i32 %a, i32 %b) {
+; GFX10-LABEL: test_smin3_with_constants:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_i32 v0, v0, v1, 7
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ %min2 = call i32 @llvm.smin.i32(i32 %min1, i32 7)
+ ret i32 %min2
+}
+
+define i32 @test_smin3_smin_umin(i32 %a, i32 %b) {
+; GFX10-LABEL: test_smin3_smin_umin:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX10-NEXT: v_min_u32_e32 v0, 7, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ %min2 = call i32 @llvm.umin.i32(i32 %min1, i32 7)
+ ret i32 %min2
+}
+
+define <2 x i16> @test_smin3_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
+; GFX10-LABEL: test_smin3_v2i16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_min_i16 v0, v0, v1
+; GFX10-NEXT: v_pk_min_i16 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call <2 x i16> @llvm.smin.v2i16(<2 x i16> %a, <2 x i16> %b)
+ %min2 = call <2 x i16> @llvm.smin.v2i16(<2 x i16> %min1, <2 x i16> %c)
+ ret <2 x i16> %min2
+}
+
+define i32 @test_smax3(i32 %a, i32 %b, i32 %c) {
+; GFX10-LABEL: test_smax3:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_i32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %max2 = call i32 @llvm.smax.i32(i32 %max1, i32 %c)
+ ret i32 %max2
+}
+
+define i32 @test_smax3_with_constants(i32 %a, i32 %b) {
+; GFX10-LABEL: test_smax3_with_constants:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_i32 v0, v0, v1, 7
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %min2 = call i32 @llvm.smax.i32(i32 %min1, i32 7)
+ ret i32 %min2
+}
+
+define i32 @test_smin3_smax_umax(i32 %a, i32 %b) {
+; GFX10-LABEL: test_smin3_smax_umax:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX10-NEXT: v_max_u32_e32 v0, 7, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ %min2 = call i32 @llvm.umax.i32(i32 %min1, i32 7)
+ ret i32 %min2
+}
+
+define <2 x i16> @test_smax3_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
+; GFX10-LABEL: test_smax3_v2i16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_max_i16 v0, v0, v1
+; GFX10-NEXT: v_pk_max_i16 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %a, <2 x i16> %b)
+ %max2 = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %max1, <2 x i16> %c)
+ ret <2 x i16> %max2
+}
+
+define i32 @test_umin3(i32 %a, i32 %b, i32 %c) {
+; GFX10-LABEL: test_umin3:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_u32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %min2 = call i32 @llvm.umin.i32(i32 %min1, i32 %c)
+ ret i32 %min2
+}
+
+define i32 @test_umin3_with_constants(i32 %a, i32 %b) {
+; GFX10-LABEL: test_umin3_with_constants:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_u32 v0, v0, v1, 7
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %min2 = call i32 @llvm.umin.i32(i32 %min1, i32 7)
+ ret i32 %min2
+}
+
+define <2 x i16> @test_umin3_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
+; GFX10-LABEL: test_umin3_v2i16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_min_u16 v0, v0, v1
+; GFX10-NEXT: v_pk_min_u16 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call <2 x i16> @llvm.umin.v2i16(<2 x i16> %a, <2 x i16> %b)
+ %min2 = call <2 x i16> @llvm.umin.v2i16(<2 x i16> %min1, <2 x i16> %c)
+ ret <2 x i16> %min2
+}
+
+define i32 @test_umax3(i32 %a, i32 %b, i32 %c) {
+; GFX10-LABEL: test_umax3:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %max2 = call i32 @llvm.umax.i32(i32 %max1, i32 %c)
+ ret i32 %max2
+}
+
+define i32 @test_umax3_with_constants(i32 %a, i32 %b) {
+; GFX10-LABEL: test_umax3_with_constants:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_u32 v0, v0, v1, 7
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %max2 = call i32 @llvm.umax.i32(i32 %max1, i32 7)
+ ret i32 %max2
+}
+
+define <2 x i16> @test_umax3_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
+; GFX10-LABEL: test_umax3_v2i16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_pk_max_u16 v0, v0, v1
+; GFX10-NEXT: v_pk_max_u16 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call <2 x i16> @llvm.umax.v2i16(<2 x i16> %a, <2 x i16> %b)
+ %max2 = call <2 x i16> @llvm.umax.v2i16(<2 x i16> %max1, <2 x i16> %c)
+ ret <2 x i16> %max2
+}
+
+declare i32 @llvm.smin.i32(i32, i32)
+declare i32 @llvm.umin.i32(i32, i32)
+declare i32 @llvm.smax.i32(i32, i32)
+declare i32 @llvm.umax.i32(i32, i32)
+declare <2 x i16> @llvm.smin.v2i16(<2 x i16>, <2 x i16>)
+declare <2 x i16> @llvm.umin.v2i16(<2 x i16>, <2 x i16>)
+declare <2 x i16> @llvm.smax.v2i16(<2 x i16>, <2 x i16>)
+declare <2 x i16> @llvm.umax.v2i16(<2 x i16>, <2 x i16>)
\ No newline at end of file
>From f0d07162faf2ca9f412982f6e9ec92b1139830fc Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Mon, 1 Jun 2026 22:31:56 +0800
Subject: [PATCH 02/13] opt in regcombine
---
llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 8 +-
.../AMDGPU/AMDGPUPreLegalizerCombiner.cpp | 59 ---
.../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 64 +++
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 20 -
.../AMDGPU/GlobalISel/fmin3-fmax3-combine.ll | 494 +++++++++++++++++-
5 files changed, 559 insertions(+), 86 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index a20ed2a89029b..f9b0e0956b13f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -236,9 +236,7 @@ def AMDGPUPreLegalizerCombiner: GICombiner<
"AMDGPUPreLegalizerCombinerImpl",
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
foldable_fneg, combine_shuffle_vector, combine_shuffle_vector_to_build_vector,
- binop_s64_with_s32_mask_combines, combine_or_s64_s32, smax_to_minmax3,
- smin_to_minmax3, umax_to_minmax3, umin_to_minmax3, fmax_to_minmax3,
- fmin_to_minmax3, fmax_ieee_to_minmax3, fmin_ieee_to_minmax3]> {
+ binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
@@ -258,5 +256,7 @@ def AMDGPURegBankCombiner : GICombiner<
fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp,
identity_combines, redundant_and, constant_fold_cast_op,
cast_of_cast_combines, sext_trunc, zext_of_shift_amount_combines,
- d16_load]> {
+ d16_load, smax_to_minmax3, smin_to_minmax3, umax_to_minmax3,
+ umin_to_minmax3, fmax_to_minmax3, fmin_to_minmax3, fmax_ieee_to_minmax3,
+ fmin_ieee_to_minmax3]> {
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index d1966893e18a2..67c0bdd35f367 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -16,7 +16,6 @@
#include "AMDGPULegalizerInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
-#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
@@ -67,11 +66,6 @@ class AMDGPUPreLegalizerCombinerImpl : public Combiner {
Register Origin;
};
- struct MinMaxToMinMax3MatchInfo {
- unsigned Opc;
- Register Val0, Val1, Val2;
- };
-
bool matchClampI64ToI16(MachineInstr &MI, const MachineRegisterInfo &MRI,
const MachineFunction &MF,
ClampI64ToI16MatchInfo &MatchInfo) const;
@@ -79,10 +73,6 @@ class AMDGPUPreLegalizerCombinerImpl : public Combiner {
void applyClampI64ToI16(MachineInstr &MI,
const ClampI64ToI16MatchInfo &MatchInfo) const;
- bool matchMinMaxToMinMax3(MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const;
-
- void applyMinMaxToMinMax3(MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const;
-
private:
#define GET_GICOMBINER_CLASS_MEMBERS
#define AMDGPUSubtarget GCNSubtarget
@@ -116,55 +106,6 @@ bool AMDGPUPreLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
return false;
}
-void AMDGPUPreLegalizerCombinerImpl::applyMinMaxToMinMax3(
- MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const {
- B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
- {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2}, MI.getFlags());
- MI.eraseFromParent();
- return;
-}
-
-bool AMDGPUPreLegalizerCombinerImpl::matchMinMaxToMinMax3(
- MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const {
- Register dst = MI.getOperand(0).getReg();
- LLT t = MRI.getType(dst);
- if (t == LLT::scalar(16)) {
- if (!STI.hasMin3Max3_16()) {
- return false;
- }
- } else if (t != LLT::scalar(32)) {
- if (!(t.isVector() && t.getScalarSizeInBits() == 32))
- return false;
- }
-
- Register R0, R1, R2;
- unsigned opc = MI.getOpcode();
- auto matchVOP3 = [&](MachineInstr &MI, MachineRegisterInfo &MRI, unsigned op,
- Register &r0, Register &r1, Register &r2) {
- auto p1 = m_BinOp(op, m_OneNonDBGUse(m_BinOp(op, m_Reg(r0), m_Reg(r1))),
- m_Reg(r2));
- auto p2 = m_BinOp(op, m_Reg(r0),
- m_OneNonDBGUse(m_BinOp(op, m_Reg(r1), m_Reg(r2))));
-
- return mi_match(MI, MRI, m_any_of(p1, p2));
- };
- if (!matchVOP3(MI, MRI, opc, R0, R1, R2)) {
- return false;
- }
-
- llvm::SmallDenseMap<uint16_t, uint16_t, 8> mp = {
- {AMDGPU::G_SMAX, AMDGPU::G_AMDGPU_SMAX3},
- {AMDGPU::G_SMIN, AMDGPU::G_AMDGPU_SMIN3},
- {AMDGPU::G_UMAX, AMDGPU::G_AMDGPU_UMAX3},
- {AMDGPU::G_UMIN, AMDGPU::G_AMDGPU_UMIN3},
- {AMDGPU::G_FMAXNUM, AMDGPU::G_AMDGPU_FMAX3},
- {AMDGPU::G_FMAXNUM_IEEE, AMDGPU::G_AMDGPU_FMAX3},
- {AMDGPU::G_FMINNUM, AMDGPU::G_AMDGPU_FMIN3},
- {AMDGPU::G_FMINNUM_IEEE, AMDGPU::G_AMDGPU_FMIN3}};
- MatchInfo = {mp.at(opc), R0, R1, R2};
- return true;
-}
-
bool AMDGPUPreLegalizerCombinerImpl::matchClampI64ToI16(
MachineInstr &MI, const MachineRegisterInfo &MRI, const MachineFunction &MF,
ClampI64ToI16MatchInfo &MatchInfo) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 35c0d4046f41e..9b9db0849e744 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -74,6 +74,11 @@ class AMDGPURegBankCombinerImpl : public Combiner {
Register Val0, Val1, Val2;
};
+ struct MinMaxToMinMax3MatchInfo {
+ unsigned Opc;
+ Register Val0, Val1, Val2;
+ };
+
MinMaxMedOpc getMinMaxPair(unsigned Opc) const;
template <class m_Cst, typename CstTy>
@@ -93,6 +98,9 @@ class AMDGPURegBankCombinerImpl : public Combiner {
bool applyD16Load(unsigned D16Opc, MachineInstr &DstMI,
MachineInstr *SmallLoad, Register ToOverwriteD16) const;
+ bool matchMinMaxToMinMax3(MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const;
+ void applyMinMaxToMinMax3(MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const;
+
private:
SIModeRegisterDefaults getMode() const;
bool getIEEE() const;
@@ -481,6 +489,62 @@ bool AMDGPURegBankCombinerImpl::combineD16Load(MachineInstr &MI) const {
return false;
}
+void AMDGPURegBankCombinerImpl::applyMinMaxToMinMax3(
+ MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const {
+ B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
+ {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2}, MI.getFlags());
+ MI.eraseFromParent();
+ return;
+}
+
+bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
+ MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const {
+ Register dst = MI.getOperand(0).getReg();
+ Register src1 = MI.getOperand(1).getReg();
+ Register src2 = MI.getOperand(2).getReg();
+ // if the register is SGPR, don't optimize it.
+ if (!(isVgprRegBank(dst) && isVgprRegBank(src1) && isVgprRegBank(src2))) {
+ return false;
+ }
+
+ LLT t = MRI.getType(dst);
+ if (t == LLT::scalar(16)) {
+ if (!STI.hasMin3Max3_16()) {
+ return false;
+ }
+ } else if (t != LLT::scalar(32)) {
+ if (!(t.isVector() && t.getScalarSizeInBits() == 32))
+ return false;
+ }
+
+ Register R0, R1, R2;
+ unsigned opc = MI.getOpcode();
+ auto matchMinOrMax3 = [&](MachineInstr &MI, MachineRegisterInfo &MRI, unsigned op,
+ Register &r0, Register &r1, Register &r2) {
+ auto p1 = m_BinOp(op, m_OneNonDBGUse(m_BinOp(op, m_Reg(r0), m_Reg(r1))),
+ m_Reg(r2));
+ auto p2 = m_BinOp(op, m_Reg(r0),
+ m_OneNonDBGUse(m_BinOp(op, m_Reg(r1), m_Reg(r2))));
+
+ return mi_match(MI, MRI, m_any_of(p1, p2));
+ };
+ if (!matchMinOrMax3(MI, MRI, opc, R0, R1, R2)) {
+ return false;
+ }
+
+ llvm::SmallDenseMap<uint16_t, uint16_t, 8> mp = {
+ {AMDGPU::G_SMAX, AMDGPU::G_AMDGPU_SMAX3},
+ {AMDGPU::G_SMIN, AMDGPU::G_AMDGPU_SMIN3},
+ {AMDGPU::G_UMAX, AMDGPU::G_AMDGPU_UMAX3},
+ {AMDGPU::G_UMIN, AMDGPU::G_AMDGPU_UMIN3},
+ {AMDGPU::G_FMAXNUM, AMDGPU::G_AMDGPU_FMAX3},
+ {AMDGPU::G_FMAXNUM_IEEE, AMDGPU::G_AMDGPU_FMAX3},
+ {AMDGPU::G_FMINNUM, AMDGPU::G_AMDGPU_FMIN3},
+ {AMDGPU::G_FMINNUM_IEEE, AMDGPU::G_AMDGPU_FMIN3}};
+ MatchInfo = {mp.at(opc), R0, R1, R2};
+ return true;
+}
+
bool AMDGPURegBankCombinerImpl::applyD16Load(
unsigned D16Opc, MachineInstr &DstMI, MachineInstr *SmallLoad,
Register SrcReg32ToOverwriteD16) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index d67dab6e7cd1c..b7a4c6c9bd9ec 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3972,26 +3972,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
return getInvalidInstructionMapping();
- case AMDGPU::G_AMDGPU_SMAX3:
- case AMDGPU::G_AMDGPU_SMIN3:
- case AMDGPU::G_AMDGPU_UMAX3:
- case AMDGPU::G_AMDGPU_UMIN3:
- case AMDGPU::G_AMDGPU_FMAX3:
- case AMDGPU::G_AMDGPU_FMIN3: {
- unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
- assert(Size == 32);
- auto op1 = getRegBankID(MI.getOperand(1).getReg(), MRI,
- AMDGPU::VCCRegBankID);
- auto op2 = getRegBankID(MI.getOperand(2).getReg(), MRI,
- AMDGPU::VCCRegBankID);
- auto op3 = getRegBankID(MI.getOperand(3).getReg(), MRI,
- AMDGPU::VCCRegBankID);
- OpdsMapping[0] = AMDGPU::getValueMapping(op1, Size);
- OpdsMapping[1] = AMDGPU::getValueMapping(op1, Size);
- OpdsMapping[2] = AMDGPU::getValueMapping(op2, Size);
- OpdsMapping[3] = AMDGPU::getValueMapping(op3, Size);
- break;
- }
case AMDGPU::G_AND:
case AMDGPU::G_OR:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
index 0a6a63e5289c1..959bb04100fa5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
@@ -1,12 +1,65 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
-
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
define float @test_fmin3(float %a, float %b, float %c) {
; GFX10-LABEL: test_fmin3:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min3_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call float @llvm.minnum.f32(float %a, float %b)
+ %min2 = call float @llvm.minnum.f32(float %min1, float %c)
+ ret float %min2
+}
+
+define float @test_fmin3_inreg(float inreg %a, float inreg %b, float inreg %c) {
+; GFX10-LABEL: test_fmin3_inreg:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e64 v0, s16, s16
+; GFX10-NEXT: v_max_f32_e64 v1, s17, s17
+; GFX10-NEXT: v_max_f32_e64 v2, s18, s18
+; GFX10-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_inreg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0
+; GFX12-NEXT: v_max_num_f32_e64 v1, s1, s1
+; GFX12-NEXT: v_max_num_f32_e64 v2, s2, s2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_min_num_f32 s0, s0, s2
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call float @llvm.minnum.f32(float %a, float %b)
%min2 = call float @llvm.minnum.f32(float %min1, float %c)
ret float %min2
@@ -18,17 +71,149 @@ define float @test_fmin3_nnan(float %a, float %b, float %c) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_nnan:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call nnan float @llvm.minnum.f32(float %a, float %b)
+ %min2 = call nnan float @llvm.minnum.f32(float %min1, float %c)
+ ret float %min2
+}
+
+define float @test_fmin3_nnan_inreg(float inreg %a, float inreg %b, float inreg %c) {
+; GFX10-LABEL: test_fmin3_nnan_inreg:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, s18
+; GFX10-NEXT: v_min3_f32 v0, s16, s17, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_nnan_inreg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: s_min_num_f32 s0, s0, s2
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call nnan float @llvm.minnum.f32(float %a, float %b)
%min2 = call nnan float @llvm.minnum.f32(float %min1, float %c)
ret float %min2
}
+define float @test_fmin3_with_constants(float %a, float %b) {
+; GFX10-LABEL: test_fmin3_with_constants:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT: v_min3_f32 v0, v0, v1, 0x40e00000
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_with_constants:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min3_num_f32 v0, v0, v1, 0x40e00000
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call float @llvm.minnum.f32(float %a, float %b)
+ %min2 = call float @llvm.minnum.f32(float %min1, float 7.0)
+ ret float %min2
+}
+
+define float @test_fmin3_with_constants_inreg(float inreg %a, float inreg %b) {
+; GFX10-LABEL: test_fmin3_with_constants_inreg:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e64 v0, s16, s16
+; GFX10-NEXT: v_max_f32_e64 v1, s17, s17
+; GFX10-NEXT: v_min3_f32 v0, v0, v1, 0x40e00000
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_with_constants_inreg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0
+; GFX12-NEXT: v_max_num_f32_e64 v1, s1, s1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: s_min_num_f32 s0, s0, 0x40e00000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call float @llvm.minnum.f32(float %a, float %b)
+ %min2 = call float @llvm.minnum.f32(float %min1, float 7.0)
+ ret float %min2
+}
+
define float @test_fmin3_with_constants_nnan(float %a, float %b) {
; GFX10-LABEL: test_fmin3_with_constants_nnan:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min3_f32 v0, v0, v1, 0x40e00000
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_with_constants_nnan:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_num_f32 v0, v0, v1, 0x40e00000
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call nnan float @llvm.minnum.f32(float %a, float %b)
+ %min2 = call nnan float @llvm.minnum.f32(float %min1, float 7.0)
+ ret float %min2
+}
+
+define float @test_fmin3_with_constants_nnan_inreg(float inreg %a, float inreg %b) {
+; GFX10-LABEL: test_fmin3_with_constants_nnan_inreg:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, 0x40e00000
+; GFX10-NEXT: v_min3_f32 v0, s16, s17, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_with_constants_nnan_inreg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: s_min_num_f32 s0, s0, 0x40e00000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call nnan float @llvm.minnum.f32(float %a, float %b)
%min2 = call nnan float @llvm.minnum.f32(float %min1, float 7.0)
ret float %min2
@@ -38,8 +223,61 @@ define float @test_fmax3(float %a, float %b, float %c) {
; GFX10-LABEL: test_fmax3:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call float @llvm.maxnum.f32(float %a, float %b)
+ %max2 = call float @llvm.maxnum.f32(float %max1, float %c)
+ ret float %max2
+}
+
+define float @test_fmax3_inreg(float inreg %a, float inreg %b, float inreg %c) {
+; GFX10-LABEL: test_fmax3_inreg:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e64 v0, s16, s16
+; GFX10-NEXT: v_max_f32_e64 v1, s17, s17
+; GFX10-NEXT: v_max_f32_e64 v2, s18, s18
+; GFX10-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_inreg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0
+; GFX12-NEXT: v_max_num_f32_e64 v1, s1, s1
+; GFX12-NEXT: v_max_num_f32_e64 v2, s2, s2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_max_num_f32 s0, s0, s2
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call float @llvm.maxnum.f32(float %a, float %b)
%max2 = call float @llvm.maxnum.f32(float %max1, float %c)
ret float %max2
@@ -51,21 +289,271 @@ define float @test_fmax3_nnan(float %a, float %b, float %c) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_nnan:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call nnan float @llvm.maxnum.f32(float %a, float %b)
%max2 = call nnan float @llvm.maxnum.f32(float %max1, float %c)
ret float %max2
}
+define float @test_fmax3_nnan_inreg(float inreg %a, float inreg %b, float inreg %c) {
+; GFX10-LABEL: test_fmax3_nnan_inreg:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, s18
+; GFX10-NEXT: v_max3_f32 v0, s16, s17, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_nnan_inreg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: s_max_num_f32 s0, s0, s2
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call nnan float @llvm.maxnum.f32(float %a, float %b)
+ %max2 = call nnan float @llvm.maxnum.f32(float %max1, float %c)
+ ret float %max2
+}
+
+define float @test_fmax3_with_constants(float %a, float %b) {
+; GFX10-LABEL: test_fmax3_with_constants:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT: v_max3_f32 v0, v0, v1, 0x40e00000
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_with_constants:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max3_num_f32 v0, v0, v1, 0x40e00000
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call float @llvm.maxnum.f32(float %a, float %b)
+ %max2 = call float @llvm.maxnum.f32(float %max1, float 7.0)
+ ret float %max2
+}
+
+define float @test_fmax3_with_constants_inreg(float inreg %a, float inreg %b) {
+; GFX10-LABEL: test_fmax3_with_constants_inreg:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e64 v0, s16, s16
+; GFX10-NEXT: v_max_f32_e64 v1, s17, s17
+; GFX10-NEXT: v_max3_f32 v0, v0, v1, 0x40e00000
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_with_constants_inreg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_num_f32_e64 v0, s0, s0
+; GFX12-NEXT: v_max_num_f32_e64 v1, s1, s1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: s_max_num_f32 s0, s0, 0x40e00000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call float @llvm.maxnum.f32(float %a, float %b)
+ %max2 = call float @llvm.maxnum.f32(float %max1, float 7.0)
+ ret float %max2
+}
+
define float @test_fmax3_with_constants_nnan(float %a, float %b) {
; GFX10-LABEL: test_fmax3_with_constants_nnan:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max3_f32 v0, v0, v1, 0x40e00000
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_with_constants_nnan:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_num_f32 v0, v0, v1, 0x40e00000
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call nnan float @llvm.maxnum.f32(float %a, float %b)
%max2 = call nnan float @llvm.maxnum.f32(float %max1, float 7.0)
ret float %max2
}
+define float @test_fmax3_with_constants_nnan_inreg(float inreg %a, float inreg %b) {
+; GFX10-LABEL: test_fmax3_with_constants_nnan_inreg:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, 0x40e00000
+; GFX10-NEXT: v_max3_f32 v0, s16, s17, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_with_constants_nnan_inreg:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_max_num_f32 s0, s0, s1
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-NEXT: s_max_num_f32 s0, s0, 0x40e00000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call nnan float @llvm.maxnum.f32(float %a, float %b)
+ %max2 = call nnan float @llvm.maxnum.f32(float %max1, float 7.0)
+ ret float %max2
+}
+
+define <2 x float> @test_fmin3_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
+; GFX10-LABEL: test_fmin3_v2f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX10-NEXT: v_max_f32_e32 v4, v4, v4
+; GFX10-NEXT: v_max_f32_e32 v5, v5, v5
+; GFX10-NEXT: v_min3_f32 v0, v0, v2, v4
+; GFX10-NEXT: v_min3_f32 v1, v1, v3, v5
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_v2f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
+; GFX12-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_min3_num_f32 v0, v0, v2, v4
+; GFX12-NEXT: v_min3_num_f32 v1, v1, v3, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b)
+ %min2 = call <2 x float> @llvm.minnum.v2f32(<2 x float> %min1, <2 x float> %c)
+ ret <2 x float> %min2
+}
+
+define <2 x float> @test_fmax3_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
+; GFX10-LABEL: test_fmax3_v2f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX10-NEXT: v_max_f32_e32 v4, v4, v4
+; GFX10-NEXT: v_max_f32_e32 v5, v5, v5
+; GFX10-NEXT: v_max3_f32 v0, v0, v2, v4
+; GFX10-NEXT: v_max3_f32 v1, v1, v3, v5
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_v2f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
+; GFX12-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_max3_num_f32 v0, v0, v2, v4
+; GFX12-NEXT: v_max3_num_f32 v1, v1, v3, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
+ %max2 = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %max1, <2 x float> %c)
+ ret <2 x float> %max2
+}
+
+define <2 x float> @test_fmin3_v2f32_nnan(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
+; GFX10-LABEL: test_fmin3_v2f32_nnan:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_f32 v0, v0, v2, v4
+; GFX10-NEXT: v_min3_f32 v1, v1, v3, v5
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmin3_v2f32_nnan:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_num_f32 v0, v0, v2, v4
+; GFX12-NEXT: v_min3_num_f32 v1, v1, v3, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %min1 = call nnan <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b)
+ %min2 = call nnan <2 x float> @llvm.minnum.v2f32(<2 x float> %min1, <2 x float> %c)
+ ret <2 x float> %min2
+}
+
+define <2 x float> @test_fmax3_v2f32_nnan(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
+; GFX10-LABEL: test_fmax3_v2f32_nnan:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_f32 v0, v0, v2, v4
+; GFX10-NEXT: v_max3_f32 v1, v1, v3, v5
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_fmax3_v2f32_nnan:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_num_f32 v0, v0, v2, v4
+; GFX12-NEXT: v_max3_num_f32 v1, v1, v3, v5
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %max1 = call nnan <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
+ %max2 = call nnan <2 x float> @llvm.maxnum.v2f32(<2 x float> %max1, <2 x float> %c)
+ ret <2 x float> %max2
+}
+
declare float @llvm.minnum.f32(float, float)
declare float @llvm.maxnum.f32(float, float)
+declare double @llvm.minnum.f64(double, double)
+declare double @llvm.maxnum.f64(double, double)
+declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
+declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
+declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
+declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
>From 01e1e9bf2ea26a454b4e9440f95b0cbb4ff8dc8c Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Wed, 3 Jun 2026 23:39:36 +0800
Subject: [PATCH 03/13] remove temporary map
---
.../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 34 +++++++++++++------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 9b9db0849e744..45738bdf7d7ac 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -532,16 +532,30 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
return false;
}
- llvm::SmallDenseMap<uint16_t, uint16_t, 8> mp = {
- {AMDGPU::G_SMAX, AMDGPU::G_AMDGPU_SMAX3},
- {AMDGPU::G_SMIN, AMDGPU::G_AMDGPU_SMIN3},
- {AMDGPU::G_UMAX, AMDGPU::G_AMDGPU_UMAX3},
- {AMDGPU::G_UMIN, AMDGPU::G_AMDGPU_UMIN3},
- {AMDGPU::G_FMAXNUM, AMDGPU::G_AMDGPU_FMAX3},
- {AMDGPU::G_FMAXNUM_IEEE, AMDGPU::G_AMDGPU_FMAX3},
- {AMDGPU::G_FMINNUM, AMDGPU::G_AMDGPU_FMIN3},
- {AMDGPU::G_FMINNUM_IEEE, AMDGPU::G_AMDGPU_FMIN3}};
- MatchInfo = {mp.at(opc), R0, R1, R2};
+ auto getAMDGPUOp = [](unsigned Opc) -> unsigned {
+ switch (Opc) {
+ case AMDGPU::G_SMAX:
+ return AMDGPU::G_AMDGPU_SMAX3;
+ case AMDGPU::G_SMIN:
+ return AMDGPU::G_AMDGPU_SMIN3;
+ case AMDGPU::G_UMAX:
+ return AMDGPU::G_AMDGPU_UMAX3;
+ case AMDGPU::G_UMIN:
+ return AMDGPU::G_AMDGPU_UMIN3;
+ case AMDGPU::G_FMAXNUM:
+ case AMDGPU::G_FMAXNUM_IEEE:
+ return AMDGPU::G_AMDGPU_FMAX3;
+ case AMDGPU::G_FMINNUM:
+ case AMDGPU::G_FMINNUM_IEEE:
+ return AMDGPU::G_AMDGPU_FMIN3;
+ default:
+ return 0;
+ }
+ };
+ unsigned amdgpuOpc = getAMDGPUOp(opc);
+ if (!amdgpuOpc)
+ return false;
+ MatchInfo = {getAMDGPUOp(opc), R0, R1, R2};
return true;
}
>From 69db292981486c9d3576b59ea93b88787ba4afd0 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Wed, 3 Jun 2026 23:41:25 +0800
Subject: [PATCH 04/13] demorgan condition
---
.../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 61 ++++++++++---------
1 file changed, 31 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 45738bdf7d7ac..6eab272c54e7c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -98,8 +98,10 @@ class AMDGPURegBankCombinerImpl : public Combiner {
bool applyD16Load(unsigned D16Opc, MachineInstr &DstMI,
MachineInstr *SmallLoad, Register ToOverwriteD16) const;
- bool matchMinMaxToMinMax3(MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const;
- void applyMinMaxToMinMax3(MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const;
+ bool matchMinMaxToMinMax3(MachineInstr &MI,
+ MinMaxToMinMax3MatchInfo &MatchInfo) const;
+ void applyMinMaxToMinMax3(MachineInstr &MI,
+ MinMaxToMinMax3MatchInfo &MatchInfo) const;
private:
SIModeRegisterDefaults getMode() const;
@@ -508,19 +510,18 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
}
LLT t = MRI.getType(dst);
- if (t == LLT::scalar(16)) {
- if (!STI.hasMin3Max3_16()) {
- return false;
- }
- } else if (t != LLT::scalar(32)) {
- if (!(t.isVector() && t.getScalarSizeInBits() == 32))
- return false;
- }
+ bool IsSupportedTy = t == LLT::scalar(32) ||
+ (t == LLT::scalar(16) && STI.hasMin3Max3_16()) ||
+ (t.isVector() && t.getScalarSizeInBits() == 32);
+
+ if (!IsSupportedTy)
+ return false;
Register R0, R1, R2;
unsigned opc = MI.getOpcode();
- auto matchMinOrMax3 = [&](MachineInstr &MI, MachineRegisterInfo &MRI, unsigned op,
- Register &r0, Register &r1, Register &r2) {
+ auto matchMinOrMax3 = [&](MachineInstr &MI, MachineRegisterInfo &MRI,
+ unsigned op, Register &r0, Register &r1,
+ Register &r2) {
auto p1 = m_BinOp(op, m_OneNonDBGUse(m_BinOp(op, m_Reg(r0), m_Reg(r1))),
m_Reg(r2));
auto p2 = m_BinOp(op, m_Reg(r0),
@@ -533,24 +534,24 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
}
auto getAMDGPUOp = [](unsigned Opc) -> unsigned {
- switch (Opc) {
- case AMDGPU::G_SMAX:
- return AMDGPU::G_AMDGPU_SMAX3;
- case AMDGPU::G_SMIN:
- return AMDGPU::G_AMDGPU_SMIN3;
- case AMDGPU::G_UMAX:
- return AMDGPU::G_AMDGPU_UMAX3;
- case AMDGPU::G_UMIN:
- return AMDGPU::G_AMDGPU_UMIN3;
- case AMDGPU::G_FMAXNUM:
- case AMDGPU::G_FMAXNUM_IEEE:
- return AMDGPU::G_AMDGPU_FMAX3;
- case AMDGPU::G_FMINNUM:
- case AMDGPU::G_FMINNUM_IEEE:
- return AMDGPU::G_AMDGPU_FMIN3;
- default:
- return 0;
- }
+ switch (Opc) {
+ case AMDGPU::G_SMAX:
+ return AMDGPU::G_AMDGPU_SMAX3;
+ case AMDGPU::G_SMIN:
+ return AMDGPU::G_AMDGPU_SMIN3;
+ case AMDGPU::G_UMAX:
+ return AMDGPU::G_AMDGPU_UMAX3;
+ case AMDGPU::G_UMIN:
+ return AMDGPU::G_AMDGPU_UMIN3;
+ case AMDGPU::G_FMAXNUM:
+ case AMDGPU::G_FMAXNUM_IEEE:
+ return AMDGPU::G_AMDGPU_FMAX3;
+ case AMDGPU::G_FMINNUM:
+ case AMDGPU::G_FMINNUM_IEEE:
+ return AMDGPU::G_AMDGPU_FMIN3;
+ default:
+ return 0;
+ }
};
unsigned amdgpuOpc = getAMDGPUOp(opc);
if (!amdgpuOpc)
>From 63e1aa1cace23e40900f716e9085fc3028e54a70 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 00:00:23 +0800
Subject: [PATCH 05/13] chore
---
llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
index e4165c090c399..855f904554986 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
@@ -168,4 +168,4 @@ declare i32 @llvm.umax.i32(i32, i32)
declare <2 x i16> @llvm.smin.v2i16(<2 x i16>, <2 x i16>)
declare <2 x i16> @llvm.umin.v2i16(<2 x i16>, <2 x i16>)
declare <2 x i16> @llvm.smax.v2i16(<2 x i16>, <2 x i16>)
-declare <2 x i16> @llvm.umax.v2i16(<2 x i16>, <2 x i16>)
\ No newline at end of file
+declare <2 x i16> @llvm.umax.v2i16(<2 x i16>, <2 x i16>)
>From d41cc5a525aea851ca3fc10b00fa2916f8b23c8f Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 00:24:31 +0800
Subject: [PATCH 06/13] vector test changes
---
.../test/CodeGen/AMDGPU/vector-reduce-fmax.ll | 1252 ++++++++---------
.../test/CodeGen/AMDGPU/vector-reduce-fmin.ll | 1252 ++++++++---------
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 915 +++++-------
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 915 +++++-------
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 904 +++++-------
.../test/CodeGen/AMDGPU/vector-reduce-umin.ll | 736 ++++------
6 files changed, 2523 insertions(+), 3451 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index 6b2be6b05b120..643e4daa913e3 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -276,9 +276,8 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v0, v0
; GFX9-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v2, v0
; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_f16 v0, v2, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmax_v3half:
@@ -297,8 +296,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v0, v0
; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v2, v0
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max3_f16 v0, v2, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -330,10 +328,9 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -344,9 +341,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v2
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v0, v0, v2, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -378,10 +373,9 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -392,9 +386,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v2
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -438,10 +430,9 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -456,9 +447,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v2
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v2, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fmax.v3half(<3 x half> %v)
@@ -542,13 +531,12 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmax_v4half:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f16_e32 v3, v1, v1
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v0, v0
; GFX9-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v2, v0
-; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v1, v1
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v2, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v3, v1
+; GFX9-GISEL-NEXT: v_max3_f16 v0, v2, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmax_v4half:
@@ -563,13 +551,12 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmax_v4half:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v0, v0
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v1, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v1, v1
; GFX10-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v2, v0
-; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v3, v1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v0, v0
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v2, v1
+; GFX10-GISEL-NEXT: v_max3_f16 v0, v3, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -597,32 +584,28 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v1.h, v1.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX11-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v2
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v0, v0, v3, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -650,32 +633,28 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v3
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -715,15 +694,13 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -733,18 +710,16 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v3
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v2
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v3, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fmax.v4half(<4 x half> %v)
@@ -884,20 +859,18 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmax_v8half:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f16_e32 v5, v1, v1
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v6, v3, v3
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v0, v0
; GFX9-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v4, v0
-; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v1, v1
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v4, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v2, v2
+; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v5, v1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v5, v2, v2
; GFX9-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v4, v2
-; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v3, v3
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v3, v4, v3
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_max_f16_e32 v3, v6, v3
+; GFX9-GISEL-NEXT: v_max3_f16 v0, v4, v0, v1
+; GFX9-GISEL-NEXT: v_max3_f16 v1, v5, v2, v3
; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -917,20 +890,18 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmax_v8half:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f16_e32 v4, v0, v0
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v5, v1, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v4, v1, v1
; GFX10-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v6, v2, v2
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v7, v3, v3
+; GFX10-GISEL-NEXT: v_max_f16_e32 v6, v3, v3
; GFX10-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v4, v0
-; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v5, v1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v6, v2
-; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v7, v3
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v2, v3
+; GFX10-GISEL-NEXT: v_max_f16_e32 v5, v0, v0
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v4, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v4, v2, v2
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v6, v3
+; GFX10-GISEL-NEXT: v_max3_f16 v0, v5, v0, v1
+; GFX10-GISEL-NEXT: v_max3_f16 v1, v4, v2, v3
; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -969,48 +940,44 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v1.h, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.l, v2.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v2.h, v2.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.l, v3.l, v3.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.h, v3.h, v3.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v3.l, v3.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v2.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.h, v2.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v3.l, v3.h
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.h, v1.h, v2.l, v2.h
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX11-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v4, v4, v4
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v6, v6, v6
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v3
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v7, v7, v7
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v4
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v4, v4, v4
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v5
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v6
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v6, v6
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v7
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v2, v3
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v0, v0, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v1, v2, v5, v3
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1049,48 +1016,44 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v2.l, v2.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v2.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v1.h, v2.l, v2.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v4
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v6, v6
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v3
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v4, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v5, v3
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1141,22 +1104,20 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v2.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v2.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v1.h, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1167,26 +1128,24 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v6
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v6, v6
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v4, v1
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v5, v3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -1438,37 +1397,32 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmax_v16half:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f16_e32 v9, v1, v1
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v10, v3, v3
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v11, v5, v5
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v5, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v12, v7, v7
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v7, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v0, v0
; GFX9-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v8, v0
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v1, v1
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v8, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v2, v2
+; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v9, v1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v9, v2, v2
; GFX9-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v8, v2
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v3, v3
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v3, v8, v3
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v4, v4
+; GFX9-GISEL-NEXT: v_max_f16_e32 v3, v10, v3
+; GFX9-GISEL-NEXT: v_max_f16_e32 v10, v4, v4
; GFX9-GISEL-NEXT: v_max_f16_sdwa v4, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v8, v4
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v5, v5
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v5, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v5, v8, v5
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v6, v6
+; GFX9-GISEL-NEXT: v_max_f16_e32 v5, v11, v5
+; GFX9-GISEL-NEXT: v_max_f16_e32 v11, v6, v6
; GFX9-GISEL-NEXT: v_max_f16_sdwa v6, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v6, v8, v6
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v7, v7
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v7, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v7, v8, v7
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v2, v3
-; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v4, v5
-; GFX9-GISEL-NEXT: v_max_f16_e32 v3, v6, v7
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v2, v3
-; GFX9-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v7, v12, v7
+; GFX9-GISEL-NEXT: v_max3_f16 v0, v8, v0, v1
+; GFX9-GISEL-NEXT: v_max3_f16 v1, v9, v2, v3
+; GFX9-GISEL-NEXT: v_max3_f16 v2, v10, v4, v5
+; GFX9-GISEL-NEXT: v_max3_f16 v3, v11, v6, v7
+; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max3_f16 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmax_v16half:
@@ -1496,37 +1450,32 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmax_v16half:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f16_e32 v8, v0, v0
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v9, v1, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v8, v1, v1
; GFX10-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v10, v2, v2
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v8, v0
-; GFX10-GISEL-NEXT: v_max_f16_e32 v8, v3, v3
-; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v9, v1
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v10, v2
-; GFX10-GISEL-NEXT: v_max_f16_e32 v9, v4, v4
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v4, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_max_f16_e32 v10, v5, v5
; GFX10-GISEL-NEXT: v_max_f16_sdwa v5, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v11, v6, v6
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v6, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_max_f16_e32 v12, v7, v7
; GFX10-GISEL-NEXT: v_max_f16_sdwa v7, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v8, v3
-; GFX10-GISEL-NEXT: v_max_f16_e32 v4, v9, v4
+; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v8, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v8, v3, v3
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v11, v4, v4
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v4, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_max_f16_e32 v5, v10, v5
-; GFX10-GISEL-NEXT: v_max_f16_e32 v6, v11, v6
+; GFX10-GISEL-NEXT: v_max_f16_e32 v10, v6, v6
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v6, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_max_f16_e32 v7, v12, v7
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v2, v3
+; GFX10-GISEL-NEXT: v_max_f16_e32 v9, v0, v0
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v12, v2, v2
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v8, v3
+; GFX10-GISEL-NEXT: v_max3_f16 v4, v11, v4, v5
+; GFX10-GISEL-NEXT: v_max3_f16 v5, v10, v6, v7
+; GFX10-GISEL-NEXT: v_max3_f16 v0, v9, v0, v1
+; GFX10-GISEL-NEXT: v_max3_f16 v1, v12, v2, v3
; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v4, v5
-; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v6, v7
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max3_f16 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1579,86 +1528,75 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v1.h, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.l, v2.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v2.h, v2.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v4.l, v4.l, v4.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v4.h, v4.h, v4.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v3.l, v3.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v3.h, v3.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v4.l, v4.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.l, v4.h, v4.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.l, v3.h, v3.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.h, v5.l, v5.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v4.l, v5.h, v5.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v4.h, v6.l, v6.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.l, v6.h, v6.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.l, v5.h, v5.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.h, v7.l, v7.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v6.l, v7.h, v7.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v1.h, v2.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.h, v3.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v3.h, v4.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.l, v4.h, v5.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.h, v5.h, v6.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v3.l, v3.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v7.l, v7.h, v7.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v2.h, v2.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.h, v3.h, v5.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.l, v6.l, v6.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v6.l, v6.h, v6.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.h, v5.h, v7.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v1.h, v3.l
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v3.l, v4.l, v4.h, v3.h
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v3.h, v5.l, v6.l, v5.h
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.h, v2.l, v2.h, v1.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v3.l, v3.h
+; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX11-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v8, v8, v8
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v9, v9, v9
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v10, v10, v10
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v8
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v5, v5
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v7, v7, v7
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v9
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v10
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v9, v11, v11
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v11, v13, v13
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v13, v15, v15
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v8, v11, v11
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v9, v12, v12
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v10, v13, v13
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v12, v12, v12
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v5, v11
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v6, v6, v6
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v11, v14, v14
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v7, v7, v7
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v12, v15, v15
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v8
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v4, v4, v9
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v5, v10
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v6, v6, v11
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v7, v7, v12
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v2, v3
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v4, v5
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v7, v7, v13
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v8, v8, v8
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v10, v10, v10
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v9
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v4, v4, v12, v5
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v5, v6, v11, v7
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v0, v0, v8, v1
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v6, v7
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v2, v3
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v1, v2, v10, v3
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v4, v5
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_max3_f16 v0, v0, v1, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1711,86 +1649,75 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v3.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.h, v4.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.h, v3.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.l, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v5.h, v5.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v6.l, v6.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.h, v6.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.h, v5.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v7.h, v7.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.h, v4.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.h, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.h, v6.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v7.l, v7.h, v7.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v5.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.l, v6.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.h, v6.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v5.h, v7.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v3.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.l, v4.l, v4.h, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.h, v5.l, v6.l, v5.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v2.l, v2.h, v1.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v3.l, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v9, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v8
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v10
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v11, v11
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v13, v13
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v13, v15, v15
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v11, v11
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v12, v12
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v13, v13
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v12, v12
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v11
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v14, v14
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v15, v15
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v8
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v10
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v11
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v12
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v4, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v13
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v9
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v4, v4, v12, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v5, v6, v11, v7
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v8, v1
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v6, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v10, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v4, v5
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v2
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1855,40 +1782,34 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v3.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.h, v4.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.h, v3.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.l, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v5.h, v5.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v6.l, v6.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.h, v6.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.h, v5.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v7.h, v7.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v3.h, v4.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.h, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.h, v6.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v7.l, v7.h, v7.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v5.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.l, v6.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.h, v6.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v5.h, v7.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v3.l
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.l, v4.l, v4.h, v3.h
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v3.h, v5.l, v6.l, v5.h
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v2.l, v2.h, v1.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1898,47 +1819,42 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v9, v9
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v8
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v9
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v10
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v11, v11
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v13, v13
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v13, v15, v15
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v11, v11
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v12, v12
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v13, v13
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v12, v12
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v11
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v14, v14
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v15, v15
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v8
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v9
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v10
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v11
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v12
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v4, v5
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v13
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v9
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v4, v4, v12, v5
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v5, v6, v11, v7
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v8, v1
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v6, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v1, v2, v10, v3
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v4, v5
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_max3_num_f16 v0, v0, v1, v2
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fmax.v16half(<16 x half> %v)
@@ -2082,9 +1998,8 @@ define float @test_vector_reduce_fmax_v3float(<3 x float> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX7-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_fmax_v3float:
@@ -2098,9 +2013,8 @@ define float @test_vector_reduce_fmax_v3float(<3 x float> %v) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_fmax_v3float:
@@ -2114,9 +2028,8 @@ define float @test_vector_reduce_fmax_v3float(<3 x float> %v) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmax_v3float:
@@ -2130,9 +2043,8 @@ define float @test_vector_reduce_fmax_v3float(<3 x float> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX10-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_fmax_v3float:
@@ -2145,9 +2057,9 @@ define float @test_vector_reduce_fmax_v3float(<3 x float> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v2
-; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v3float:
@@ -2160,9 +2072,9 @@ define float @test_vector_reduce_fmax_v3float(<3 x float> %v) {
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v2
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v3float:
@@ -2183,9 +2095,9 @@ define float @test_vector_reduce_fmax_v3float(<3 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmax.v3float(<3 x float> %v)
@@ -2205,13 +2117,12 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_fmax_v4float:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX7-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_fmax_v4float:
@@ -2226,13 +2137,12 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_fmax_v4float:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_fmax_v4float:
@@ -2247,13 +2157,12 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmax_v4float:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v3, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmax_v4float:
@@ -2268,13 +2177,12 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmax_v4float:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX10-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_fmax_v4float:
@@ -2289,11 +2197,11 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_fmax_v4float:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v4float:
@@ -2308,11 +2216,11 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v4float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v3
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v4float:
@@ -2335,11 +2243,11 @@ define float @test_vector_reduce_fmax_v4float(<4 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v3
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmax.v4float(<4 x float> %v)
@@ -2361,20 +2269,18 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_fmax_v8float:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX7-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v5
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v6
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v7
; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX7-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
-; GFX7-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v6
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; GFX7-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX7-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX7-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX7-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2392,20 +2298,18 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_fmax_v8float:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v7
; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
-; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v6
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; GFX8-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX8-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX8-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2423,20 +2327,18 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmax_v8float:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v5, v5
+; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v6, v6
+; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v7, v7
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v3, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v4, v4
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v5, v5
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v6, v6
-; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v7, v7
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX9-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX9-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2454,20 +2356,18 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmax_v8float:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v4, v4
-; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v5, v5
; GFX10-GISEL-NEXT: v_max_f32_e32 v6, v6, v6
; GFX10-GISEL-NEXT: v_max_f32_e32 v7, v7, v7
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v4, v5
-; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v6, v7
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v5, v5
+; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v6, v7
+; GFX10-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX10-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2486,15 +2386,16 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_fmax_v8float:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v5, v5, v5
-; GFX11-GISEL-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_max_f32 v7, v7, v7
+; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v7, v7, v7
+; GFX11-GISEL-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_max_f32 v1, v1, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v4, v5 :: v_dual_max_f32 v3, v6, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4
+; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v5, v5 :: v_dual_max_f32 v5, v6, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX11-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2513,15 +2414,16 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v8float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v4, v5 :: v_dual_max_num_f32 v3, v6, v7
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v3
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_max_num_f32 v5, v6, v7
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v1, v3, v4, v5
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2548,15 +2450,16 @@ define float @test_vector_reduce_fmax_v8float(<8 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v4, v5 :: v_dual_max_num_f32 v3, v6, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v3
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_max_num_f32 v5, v6, v7
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX12-GISEL-NEXT: v_max3_num_f32 v1, v3, v4, v5
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2583,37 +2486,32 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_fmax_v16float:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX7-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v5
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v6
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v7
+; GFX7-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v8
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v9
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v8, 1.0, v10
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v9, 1.0, v11
+; GFX7-GISEL-NEXT: v_max_f32_e32 v8, v8, v9
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v9, 1.0, v12
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v11, 1.0, v14
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v12, 1.0, v15
; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX7-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v10, 1.0, v13
+; GFX7-GISEL-NEXT: v_max_f32_e32 v11, v11, v12
+; GFX7-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX7-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
+; GFX7-GISEL-NEXT: v_max3_f32 v2, v6, v7, v8
+; GFX7-GISEL-NEXT: v_max3_f32 v3, v9, v10, v11
; GFX7-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v6
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; GFX7-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v8
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v9
-; GFX7-GISEL-NEXT: v_max_f32_e32 v4, v4, v5
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v10
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v11
-; GFX7-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v12
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v13
-; GFX7-GISEL-NEXT: v_max_f32_e32 v6, v6, v7
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v14
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v8, 1.0, v15
-; GFX7-GISEL-NEXT: v_max_f32_e32 v7, v7, v8
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX7-GISEL-NEXT: v_max_f32_e32 v2, v4, v5
-; GFX7-GISEL-NEXT: v_max_f32_e32 v3, v6, v7
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX7-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_fmax_v16float:
@@ -2634,37 +2532,32 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_fmax_v16float:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v7
+; GFX8-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v8
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v9
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v8, 1.0, v10
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v9, 1.0, v11
+; GFX8-GISEL-NEXT: v_max_f32_e32 v8, v8, v9
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v9, 1.0, v12
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v11, 1.0, v14
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v12, 1.0, v15
; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v10, 1.0, v13
+; GFX8-GISEL-NEXT: v_max_f32_e32 v11, v11, v12
+; GFX8-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX8-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
+; GFX8-GISEL-NEXT: v_max3_f32 v2, v6, v7, v8
+; GFX8-GISEL-NEXT: v_max3_f32 v3, v9, v10, v11
; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v6
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; GFX8-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v8
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v9
-; GFX8-GISEL-NEXT: v_max_f32_e32 v4, v4, v5
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v10
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v11
-; GFX8-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v12
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v13
-; GFX8-GISEL-NEXT: v_max_f32_e32 v6, v6, v7
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v14
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v8, 1.0, v15
-; GFX8-GISEL-NEXT: v_max_f32_e32 v7, v7, v8
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX8-GISEL-NEXT: v_max_f32_e32 v2, v4, v5
-; GFX8-GISEL-NEXT: v_max_f32_e32 v3, v6, v7
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX8-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_fmax_v16float:
@@ -2685,37 +2578,32 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmax_v16float:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v5, v5
+; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v6, v6
+; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v7, v7
+; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
+; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v8, v8
+; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v9, v9
+; GFX9-GISEL-NEXT: v_max_f32_e32 v8, v10, v10
+; GFX9-GISEL-NEXT: v_max_f32_e32 v9, v11, v11
+; GFX9-GISEL-NEXT: v_max_f32_e32 v8, v8, v9
+; GFX9-GISEL-NEXT: v_max_f32_e32 v9, v12, v12
+; GFX9-GISEL-NEXT: v_max_f32_e32 v11, v14, v14
+; GFX9-GISEL-NEXT: v_max_f32_e32 v12, v15, v15
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v3, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v4, v4
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v5, v5
+; GFX9-GISEL-NEXT: v_max_f32_e32 v10, v13, v13
+; GFX9-GISEL-NEXT: v_max_f32_e32 v11, v11, v12
+; GFX9-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX9-GISEL-NEXT: v_max3_f32 v1, v3, v4, v5
+; GFX9-GISEL-NEXT: v_max3_f32 v2, v6, v7, v8
+; GFX9-GISEL-NEXT: v_max3_f32 v3, v9, v10, v11
; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v6, v6
-; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v7, v7
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
-; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v8, v8
-; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v9, v9
-; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v4, v5
-; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v10, v10
-; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v11, v11
-; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v5, v6
-; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v12, v12
-; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v13, v13
-; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v6, v7
-; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v14, v14
-; GFX9-GISEL-NEXT: v_max_f32_e32 v8, v15, v15
-; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v7, v8
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v4, v5
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v6, v7
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmax_v16float:
@@ -2736,37 +2624,32 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmax_v16float:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v4, v4
-; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v5, v5
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
+; GFX10-GISEL-NEXT: v_max_f32_e32 v8, v8, v8
+; GFX10-GISEL-NEXT: v_max_f32_e32 v9, v9, v9
+; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v3
; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v6, v6
-; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v4, v5
-; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v7, v7
-; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v8, v8
-; GFX10-GISEL-NEXT: v_max_f32_e32 v6, v9, v9
+; GFX10-GISEL-NEXT: v_max_f32_e32 v6, v7, v7
; GFX10-GISEL-NEXT: v_max_f32_e32 v7, v10, v10
-; GFX10-GISEL-NEXT: v_max_f32_e32 v8, v11, v11
-; GFX10-GISEL-NEXT: v_max_f32_e32 v9, v12, v12
-; GFX10-GISEL-NEXT: v_max_f32_e32 v10, v13, v13
+; GFX10-GISEL-NEXT: v_max_f32_e32 v10, v11, v11
; GFX10-GISEL-NEXT: v_max_f32_e32 v11, v14, v14
-; GFX10-GISEL-NEXT: v_max_f32_e32 v12, v15, v15
-; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v3, v4
-; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v5, v6
-; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v7, v8
-; GFX10-GISEL-NEXT: v_max_f32_e32 v6, v9, v10
-; GFX10-GISEL-NEXT: v_max_f32_e32 v7, v11, v12
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v4, v5
-; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v6, v7
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v14, v15, v15
+; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v4, v4
+; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v5, v5
+; GFX10-GISEL-NEXT: v_max_f32_e32 v7, v7, v10
+; GFX10-GISEL-NEXT: v_max_f32_e32 v10, v12, v12
+; GFX10-GISEL-NEXT: v_max_f32_e32 v12, v13, v13
+; GFX10-GISEL-NEXT: v_max_f32_e32 v11, v11, v14
+; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v3, v6
+; GFX10-GISEL-NEXT: v_max3_f32 v6, v8, v9, v7
+; GFX10-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX10-GISEL-NEXT: v_max3_f32 v7, v10, v12, v11
+; GFX10-GISEL-NEXT: v_max3_f32 v1, v4, v5, v3
+; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v6, v7
+; GFX10-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_fmax_v16float:
@@ -2790,28 +2673,27 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_fmax_v16float:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v5, v5, v5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v6, v6 :: v_dual_max_f32 v2, v4, v5
-; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v7, v7 :: v_dual_max_f32 v5, v8, v8
-; GFX11-GISEL-NEXT: v_dual_max_f32 v6, v9, v9 :: v_dual_max_f32 v7, v10, v10
-; GFX11-GISEL-NEXT: v_dual_max_f32 v8, v11, v11 :: v_dual_max_f32 v9, v12, v12
-; GFX11-GISEL-NEXT: v_dual_max_f32 v10, v13, v13 :: v_dual_max_f32 v11, v14, v14
-; GFX11-GISEL-NEXT: v_max_f32_e32 v12, v15, v15
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v3, v4 :: v_dual_max_f32 v4, v5, v6
-; GFX11-GISEL-NEXT: v_dual_max_f32 v5, v7, v8 :: v_dual_max_f32 v6, v9, v10
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v7, v11, v12 :: v_dual_max_f32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_dual_max_f32 v1, v2, v3 :: v_dual_max_f32 v2, v4, v5
+; GFX11-GISEL-NEXT: v_max_f32_e32 v8, v8, v8
+; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v2, v2, v3
+; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v6, v6 :: v_dual_max_f32 v6, v7, v7
+; GFX11-GISEL-NEXT: v_dual_max_f32 v7, v10, v10 :: v_dual_max_f32 v10, v11, v11
+; GFX11-GISEL-NEXT: v_dual_max_f32 v11, v14, v14 :: v_dual_max_f32 v14, v15, v15
+; GFX11-GISEL-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4
+; GFX11-GISEL-NEXT: v_max_f32_e32 v3, v3, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_dual_max_f32 v7, v7, v10 :: v_dual_max_f32 v10, v12, v12
+; GFX11-GISEL-NEXT: v_dual_max_f32 v12, v13, v13 :: v_dual_max_f32 v11, v11, v14
+; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_max3_f32 v6, v8, v9, v7
+; GFX11-GISEL-NEXT: v_max3_f32 v1, v4, v5, v3
+; GFX11-GISEL-NEXT: v_max3_f32 v7, v10, v12, v11
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v6, v7 :: v_dual_max_f32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_max_f32_e32 v1, v2, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v6, v7
+; GFX11-GISEL-NEXT: v_max3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fmax_v16float:
@@ -2835,28 +2717,27 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX1170-GISEL-LABEL: test_vector_reduce_fmax_v16float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v2, v4, v5
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v7, v7 :: v_dual_max_num_f32 v5, v8, v8
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v9, v9 :: v_dual_max_num_f32 v7, v10, v10
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v8, v11, v11 :: v_dual_max_num_f32 v9, v12, v12
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v10, v13, v13 :: v_dual_max_num_f32 v11, v14, v14
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v12, v15, v15
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v3, v4 :: v_dual_max_num_f32 v4, v5, v6
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v5, v7, v8 :: v_dual_max_num_f32 v6, v9, v10
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v11, v12 :: v_dual_max_num_f32 v0, v0, v1
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v1, v2, v3 :: v_dual_max_num_f32 v2, v4, v5
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_max_num_f32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v3, v3, v6
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_max_num_f32 v11, v11, v14
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v6, v8, v9, v7
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v1, v4, v5, v3
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v7, v10, v12, v11
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v7 :: v_dual_max_num_f32 v0, v0, v1
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v1, v2, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v6, v7
+; GFX1170-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v16float:
@@ -2888,28 +2769,27 @@ define float @test_vector_reduce_fmax_v16float(<16 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v2, v4, v5
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v7, v7 :: v_dual_max_num_f32 v5, v8, v8
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v9, v9 :: v_dual_max_num_f32 v7, v10, v10
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v8, v11, v11 :: v_dual_max_num_f32 v9, v12, v12
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v10, v13, v13 :: v_dual_max_num_f32 v11, v14, v14
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v12, v15, v15
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v3, v3, v4 :: v_dual_max_num_f32 v4, v5, v6
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v5, v7, v8 :: v_dual_max_num_f32 v6, v9, v10
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v7, v11, v12 :: v_dual_max_num_f32 v0, v0, v1
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v1, v2, v3 :: v_dual_max_num_f32 v2, v4, v5
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_max_num_f32 v2, v2, v3
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v3, v3, v6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_max_num_f32 v11, v11, v14
+; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_max3_num_f32 v6, v8, v9, v7
+; GFX12-GISEL-NEXT: v_max3_num_f32 v1, v4, v5, v3
+; GFX12-GISEL-NEXT: v_max3_num_f32 v7, v10, v12, v11
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v7 :: v_dual_max_num_f32 v0, v0, v1
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v1, v2, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v6, v7
+; GFX12-GISEL-NEXT: v_max3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmax.v16float(<16 x float> %v)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index efb210d6f07f1..c574bf0fbe86e 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -276,9 +276,8 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v0, v0
; GFX9-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v2, v0
; GFX9-GISEL-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_f16 v0, v2, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmin_v3half:
@@ -297,8 +296,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v0, v0
; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v2, v0
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_f16 v0, v2, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -330,10 +328,9 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -344,9 +341,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v2
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v0, v0, v2, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -378,10 +373,9 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -392,9 +386,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v2
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -438,10 +430,9 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -456,9 +447,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v2
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v2, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fmin.v3half(<3 x half> %v)
@@ -542,13 +531,12 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmin_v4half:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f16_e32 v3, v1, v1
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v0, v0
; GFX9-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v2, v0
-; GFX9-GISEL-NEXT: v_max_f16_e32 v2, v1, v1
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v2, v1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v3, v1
+; GFX9-GISEL-NEXT: v_min3_f16 v0, v2, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmin_v4half:
@@ -563,13 +551,12 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmin_v4half:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v0, v0
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v1, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v2, v1, v1
; GFX10-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v2, v0
-; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v3, v1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v3, v0, v0
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v2, v1
+; GFX10-GISEL-NEXT: v_min3_f16 v0, v3, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -597,32 +584,28 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v1.h, v1.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX11-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v2
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v1, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v1, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v0, v0, v3, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -650,32 +633,28 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v3
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -715,15 +694,13 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -733,18 +710,16 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v2
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v3
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v2
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v3, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fmin.v4half(<4 x half> %v)
@@ -884,20 +859,18 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmin_v8half:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f16_e32 v5, v1, v1
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v6, v3, v3
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v0, v0
; GFX9-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v4, v0
-; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v1, v1
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v4, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v2, v2
+; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v5, v1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v5, v2, v2
; GFX9-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v2, v4, v2
-; GFX9-GISEL-NEXT: v_max_f16_e32 v4, v3, v3
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v3, v4, v3
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_min_f16_e32 v3, v6, v3
+; GFX9-GISEL-NEXT: v_min3_f16 v0, v4, v0, v1
+; GFX9-GISEL-NEXT: v_min3_f16 v1, v5, v2, v3
; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -917,20 +890,18 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmin_v8half:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f16_e32 v4, v0, v0
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v5, v1, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v4, v1, v1
; GFX10-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v6, v2, v2
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v7, v3, v3
+; GFX10-GISEL-NEXT: v_max_f16_e32 v6, v3, v3
; GFX10-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v4, v0
-; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v5, v1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v2, v6, v2
-; GFX10-GISEL-NEXT: v_min_f16_e32 v3, v7, v3
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v2, v3
+; GFX10-GISEL-NEXT: v_max_f16_e32 v5, v0, v0
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v4, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v4, v2, v2
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_min_f16_e32 v3, v6, v3
+; GFX10-GISEL-NEXT: v_min3_f16 v0, v5, v0, v1
+; GFX10-GISEL-NEXT: v_min3_f16 v1, v4, v2, v3
; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -969,48 +940,44 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v1.h, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.l, v2.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v2.h, v2.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.l, v3.l, v3.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.h, v3.h, v3.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v2.l, v2.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.h, v3.l, v3.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v2.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.h, v2.h
+; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v2.h, v3.l, v3.h
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.h, v1.h, v2.l, v2.h
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX11-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v4, v4, v4
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v6, v6, v6
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v3
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v7, v7, v7
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v4
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v4, v4, v4
; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v1, v1, v5
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v2, v2, v6
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v6, v6
; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v3, v3, v7
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v1, v2, v3
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v0, v0, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v1, v2, v5, v3
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1049,48 +1016,44 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v2.l, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v2.l, v2.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v2.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v1.h, v2.l, v2.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v4
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v6, v6
; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v2, v3
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v4, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v5, v3
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1141,22 +1104,20 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.l, v3.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v3.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v2.l, v2.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v2.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.h, v2.h
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v1.h, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1167,26 +1128,24 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v5
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v6
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v6, v6
; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v7
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v4, v1
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v5, v3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -1438,37 +1397,32 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmin_v16half:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f16_e32 v9, v1, v1
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v10, v3, v3
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v11, v5, v5
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v5, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v12, v7, v7
+; GFX9-GISEL-NEXT: v_max_f16_sdwa v7, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v0, v0
; GFX9-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v8, v0
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v1, v1
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v8, v1
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v2, v2
+; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v9, v1
+; GFX9-GISEL-NEXT: v_max_f16_e32 v9, v2, v2
; GFX9-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v2, v8, v2
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v3, v3
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v3, v8, v3
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v4, v4
+; GFX9-GISEL-NEXT: v_min_f16_e32 v3, v10, v3
+; GFX9-GISEL-NEXT: v_max_f16_e32 v10, v4, v4
; GFX9-GISEL-NEXT: v_max_f16_sdwa v4, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v4, v8, v4
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v5, v5
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v5, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v5, v8, v5
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v6, v6
+; GFX9-GISEL-NEXT: v_min_f16_e32 v5, v11, v5
+; GFX9-GISEL-NEXT: v_max_f16_e32 v11, v6, v6
; GFX9-GISEL-NEXT: v_max_f16_sdwa v6, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v6, v8, v6
-; GFX9-GISEL-NEXT: v_max_f16_e32 v8, v7, v7
-; GFX9-GISEL-NEXT: v_max_f16_sdwa v7, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v7, v8, v7
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v2, v3
-; GFX9-GISEL-NEXT: v_min_f16_e32 v2, v4, v5
-; GFX9-GISEL-NEXT: v_min_f16_e32 v3, v6, v7
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_min_f16_e32 v1, v2, v3
-; GFX9-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min_f16_e32 v7, v12, v7
+; GFX9-GISEL-NEXT: v_min3_f16 v0, v8, v0, v1
+; GFX9-GISEL-NEXT: v_min3_f16 v1, v9, v2, v3
+; GFX9-GISEL-NEXT: v_min3_f16 v2, v10, v4, v5
+; GFX9-GISEL-NEXT: v_min3_f16 v3, v11, v6, v7
+; GFX9-GISEL-NEXT: v_min_f16_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_min3_f16 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmin_v16half:
@@ -1496,37 +1450,32 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmin_v16half:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f16_e32 v8, v0, v0
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v9, v1, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v8, v1, v1
; GFX10-GISEL-NEXT: v_max_f16_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v10, v2, v2
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v8, v0
-; GFX10-GISEL-NEXT: v_max_f16_e32 v8, v3, v3
-; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v9, v1
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v2, v10, v2
-; GFX10-GISEL-NEXT: v_max_f16_e32 v9, v4, v4
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v4, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_max_f16_e32 v10, v5, v5
; GFX10-GISEL-NEXT: v_max_f16_sdwa v5, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_max_f16_e32 v11, v6, v6
-; GFX10-GISEL-NEXT: v_max_f16_sdwa v6, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_max_f16_e32 v12, v7, v7
; GFX10-GISEL-NEXT: v_max_f16_sdwa v7, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v3, v8, v3
-; GFX10-GISEL-NEXT: v_min_f16_e32 v4, v9, v4
+; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v8, v1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v8, v3, v3
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v11, v4, v4
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v4, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_min_f16_e32 v5, v10, v5
-; GFX10-GISEL-NEXT: v_min_f16_e32 v6, v11, v6
+; GFX10-GISEL-NEXT: v_max_f16_e32 v10, v6, v6
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v6, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX10-GISEL-NEXT: v_min_f16_e32 v7, v12, v7
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v2, v3
+; GFX10-GISEL-NEXT: v_max_f16_e32 v9, v0, v0
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_max_f16_e32 v12, v2, v2
+; GFX10-GISEL-NEXT: v_max_f16_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_min_f16_e32 v3, v8, v3
+; GFX10-GISEL-NEXT: v_min3_f16 v4, v11, v4, v5
+; GFX10-GISEL-NEXT: v_min3_f16 v5, v10, v6, v7
+; GFX10-GISEL-NEXT: v_min3_f16 v0, v9, v0, v1
+; GFX10-GISEL-NEXT: v_min3_f16 v1, v12, v2, v3
; GFX10-GISEL-NEXT: v_min_f16_e32 v2, v4, v5
-; GFX10-GISEL-NEXT: v_min_f16_e32 v3, v6, v7
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f16_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_f16 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1579,86 +1528,75 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v1.h, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.l, v2.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v2.h, v2.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v4.l, v4.l, v4.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v4.h, v4.h, v4.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v1.l, v1.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.h, v3.l, v3.l
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v2.l, v2.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v3.h, v3.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v4.l, v4.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.l, v4.h, v4.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.l, v3.h, v3.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v3.h, v5.l, v5.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v4.l, v5.h, v5.h
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v4.h, v6.l, v6.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.l, v6.h, v6.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.l, v5.h, v5.h
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.h, v7.l, v7.l
-; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v6.l, v7.h, v7.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.h, v1.h, v2.l
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v2.l, v2.h, v3.l
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v2.h, v3.h, v4.l
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v3.l, v4.h, v5.l
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v3.h, v5.h, v6.l
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v2.l, v2.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.h, v3.l, v3.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v7.l, v7.h, v7.h
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.l, v2.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v2.h, v2.h, v2.h
+; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v3.h, v3.h, v5.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v5.l, v6.l, v6.l
+; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v6.l, v6.h, v6.h
+; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v5.h, v5.h, v7.l
+; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.h, v1.h, v3.l
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v3.l, v4.l, v4.h, v3.h
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v3.h, v5.l, v6.l, v5.h
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.h, v2.l, v2.h, v1.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v3.l, v3.h
+; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX11-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v8, v8, v8
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v9, v9, v9
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v10, v10, v10
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v8
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v5, v5
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v7, v7, v7
; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v1, v1, v9
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v2, v2, v10
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v9, v11, v11
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v11, v13, v13
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v13, v15, v15
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v8, v11, v11
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v9, v12, v12
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v10, v13, v13
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v12, v12, v12
+; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v5, v5, v11
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v6, v6, v6
; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v11, v14, v14
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v7, v7, v7
-; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v12, v15, v15
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v3, v3, v8
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v4, v4, v9
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v5, v5, v10
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v6, v6, v11
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v7, v7, v12
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v1, v2, v3
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v2, v4, v5
+; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v7, v7, v13
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v8, v8, v8
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT: v_max_f16_e32 v10, v10, v10
+; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v3, v3, v9
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v4, v4, v12, v5
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v5, v6, v11, v7
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v0, v0, v8, v1
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v3, v6, v7
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v1, v2, v3
-; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v1, v2, v10, v3
+; GFX11-GISEL-FAKE16-NEXT: v_min_f16_e32 v2, v4, v5
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_min3_f16 v0, v0, v1, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1711,86 +1649,75 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v2.l, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v3.h, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.h, v4.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.h, v3.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.l, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v5.h, v5.h
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v6.l, v6.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.h, v6.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.h, v5.h
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.l
-; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v7.h, v7.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v1.h, v2.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v2.l, v2.h, v3.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.h, v4.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v4.h, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v3.h, v5.h, v6.l
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v2.l, v2.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v7.l, v7.h, v7.h
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v3.h, v3.h, v5.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.l, v6.l
+; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.h, v6.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v5.h, v5.h, v7.l
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v1.h, v3.l
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.l, v4.l, v4.h, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.h, v5.l, v6.l, v5.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v2.l, v2.h, v1.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v3.l, v3.h
+; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v9, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v8
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v10
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v11, v11
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v13, v13
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v13, v15, v15
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v11, v11
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v12, v12
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v13, v13
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v12, v12
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v11
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v14, v14
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v15, v15
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v8
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v4, v4, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v10
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v6, v6, v11
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v7, v7, v12
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v2, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v4, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v7, v7, v13
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v9
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v4, v4, v12, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v5, v6, v11, v7
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v8, v1
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v6, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v2, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v10, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v4, v5
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v2
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1855,40 +1782,34 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v1.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v4.l, v4.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v4.h, v4.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.h, v3.l, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v2.l, v2.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v3.h, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v4.l, v4.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v4.h, v4.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.l, v3.h, v3.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v3.h, v5.l, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.l, v5.h, v5.h
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v4.h, v6.l, v6.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.h, v6.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v5.h, v5.h
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.h, v7.l, v7.l
-; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v7.h, v7.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v1.h, v2.l
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v2.l, v2.h, v3.l
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v2.h, v3.h, v4.l
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v3.l, v4.h, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v3.h, v5.h, v6.l
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v2.l, v2.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v7.l, v7.h, v7.h
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.l, v2.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v2.h, v2.h, v2.h
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v3.h, v3.h, v5.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v5.l, v6.l, v6.l
+; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v6.l, v6.h, v6.h
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v5.h, v5.h, v7.l
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.h, v1.h, v3.l
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.l, v4.l, v4.h, v3.h
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v3.h, v5.l, v6.l, v5.h
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v2.l, v2.h, v1.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1898,47 +1819,42 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v9, v9
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v8
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v1, v9
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v2, v10
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v11, v11
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v13, v13
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v13, v15, v15
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v11, v11
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v9, v12, v12
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v13, v13
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v12, v12
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v11
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v6, v6, v6
; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v11, v14, v14
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v12, v15, v15
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v8
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v4, v4, v9
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v5, v5, v10
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v6, v6, v11
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v7, v7, v12
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v4, v5
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v7, v7, v13
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v8, v8, v8
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT: v_max_num_f16_e32 v10, v10, v10
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v3, v9
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v4, v4, v12, v5
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v5, v6, v11, v7
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v8, v1
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v3, v6, v7
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v1, v2, v10, v3
+; GFX12-GISEL-FAKE16-NEXT: v_min_num_f16_e32 v2, v4, v5
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_min3_num_f16 v0, v0, v1, v2
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fmin.v16half(<16 x half> %v)
@@ -2082,9 +1998,8 @@ define float @test_vector_reduce_fmin_v3float(<3 x float> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX7-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_fmin_v3float:
@@ -2098,9 +2013,8 @@ define float @test_vector_reduce_fmin_v3float(<3 x float> %v) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_fmin_v3float:
@@ -2114,9 +2028,8 @@ define float @test_vector_reduce_fmin_v3float(<3 x float> %v) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmin_v3float:
@@ -2130,9 +2043,8 @@ define float @test_vector_reduce_fmin_v3float(<3 x float> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX10-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_fmin_v3float:
@@ -2145,9 +2057,9 @@ define float @test_vector_reduce_fmin_v3float(<3 x float> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v2
-; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v3float:
@@ -2160,9 +2072,9 @@ define float @test_vector_reduce_fmin_v3float(<3 x float> %v) {
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v2
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v3float:
@@ -2183,9 +2095,9 @@ define float @test_vector_reduce_fmin_v3float(<3 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_max_num_f32 v1, v2, v2
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v2, v2, v2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmin.v3float(<3 x float> %v)
@@ -2205,13 +2117,12 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_fmin_v4float:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX7-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_fmin_v4float:
@@ -2226,13 +2137,12 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_fmin_v4float:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_fmin_v4float:
@@ -2247,13 +2157,12 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmin_v4float:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v3, v3
-; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmin_v4float:
@@ -2268,13 +2177,12 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmin_v4float:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX10-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_fmin_v4float:
@@ -2289,11 +2197,11 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_fmin_v4float:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
-; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v4float:
@@ -2308,11 +2216,11 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v4float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_min_num_f32 v1, v2, v3
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v4float:
@@ -2335,11 +2243,11 @@ define float @test_vector_reduce_fmin_v4float(<4 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_min_num_f32 v1, v2, v3
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmin.v4float(<4 x float> %v)
@@ -2361,20 +2269,18 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_fmin_v8float:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX7-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v5
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v6
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v7
; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX7-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
-; GFX7-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v6
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; GFX7-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX7-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX7-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX7-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2392,20 +2298,18 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_fmin_v8float:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v7
; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
-; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v6
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; GFX8-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX8-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX8-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX8-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2423,20 +2327,18 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmin_v8float:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v5, v5
+; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v6, v6
+; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v7, v7
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v3, v3
-; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v4, v4
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v5, v5
-; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v6, v6
-; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v7, v7
-; GFX9-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX9-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX9-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2454,20 +2356,18 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmin_v8float:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v4, v4
-; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v5, v5
; GFX10-GISEL-NEXT: v_max_f32_e32 v6, v6, v6
; GFX10-GISEL-NEXT: v_max_f32_e32 v7, v7, v7
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_min_f32_e32 v2, v4, v5
-; GFX10-GISEL-NEXT: v_min_f32_e32 v3, v6, v7
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v5, v5
+; GFX10-GISEL-NEXT: v_min_f32_e32 v5, v6, v7
+; GFX10-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX10-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2486,15 +2386,16 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_fmin_v8float:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v5, v5, v5
-; GFX11-GISEL-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_max_f32 v7, v7, v7
+; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v7, v7, v7
+; GFX11-GISEL-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_max_f32 v1, v1, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
-; GFX11-GISEL-NEXT: v_dual_min_f32 v2, v4, v5 :: v_dual_min_f32 v3, v6, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
+; GFX11-GISEL-NEXT: v_dual_min_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4
+; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v5, v5 :: v_dual_min_f32 v5, v6, v7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX11-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2513,15 +2414,16 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v8float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_min_num_f32 v1, v2, v3
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v2, v4, v5 :: v_dual_min_num_f32 v3, v6, v7
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_min_num_f32 v1, v2, v3
+; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_min_num_f32 v5, v6, v7
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v1, v3, v4, v5
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2548,15 +2450,16 @@ define float @test_vector_reduce_fmin_v8float(<8 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v7, v7, v7
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v1, v1, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_min_num_f32 v1, v2, v3
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v2, v4, v5 :: v_dual_min_num_f32 v3, v6, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_min_num_f32 v1, v2, v3
+; GFX12-GISEL-NEXT: v_dual_min_num_f32 v2, v2, v3 :: v_dual_max_num_f32 v3, v4, v4
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v5, v5 :: v_dual_min_num_f32 v5, v6, v7
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
+; GFX12-GISEL-NEXT: v_min3_num_f32 v1, v3, v4, v5
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2583,37 +2486,32 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_fmin_v16float:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX7-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v5
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v6
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v7
+; GFX7-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v8
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v9
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v8, 1.0, v10
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v9, 1.0, v11
+; GFX7-GISEL-NEXT: v_min_f32_e32 v8, v8, v9
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v9, 1.0, v12
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v11, 1.0, v14
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v12, 1.0, v15
; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX7-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; GFX7-GISEL-NEXT: v_mul_f32_e32 v10, 1.0, v13
+; GFX7-GISEL-NEXT: v_min_f32_e32 v11, v11, v12
+; GFX7-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX7-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
+; GFX7-GISEL-NEXT: v_min3_f32 v2, v6, v7, v8
+; GFX7-GISEL-NEXT: v_min3_f32 v3, v9, v10, v11
; GFX7-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v6
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; GFX7-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v8
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v9
-; GFX7-GISEL-NEXT: v_min_f32_e32 v4, v4, v5
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v10
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v11
-; GFX7-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v12
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v13
-; GFX7-GISEL-NEXT: v_min_f32_e32 v6, v6, v7
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v14
-; GFX7-GISEL-NEXT: v_mul_f32_e32 v8, 1.0, v15
-; GFX7-GISEL-NEXT: v_min_f32_e32 v7, v7, v8
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX7-GISEL-NEXT: v_min_f32_e32 v2, v4, v5
-; GFX7-GISEL-NEXT: v_min_f32_e32 v3, v6, v7
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX7-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_fmin_v16float:
@@ -2634,37 +2532,32 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_fmin_v16float:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v3
+; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v4
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v7
+; GFX8-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v8
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v9
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v8, 1.0, v10
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v9, 1.0, v11
+; GFX8-GISEL-NEXT: v_min_f32_e32 v8, v8, v9
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v9, 1.0, v12
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v11, 1.0, v14
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v12, 1.0, v15
; GFX8-GISEL-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v1, 1.0, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v3
-; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v4
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v5
+; GFX8-GISEL-NEXT: v_mul_f32_e32 v10, 1.0, v13
+; GFX8-GISEL-NEXT: v_min_f32_e32 v11, v11, v12
+; GFX8-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX8-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
+; GFX8-GISEL-NEXT: v_min3_f32 v2, v6, v7, v8
+; GFX8-GISEL-NEXT: v_min3_f32 v3, v9, v10, v11
; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v3, 1.0, v6
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v7
-; GFX8-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v4, 1.0, v8
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v9
-; GFX8-GISEL-NEXT: v_min_f32_e32 v4, v4, v5
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v5, 1.0, v10
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v11
-; GFX8-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v6, 1.0, v12
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v13
-; GFX8-GISEL-NEXT: v_min_f32_e32 v6, v6, v7
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v7, 1.0, v14
-; GFX8-GISEL-NEXT: v_mul_f32_e32 v8, 1.0, v15
-; GFX8-GISEL-NEXT: v_min_f32_e32 v7, v7, v8
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX8-GISEL-NEXT: v_min_f32_e32 v2, v4, v5
-; GFX8-GISEL-NEXT: v_min_f32_e32 v3, v6, v7
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX8-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_fmin_v16float:
@@ -2685,37 +2578,32 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_fmin_v16float:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
+; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v4, v4
+; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v5, v5
+; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v6, v6
+; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v7, v7
+; GFX9-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
+; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v8, v8
+; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v9, v9
+; GFX9-GISEL-NEXT: v_max_f32_e32 v8, v10, v10
+; GFX9-GISEL-NEXT: v_max_f32_e32 v9, v11, v11
+; GFX9-GISEL-NEXT: v_min_f32_e32 v8, v8, v9
+; GFX9-GISEL-NEXT: v_max_f32_e32 v9, v12, v12
+; GFX9-GISEL-NEXT: v_max_f32_e32 v11, v14, v14
+; GFX9-GISEL-NEXT: v_max_f32_e32 v12, v15, v15
; GFX9-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_f32_e32 v1, v2, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v3, v3
-; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v1, v2
-; GFX9-GISEL-NEXT: v_max_f32_e32 v2, v4, v4
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v5, v5
+; GFX9-GISEL-NEXT: v_max_f32_e32 v10, v13, v13
+; GFX9-GISEL-NEXT: v_min_f32_e32 v11, v11, v12
+; GFX9-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX9-GISEL-NEXT: v_min3_f32 v1, v3, v4, v5
+; GFX9-GISEL-NEXT: v_min3_f32 v2, v6, v7, v8
+; GFX9-GISEL-NEXT: v_min3_f32 v3, v9, v10, v11
; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX9-GISEL-NEXT: v_max_f32_e32 v3, v6, v6
-; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v7, v7
-; GFX9-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
-; GFX9-GISEL-NEXT: v_max_f32_e32 v4, v8, v8
-; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v9, v9
-; GFX9-GISEL-NEXT: v_min_f32_e32 v4, v4, v5
-; GFX9-GISEL-NEXT: v_max_f32_e32 v5, v10, v10
-; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v11, v11
-; GFX9-GISEL-NEXT: v_min_f32_e32 v5, v5, v6
-; GFX9-GISEL-NEXT: v_max_f32_e32 v6, v12, v12
-; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v13, v13
-; GFX9-GISEL-NEXT: v_min_f32_e32 v6, v6, v7
-; GFX9-GISEL-NEXT: v_max_f32_e32 v7, v14, v14
-; GFX9-GISEL-NEXT: v_max_f32_e32 v8, v15, v15
-; GFX9-GISEL-NEXT: v_min_f32_e32 v7, v7, v8
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX9-GISEL-NEXT: v_min_f32_e32 v2, v4, v5
-; GFX9-GISEL-NEXT: v_min_f32_e32 v3, v6, v7
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX9-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_fmin_v16float:
@@ -2736,37 +2624,32 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_fmin_v16float:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
-; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
; GFX10-GISEL-NEXT: v_max_f32_e32 v2, v2, v2
; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v3, v3
-; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v4, v4
-; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v5, v5
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
+; GFX10-GISEL-NEXT: v_max_f32_e32 v8, v8, v8
+; GFX10-GISEL-NEXT: v_max_f32_e32 v9, v9, v9
+; GFX10-GISEL-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX10-GISEL-NEXT: v_max_f32_e32 v1, v1, v1
+; GFX10-GISEL-NEXT: v_min_f32_e32 v2, v2, v3
; GFX10-GISEL-NEXT: v_max_f32_e32 v3, v6, v6
-; GFX10-GISEL-NEXT: v_min_f32_e32 v2, v4, v5
-; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v7, v7
-; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v8, v8
-; GFX10-GISEL-NEXT: v_max_f32_e32 v6, v9, v9
+; GFX10-GISEL-NEXT: v_max_f32_e32 v6, v7, v7
; GFX10-GISEL-NEXT: v_max_f32_e32 v7, v10, v10
-; GFX10-GISEL-NEXT: v_max_f32_e32 v8, v11, v11
-; GFX10-GISEL-NEXT: v_max_f32_e32 v9, v12, v12
-; GFX10-GISEL-NEXT: v_max_f32_e32 v10, v13, v13
+; GFX10-GISEL-NEXT: v_max_f32_e32 v10, v11, v11
; GFX10-GISEL-NEXT: v_max_f32_e32 v11, v14, v14
-; GFX10-GISEL-NEXT: v_max_f32_e32 v12, v15, v15
-; GFX10-GISEL-NEXT: v_min_f32_e32 v3, v3, v4
-; GFX10-GISEL-NEXT: v_min_f32_e32 v4, v5, v6
-; GFX10-GISEL-NEXT: v_min_f32_e32 v5, v7, v8
-; GFX10-GISEL-NEXT: v_min_f32_e32 v6, v9, v10
-; GFX10-GISEL-NEXT: v_min_f32_e32 v7, v11, v12
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_min_f32_e32 v2, v4, v5
-; GFX10-GISEL-NEXT: v_min_f32_e32 v3, v6, v7
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX10-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max_f32_e32 v14, v15, v15
+; GFX10-GISEL-NEXT: v_max_f32_e32 v4, v4, v4
+; GFX10-GISEL-NEXT: v_max_f32_e32 v5, v5, v5
+; GFX10-GISEL-NEXT: v_min_f32_e32 v7, v7, v10
+; GFX10-GISEL-NEXT: v_max_f32_e32 v10, v12, v12
+; GFX10-GISEL-NEXT: v_max_f32_e32 v12, v13, v13
+; GFX10-GISEL-NEXT: v_min_f32_e32 v11, v11, v14
+; GFX10-GISEL-NEXT: v_min_f32_e32 v3, v3, v6
+; GFX10-GISEL-NEXT: v_min3_f32 v6, v8, v9, v7
+; GFX10-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX10-GISEL-NEXT: v_min3_f32 v7, v10, v12, v11
+; GFX10-GISEL-NEXT: v_min3_f32 v1, v4, v5, v3
+; GFX10-GISEL-NEXT: v_min_f32_e32 v2, v6, v7
+; GFX10-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_fmin_v16float:
@@ -2790,28 +2673,27 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_fmin_v16float:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
; GFX11-GISEL-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v5, v5, v5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
-; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v6, v6 :: v_dual_min_f32 v2, v4, v5
-; GFX11-GISEL-NEXT: v_dual_max_f32 v4, v7, v7 :: v_dual_max_f32 v5, v8, v8
-; GFX11-GISEL-NEXT: v_dual_max_f32 v6, v9, v9 :: v_dual_max_f32 v7, v10, v10
-; GFX11-GISEL-NEXT: v_dual_max_f32 v8, v11, v11 :: v_dual_max_f32 v9, v12, v12
-; GFX11-GISEL-NEXT: v_dual_max_f32 v10, v13, v13 :: v_dual_max_f32 v11, v14, v14
-; GFX11-GISEL-NEXT: v_max_f32_e32 v12, v15, v15
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v3, v3, v4 :: v_dual_min_f32 v4, v5, v6
-; GFX11-GISEL-NEXT: v_dual_min_f32 v5, v7, v8 :: v_dual_min_f32 v6, v9, v10
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v7, v11, v12 :: v_dual_min_f32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_dual_min_f32 v1, v2, v3 :: v_dual_min_f32 v2, v4, v5
+; GFX11-GISEL-NEXT: v_max_f32_e32 v8, v8, v8
+; GFX11-GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_min_f32 v2, v2, v3
+; GFX11-GISEL-NEXT: v_dual_max_f32 v3, v6, v6 :: v_dual_max_f32 v6, v7, v7
+; GFX11-GISEL-NEXT: v_dual_max_f32 v7, v10, v10 :: v_dual_max_f32 v10, v11, v11
+; GFX11-GISEL-NEXT: v_dual_max_f32 v11, v14, v14 :: v_dual_max_f32 v14, v15, v15
+; GFX11-GISEL-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4
+; GFX11-GISEL-NEXT: v_min_f32_e32 v3, v3, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_dual_min_f32 v7, v7, v10 :: v_dual_max_f32 v10, v12, v12
+; GFX11-GISEL-NEXT: v_dual_max_f32 v12, v13, v13 :: v_dual_min_f32 v11, v11, v14
+; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_min3_f32 v6, v8, v9, v7
+; GFX11-GISEL-NEXT: v_min3_f32 v1, v4, v5, v3
+; GFX11-GISEL-NEXT: v_min3_f32 v7, v10, v12, v11
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_min_f32 v3, v6, v7 :: v_dual_min_f32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_min_f32_e32 v1, v2, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_min_f32_e32 v2, v6, v7
+; GFX11-GISEL-NEXT: v_min3_f32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fmin_v16float:
@@ -2835,28 +2717,27 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX1170-GISEL-LABEL: test_vector_reduce_fmin_v16float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_min_num_f32 v1, v2, v3
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_min_num_f32 v2, v4, v5
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v4, v7, v7 :: v_dual_max_num_f32 v5, v8, v8
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v6, v9, v9 :: v_dual_max_num_f32 v7, v10, v10
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v8, v11, v11 :: v_dual_max_num_f32 v9, v12, v12
-; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v10, v13, v13 :: v_dual_max_num_f32 v11, v14, v14
-; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v12, v15, v15
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v3, v3, v4 :: v_dual_min_num_f32 v4, v5, v6
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v5, v7, v8 :: v_dual_min_num_f32 v6, v9, v10
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v7, v11, v12 :: v_dual_min_num_f32 v0, v0, v1
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v1, v2, v3 :: v_dual_min_num_f32 v2, v4, v5
+; GFX1170-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_min_num_f32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v3, v3, v6
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
+; GFX1170-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_min_num_f32 v11, v11, v14
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v6, v8, v9, v7
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v1, v4, v5, v3
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v7, v10, v12, v11
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_dual_min_num_f32 v3, v6, v7 :: v_dual_min_num_f32 v0, v0, v1
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v1, v2, v3
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX1170-GISEL-NEXT: v_min_num_f32_e32 v2, v6, v7
+; GFX1170-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v16float:
@@ -2888,28 +2769,27 @@ define float @test_vector_reduce_fmin_v16float(<16 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
; GFX12-GISEL-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v1 :: v_dual_min_num_f32 v1, v2, v3
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_min_num_f32 v2, v4, v5
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v4, v7, v7 :: v_dual_max_num_f32 v5, v8, v8
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v6, v9, v9 :: v_dual_max_num_f32 v7, v10, v10
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v8, v11, v11 :: v_dual_max_num_f32 v9, v12, v12
-; GFX12-GISEL-NEXT: v_dual_max_num_f32 v10, v13, v13 :: v_dual_max_num_f32 v11, v14, v14
-; GFX12-GISEL-NEXT: v_max_num_f32_e32 v12, v15, v15
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v3, v3, v4 :: v_dual_min_num_f32 v4, v5, v6
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v5, v7, v8 :: v_dual_min_num_f32 v6, v9, v10
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v7, v11, v12 :: v_dual_min_num_f32 v0, v0, v1
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v1, v2, v3 :: v_dual_min_num_f32 v2, v4, v5
+; GFX12-GISEL-NEXT: v_max_num_f32_e32 v8, v8, v8
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v9, v9, v9 :: v_dual_min_num_f32 v2, v2, v3
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v3, v6, v6 :: v_dual_max_num_f32 v6, v7, v7
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v7, v10, v10 :: v_dual_max_num_f32 v10, v11, v11
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v11, v14, v14 :: v_dual_max_num_f32 v14, v15, v15
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v5, v5, v5 :: v_dual_max_num_f32 v4, v4, v4
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v3, v3, v6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_dual_min_num_f32 v7, v7, v10 :: v_dual_max_num_f32 v10, v12, v12
+; GFX12-GISEL-NEXT: v_dual_max_num_f32 v12, v13, v13 :: v_dual_min_num_f32 v11, v11, v14
+; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_min3_num_f32 v6, v8, v9, v7
+; GFX12-GISEL-NEXT: v_min3_num_f32 v1, v4, v5, v3
+; GFX12-GISEL-NEXT: v_min3_num_f32 v7, v10, v12, v11
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_dual_min_num_f32 v3, v6, v7 :: v_dual_min_num_f32 v0, v0, v1
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v1, v2, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v6, v7
+; GFX12-GISEL-NEXT: v_min3_num_f32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmin.v16float(<16 x float> %v)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 8ca36d4b9a5fa..efad5770a0261 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -149,9 +149,8 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_smax_v3i8:
@@ -181,8 +180,10 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v3i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX9-GISEL-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_smax_v3i8:
@@ -200,9 +201,8 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX10-GISEL-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8:
@@ -237,10 +237,9 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v1
+; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8:
@@ -287,10 +286,9 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v1
-; GFX12-GISEL-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v1
+; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i8 @llvm.vector.reduce.smax.v3i8(<3 x i8> %v)
@@ -312,24 +310,21 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v4i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
; GFX7-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: v_max_i32_e32 v1, s4, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, s4, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, s4, v2
+; GFX7-GISEL-NEXT: v_max3_i32 v2, v2, s4, s4
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, s4, v3
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, s4, v3
+; GFX7-GISEL-NEXT: v_max3_i32 v3, v3, s4, s4
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
@@ -384,16 +379,16 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v4i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v1, sext(v1), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX9-GISEL-NEXT: v_max_i16_sdwa v1, sext(v1), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-GISEL-NEXT: s_sext_i32_i8 s0, s0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v2, sext(v2), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v3, sext(v3), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_max_i16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: v_max_i16_e32 v1, s0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX9-GISEL-NEXT: v_max_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_max_i16_e32 v3, s0, v3
+; GFX9-GISEL-NEXT: v_max3_i16 v2, v2, s0, s0
+; GFX9-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xff
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v4, v1
@@ -425,21 +420,18 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX10-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-GISEL-NEXT: s_sext_i32_i8 s4, s4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
; GFX10-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_i16 v4, v2, s4
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_i16 v2, v1, s4
-; GFX10-GISEL-NEXT: v_max_i16 v4, v4, s4
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX10-GISEL-NEXT: v_max3_i16 v5, v2, s4, s4
+; GFX10-GISEL-NEXT: v_max3_i16 v3, v3, s4, s4
+; GFX10-GISEL-NEXT: v_max_i16 v6, v1, s4
+; GFX10-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v2, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX10-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -485,29 +477,23 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-GISEL-NEXT: s_sext_i32_i8 s0, s0
+; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX11-GISEL-NEXT: v_max_i16 v4, v2, s0
-; GFX11-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_max_i16 v5, v1, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i16 v2, v4, s0
-; GFX11-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX11-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
+; GFX11-GISEL-NEXT: v_max3_i16 v5, v2, s0, s0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_max_i16 v4, v1, s0
+; GFX11-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -567,32 +553,26 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT: s_sext_i32_i8 s0, s0
+; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v3
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_max_i16 v4, v2, s0
-; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_max_i16 v5, v1, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_i16 v2, v4, s0
-; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v1
-; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX12-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
+; GFX12-GISEL-NEXT: v_max3_i16 v5, v2, s0, s0
+; GFX12-GISEL-NEXT: v_max_i16 v4, v1, s0
+; GFX12-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -622,32 +602,28 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v8i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
+; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
+; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v6, v7, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v5, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v4
-; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v6, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v4
-; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v7, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, v3, v4
+; GFX7-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX7-GISEL-NEXT: v_max_i32_e32 v3, v3, v6
; GFX7-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_max3_i32 v1, v1, v5, v3
; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_max_i32_e32 v1, s4, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, s4, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, s4, v2
+; GFX7-GISEL-NEXT: v_max3_i32 v2, v2, s4, s4
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, s4, v3
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, s4, v3
+; GFX7-GISEL-NEXT: v_max3_i32 v3, v3, s4, s4
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
@@ -714,20 +690,20 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v8i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v1, sext(v1), sext(v5) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX9-GISEL-NEXT: v_max_i16_sdwa v2, sext(v2), sext(v6) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_max_i16_sdwa v3, sext(v3), sext(v7) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: s_sext_i32_i8 s0, s0
-; GFX9-GISEL-NEXT: v_max_i16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: v_max_i16_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_max_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_max_i16_e32 v3, s0, v3
+; GFX9-GISEL-NEXT: v_max3_i16 v0, v0, v4, v2
+; GFX9-GISEL-NEXT: v_max3_i16 v1, v1, v5, v3
; GFX9-GISEL-NEXT: v_max_i16_e32 v0, v0, v1
; GFX9-GISEL-NEXT: v_max_i16_e32 v1, s0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX9-GISEL-NEXT: v_max_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_max_i16_e32 v3, s0, v3
+; GFX9-GISEL-NEXT: v_max3_i16 v2, v2, s0, s0
+; GFX9-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xff
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v4, v1
@@ -762,33 +738,29 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smax_v8i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
+; GFX10-GISEL-NEXT: v_max_i16 v3, v3, v7
; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX10-GISEL-NEXT: v_max_i16 v1, v1, v5
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, v7
-; GFX10-GISEL-NEXT: v_max_i16 v2, v2, v6
; GFX10-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v4
+; GFX10-GISEL-NEXT: v_max_i16 v2, v2, v6
+; GFX10-GISEL-NEXT: v_max3_i16 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX10-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_i16 v4, v2, s4
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_i16 v2, v1, s4
-; GFX10-GISEL-NEXT: v_max_i16 v4, v4, s4
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX10-GISEL-NEXT: v_max3_i16 v3, v3, s4, s4
+; GFX10-GISEL-NEXT: v_max3_i16 v0, v0, v4, v2
+; GFX10-GISEL-NEXT: v_max_i16 v4, v1, s4
+; GFX10-GISEL-NEXT: v_max3_i16 v2, v2, s4, s4
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v2, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX10-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -860,37 +832,30 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v8i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-GISEL-NEXT: v_max_i16 v1, v1, v5
-; GFX11-GISEL-NEXT: v_bfe_i32 v5, v6, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
; GFX11-GISEL-NEXT: v_max_i16 v3, v3, v7
-; GFX11-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
; GFX11-GISEL-NEXT: s_sext_i32_i8 s0, s0
+; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX11-GISEL-NEXT: v_max_i16 v2, v2, v6
+; GFX11-GISEL-NEXT: v_max3_i16 v1, v1, v5, v3
+; GFX11-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_max_i16 v2, v2, v5
-; GFX11-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v4
-; GFX11-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: v_max_i16 v4, v2, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_max3_i16 v0, v0, v4, v2
; GFX11-GISEL-NEXT: v_max_i16 v5, v1, s0
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: v_max_i16 v2, v4, s0
+; GFX11-GISEL-NEXT: v_max3_i16 v2, v2, s0, s0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -978,37 +943,31 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v5
-; GFX12-GISEL-NEXT: v_bfe_i32 v5, v6, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
; GFX12-GISEL-NEXT: v_max_i16 v3, v3, v7
-; GFX12-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
; GFX12-GISEL-NEXT: s_sext_i32_i8 s0, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_max_i16 v2, v2, v5
-; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v4
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX12-GISEL-NEXT: v_max_i16 v2, v2, v6
+; GFX12-GISEL-NEXT: v_max3_i16 v1, v1, v5, v3
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_max_i16 v4, v2, s0
+; GFX12-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-NEXT: v_max3_i16 v0, v0, v4, v2
; GFX12-GISEL-NEXT: v_max_i16 v5, v1, s0
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_max_i16 v2, v4, s0
+; GFX12-GISEL-NEXT: v_max3_i16 v2, v2, s0, s0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -1057,48 +1016,41 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v16i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v9, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v8
-; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v10, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v8
-; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v11, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, v3, v8
; GFX7-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v12, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v4, v4, v8
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v12, 0, 8
+; GFX7-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
; GFX7-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v13, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v5, v5, v8
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v13, 0, 8
+; GFX7-GISEL-NEXT: v_max_i32_e32 v5, v5, v12
; GFX7-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v14, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v6, v6, v8
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v14, 0, 8
+; GFX7-GISEL-NEXT: v_max_i32_e32 v6, v6, v12
; GFX7-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v15, 0, 8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v7, v7, v8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v15, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
+; GFX7-GISEL-NEXT: v_max_i32_e32 v7, v7, v12
+; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v10, v10, 0, 8
+; GFX7-GISEL-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX7-GISEL-NEXT: v_max3_i32 v3, v3, v11, v7
; GFX7-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v8, v4
+; GFX7-GISEL-NEXT: v_max3_i32 v2, v2, v10, v6
; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: v_max_i32_e32 v1, s4, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, s4, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, s4, v2
+; GFX7-GISEL-NEXT: v_max3_i32 v2, v2, s4, s4
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, s4, v3
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, s4, v3
+; GFX7-GISEL-NEXT: v_max3_i32 v3, v3, s4, s4
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
@@ -1187,28 +1139,29 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v16i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v8) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v1, sext(v1), sext(v9) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v2, sext(v2), sext(v10) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v3, sext(v3), sext(v11) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v4, sext(v4), sext(v12) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
; GFX9-GISEL-NEXT: v_max_i16_sdwa v5, sext(v5), sext(v13) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v6, sext(v6), sext(v14) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_max_i16_sdwa v7, sext(v7), sext(v15) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_i16_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_max_i16_e32 v1, v1, v5
-; GFX9-GISEL-NEXT: v_max_i16_e32 v2, v2, v6
-; GFX9-GISEL-NEXT: v_max_i16_e32 v3, v3, v7
+; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v10, v10, 0, 8
+; GFX9-GISEL-NEXT: v_max_i16_sdwa v4, sext(v4), sext(v12) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_max_i16_sdwa v6, sext(v6), sext(v14) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_max3_i16 v1, v1, v9, v5
+; GFX9-GISEL-NEXT: v_max3_i16 v3, v3, v11, v7
; GFX9-GISEL-NEXT: s_sext_i32_i8 s0, s0
-; GFX9-GISEL-NEXT: v_max_i16_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: v_max3_i16 v0, v0, v8, v4
+; GFX9-GISEL-NEXT: v_max3_i16 v2, v2, v10, v6
; GFX9-GISEL-NEXT: v_max_i16_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_max_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_max_i16_e32 v3, s0, v3
-; GFX9-GISEL-NEXT: v_max_i16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: v_max_i16_e32 v1, s0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX9-GISEL-NEXT: v_max_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_max_i16_e32 v3, s0, v3
+; GFX9-GISEL-NEXT: v_max3_i16 v2, v2, s0, s0
+; GFX9-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xff
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v4, v1
@@ -1257,47 +1210,40 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smax_v16i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v15, v15, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v8
-; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX10-GISEL-NEXT: v_max_i16 v1, v1, v9
-; GFX10-GISEL-NEXT: v_bfe_i32 v8, v10, 0, 8
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, v11
-; GFX10-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v9, v13, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v10, v15, 0, 8
+; GFX10-GISEL-NEXT: v_max_i16 v5, v5, v13
+; GFX10-GISEL-NEXT: v_max_i16 v7, v7, v15
; GFX10-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v11, v14, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v13, v14, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v12, v12, 0, 8
-; GFX10-GISEL-NEXT: v_max_i16 v5, v5, v9
-; GFX10-GISEL-NEXT: v_max_i16 v7, v7, v10
-; GFX10-GISEL-NEXT: v_max_i16 v2, v2, v8
-; GFX10-GISEL-NEXT: v_max_i16 v6, v6, v11
+; GFX10-GISEL-NEXT: v_max3_i16 v1, v1, v9, v5
+; GFX10-GISEL-NEXT: v_max3_i16 v3, v3, v11, v7
+; GFX10-GISEL-NEXT: v_bfe_i32 v5, v10, 0, 8
+; GFX10-GISEL-NEXT: v_max_i16 v6, v6, v13
+; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v7, v8, 0, 8
; GFX10-GISEL-NEXT: v_max_i16 v4, v4, v12
-; GFX10-GISEL-NEXT: v_max_i16 v1, v1, v5
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, v7
+; GFX10-GISEL-NEXT: v_max_i16 v1, v1, v3
+; GFX10-GISEL-NEXT: v_max3_i16 v2, v2, v5, v6
; GFX10-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX10-GISEL-NEXT: v_max_i16 v2, v2, v6
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v4
; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX10-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_max_i16 v4, v2, s4
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_i16 v2, v1, s4
-; GFX10-GISEL-NEXT: v_max_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_max_i16 v4, v4, s4
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_max3_i16 v0, v0, v7, v4
+; GFX10-GISEL-NEXT: v_max_i16 v4, v1, s4
+; GFX10-GISEL-NEXT: v_max3_i16 v6, v2, s4, s4
+; GFX10-GISEL-NEXT: v_max3_i16 v3, v3, s4, s4
+; GFX10-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
@@ -1406,57 +1352,48 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v16i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v15, v15, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
-; GFX11-GISEL-NEXT: v_max_i16 v1, v1, v9
-; GFX11-GISEL-NEXT: v_bfe_i32 v9, v10, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v10, v11, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v11, v13, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v13, v15, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
+; GFX11-GISEL-NEXT: v_max_i16 v5, v5, v13
+; GFX11-GISEL-NEXT: v_max_i16 v7, v7, v15
; GFX11-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX11-GISEL-NEXT: v_max_i16 v2, v2, v9
-; GFX11-GISEL-NEXT: v_max_i16 v3, v3, v10
-; GFX11-GISEL-NEXT: v_max_i16 v5, v5, v11
-; GFX11-GISEL-NEXT: v_max_i16 v7, v7, v13
-; GFX11-GISEL-NEXT: v_bfe_i32 v9, v14, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v10, v12, 0, 8
-; GFX11-GISEL-NEXT: v_max_i16 v1, v1, v5
-; GFX11-GISEL-NEXT: v_max_i16 v3, v3, v7
-; GFX11-GISEL-NEXT: v_max_i16 v5, v6, v9
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v8
-; GFX11-GISEL-NEXT: v_max_i16 v4, v4, v10
+; GFX11-GISEL-NEXT: v_max3_i16 v1, v1, v9, v5
+; GFX11-GISEL-NEXT: v_max3_i16 v3, v3, v11, v7
+; GFX11-GISEL-NEXT: v_bfe_i32 v5, v14, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v7, v10, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v9, v12, 0, 8
; GFX11-GISEL-NEXT: s_sext_i32_i8 s0, s0
; GFX11-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX11-GISEL-NEXT: v_max_i16 v2, v2, v5
-; GFX11-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v4
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i16 v4, v1, s0
-; GFX11-GISEL-NEXT: v_max_i16 v5, v2, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v2
+; GFX11-GISEL-NEXT: v_max_i16 v5, v6, v5
+; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v6, v8, 0, 8
+; GFX11-GISEL-NEXT: v_max_i16 v4, v4, v9
+; GFX11-GISEL-NEXT: v_max_i16 v8, v1, s0
+; GFX11-GISEL-NEXT: v_max3_i16 v2, v2, v7, v5
+; GFX11-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-GISEL-NEXT: v_max_i16 v4, v5, s0
+; GFX11-GISEL-NEXT: v_max3_i16 v0, v0, v6, v4
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_max3_i16 v5, v2, s0, s0
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1574,52 +1511,44 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v15, v15, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
-; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v9
-; GFX12-GISEL-NEXT: v_bfe_i32 v9, v10, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v10, v11, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v11, v13, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v13, v15, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
+; GFX12-GISEL-NEXT: v_max_i16 v5, v5, v13
+; GFX12-GISEL-NEXT: v_max_i16 v7, v7, v15
; GFX12-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX12-GISEL-NEXT: v_max_i16 v2, v2, v9
-; GFX12-GISEL-NEXT: v_max_i16 v3, v3, v10
-; GFX12-GISEL-NEXT: v_max_i16 v5, v5, v11
-; GFX12-GISEL-NEXT: v_max_i16 v7, v7, v13
-; GFX12-GISEL-NEXT: v_bfe_i32 v9, v14, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v10, v12, 0, 8
-; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v5
-; GFX12-GISEL-NEXT: v_max_i16 v3, v3, v7
-; GFX12-GISEL-NEXT: v_max_i16 v5, v6, v9
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v8
-; GFX12-GISEL-NEXT: v_max_i16 v4, v4, v10
+; GFX12-GISEL-NEXT: v_max3_i16 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_max3_i16 v3, v3, v11, v7
+; GFX12-GISEL-NEXT: v_bfe_i32 v5, v14, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v7, v10, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v9, v12, 0, 8
; GFX12-GISEL-NEXT: s_sext_i32_i8 s0, s0
; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX12-GISEL-NEXT: v_max_i16 v2, v2, v5
+; GFX12-GISEL-NEXT: v_max_i16 v5, v6, v5
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v6, v8, 0, 8
+; GFX12-GISEL-NEXT: v_max_i16 v4, v4, v9
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v4
-; GFX12-GISEL-NEXT: v_max_i16 v4, v1, s0
-; GFX12-GISEL-NEXT: v_max_i16 v5, v2, s0
+; GFX12-GISEL-NEXT: v_max_i16 v8, v1, s0
+; GFX12-GISEL-NEXT: v_max3_i16 v2, v2, v7, v5
+; GFX12-GISEL-NEXT: v_max3_i16 v3, v3, s0, s0
+; GFX12-GISEL-NEXT: v_max3_i16 v0, v0, v6, v4
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX12-GISEL-NEXT: v_max_i16 v4, v5, s0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v8
+; GFX12-GISEL-NEXT: v_max3_i16 v5, v2, s0, s0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v1
+; GFX12-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
@@ -1774,9 +1703,8 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_bfe_i32 v2, v0, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v2, v0
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v2, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_smax_v3i16:
@@ -1800,8 +1728,8 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v3i16:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_i16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_smax_v3i16:
@@ -1818,8 +1746,7 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_i16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i16:
@@ -1847,9 +1774,8 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_max_i16 v0, v0, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i16:
@@ -1890,9 +1816,8 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i16 @llvm.vector.reduce.smax.v3i16(<3 x i16> %v)
@@ -1919,9 +1844,8 @@ define i16 @test_vector_reduce_smax_v4i16(<4 x i16> %v) {
; GFX7-GISEL-NEXT: v_bfe_i32 v3, v1, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v3
; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v2, v0
+; GFX7-GISEL-NEXT: v_max3_i32 v1, v2, v3, v0
; GFX7-GISEL-NEXT: v_max_i32_e32 v0, 0, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -2072,21 +1996,19 @@ define i16 @test_vector_reduce_smax_v8i16(<8 x i16> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v8i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_bfe_i32 v6, v1, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v7, v3, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v4, v0, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v5, v2, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 16, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v4, v4, v5
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_bfe_i32 v2, v1, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v5, v3, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 16, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v5
+; GFX7-GISEL-NEXT: v_max_i32_e32 v6, v6, v7
; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v4, v2
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v2, v0
+; GFX7-GISEL-NEXT: v_max3_i32 v3, v4, v5, v6
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
+; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v3, v0
; GFX7-GISEL-NEXT: v_max_i32_e32 v0, 0, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -2285,37 +2207,32 @@ define i16 @test_vector_reduce_smax_v16i16(<16 x i16> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v16i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v0, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v9, v4, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v4, 16, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v8, v8, v9
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v1, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v9, v5, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v5, v5, 16, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v4, v4, v9
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_bfe_i32 v5, v2, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v9, v6, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v2, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v13, v6, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v6, v6, 16, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v5, v5, v9
+; GFX7-GISEL-NEXT: v_max_i32_e32 v12, v12, v13
; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
; GFX7-GISEL-NEXT: v_bfe_i32 v6, v3, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v9, v7, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v13, v7, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v7, v7, 16, 16
-; GFX7-GISEL-NEXT: v_max_i32_e32 v6, v6, v9
+; GFX7-GISEL-NEXT: v_bfe_i32 v8, v0, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v9, v4, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v4, v4, 16, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v10, v1, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v11, v5, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v5, v5, 16, 16
; GFX7-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_max_i32_e32 v5, v8, v5
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v4, v6
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v5, v2
+; GFX7-GISEL-NEXT: v_max_i32_e32 v6, v6, v13
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_max3_i32 v1, v1, v5, v3
+; GFX7-GISEL-NEXT: v_max3_i32 v7, v8, v9, v12
+; GFX7-GISEL-NEXT: v_max3_i32 v2, v10, v11, v6
; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v2, v0
+; GFX7-GISEL-NEXT: v_max3_i32 v1, v7, v2, v0
; GFX7-GISEL-NEXT: v_max_i32_e32 v0, 0, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -2586,93 +2503,45 @@ entry:
}
define i32 @test_vector_reduce_smax_v3i32(<3 x i32> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_smax_v3i32:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_max3_i32 v0, v0, v1, v2
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_smax_v3i32:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_smax_v3i32:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_max3_i32 v0, v0, v1, v2
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_smax_v3i32:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_smax_v3i32:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_max3_i32 v0, v0, v1, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_smax_v3i32:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_smax_v3i32:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_max3_i32 v0, v0, v1, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_smax_v3i32:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_max3_i32 v0, v0, v1, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_smax_v3i32:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_smax_v3i32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_max3_i32 v0, v0, v1, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v3i32:
-; GFX11-SDAG: ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_max3_i32 v0, v0, v1, v2
-; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_smax_v3i32:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_max3_i32 v0, v0, v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: test_vector_reduce_smax_v3i32:
-; GFX11-GISEL: ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_smax_v3i32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_i32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v3i32:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max3_i32 v0, v0, v1, v2
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_vector_reduce_smax_v3i32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_max3_i32 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: test_vector_reduce_smax_v3i32:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_vector_reduce_smax_v3i32:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_i32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.smax.v3i32(<3 x i32> %v)
ret i32 %res
@@ -2689,9 +2558,8 @@ define i32 @test_vector_reduce_smax_v4i32(<4 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v4i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_smax_v4i32:
@@ -2704,9 +2572,8 @@ define i32 @test_vector_reduce_smax_v4i32(<4 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_smax_v4i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v4i32:
@@ -2719,9 +2586,8 @@ define i32 @test_vector_reduce_smax_v4i32(<4 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v4i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
; GFX9-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_smax_v4i32:
@@ -2734,9 +2600,8 @@ define i32 @test_vector_reduce_smax_v4i32(<4 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smax_v4i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_smax_v4i32:
@@ -2750,10 +2615,9 @@ define i32 @test_vector_reduce_smax_v4i32(<4 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v4i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
; GFX11-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_smax_v4i32:
@@ -2775,10 +2639,9 @@ define i32 @test_vector_reduce_smax_v4i32(<4 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
; GFX12-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v)
@@ -2798,12 +2661,10 @@ define i32 @test_vector_reduce_smax_v8i32(<8 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v8i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
; GFX7-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_max3_i32 v1, v1, v5, v3
; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2819,12 +2680,10 @@ define i32 @test_vector_reduce_smax_v8i32(<8 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_smax_v8i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX8-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
; GFX8-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
; GFX8-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
+; GFX8-GISEL-NEXT: v_max3_i32 v0, v0, v4, v2
+; GFX8-GISEL-NEXT: v_max3_i32 v1, v1, v5, v3
; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2840,12 +2699,10 @@ define i32 @test_vector_reduce_smax_v8i32(<8 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v8i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
; GFX9-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
; GFX9-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
+; GFX9-GISEL-NEXT: v_max3_i32 v0, v0, v4, v2
+; GFX9-GISEL-NEXT: v_max3_i32 v1, v1, v5, v3
; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2861,12 +2718,10 @@ define i32 @test_vector_reduce_smax_v8i32(<8 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smax_v8i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX10-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
; GFX10-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
; GFX10-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
+; GFX10-GISEL-NEXT: v_max3_i32 v0, v0, v4, v2
+; GFX10-GISEL-NEXT: v_max3_i32 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2883,13 +2738,11 @@ define i32 @test_vector_reduce_smax_v8i32(<8 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v8i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX11-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
; GFX11-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
; GFX11-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX11-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
+; GFX11-GISEL-NEXT: v_max3_i32 v0, v0, v4, v2
+; GFX11-GISEL-NEXT: v_max3_i32 v1, v1, v5, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2915,13 +2768,11 @@ define i32 @test_vector_reduce_smax_v8i32(<8 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX12-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
; GFX12-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
; GFX12-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX12-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
+; GFX12-GISEL-NEXT: v_max3_i32 v0, v0, v4, v2
+; GFX12-GISEL-NEXT: v_max3_i32 v1, v1, v5, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2949,21 +2800,16 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v16i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v9
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v10
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, v3, v11
-; GFX7-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
; GFX7-GISEL-NEXT: v_max_i32_e32 v5, v5, v13
-; GFX7-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
; GFX7-GISEL-NEXT: v_max_i32_e32 v7, v7, v15
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
-; GFX7-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
+; GFX7-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
+; GFX7-GISEL-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX7-GISEL-NEXT: v_max3_i32 v3, v3, v11, v7
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v8, v4
+; GFX7-GISEL-NEXT: v_max3_i32 v2, v2, v10, v6
; GFX7-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_smax_v16i32:
@@ -2984,21 +2830,16 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_smax_v16i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX8-GISEL-NEXT: v_max_i32_e32 v1, v1, v9
-; GFX8-GISEL-NEXT: v_max_i32_e32 v2, v2, v10
-; GFX8-GISEL-NEXT: v_max_i32_e32 v3, v3, v11
-; GFX8-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
; GFX8-GISEL-NEXT: v_max_i32_e32 v5, v5, v13
-; GFX8-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
; GFX8-GISEL-NEXT: v_max_i32_e32 v7, v7, v15
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX8-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
-; GFX8-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
-; GFX8-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
+; GFX8-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
+; GFX8-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
+; GFX8-GISEL-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX8-GISEL-NEXT: v_max3_i32 v3, v3, v11, v7
+; GFX8-GISEL-NEXT: v_max3_i32 v0, v0, v8, v4
+; GFX8-GISEL-NEXT: v_max3_i32 v2, v2, v10, v6
; GFX8-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX8-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v16i32:
@@ -3019,21 +2860,16 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v16i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX9-GISEL-NEXT: v_max_i32_e32 v1, v1, v9
-; GFX9-GISEL-NEXT: v_max_i32_e32 v2, v2, v10
-; GFX9-GISEL-NEXT: v_max_i32_e32 v3, v3, v11
-; GFX9-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
; GFX9-GISEL-NEXT: v_max_i32_e32 v5, v5, v13
-; GFX9-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
; GFX9-GISEL-NEXT: v_max_i32_e32 v7, v7, v15
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
-; GFX9-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
-; GFX9-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
+; GFX9-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
+; GFX9-GISEL-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX9-GISEL-NEXT: v_max3_i32 v3, v3, v11, v7
+; GFX9-GISEL-NEXT: v_max3_i32 v0, v0, v8, v4
+; GFX9-GISEL-NEXT: v_max3_i32 v2, v2, v10, v6
; GFX9-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_smax_v16i32:
@@ -3054,21 +2890,16 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smax_v16i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX10-GISEL-NEXT: v_max_i32_e32 v1, v1, v9
-; GFX10-GISEL-NEXT: v_max_i32_e32 v2, v2, v10
-; GFX10-GISEL-NEXT: v_max_i32_e32 v3, v3, v11
-; GFX10-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
; GFX10-GISEL-NEXT: v_max_i32_e32 v5, v5, v13
-; GFX10-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
; GFX10-GISEL-NEXT: v_max_i32_e32 v7, v7, v15
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX10-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
-; GFX10-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
-; GFX10-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
+; GFX10-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
+; GFX10-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
+; GFX10-GISEL-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX10-GISEL-NEXT: v_max3_i32 v3, v3, v11, v7
+; GFX10-GISEL-NEXT: v_max3_i32 v0, v0, v8, v4
+; GFX10-GISEL-NEXT: v_max3_i32 v2, v2, v10, v6
; GFX10-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_smax_v16i32:
@@ -3091,25 +2922,19 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v16i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX11-GISEL-NEXT: v_max_i32_e32 v1, v1, v9
-; GFX11-GISEL-NEXT: v_max_i32_e32 v2, v2, v10
-; GFX11-GISEL-NEXT: v_max_i32_e32 v3, v3, v11
-; GFX11-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
; GFX11-GISEL-NEXT: v_max_i32_e32 v5, v5, v13
-; GFX11-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
; GFX11-GISEL-NEXT: v_max_i32_e32 v7, v7, v15
+; GFX11-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
+; GFX11-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX11-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
+; GFX11-GISEL-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX11-GISEL-NEXT: v_max3_i32 v3, v3, v11, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
-; GFX11-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
+; GFX11-GISEL-NEXT: v_max3_i32 v0, v0, v8, v4
+; GFX11-GISEL-NEXT: v_max3_i32 v2, v2, v10, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_smax_v16i32:
@@ -3140,25 +2965,19 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX12-GISEL-NEXT: v_max_i32_e32 v1, v1, v9
-; GFX12-GISEL-NEXT: v_max_i32_e32 v2, v2, v10
-; GFX12-GISEL-NEXT: v_max_i32_e32 v3, v3, v11
-; GFX12-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
; GFX12-GISEL-NEXT: v_max_i32_e32 v5, v5, v13
-; GFX12-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
; GFX12-GISEL-NEXT: v_max_i32_e32 v7, v7, v15
+; GFX12-GISEL-NEXT: v_max_i32_e32 v4, v4, v12
+; GFX12-GISEL-NEXT: v_max_i32_e32 v6, v6, v14
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v4
-; GFX12-GISEL-NEXT: v_max_i32_e32 v1, v1, v5
+; GFX12-GISEL-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_max3_i32 v3, v3, v11, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_i32_e32 v2, v2, v6
-; GFX12-GISEL-NEXT: v_max_i32_e32 v3, v3, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v2
+; GFX12-GISEL-NEXT: v_max3_i32 v0, v0, v8, v4
+; GFX12-GISEL-NEXT: v_max3_i32 v2, v2, v10, v6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_i32_e32 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_max3_i32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %v)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 2107f2d6dd587..2be894755078a 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -149,9 +149,8 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_smin_v3i8:
@@ -181,8 +180,10 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v3i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX9-GISEL-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_smin_v3i8:
@@ -200,9 +201,8 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX10-GISEL-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8:
@@ -237,10 +237,9 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v1
+; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8:
@@ -287,10 +286,9 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v1
-; GFX12-GISEL-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v1
+; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i8 @llvm.vector.reduce.smin.v3i8(<3 x i8> %v)
@@ -312,24 +310,21 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v4i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
; GFX7-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, s4, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, s4, v2
+; GFX7-GISEL-NEXT: v_min3_i32 v2, v2, s4, s4
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, s4, v3
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, s4, v3
+; GFX7-GISEL-NEXT: v_min3_i32 v3, v3, s4, s4
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
@@ -384,16 +379,16 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v4i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v1, sext(v1), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX9-GISEL-NEXT: v_min_i16_sdwa v1, sext(v1), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-GISEL-NEXT: s_sext_i32_i8 s0, s0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v2, sext(v2), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v3, sext(v3), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_min_i16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: v_min_i16_e32 v1, s0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX9-GISEL-NEXT: v_min_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_min_i16_e32 v3, s0, v3
+; GFX9-GISEL-NEXT: v_min3_i16 v2, v2, s0, s0
+; GFX9-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xff
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v4, v1
@@ -425,21 +420,18 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX10-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-GISEL-NEXT: s_sext_i32_i8 s4, s4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
; GFX10-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_i16 v4, v2, s4
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_min_i16 v2, v1, s4
-; GFX10-GISEL-NEXT: v_min_i16 v4, v4, s4
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX10-GISEL-NEXT: v_min3_i16 v5, v2, s4, s4
+; GFX10-GISEL-NEXT: v_min3_i16 v3, v3, s4, s4
+; GFX10-GISEL-NEXT: v_min_i16 v6, v1, s4
+; GFX10-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v2, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX10-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -485,29 +477,23 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-GISEL-NEXT: s_sext_i32_i8 s0, s0
+; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX11-GISEL-NEXT: v_min_i16 v4, v2, s0
-; GFX11-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_min_i16 v5, v1, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i16 v2, v4, s0
-; GFX11-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX11-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
+; GFX11-GISEL-NEXT: v_min3_i16 v5, v2, s0, s0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_min_i16 v4, v1, s0
+; GFX11-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -567,32 +553,26 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT: s_sext_i32_i8 s0, s0
+; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v3
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_min_i16 v4, v2, s0
-; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_min_i16 v5, v1, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_i16 v2, v4, s0
-; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v1
-; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX12-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
+; GFX12-GISEL-NEXT: v_min3_i16 v5, v2, s0, s0
+; GFX12-GISEL-NEXT: v_min_i16 v4, v1, s0
+; GFX12-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -622,32 +602,28 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v8i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
+; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
+; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v6, v7, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX7-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v5, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v4
-; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v6, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v4
-; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v7, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, v3, v4
+; GFX7-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX7-GISEL-NEXT: v_min_i32_e32 v3, v3, v6
; GFX7-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_min3_i32 v1, v1, v5, v3
; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, s4, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, s4, v2
+; GFX7-GISEL-NEXT: v_min3_i32 v2, v2, s4, s4
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, s4, v3
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, s4, v3
+; GFX7-GISEL-NEXT: v_min3_i32 v3, v3, s4, s4
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
@@ -714,20 +690,20 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v8i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v1, sext(v1), sext(v5) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX9-GISEL-NEXT: v_min_i16_sdwa v2, sext(v2), sext(v6) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_min_i16_sdwa v3, sext(v3), sext(v7) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: s_sext_i32_i8 s0, s0
-; GFX9-GISEL-NEXT: v_min_i16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: v_min_i16_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_min_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_min_i16_e32 v3, s0, v3
+; GFX9-GISEL-NEXT: v_min3_i16 v0, v0, v4, v2
+; GFX9-GISEL-NEXT: v_min3_i16 v1, v1, v5, v3
; GFX9-GISEL-NEXT: v_min_i16_e32 v0, v0, v1
; GFX9-GISEL-NEXT: v_min_i16_e32 v1, s0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX9-GISEL-NEXT: v_min_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_min_i16_e32 v3, s0, v3
+; GFX9-GISEL-NEXT: v_min3_i16 v2, v2, s0, s0
+; GFX9-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xff
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v4, v1
@@ -762,33 +738,29 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smin_v8i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
+; GFX10-GISEL-NEXT: v_min_i16 v3, v3, v7
; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX10-GISEL-NEXT: v_min_i16 v1, v1, v5
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, v7
-; GFX10-GISEL-NEXT: v_min_i16 v2, v2, v6
; GFX10-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v4
+; GFX10-GISEL-NEXT: v_min_i16 v2, v2, v6
+; GFX10-GISEL-NEXT: v_min3_i16 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX10-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_i16 v4, v2, s4
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_min_i16 v2, v1, s4
-; GFX10-GISEL-NEXT: v_min_i16 v4, v4, s4
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX10-GISEL-NEXT: v_min3_i16 v3, v3, s4, s4
+; GFX10-GISEL-NEXT: v_min3_i16 v0, v0, v4, v2
+; GFX10-GISEL-NEXT: v_min_i16 v4, v1, s4
+; GFX10-GISEL-NEXT: v_min3_i16 v2, v2, s4, s4
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v2, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX10-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -860,37 +832,30 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v8i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-GISEL-NEXT: v_min_i16 v1, v1, v5
-; GFX11-GISEL-NEXT: v_bfe_i32 v5, v6, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
; GFX11-GISEL-NEXT: v_min_i16 v3, v3, v7
-; GFX11-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
; GFX11-GISEL-NEXT: s_sext_i32_i8 s0, s0
+; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX11-GISEL-NEXT: v_min_i16 v2, v2, v6
+; GFX11-GISEL-NEXT: v_min3_i16 v1, v1, v5, v3
+; GFX11-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_min_i16 v2, v2, v5
-; GFX11-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v4
-; GFX11-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: v_min_i16 v4, v2, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_min3_i16 v0, v0, v4, v2
; GFX11-GISEL-NEXT: v_min_i16 v5, v1, s0
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: v_min_i16 v2, v4, s0
+; GFX11-GISEL-NEXT: v_min3_i16 v2, v2, s0, s0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -978,37 +943,31 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v5
-; GFX12-GISEL-NEXT: v_bfe_i32 v5, v6, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
; GFX12-GISEL-NEXT: v_min_i16 v3, v3, v7
-; GFX12-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
; GFX12-GISEL-NEXT: s_sext_i32_i8 s0, s0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_min_i16 v2, v2, v5
-; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v4
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX12-GISEL-NEXT: v_min_i16 v2, v2, v6
+; GFX12-GISEL-NEXT: v_min3_i16 v1, v1, v5, v3
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_min_i16 v4, v2, s0
+; GFX12-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-NEXT: v_min3_i16 v0, v0, v4, v2
; GFX12-GISEL-NEXT: v_min_i16 v5, v1, s0
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_min_i16 v2, v4, s0
+; GFX12-GISEL-NEXT: v_min3_i16 v2, v2, s0, s0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -1057,48 +1016,41 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v16i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v9, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v8
-; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v10, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v8
-; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v11, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, v3, v8
; GFX7-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v12, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v4, v4, v8
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v12, 0, 8
+; GFX7-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
; GFX7-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v13, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v5, v5, v8
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v13, 0, 8
+; GFX7-GISEL-NEXT: v_min_i32_e32 v5, v5, v12
; GFX7-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v14, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v6, v6, v8
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v14, 0, 8
+; GFX7-GISEL-NEXT: v_min_i32_e32 v6, v6, v12
; GFX7-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v15, 0, 8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v7, v7, v8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v15, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
+; GFX7-GISEL-NEXT: v_min_i32_e32 v7, v7, v12
+; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-GISEL-NEXT: v_bfe_i32 v10, v10, 0, 8
+; GFX7-GISEL-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX7-GISEL-NEXT: v_min3_i32 v3, v3, v11, v7
; GFX7-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v8, v4
+; GFX7-GISEL-NEXT: v_min3_i32 v2, v2, v10, v6
; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: v_min_i32_e32 v1, s4, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, s4, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, s4, v2
+; GFX7-GISEL-NEXT: v_min3_i32 v2, v2, s4, s4
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, s4, v3
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, s4, v3
+; GFX7-GISEL-NEXT: v_min3_i32 v3, v3, s4, s4
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
@@ -1187,28 +1139,29 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v16i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v8) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v1, sext(v1), sext(v9) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v2, sext(v2), sext(v10) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v3, sext(v3), sext(v11) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v4, sext(v4), sext(v12) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
; GFX9-GISEL-NEXT: v_min_i16_sdwa v5, sext(v5), sext(v13) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v6, sext(v6), sext(v14) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_min_i16_sdwa v7, sext(v7), sext(v15) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_i16_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_min_i16_e32 v1, v1, v5
-; GFX9-GISEL-NEXT: v_min_i16_e32 v2, v2, v6
-; GFX9-GISEL-NEXT: v_min_i16_e32 v3, v3, v7
+; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX9-GISEL-NEXT: v_bfe_i32 v10, v10, 0, 8
+; GFX9-GISEL-NEXT: v_min_i16_sdwa v4, sext(v4), sext(v12) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_min_i16_sdwa v6, sext(v6), sext(v14) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_min3_i16 v1, v1, v9, v5
+; GFX9-GISEL-NEXT: v_min3_i16 v3, v3, v11, v7
; GFX9-GISEL-NEXT: s_sext_i32_i8 s0, s0
-; GFX9-GISEL-NEXT: v_min_i16_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: v_min3_i16 v0, v0, v8, v4
+; GFX9-GISEL-NEXT: v_min3_i16 v2, v2, v10, v6
; GFX9-GISEL-NEXT: v_min_i16_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_min_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_min_i16_e32 v3, s0, v3
-; GFX9-GISEL-NEXT: v_min_i16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: v_min_i16_e32 v1, s0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX9-GISEL-NEXT: v_min_i16_e32 v2, s0, v2
-; GFX9-GISEL-NEXT: v_min_i16_e32 v3, s0, v3
+; GFX9-GISEL-NEXT: v_min3_i16 v2, v2, s0, s0
+; GFX9-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xff
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v4, v1
@@ -1257,47 +1210,40 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smin_v16i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v15, v15, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v8
-; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX10-GISEL-NEXT: v_min_i16 v1, v1, v9
-; GFX10-GISEL-NEXT: v_bfe_i32 v8, v10, 0, 8
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, v11
-; GFX10-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v9, v13, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v10, v15, 0, 8
+; GFX10-GISEL-NEXT: v_min_i16 v5, v5, v13
+; GFX10-GISEL-NEXT: v_min_i16 v7, v7, v15
; GFX10-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX10-GISEL-NEXT: v_bfe_i32 v11, v14, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v13, v14, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
; GFX10-GISEL-NEXT: v_bfe_i32 v12, v12, 0, 8
-; GFX10-GISEL-NEXT: v_min_i16 v5, v5, v9
-; GFX10-GISEL-NEXT: v_min_i16 v7, v7, v10
-; GFX10-GISEL-NEXT: v_min_i16 v2, v2, v8
-; GFX10-GISEL-NEXT: v_min_i16 v6, v6, v11
+; GFX10-GISEL-NEXT: v_min3_i16 v1, v1, v9, v5
+; GFX10-GISEL-NEXT: v_min3_i16 v3, v3, v11, v7
+; GFX10-GISEL-NEXT: v_bfe_i32 v5, v10, 0, 8
+; GFX10-GISEL-NEXT: v_min_i16 v6, v6, v13
+; GFX10-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX10-GISEL-NEXT: v_bfe_i32 v7, v8, 0, 8
; GFX10-GISEL-NEXT: v_min_i16 v4, v4, v12
-; GFX10-GISEL-NEXT: v_min_i16 v1, v1, v5
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, v7
+; GFX10-GISEL-NEXT: v_min_i16 v1, v1, v3
+; GFX10-GISEL-NEXT: v_min3_i16 v2, v2, v5, v6
; GFX10-GISEL-NEXT: s_sext_i32_i8 s4, s4
-; GFX10-GISEL-NEXT: v_min_i16 v2, v2, v6
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v4
; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX10-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_min_i16 v4, v2, s4
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_min_i16 v2, v1, s4
-; GFX10-GISEL-NEXT: v_min_i16 v3, v3, s4
-; GFX10-GISEL-NEXT: v_min_i16 v4, v4, s4
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_min3_i16 v0, v0, v7, v4
+; GFX10-GISEL-NEXT: v_min_i16 v4, v1, s4
+; GFX10-GISEL-NEXT: v_min3_i16 v6, v2, s4, s4
+; GFX10-GISEL-NEXT: v_min3_i16 v3, v3, s4, s4
+; GFX10-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
@@ -1406,57 +1352,48 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v16i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v15, v15, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
-; GFX11-GISEL-NEXT: v_min_i16 v1, v1, v9
-; GFX11-GISEL-NEXT: v_bfe_i32 v9, v10, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v10, v11, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v11, v13, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v13, v15, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
+; GFX11-GISEL-NEXT: v_min_i16 v5, v5, v13
+; GFX11-GISEL-NEXT: v_min_i16 v7, v7, v15
; GFX11-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX11-GISEL-NEXT: v_min_i16 v2, v2, v9
-; GFX11-GISEL-NEXT: v_min_i16 v3, v3, v10
-; GFX11-GISEL-NEXT: v_min_i16 v5, v5, v11
-; GFX11-GISEL-NEXT: v_min_i16 v7, v7, v13
-; GFX11-GISEL-NEXT: v_bfe_i32 v9, v14, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX11-GISEL-NEXT: v_bfe_i32 v10, v12, 0, 8
-; GFX11-GISEL-NEXT: v_min_i16 v1, v1, v5
-; GFX11-GISEL-NEXT: v_min_i16 v3, v3, v7
-; GFX11-GISEL-NEXT: v_min_i16 v5, v6, v9
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v8
-; GFX11-GISEL-NEXT: v_min_i16 v4, v4, v10
+; GFX11-GISEL-NEXT: v_min3_i16 v1, v1, v9, v5
+; GFX11-GISEL-NEXT: v_min3_i16 v3, v3, v11, v7
+; GFX11-GISEL-NEXT: v_bfe_i32 v5, v14, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v7, v10, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v9, v12, 0, 8
; GFX11-GISEL-NEXT: s_sext_i32_i8 s0, s0
; GFX11-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX11-GISEL-NEXT: v_min_i16 v2, v2, v5
-; GFX11-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v4
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i16 v4, v1, s0
-; GFX11-GISEL-NEXT: v_min_i16 v5, v2, s0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v2
+; GFX11-GISEL-NEXT: v_min_i16 v5, v6, v5
+; GFX11-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-GISEL-NEXT: v_bfe_i32 v6, v8, 0, 8
+; GFX11-GISEL-NEXT: v_min_i16 v4, v4, v9
+; GFX11-GISEL-NEXT: v_min_i16 v8, v1, s0
+; GFX11-GISEL-NEXT: v_min3_i16 v2, v2, v7, v5
+; GFX11-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-GISEL-NEXT: v_min_i16 v4, v5, s0
+; GFX11-GISEL-NEXT: v_min3_i16 v0, v0, v6, v4
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v8
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_min3_i16 v5, v2, s0, s0
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1574,52 +1511,44 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v15, v15, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v9, v9, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
-; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v9
-; GFX12-GISEL-NEXT: v_bfe_i32 v9, v10, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v10, v11, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v11, v13, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v13, v15, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v11, v11, 0, 8
+; GFX12-GISEL-NEXT: v_min_i16 v5, v5, v13
+; GFX12-GISEL-NEXT: v_min_i16 v7, v7, v15
; GFX12-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX12-GISEL-NEXT: v_min_i16 v2, v2, v9
-; GFX12-GISEL-NEXT: v_min_i16 v3, v3, v10
-; GFX12-GISEL-NEXT: v_min_i16 v5, v5, v11
-; GFX12-GISEL-NEXT: v_min_i16 v7, v7, v13
-; GFX12-GISEL-NEXT: v_bfe_i32 v9, v14, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
-; GFX12-GISEL-NEXT: v_bfe_i32 v10, v12, 0, 8
-; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v5
-; GFX12-GISEL-NEXT: v_min_i16 v3, v3, v7
-; GFX12-GISEL-NEXT: v_min_i16 v5, v6, v9
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v8
-; GFX12-GISEL-NEXT: v_min_i16 v4, v4, v10
+; GFX12-GISEL-NEXT: v_min3_i16 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_min3_i16 v3, v3, v11, v7
+; GFX12-GISEL-NEXT: v_bfe_i32 v5, v14, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v7, v10, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v9, v12, 0, 8
; GFX12-GISEL-NEXT: s_sext_i32_i8 s0, s0
; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX12-GISEL-NEXT: v_min_i16 v2, v2, v5
+; GFX12-GISEL-NEXT: v_min_i16 v5, v6, v5
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v6, v8, 0, 8
+; GFX12-GISEL-NEXT: v_min_i16 v4, v4, v9
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v4
-; GFX12-GISEL-NEXT: v_min_i16 v4, v1, s0
-; GFX12-GISEL-NEXT: v_min_i16 v5, v2, s0
+; GFX12-GISEL-NEXT: v_min_i16 v8, v1, s0
+; GFX12-GISEL-NEXT: v_min3_i16 v2, v2, v7, v5
+; GFX12-GISEL-NEXT: v_min3_i16 v3, v3, s0, s0
+; GFX12-GISEL-NEXT: v_min3_i16 v0, v0, v6, v4
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX12-GISEL-NEXT: v_min_i16 v4, v5, s0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v8
+; GFX12-GISEL-NEXT: v_min3_i16 v5, v2, s0, s0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v1
+; GFX12-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
@@ -1774,9 +1703,8 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_bfe_i32 v2, v0, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v2, v0
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v2, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_smin_v3i16:
@@ -1800,8 +1728,8 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v3i16:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_i16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_smin_v3i16:
@@ -1818,8 +1746,7 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_min_i16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i16:
@@ -1847,9 +1774,8 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_min_i16 v0, v0, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i16:
@@ -1890,9 +1816,8 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i16 @llvm.vector.reduce.smin.v3i16(<3 x i16> %v)
@@ -1919,9 +1844,8 @@ define i16 @test_vector_reduce_smin_v4i16(<4 x i16> %v) {
; GFX7-GISEL-NEXT: v_bfe_i32 v3, v1, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v3
; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v2, v0
+; GFX7-GISEL-NEXT: v_min3_i32 v1, v2, v3, v0
; GFX7-GISEL-NEXT: v_min_i32_e32 v0, 0, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -2072,21 +1996,19 @@ define i16 @test_vector_reduce_smin_v8i16(<8 x i16> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v8i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_bfe_i32 v6, v1, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v7, v3, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v4, v0, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v5, v2, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 16, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v4, v4, v5
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_bfe_i32 v2, v1, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v5, v3, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 16, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v5
+; GFX7-GISEL-NEXT: v_min_i32_e32 v6, v6, v7
; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v4, v2
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v2, v0
+; GFX7-GISEL-NEXT: v_min3_i32 v3, v4, v5, v6
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
+; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v3, v0
; GFX7-GISEL-NEXT: v_min_i32_e32 v0, 0, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -2284,37 +2206,32 @@ define i16 @test_vector_reduce_smin_v16i16(<16 x i16> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v16i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_bfe_i32 v8, v0, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v9, v4, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v4, 16, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v8, v8, v9
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_bfe_i32 v4, v1, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v9, v5, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v5, v5, 16, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v4, v4, v9
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_bfe_i32 v5, v2, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v9, v6, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v12, v2, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v13, v6, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v2, v2, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v6, v6, 16, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v5, v5, v9
+; GFX7-GISEL-NEXT: v_min_i32_e32 v12, v12, v13
; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
; GFX7-GISEL-NEXT: v_bfe_i32 v6, v3, 0, 16
-; GFX7-GISEL-NEXT: v_bfe_i32 v9, v7, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v13, v7, 0, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v3, v3, 16, 16
; GFX7-GISEL-NEXT: v_bfe_i32 v7, v7, 16, 16
-; GFX7-GISEL-NEXT: v_min_i32_e32 v6, v6, v9
+; GFX7-GISEL-NEXT: v_bfe_i32 v8, v0, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v9, v4, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v0, v0, 16, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v4, v4, 16, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v10, v1, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v11, v5, 0, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v1, v1, 16, 16
+; GFX7-GISEL-NEXT: v_bfe_i32 v5, v5, 16, 16
; GFX7-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_min_i32_e32 v5, v8, v5
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v4, v6
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v5, v2
+; GFX7-GISEL-NEXT: v_min_i32_e32 v6, v6, v13
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_min3_i32 v1, v1, v5, v3
+; GFX7-GISEL-NEXT: v_min3_i32 v7, v8, v9, v12
+; GFX7-GISEL-NEXT: v_min3_i32 v2, v10, v11, v6
; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v2, v0
+; GFX7-GISEL-NEXT: v_min3_i32 v1, v7, v2, v0
; GFX7-GISEL-NEXT: v_min_i32_e32 v0, 0, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -2585,93 +2502,45 @@ entry:
}
define i32 @test_vector_reduce_smin_v3i32(<3 x i32> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_smin_v3i32:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_min3_i32 v0, v0, v1, v2
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_smin_v3i32:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_smin_v3i32:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_min3_i32 v0, v0, v1, v2
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_smin_v3i32:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_smin_v3i32:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_min3_i32 v0, v0, v1, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_smin_v3i32:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_smin_v3i32:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_min3_i32 v0, v0, v1, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_smin_v3i32:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_min3_i32 v0, v0, v1, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_smin_v3i32:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_smin_v3i32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_min3_i32 v0, v0, v1, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v3i32:
-; GFX11-SDAG: ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_min3_i32 v0, v0, v1, v2
-; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_smin_v3i32:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_min3_i32 v0, v0, v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: test_vector_reduce_smin_v3i32:
-; GFX11-GISEL: ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_smin_v3i32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_i32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v3i32:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_min3_i32 v0, v0, v1, v2
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_vector_reduce_smin_v3i32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_min3_i32 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: test_vector_reduce_smin_v3i32:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_vector_reduce_smin_v3i32:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_i32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.smin.v3i32(<3 x i32> %v)
ret i32 %res
@@ -2688,9 +2557,8 @@ define i32 @test_vector_reduce_smin_v4i32(<4 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v4i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_smin_v4i32:
@@ -2703,9 +2571,8 @@ define i32 @test_vector_reduce_smin_v4i32(<4 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_smin_v4i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v4i32:
@@ -2718,9 +2585,8 @@ define i32 @test_vector_reduce_smin_v4i32(<4 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v4i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
; GFX9-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_smin_v4i32:
@@ -2733,9 +2599,8 @@ define i32 @test_vector_reduce_smin_v4i32(<4 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smin_v4i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_smin_v4i32:
@@ -2749,10 +2614,9 @@ define i32 @test_vector_reduce_smin_v4i32(<4 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v4i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
; GFX11-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_smin_v4i32:
@@ -2774,10 +2638,9 @@ define i32 @test_vector_reduce_smin_v4i32(<4 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
; GFX12-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v)
@@ -2797,12 +2660,10 @@ define i32 @test_vector_reduce_smin_v8i32(<8 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v8i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
; GFX7-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_min3_i32 v1, v1, v5, v3
; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2818,12 +2679,10 @@ define i32 @test_vector_reduce_smin_v8i32(<8 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_smin_v8i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX8-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
; GFX8-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
; GFX8-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
+; GFX8-GISEL-NEXT: v_min3_i32 v0, v0, v4, v2
+; GFX8-GISEL-NEXT: v_min3_i32 v1, v1, v5, v3
; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2839,12 +2698,10 @@ define i32 @test_vector_reduce_smin_v8i32(<8 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v8i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
; GFX9-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
; GFX9-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
+; GFX9-GISEL-NEXT: v_min3_i32 v0, v0, v4, v2
+; GFX9-GISEL-NEXT: v_min3_i32 v1, v1, v5, v3
; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2860,12 +2717,10 @@ define i32 @test_vector_reduce_smin_v8i32(<8 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smin_v8i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX10-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
; GFX10-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
; GFX10-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
+; GFX10-GISEL-NEXT: v_min3_i32 v0, v0, v4, v2
+; GFX10-GISEL-NEXT: v_min3_i32 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2882,13 +2737,11 @@ define i32 @test_vector_reduce_smin_v8i32(<8 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v8i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX11-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
; GFX11-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
; GFX11-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX11-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
+; GFX11-GISEL-NEXT: v_min3_i32 v0, v0, v4, v2
+; GFX11-GISEL-NEXT: v_min3_i32 v1, v1, v5, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2914,13 +2767,11 @@ define i32 @test_vector_reduce_smin_v8i32(<8 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX12-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
; GFX12-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
; GFX12-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX12-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
+; GFX12-GISEL-NEXT: v_min3_i32 v0, v0, v4, v2
+; GFX12-GISEL-NEXT: v_min3_i32 v1, v1, v5, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2948,21 +2799,16 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v16i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v9
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v10
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, v3, v11
-; GFX7-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
; GFX7-GISEL-NEXT: v_min_i32_e32 v5, v5, v13
-; GFX7-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
; GFX7-GISEL-NEXT: v_min_i32_e32 v7, v7, v15
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
-; GFX7-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
+; GFX7-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
+; GFX7-GISEL-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX7-GISEL-NEXT: v_min3_i32 v3, v3, v11, v7
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v8, v4
+; GFX7-GISEL-NEXT: v_min3_i32 v2, v2, v10, v6
; GFX7-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_smin_v16i32:
@@ -2983,21 +2829,16 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_smin_v16i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX8-GISEL-NEXT: v_min_i32_e32 v1, v1, v9
-; GFX8-GISEL-NEXT: v_min_i32_e32 v2, v2, v10
-; GFX8-GISEL-NEXT: v_min_i32_e32 v3, v3, v11
-; GFX8-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
; GFX8-GISEL-NEXT: v_min_i32_e32 v5, v5, v13
-; GFX8-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
; GFX8-GISEL-NEXT: v_min_i32_e32 v7, v7, v15
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX8-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
-; GFX8-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
-; GFX8-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
+; GFX8-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
+; GFX8-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
+; GFX8-GISEL-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX8-GISEL-NEXT: v_min3_i32 v3, v3, v11, v7
+; GFX8-GISEL-NEXT: v_min3_i32 v0, v0, v8, v4
+; GFX8-GISEL-NEXT: v_min3_i32 v2, v2, v10, v6
; GFX8-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX8-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v16i32:
@@ -3018,21 +2859,16 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v16i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX9-GISEL-NEXT: v_min_i32_e32 v1, v1, v9
-; GFX9-GISEL-NEXT: v_min_i32_e32 v2, v2, v10
-; GFX9-GISEL-NEXT: v_min_i32_e32 v3, v3, v11
-; GFX9-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
; GFX9-GISEL-NEXT: v_min_i32_e32 v5, v5, v13
-; GFX9-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
; GFX9-GISEL-NEXT: v_min_i32_e32 v7, v7, v15
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
-; GFX9-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
-; GFX9-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
+; GFX9-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
+; GFX9-GISEL-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX9-GISEL-NEXT: v_min3_i32 v3, v3, v11, v7
+; GFX9-GISEL-NEXT: v_min3_i32 v0, v0, v8, v4
+; GFX9-GISEL-NEXT: v_min3_i32 v2, v2, v10, v6
; GFX9-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_smin_v16i32:
@@ -3053,21 +2889,16 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_smin_v16i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX10-GISEL-NEXT: v_min_i32_e32 v1, v1, v9
-; GFX10-GISEL-NEXT: v_min_i32_e32 v2, v2, v10
-; GFX10-GISEL-NEXT: v_min_i32_e32 v3, v3, v11
-; GFX10-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
; GFX10-GISEL-NEXT: v_min_i32_e32 v5, v5, v13
-; GFX10-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
; GFX10-GISEL-NEXT: v_min_i32_e32 v7, v7, v15
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX10-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
-; GFX10-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
-; GFX10-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
+; GFX10-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
+; GFX10-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
+; GFX10-GISEL-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX10-GISEL-NEXT: v_min3_i32 v3, v3, v11, v7
+; GFX10-GISEL-NEXT: v_min3_i32 v0, v0, v8, v4
+; GFX10-GISEL-NEXT: v_min3_i32 v2, v2, v10, v6
; GFX10-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_smin_v16i32:
@@ -3090,25 +2921,19 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v16i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX11-GISEL-NEXT: v_min_i32_e32 v1, v1, v9
-; GFX11-GISEL-NEXT: v_min_i32_e32 v2, v2, v10
-; GFX11-GISEL-NEXT: v_min_i32_e32 v3, v3, v11
-; GFX11-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
; GFX11-GISEL-NEXT: v_min_i32_e32 v5, v5, v13
-; GFX11-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
; GFX11-GISEL-NEXT: v_min_i32_e32 v7, v7, v15
+; GFX11-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
+; GFX11-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX11-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
+; GFX11-GISEL-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX11-GISEL-NEXT: v_min3_i32 v3, v3, v11, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
-; GFX11-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
+; GFX11-GISEL-NEXT: v_min3_i32 v0, v0, v8, v4
+; GFX11-GISEL-NEXT: v_min3_i32 v2, v2, v10, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_smin_v16i32:
@@ -3139,25 +2964,19 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX12-GISEL-NEXT: v_min_i32_e32 v1, v1, v9
-; GFX12-GISEL-NEXT: v_min_i32_e32 v2, v2, v10
-; GFX12-GISEL-NEXT: v_min_i32_e32 v3, v3, v11
-; GFX12-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
; GFX12-GISEL-NEXT: v_min_i32_e32 v5, v5, v13
-; GFX12-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
; GFX12-GISEL-NEXT: v_min_i32_e32 v7, v7, v15
+; GFX12-GISEL-NEXT: v_min_i32_e32 v4, v4, v12
+; GFX12-GISEL-NEXT: v_min_i32_e32 v6, v6, v14
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v4
-; GFX12-GISEL-NEXT: v_min_i32_e32 v1, v1, v5
+; GFX12-GISEL-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_min3_i32 v3, v3, v11, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_i32_e32 v2, v2, v6
-; GFX12-GISEL-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v2
+; GFX12-GISEL-NEXT: v_min3_i32 v0, v0, v8, v4
+; GFX12-GISEL-NEXT: v_min3_i32 v2, v2, v10, v6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_min3_i32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %v)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 78a8ec8d408d0..2b4a226274b41 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -147,9 +147,8 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umax_v3i8:
@@ -178,8 +177,10 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v3i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX9-GISEL-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_umax_v3i8:
@@ -196,9 +197,8 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX10-GISEL-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i8:
@@ -226,10 +226,9 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i8:
@@ -269,10 +268,9 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v1
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %v)
@@ -294,19 +292,16 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v4i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, 0, v2
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, 0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, 0, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, 0, v2
+; GFX7-GISEL-NEXT: v_max3_u32 v2, v2, 0, 0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, 0, v3
+; GFX7-GISEL-NEXT: v_max3_u32 v3, v3, 0, 0
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
@@ -359,17 +354,16 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v4i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_max_u16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX9-GISEL-NEXT: v_max_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: v_max_u16_e32 v1, 0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 8
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX9-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
-; GFX9-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
+; GFX9-GISEL-NEXT: v_max3_u16 v2, v2, 0, 0
+; GFX9-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
@@ -399,21 +393,18 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
; GFX10-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_u16 v4, v2, 0
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_u16 v2, v1, 0
-; GFX10-GISEL-NEXT: v_max_u16 v4, v4, 0
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX10-GISEL-NEXT: v_max3_u16 v5, v2, 0, 0
+; GFX10-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX10-GISEL-NEXT: v_max_u16 v6, v1, 0
+; GFX10-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v2, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX10-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -460,27 +451,21 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX11-GISEL-NEXT: v_max_u16 v4, v2, 0
-; GFX11-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_max_u16 v5, v1, 0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v2, v4, 0
-; GFX11-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX11-GISEL-NEXT: v_max3_u16 v5, v2, 0, 0
+; GFX11-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_max_u16 v4, v1, 0
+; GFX11-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -538,27 +523,21 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX12-GISEL-NEXT: v_max_u16 v4, v2, 0
-; GFX12-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_max_u16 v5, v1, 0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v2, v4, 0
-; GFX12-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX12-GISEL-NEXT: v_max3_u16 v5, v2, 0, 0
+; GFX12-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_max_u16 v4, v1, 0
+; GFX12-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v5
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -588,27 +567,23 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v8i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
+; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX7-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v4
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v6
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v4
-; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v7
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v3, v4
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, 0, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v3, v6
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_max3_u32 v1, v1, v5, v3
; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, 0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, 0, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, 0, v2
+; GFX7-GISEL-NEXT: v_max3_u32 v2, v2, 0, 0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, 0, v3
+; GFX7-GISEL-NEXT: v_max3_u32 v3, v3, 0, 0
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
@@ -674,20 +649,20 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v8i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX9-GISEL-NEXT: v_max_u16_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_max_u16_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: v_max_u16_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
-; GFX9-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
+; GFX9-GISEL-NEXT: v_max3_u16 v0, v0, v4, v2
+; GFX9-GISEL-NEXT: v_max3_u16 v1, v1, v5, v3
; GFX9-GISEL-NEXT: v_max_u16_e32 v0, v0, v1
; GFX9-GISEL-NEXT: v_max_u16_e32 v1, 0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX9-GISEL-NEXT: v_mov_b32_e32 v8, 0xff
-; GFX9-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
-; GFX9-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
+; GFX9-GISEL-NEXT: v_max3_u16 v2, v2, 0, 0
+; GFX9-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v8, v1
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
@@ -721,32 +696,28 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umax_v8i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX10-GISEL-NEXT: v_max_u16 v3, v3, v7
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX10-GISEL-NEXT: v_max_u16 v1, v1, v5
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, v7
; GFX10-GISEL-NEXT: v_max_u16 v2, v2, v6
+; GFX10-GISEL-NEXT: v_max3_u16 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v4
-; GFX10-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_u16 v4, v2, 0
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_u16 v2, v1, 0
-; GFX10-GISEL-NEXT: v_max_u16 v4, v4, 0
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX10-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX10-GISEL-NEXT: v_max3_u16 v0, v0, v4, v2
+; GFX10-GISEL-NEXT: v_max_u16 v4, v1, 0
+; GFX10-GISEL-NEXT: v_max3_u16 v2, v2, 0, 0
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v2, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX10-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -803,36 +774,30 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v8i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-GISEL-NEXT: v_max_u16 v1, v1, v5
-; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v6
+; GFX11-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-GISEL-NEXT: v_max_u16 v3, v3, v7
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_max_u16 v2, v2, v5
-; GFX11-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v4
-; GFX11-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX11-GISEL-NEXT: v_max_u16 v4, v2, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_max_u16 v2, v2, v6
+; GFX11-GISEL-NEXT: v_max3_u16 v1, v1, v5, v3
+; GFX11-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_max3_u16 v0, v0, v4, v2
; GFX11-GISEL-NEXT: v_max_u16 v5, v1, 0
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX11-GISEL-NEXT: v_max_u16 v2, v4, 0
+; GFX11-GISEL-NEXT: v_max3_u16 v2, v2, 0, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -905,36 +870,30 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX12-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-GISEL-NEXT: v_max_u16 v1, v1, v5
-; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v6
+; GFX12-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX12-GISEL-NEXT: v_max_u16 v3, v3, v7
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT: v_max_u16 v2, v2, v5
-; GFX12-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v4
-; GFX12-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX12-GISEL-NEXT: v_max_u16 v4, v2, 0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_max_u16 v2, v2, v6
+; GFX12-GISEL-NEXT: v_max3_u16 v1, v1, v5, v3
+; GFX12-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-NEXT: v_max3_u16 v0, v0, v4, v2
; GFX12-GISEL-NEXT: v_max_u16 v5, v1, 0
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX12-GISEL-NEXT: v_max_u16 v2, v4, 0
+; GFX12-GISEL-NEXT: v_max3_u16 v2, v2, 0, 0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -983,43 +942,36 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v16i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v8
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v10
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v8
-; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v11
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v3, v8
; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v12
-; GFX7-GISEL-NEXT: v_max_u32_e32 v4, v4, v8
+; GFX7-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX7-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
; GFX7-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v13
-; GFX7-GISEL-NEXT: v_max_u32_e32 v5, v5, v8
+; GFX7-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX7-GISEL-NEXT: v_max_u32_e32 v5, v5, v12
; GFX7-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v14
-; GFX7-GISEL-NEXT: v_max_u32_e32 v6, v6, v8
+; GFX7-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v14
+; GFX7-GISEL-NEXT: v_max_u32_e32 v6, v6, v12
; GFX7-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v15
-; GFX7-GISEL-NEXT: v_max_u32_e32 v7, v7, v8
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v15
+; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX7-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX7-GISEL-NEXT: v_max_u32_e32 v7, v7, v12
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX7-GISEL-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX7-GISEL-NEXT: v_max3_u32 v3, v3, v11, v7
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v8, v4
+; GFX7-GISEL-NEXT: v_max3_u32 v2, v2, v10, v6
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, 0, v2
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, 0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, 0, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, 0, v2
+; GFX7-GISEL-NEXT: v_max3_u32 v2, v2, 0, 0
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, 0, v3
+; GFX7-GISEL-NEXT: v_max3_u32 v3, v3, 0, 0
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
@@ -1111,28 +1063,29 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v16i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v2, v2, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v3, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v4, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX9-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX9-GISEL-NEXT: v_max_u16_sdwa v5, v5, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v6, v6, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_max_u16_sdwa v7, v7, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_max_u16_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_max_u16_e32 v1, v1, v5
-; GFX9-GISEL-NEXT: v_max_u16_e32 v2, v2, v6
-; GFX9-GISEL-NEXT: v_max_u16_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_max_u16_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-GISEL-NEXT: v_max_u16_sdwa v4, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_max_u16_sdwa v6, v6, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_max3_u16 v1, v1, v9, v5
+; GFX9-GISEL-NEXT: v_max3_u16 v3, v3, v11, v7
+; GFX9-GISEL-NEXT: v_max3_u16 v0, v0, v8, v4
+; GFX9-GISEL-NEXT: v_max3_u16 v2, v2, v10, v6
; GFX9-GISEL-NEXT: v_max_u16_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
-; GFX9-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
-; GFX9-GISEL-NEXT: v_max_u16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: v_max_u16_e32 v1, 0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX9-GISEL-NEXT: v_mov_b32_e32 v16, 0xff
-; GFX9-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
-; GFX9-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
+; GFX9-GISEL-NEXT: v_max3_u16 v2, v2, 0, 0
+; GFX9-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
; GFX9-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v16, v1
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
@@ -1182,46 +1135,39 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umax_v16i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX10-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v13
+; GFX10-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX10-GISEL-NEXT: v_and_b32_e32 v15, 0xff, v15
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v8
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX10-GISEL-NEXT: v_max_u16 v1, v1, v9
-; GFX10-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v10
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, v11
-; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX10-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v13
-; GFX10-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX10-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v15
+; GFX10-GISEL-NEXT: v_max_u16 v5, v5, v13
+; GFX10-GISEL-NEXT: v_max_u16 v7, v7, v15
; GFX10-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX10-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v14
+; GFX10-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX10-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX10-GISEL-NEXT: v_max_u16 v5, v5, v9
-; GFX10-GISEL-NEXT: v_max_u16 v7, v7, v10
-; GFX10-GISEL-NEXT: v_max_u16 v2, v2, v8
-; GFX10-GISEL-NEXT: v_max_u16 v6, v6, v11
+; GFX10-GISEL-NEXT: v_max3_u16 v1, v1, v9, v5
+; GFX10-GISEL-NEXT: v_max3_u16 v3, v3, v11, v7
+; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v10
+; GFX10-GISEL-NEXT: v_max_u16 v6, v6, v13
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX10-GISEL-NEXT: v_max_u16 v4, v4, v12
-; GFX10-GISEL-NEXT: v_max_u16 v1, v1, v5
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, v7
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
-; GFX10-GISEL-NEXT: v_max_u16 v2, v2, v6
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v4
; GFX10-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX10-GISEL-NEXT: v_max_u16 v4, v2, 0
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_u16 v2, v1, 0
-; GFX10-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX10-GISEL-NEXT: v_max_u16 v4, v4, 0
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_max3_u16 v2, v2, v5, v6
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 8
+; GFX10-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX10-GISEL-NEXT: v_max3_u16 v0, v0, v7, v4
+; GFX10-GISEL-NEXT: v_max_u16 v4, v1, 0
+; GFX10-GISEL-NEXT: v_max3_u16 v6, v2, 0, 0
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX10-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX10-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v6
; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v3
@@ -1313,53 +1259,43 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v16i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v13
+; GFX11-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-GISEL-NEXT: v_and_b32_e32 v15, 0xff, v15
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-GISEL-NEXT: v_max_u16 v1, v1, v9
-; GFX11-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v10
-; GFX11-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v13
-; GFX11-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v15
+; GFX11-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-GISEL-NEXT: v_max_u16 v5, v5, v13
+; GFX11-GISEL-NEXT: v_max_u16 v7, v7, v15
; GFX11-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-GISEL-NEXT: v_max_u16 v2, v2, v9
-; GFX11-GISEL-NEXT: v_max_u16 v3, v3, v10
-; GFX11-GISEL-NEXT: v_max_u16 v5, v5, v11
-; GFX11-GISEL-NEXT: v_max_u16 v7, v7, v13
-; GFX11-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v14
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v12
-; GFX11-GISEL-NEXT: v_max_u16 v1, v1, v5
-; GFX11-GISEL-NEXT: v_max_u16 v3, v3, v7
-; GFX11-GISEL-NEXT: v_max_u16 v5, v6, v9
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v8
-; GFX11-GISEL-NEXT: v_max_u16 v4, v4, v10
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_max3_u16 v1, v1, v9, v5
+; GFX11-GISEL-NEXT: v_max3_u16 v3, v3, v11, v7
+; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v14
+; GFX11-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v10
+; GFX11-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v12
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX11-GISEL-NEXT: v_max_u16 v2, v2, v5
-; GFX11-GISEL-NEXT: v_max_u16 v3, v3, 0
+; GFX11-GISEL-NEXT: v_max_u16 v5, v6, v5
+; GFX11-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v8
+; GFX11-GISEL-NEXT: v_max_u16 v4, v4, v9
+; GFX11-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX11-GISEL-NEXT: v_max_u16 v8, v1, 0
+; GFX11-GISEL-NEXT: v_max3_u16 v2, v2, v7, v5
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v4
-; GFX11-GISEL-NEXT: v_max_u16 v4, v1, 0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v5, v2, 0
-; GFX11-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v4, v5, 0
+; GFX11-GISEL-NEXT: v_max3_u16 v0, v0, v6, v4
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v8
+; GFX11-GISEL-NEXT: v_max3_u16 v5, v2, 0, 0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
@@ -1464,53 +1400,43 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v13
+; GFX12-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX12-GISEL-NEXT: v_and_b32_e32 v15, 0xff, v15
; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX12-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX12-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX12-GISEL-NEXT: v_max_u16 v1, v1, v9
-; GFX12-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v10
-; GFX12-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX12-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v13
-; GFX12-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v15
+; GFX12-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX12-GISEL-NEXT: v_max_u16 v5, v5, v13
+; GFX12-GISEL-NEXT: v_max_u16 v7, v7, v15
; GFX12-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX12-GISEL-NEXT: v_max_u16 v2, v2, v9
-; GFX12-GISEL-NEXT: v_max_u16 v3, v3, v10
-; GFX12-GISEL-NEXT: v_max_u16 v5, v5, v11
-; GFX12-GISEL-NEXT: v_max_u16 v7, v7, v13
-; GFX12-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v14
-; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX12-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v12
-; GFX12-GISEL-NEXT: v_max_u16 v1, v1, v5
-; GFX12-GISEL-NEXT: v_max_u16 v3, v3, v7
-; GFX12-GISEL-NEXT: v_max_u16 v5, v6, v9
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v8
-; GFX12-GISEL-NEXT: v_max_u16 v4, v4, v10
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-NEXT: v_max3_u16 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_max3_u16 v3, v3, v11, v7
+; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v14
+; GFX12-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v10
+; GFX12-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v12
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-GISEL-NEXT: v_max_u16 v1, v1, v3
-; GFX12-GISEL-NEXT: v_max_u16 v2, v2, v5
-; GFX12-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v4
-; GFX12-GISEL-NEXT: v_max_u16 v4, v1, 0
+; GFX12-GISEL-NEXT: v_max_u16 v5, v6, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v8
+; GFX12-GISEL-NEXT: v_max_u16 v4, v4, v9
+; GFX12-GISEL-NEXT: v_max3_u16 v3, v3, 0, 0
+; GFX12-GISEL-NEXT: v_max_u16 v8, v1, 0
+; GFX12-GISEL-NEXT: v_max3_u16 v2, v2, v7, v5
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v5, v2, 0
-; GFX12-GISEL-NEXT: v_max_u16 v3, v3, 0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v4, v5, 0
+; GFX12-GISEL-NEXT: v_max3_u16 v0, v0, v6, v4
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v1
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v8
+; GFX12-GISEL-NEXT: v_max3_u16 v5, v2, 0, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX12-GISEL-NEXT: v_and_or_b32 v0, 0xff, v0, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
@@ -1661,9 +1587,8 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_umax_v3i16:
@@ -1685,8 +1610,8 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v3i16:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_max_u16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_umax_v3i16:
@@ -1702,8 +1627,7 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_u16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i16:
@@ -1730,9 +1654,8 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_max_u16 v0, v0, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i16:
@@ -1771,9 +1694,8 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_max_u16 v0, v0, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i16 @llvm.vector.reduce.umax.v3i16(<3 x i16> %v)
@@ -1800,10 +1722,9 @@ define i16 @test_vector_reduce_umax_v4i16(<4 x i16> %v) {
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v2, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, 0, v1
+; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX7-GISEL-NEXT: v_max_u32_e32 v1, 0, v2
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1951,20 +1872,18 @@ define i16 @test_vector_reduce_umax_v8i16(<8 x i16> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v8i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v4, v6
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v5, v7
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v2, v3
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
+; GFX7-GISEL-NEXT: v_max3_u32 v1, v4, v6, v3
; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, 0, v1
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -2162,38 +2081,33 @@ define i16 @test_vector_reduce_umax_v16i16(<16 x i16> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v16i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v4
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v6
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7-GISEL-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_max_u32_e32 v4, v8, v12
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_max_u32_e32 v5, v9, v13
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v5
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
; GFX7-GISEL-NEXT: v_max_u32_e32 v6, v10, v14
; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
; GFX7-GISEL-NEXT: v_max_u32_e32 v7, v11, v15
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v4, v6
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v5, v7
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v2, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, 0, v1
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_max3_u32 v2, v8, v12, v6
+; GFX7-GISEL-NEXT: v_max3_u32 v1, v1, v5, v3
+; GFX7-GISEL-NEXT: v_max3_u32 v3, v9, v13, v7
+; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX7-GISEL-NEXT: v_max_u32_e32 v1, 0, v2
; GFX7-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2461,93 +2375,45 @@ entry:
}
define i32 @test_vector_reduce_umax_v3i32(<3 x i32> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_umax_v3i32:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_max3_u32 v0, v0, v1, v2
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_umax_v3i32:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_umax_v3i32:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_max3_u32 v0, v0, v1, v2
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_umax_v3i32:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_umax_v3i32:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_max3_u32 v0, v0, v1, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_umax_v3i32:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_umax_v3i32:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_max3_u32 v0, v0, v1, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_umax_v3i32:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_umax_v3i32:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_umax_v3i32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v3i32:
-; GFX11-SDAG: ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_max3_u32 v0, v0, v1, v2
-; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_umax_v3i32:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: test_vector_reduce_umax_v3i32:
-; GFX11-GISEL: ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_umax_v3i32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v3i32:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max3_u32 v0, v0, v1, v2
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_vector_reduce_umax_v3i32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: test_vector_reduce_umax_v3i32:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_vector_reduce_umax_v3i32:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %v)
ret i32 %res
@@ -2564,9 +2430,8 @@ define i32 @test_vector_reduce_umax_v4i32(<4 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v4i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umax_v4i32:
@@ -2579,9 +2444,8 @@ define i32 @test_vector_reduce_umax_v4i32(<4 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_umax_v4i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v4i32:
@@ -2594,9 +2458,8 @@ define i32 @test_vector_reduce_umax_v4i32(<4 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v4i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
; GFX9-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_umax_v4i32:
@@ -2609,9 +2472,8 @@ define i32 @test_vector_reduce_umax_v4i32(<4 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umax_v4i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_umax_v4i32:
@@ -2625,10 +2487,9 @@ define i32 @test_vector_reduce_umax_v4i32(<4 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v4i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_umax_v4i32:
@@ -2650,10 +2511,9 @@ define i32 @test_vector_reduce_umax_v4i32(<4 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
; GFX12-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %v)
@@ -2673,12 +2533,10 @@ define i32 @test_vector_reduce_umax_v8i32(<8 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v8i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_max3_u32 v1, v1, v5, v3
; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2694,12 +2552,10 @@ define i32 @test_vector_reduce_umax_v8i32(<8 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_umax_v8i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX8-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
; GFX8-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
; GFX8-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
+; GFX8-GISEL-NEXT: v_max3_u32 v0, v0, v4, v2
+; GFX8-GISEL-NEXT: v_max3_u32 v1, v1, v5, v3
; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2715,12 +2571,10 @@ define i32 @test_vector_reduce_umax_v8i32(<8 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v8i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
; GFX9-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
; GFX9-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
+; GFX9-GISEL-NEXT: v_max3_u32 v0, v0, v4, v2
+; GFX9-GISEL-NEXT: v_max3_u32 v1, v1, v5, v3
; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2736,12 +2590,10 @@ define i32 @test_vector_reduce_umax_v8i32(<8 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umax_v8i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX10-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
; GFX10-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
; GFX10-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
+; GFX10-GISEL-NEXT: v_max3_u32 v0, v0, v4, v2
+; GFX10-GISEL-NEXT: v_max3_u32 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2758,13 +2610,11 @@ define i32 @test_vector_reduce_umax_v8i32(<8 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v8i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
; GFX11-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
; GFX11-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
+; GFX11-GISEL-NEXT: v_max3_u32 v0, v0, v4, v2
+; GFX11-GISEL-NEXT: v_max3_u32 v1, v1, v5, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2790,13 +2640,11 @@ define i32 @test_vector_reduce_umax_v8i32(<8 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX12-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
; GFX12-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
; GFX12-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
-; GFX12-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
+; GFX12-GISEL-NEXT: v_max3_u32 v0, v0, v4, v2
+; GFX12-GISEL-NEXT: v_max3_u32 v1, v1, v5, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2824,21 +2672,16 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v16i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v9
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v10
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v3, v11
-; GFX7-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
; GFX7-GISEL-NEXT: v_max_u32_e32 v5, v5, v13
-; GFX7-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
; GFX7-GISEL-NEXT: v_max_u32_e32 v7, v7, v15
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
-; GFX7-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
+; GFX7-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
+; GFX7-GISEL-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX7-GISEL-NEXT: v_max3_u32 v3, v3, v11, v7
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v8, v4
+; GFX7-GISEL-NEXT: v_max3_u32 v2, v2, v10, v6
; GFX7-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umax_v16i32:
@@ -2859,21 +2702,16 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_umax_v16i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX8-GISEL-NEXT: v_max_u32_e32 v1, v1, v9
-; GFX8-GISEL-NEXT: v_max_u32_e32 v2, v2, v10
-; GFX8-GISEL-NEXT: v_max_u32_e32 v3, v3, v11
-; GFX8-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
; GFX8-GISEL-NEXT: v_max_u32_e32 v5, v5, v13
-; GFX8-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
; GFX8-GISEL-NEXT: v_max_u32_e32 v7, v7, v15
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX8-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
-; GFX8-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
-; GFX8-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
+; GFX8-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
+; GFX8-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
+; GFX8-GISEL-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX8-GISEL-NEXT: v_max3_u32 v3, v3, v11, v7
+; GFX8-GISEL-NEXT: v_max3_u32 v0, v0, v8, v4
+; GFX8-GISEL-NEXT: v_max3_u32 v2, v2, v10, v6
; GFX8-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX8-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v16i32:
@@ -2894,21 +2732,16 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v16i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX9-GISEL-NEXT: v_max_u32_e32 v1, v1, v9
-; GFX9-GISEL-NEXT: v_max_u32_e32 v2, v2, v10
-; GFX9-GISEL-NEXT: v_max_u32_e32 v3, v3, v11
-; GFX9-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
; GFX9-GISEL-NEXT: v_max_u32_e32 v5, v5, v13
-; GFX9-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
; GFX9-GISEL-NEXT: v_max_u32_e32 v7, v7, v15
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
-; GFX9-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
-; GFX9-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
+; GFX9-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
+; GFX9-GISEL-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX9-GISEL-NEXT: v_max3_u32 v3, v3, v11, v7
+; GFX9-GISEL-NEXT: v_max3_u32 v0, v0, v8, v4
+; GFX9-GISEL-NEXT: v_max3_u32 v2, v2, v10, v6
; GFX9-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_umax_v16i32:
@@ -2929,21 +2762,16 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umax_v16i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX10-GISEL-NEXT: v_max_u32_e32 v1, v1, v9
-; GFX10-GISEL-NEXT: v_max_u32_e32 v2, v2, v10
-; GFX10-GISEL-NEXT: v_max_u32_e32 v3, v3, v11
-; GFX10-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
; GFX10-GISEL-NEXT: v_max_u32_e32 v5, v5, v13
-; GFX10-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
; GFX10-GISEL-NEXT: v_max_u32_e32 v7, v7, v15
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX10-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
-; GFX10-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
-; GFX10-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
+; GFX10-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
+; GFX10-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
+; GFX10-GISEL-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX10-GISEL-NEXT: v_max3_u32 v3, v3, v11, v7
+; GFX10-GISEL-NEXT: v_max3_u32 v0, v0, v8, v4
+; GFX10-GISEL-NEXT: v_max3_u32 v2, v2, v10, v6
; GFX10-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX10-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_umax_v16i32:
@@ -2966,25 +2794,19 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v16i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v9
-; GFX11-GISEL-NEXT: v_max_u32_e32 v2, v2, v10
-; GFX11-GISEL-NEXT: v_max_u32_e32 v3, v3, v11
-; GFX11-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
; GFX11-GISEL-NEXT: v_max_u32_e32 v5, v5, v13
-; GFX11-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
; GFX11-GISEL-NEXT: v_max_u32_e32 v7, v7, v15
+; GFX11-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
+; GFX11-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
+; GFX11-GISEL-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX11-GISEL-NEXT: v_max3_u32 v3, v3, v11, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
-; GFX11-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
+; GFX11-GISEL-NEXT: v_max3_u32 v0, v0, v8, v4
+; GFX11-GISEL-NEXT: v_max3_u32 v2, v2, v10, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_umax_v16i32:
@@ -3015,25 +2837,19 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX12-GISEL-NEXT: v_max_u32_e32 v1, v1, v9
-; GFX12-GISEL-NEXT: v_max_u32_e32 v2, v2, v10
-; GFX12-GISEL-NEXT: v_max_u32_e32 v3, v3, v11
-; GFX12-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
; GFX12-GISEL-NEXT: v_max_u32_e32 v5, v5, v13
-; GFX12-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
; GFX12-GISEL-NEXT: v_max_u32_e32 v7, v7, v15
+; GFX12-GISEL-NEXT: v_max_u32_e32 v4, v4, v12
+; GFX12-GISEL-NEXT: v_max_u32_e32 v6, v6, v14
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v4
-; GFX12-GISEL-NEXT: v_max_u32_e32 v1, v1, v5
+; GFX12-GISEL-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_max3_u32 v3, v3, v11, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_max_u32_e32 v2, v2, v6
-; GFX12-GISEL-NEXT: v_max_u32_e32 v3, v3, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v2
+; GFX12-GISEL-NEXT: v_max3_u32 v0, v0, v8, v4
+; GFX12-GISEL-NEXT: v_max3_u32 v2, v2, v10, v6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_max_u32_e32 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %v)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 5b2c1c3134acd..bed5e861d8753 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -147,9 +147,8 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umin_v3i8:
@@ -178,8 +177,10 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v3i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX9-GISEL-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_umin_v3i8:
@@ -196,9 +197,8 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX10-GISEL-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i8:
@@ -226,10 +226,9 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i8:
@@ -269,10 +268,9 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v1
-; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i8 @llvm.vector.reduce.umin.v3i8(<3 x i8> %v)
@@ -294,13 +292,12 @@ define i8 @test_vector_reduce_umin_v4i8(<4 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v4i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v2
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umin_v4i8:
@@ -334,9 +331,10 @@ define i8 @test_vector_reduce_umin_v4i8(<4 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v4i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX9-GISEL-NEXT: v_min_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -357,13 +355,12 @@ define i8 @test_vector_reduce_umin_v4i8(<4 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v4i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v2
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX10-GISEL-NEXT: v_min_u16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX10-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -403,15 +400,14 @@ define i8 @test_vector_reduce_umin_v4i8(<4 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v4i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v2
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_u16 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX11-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -463,15 +459,14 @@ define i8 @test_vector_reduce_umin_v4i8(<4 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v2
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_u16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX12-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -501,20 +496,18 @@ define i8 @test_vector_reduce_umin_v8i8(<8 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v8i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
+; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX7-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v4
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v6
-; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v4
-; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v7
-; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v3, v4
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
+; GFX7-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v3, v6
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_min3_u32 v1, v1, v5, v3
; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -563,12 +556,14 @@ define i8 @test_vector_reduce_umin_v8i8(<8 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v8i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX9-GISEL-NEXT: v_min_u16_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_min_u16_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: v_min_u16_e32 v1, v1, v3
+; GFX9-GISEL-NEXT: v_min3_u16 v0, v0, v4, v2
+; GFX9-GISEL-NEXT: v_min3_u16 v1, v1, v5, v3
; GFX9-GISEL-NEXT: v_min_u16_e32 v0, v0, v1
; GFX9-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -597,20 +592,18 @@ define i8 @test_vector_reduce_umin_v8i8(<8 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v8i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v4
-; GFX10-GISEL-NEXT: v_min_u16 v1, v1, v5
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-GISEL-NEXT: v_min_u16 v2, v2, v6
; GFX10-GISEL-NEXT: v_min_u16 v3, v3, v7
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_min_u16 v1, v1, v3
+; GFX10-GISEL-NEXT: v_min3_u16 v0, v0, v4, v2
+; GFX10-GISEL-NEXT: v_min3_u16 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v1
; GFX10-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -667,24 +660,21 @@ define i8 @test_vector_reduce_umin_v8i8(<8 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v8i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v4
-; GFX11-GISEL-NEXT: v_min_u16 v1, v1, v5
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-GISEL-NEXT: v_min_u16 v2, v2, v6
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_min_u16 v3, v3, v7
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_u16 v1, v1, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_min3_u16 v0, v0, v4, v2
+; GFX11-GISEL-NEXT: v_min3_u16 v1, v1, v5, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -752,24 +742,21 @@ define i8 @test_vector_reduce_umin_v8i8(<8 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX12-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX12-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v4
-; GFX12-GISEL-NEXT: v_min_u16 v1, v1, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX12-GISEL-NEXT: v_min_u16 v2, v2, v6
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_min_u16 v3, v3, v7
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_u16 v1, v1, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_min3_u16 v0, v0, v4, v2
+; GFX12-GISEL-NEXT: v_min3_u16 v1, v1, v5, v3
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -813,37 +800,32 @@ define i8 @test_vector_reduce_umin_v16i8(<16 x i8> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v16i8:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v8
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v10
-; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v8
-; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v11
-; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v3, v8
; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v12
-; GFX7-GISEL-NEXT: v_min_u32_e32 v4, v4, v8
+; GFX7-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX7-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
; GFX7-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v13
-; GFX7-GISEL-NEXT: v_min_u32_e32 v5, v5, v8
+; GFX7-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX7-GISEL-NEXT: v_min_u32_e32 v5, v5, v12
; GFX7-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v14
-; GFX7-GISEL-NEXT: v_min_u32_e32 v6, v6, v8
+; GFX7-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v14
+; GFX7-GISEL-NEXT: v_min_u32_e32 v6, v6, v12
; GFX7-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v15
-; GFX7-GISEL-NEXT: v_min_u32_e32 v7, v7, v8
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
-; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v15
+; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX7-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX7-GISEL-NEXT: v_min_u32_e32 v7, v7, v12
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX7-GISEL-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX7-GISEL-NEXT: v_min3_u32 v3, v3, v11, v7
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v8, v4
+; GFX7-GISEL-NEXT: v_min3_u32 v2, v2, v10, v6
; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umin_v16i8:
@@ -917,21 +899,24 @@ define i8 @test_vector_reduce_umin_v16i8(<16 x i8> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v16i8:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v2, v2, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v3, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v4, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX9-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX9-GISEL-NEXT: v_min_u16_sdwa v5, v5, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v6, v6, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-GISEL-NEXT: v_min_u16_sdwa v7, v7, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-GISEL-NEXT: v_min_u16_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_min_u16_e32 v1, v1, v5
-; GFX9-GISEL-NEXT: v_min_u16_e32 v2, v2, v6
-; GFX9-GISEL-NEXT: v_min_u16_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_min_u16_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-GISEL-NEXT: v_min_u16_sdwa v4, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_min_u16_sdwa v6, v6, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-GISEL-NEXT: v_min3_u16 v1, v1, v9, v5
+; GFX9-GISEL-NEXT: v_min3_u16 v3, v3, v11, v7
+; GFX9-GISEL-NEXT: v_min3_u16 v0, v0, v8, v4
+; GFX9-GISEL-NEXT: v_min3_u16 v2, v2, v10, v6
; GFX9-GISEL-NEXT: v_min_u16_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_min_u16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -975,37 +960,32 @@ define i8 @test_vector_reduce_umin_v16i8(<16 x i8> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v16i8:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX10-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v13
+; GFX10-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX10-GISEL-NEXT: v_and_b32_e32 v15, 0xff, v15
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX10-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v8
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-GISEL-NEXT: v_min_u16 v1, v1, v9
-; GFX10-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v11
-; GFX10-GISEL-NEXT: v_min_u16 v2, v2, v10
+; GFX10-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX10-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX10-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v12
-; GFX10-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX10-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v13
+; GFX10-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX10-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX10-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v14
-; GFX10-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX10-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v15
-; GFX10-GISEL-NEXT: v_min_u16 v3, v3, v8
-; GFX10-GISEL-NEXT: v_min_u16 v4, v4, v9
-; GFX10-GISEL-NEXT: v_min_u16 v5, v5, v10
-; GFX10-GISEL-NEXT: v_min_u16 v6, v6, v11
-; GFX10-GISEL-NEXT: v_min_u16 v7, v7, v12
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v4
-; GFX10-GISEL-NEXT: v_min_u16 v1, v1, v5
-; GFX10-GISEL-NEXT: v_min_u16 v2, v2, v6
-; GFX10-GISEL-NEXT: v_min_u16 v3, v3, v7
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v2
+; GFX10-GISEL-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX10-GISEL-NEXT: v_min_u16 v5, v5, v13
+; GFX10-GISEL-NEXT: v_min_u16 v7, v7, v15
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX10-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX10-GISEL-NEXT: v_min_u16 v4, v4, v12
+; GFX10-GISEL-NEXT: v_min_u16 v6, v6, v14
+; GFX10-GISEL-NEXT: v_min3_u16 v1, v1, v9, v5
+; GFX10-GISEL-NEXT: v_min3_u16 v3, v3, v11, v7
+; GFX10-GISEL-NEXT: v_min3_u16 v0, v0, v8, v4
+; GFX10-GISEL-NEXT: v_min3_u16 v2, v2, v10, v6
; GFX10-GISEL-NEXT: v_min_u16 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX10-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1094,41 +1074,35 @@ define i8 @test_vector_reduce_umin_v16i8(<16 x i8> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v16i8:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v13
+; GFX11-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-GISEL-NEXT: v_and_b32_e32 v15, 0xff, v15
; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v8
; GFX11-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-GISEL-NEXT: v_min_u16 v1, v1, v9
-; GFX11-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v11
-; GFX11-GISEL-NEXT: v_min_u16 v2, v2, v10
+; GFX11-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v12
-; GFX11-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v13
+; GFX11-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v14
-; GFX11-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v15
-; GFX11-GISEL-NEXT: v_min_u16 v3, v3, v8
-; GFX11-GISEL-NEXT: v_min_u16 v4, v4, v9
-; GFX11-GISEL-NEXT: v_min_u16 v5, v5, v10
-; GFX11-GISEL-NEXT: v_min_u16 v6, v6, v11
-; GFX11-GISEL-NEXT: v_min_u16 v7, v7, v12
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v4
-; GFX11-GISEL-NEXT: v_min_u16 v1, v1, v5
+; GFX11-GISEL-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-GISEL-NEXT: v_min_u16 v5, v5, v13
+; GFX11-GISEL-NEXT: v_min_u16 v7, v7, v15
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-GISEL-NEXT: v_min_u16 v4, v4, v12
+; GFX11-GISEL-NEXT: v_min_u16 v6, v6, v14
+; GFX11-GISEL-NEXT: v_min3_u16 v1, v1, v9, v5
+; GFX11-GISEL-NEXT: v_min3_u16 v3, v3, v11, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_u16 v2, v2, v6
-; GFX11-GISEL-NEXT: v_min_u16 v3, v3, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v2
+; GFX11-GISEL-NEXT: v_min3_u16 v0, v0, v8, v4
+; GFX11-GISEL-NEXT: v_min3_u16 v2, v2, v10, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_u16 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX11-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1229,41 +1203,35 @@ define i8 @test_vector_reduce_umin_v16i8(<16 x i8> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v13, 0xff, v13
+; GFX12-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX12-GISEL-NEXT: v_and_b32_e32 v15, 0xff, v15
; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX12-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX12-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v8
; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-GISEL-NEXT: v_min_u16 v1, v1, v9
-; GFX12-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v11
-; GFX12-GISEL-NEXT: v_min_u16 v2, v2, v10
+; GFX12-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX12-GISEL-NEXT: v_and_b32_e32 v9, 0xff, v12
-; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX12-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v13
+; GFX12-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX12-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX12-GISEL-NEXT: v_and_b32_e32 v11, 0xff, v14
-; GFX12-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX12-GISEL-NEXT: v_and_b32_e32 v12, 0xff, v15
-; GFX12-GISEL-NEXT: v_min_u16 v3, v3, v8
-; GFX12-GISEL-NEXT: v_min_u16 v4, v4, v9
-; GFX12-GISEL-NEXT: v_min_u16 v5, v5, v10
-; GFX12-GISEL-NEXT: v_min_u16 v6, v6, v11
-; GFX12-GISEL-NEXT: v_min_u16 v7, v7, v12
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v4
-; GFX12-GISEL-NEXT: v_min_u16 v1, v1, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX12-GISEL-NEXT: v_min_u16 v5, v5, v13
+; GFX12-GISEL-NEXT: v_min_u16 v7, v7, v15
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX12-GISEL-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX12-GISEL-NEXT: v_min_u16 v4, v4, v12
+; GFX12-GISEL-NEXT: v_min_u16 v6, v6, v14
+; GFX12-GISEL-NEXT: v_min3_u16 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_min3_u16 v3, v3, v11, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_u16 v2, v2, v6
-; GFX12-GISEL-NEXT: v_min_u16 v3, v3, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v2
+; GFX12-GISEL-NEXT: v_min3_u16 v0, v0, v8, v4
+; GFX12-GISEL-NEXT: v_min3_u16 v2, v2, v10, v6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_u16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX12-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -1400,9 +1368,8 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_umin_v3i16:
@@ -1425,8 +1392,8 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v3i16:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_min_u16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_umin_v3i16:
@@ -1442,8 +1409,7 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i16:
@@ -1470,9 +1436,8 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v2
-; GFX11-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i16:
@@ -1511,9 +1476,8 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v2
-; GFX12-GISEL-NEXT: v_min_u16 v0, v0, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i16 @llvm.vector.reduce.umin.v3i16(<3 x i16> %v)
@@ -1540,9 +1504,8 @@ define i16 @test_vector_reduce_umin_v4i16(<4 x i16> %v) {
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v2, v3
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umin_v4i16:
@@ -1688,20 +1651,18 @@ define i16 @test_vector_reduce_umin_v8i16(<8 x i16> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v8i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v4, v6
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v5, v7
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v2, v3
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
+; GFX7-GISEL-NEXT: v_min3_u32 v1, v4, v6, v3
; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1896,37 +1857,32 @@ define i16 @test_vector_reduce_umin_v16i16(<16 x i16> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v16i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v4
-; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v6
; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX7-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7-GISEL-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_min_u32_e32 v4, v8, v12
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_min_u32_e32 v5, v9, v13
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v5
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
; GFX7-GISEL-NEXT: v_min_u32_e32 v6, v10, v14
; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
; GFX7-GISEL-NEXT: v_min_u32_e32 v7, v11, v15
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v4, v6
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v5, v7
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v2, v3
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_min3_u32 v2, v8, v12, v6
+; GFX7-GISEL-NEXT: v_min3_u32 v1, v1, v5, v3
+; GFX7-GISEL-NEXT: v_min3_u32 v3, v9, v13, v7
+; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v3
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umin_v16i16:
@@ -2192,93 +2148,45 @@ entry:
}
define i32 @test_vector_reduce_umin_v3i32(<3 x i32> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_umin_v3i32:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_min3_u32 v0, v0, v1, v2
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_umin_v3i32:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_umin_v3i32:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_min3_u32 v0, v0, v1, v2
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_umin_v3i32:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_umin_v3i32:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_min3_u32 v0, v0, v1, v2
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_umin_v3i32:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_umin_v3i32:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_min3_u32 v0, v0, v1, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_umin_v3i32:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_min3_u32 v0, v0, v1, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_umin_v3i32:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_umin_v3i32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_min3_u32 v0, v0, v1, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v3i32:
-; GFX11-SDAG: ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_min3_u32 v0, v0, v1, v2
-; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_umin_v3i32:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_min3_u32 v0, v0, v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: test_vector_reduce_umin_v3i32:
-; GFX11-GISEL: ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_umin_v3i32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min3_u32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v3i32:
-; GFX12-SDAG: ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_min3_u32 v0, v0, v1, v2
-; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_vector_reduce_umin_v3i32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_min3_u32 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-GISEL-LABEL: test_vector_reduce_umin_v3i32:
-; GFX12-GISEL: ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: test_vector_reduce_umin_v3i32:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_u32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.umin.v3i32(<3 x i32> %v)
ret i32 %res
@@ -2295,9 +2203,8 @@ define i32 @test_vector_reduce_umin_v4i32(<4 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v4i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umin_v4i32:
@@ -2310,9 +2217,8 @@ define i32 @test_vector_reduce_umin_v4i32(<4 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_umin_v4i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umin_v4i32:
@@ -2325,9 +2231,8 @@ define i32 @test_vector_reduce_umin_v4i32(<4 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v4i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
; GFX9-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_umin_v4i32:
@@ -2340,9 +2245,8 @@ define i32 @test_vector_reduce_umin_v4i32(<4 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v4i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_umin_v4i32:
@@ -2356,10 +2260,9 @@ define i32 @test_vector_reduce_umin_v4i32(<4 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v4i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
; GFX11-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_umin_v4i32:
@@ -2381,10 +2284,9 @@ define i32 @test_vector_reduce_umin_v4i32(<4 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
; GFX12-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %v)
@@ -2404,12 +2306,10 @@ define i32 @test_vector_reduce_umin_v8i32(<8 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v8i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v4, v2
+; GFX7-GISEL-NEXT: v_min3_u32 v1, v1, v5, v3
; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2425,12 +2325,10 @@ define i32 @test_vector_reduce_umin_v8i32(<8 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_umin_v8i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX8-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
; GFX8-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
; GFX8-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
+; GFX8-GISEL-NEXT: v_min3_u32 v0, v0, v4, v2
+; GFX8-GISEL-NEXT: v_min3_u32 v1, v1, v5, v3
; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2446,12 +2344,10 @@ define i32 @test_vector_reduce_umin_v8i32(<8 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v8i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
; GFX9-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
; GFX9-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
+; GFX9-GISEL-NEXT: v_min3_u32 v0, v0, v4, v2
+; GFX9-GISEL-NEXT: v_min3_u32 v1, v1, v5, v3
; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2467,12 +2363,10 @@ define i32 @test_vector_reduce_umin_v8i32(<8 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v8i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
; GFX10-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
; GFX10-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
+; GFX10-GISEL-NEXT: v_min3_u32 v0, v0, v4, v2
+; GFX10-GISEL-NEXT: v_min3_u32 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2489,13 +2383,11 @@ define i32 @test_vector_reduce_umin_v8i32(<8 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v8i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX11-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
; GFX11-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
; GFX11-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX11-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
+; GFX11-GISEL-NEXT: v_min3_u32 v0, v0, v4, v2
+; GFX11-GISEL-NEXT: v_min3_u32 v1, v1, v5, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2521,13 +2413,11 @@ define i32 @test_vector_reduce_umin_v8i32(<8 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX12-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
; GFX12-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
; GFX12-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
-; GFX12-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
+; GFX12-GISEL-NEXT: v_min3_u32 v0, v0, v4, v2
+; GFX12-GISEL-NEXT: v_min3_u32 v1, v1, v5, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2555,21 +2445,16 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v16i32:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v9
-; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v10
-; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v3, v11
-; GFX7-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
; GFX7-GISEL-NEXT: v_min_u32_e32 v5, v5, v13
-; GFX7-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
; GFX7-GISEL-NEXT: v_min_u32_e32 v7, v7, v15
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
-; GFX7-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
-; GFX7-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
+; GFX7-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
+; GFX7-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
+; GFX7-GISEL-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX7-GISEL-NEXT: v_min3_u32 v3, v3, v11, v7
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v8, v4
+; GFX7-GISEL-NEXT: v_min3_u32 v2, v2, v10, v6
; GFX7-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX7-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-SDAG-LABEL: test_vector_reduce_umin_v16i32:
@@ -2590,21 +2475,16 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX8-GISEL-LABEL: test_vector_reduce_umin_v16i32:
; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX8-GISEL-NEXT: v_min_u32_e32 v1, v1, v9
-; GFX8-GISEL-NEXT: v_min_u32_e32 v2, v2, v10
-; GFX8-GISEL-NEXT: v_min_u32_e32 v3, v3, v11
-; GFX8-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
; GFX8-GISEL-NEXT: v_min_u32_e32 v5, v5, v13
-; GFX8-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
; GFX8-GISEL-NEXT: v_min_u32_e32 v7, v7, v15
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX8-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
-; GFX8-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
-; GFX8-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
+; GFX8-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
+; GFX8-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
+; GFX8-GISEL-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX8-GISEL-NEXT: v_min3_u32 v3, v3, v11, v7
+; GFX8-GISEL-NEXT: v_min3_u32 v0, v0, v8, v4
+; GFX8-GISEL-NEXT: v_min3_u32 v2, v2, v10, v6
; GFX8-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX8-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umin_v16i32:
@@ -2625,21 +2505,16 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v16i32:
; GFX9-GISEL: ; %bb.0: ; %entry
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX9-GISEL-NEXT: v_min_u32_e32 v1, v1, v9
-; GFX9-GISEL-NEXT: v_min_u32_e32 v2, v2, v10
-; GFX9-GISEL-NEXT: v_min_u32_e32 v3, v3, v11
-; GFX9-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
; GFX9-GISEL-NEXT: v_min_u32_e32 v5, v5, v13
-; GFX9-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
; GFX9-GISEL-NEXT: v_min_u32_e32 v7, v7, v15
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX9-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
-; GFX9-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
-; GFX9-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
+; GFX9-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
+; GFX9-GISEL-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX9-GISEL-NEXT: v_min3_u32 v3, v3, v11, v7
+; GFX9-GISEL-NEXT: v_min3_u32 v0, v0, v8, v4
+; GFX9-GISEL-NEXT: v_min3_u32 v2, v2, v10, v6
; GFX9-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX9-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_umin_v16i32:
@@ -2660,21 +2535,16 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v16i32:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v1, v9
-; GFX10-GISEL-NEXT: v_min_u32_e32 v2, v2, v10
-; GFX10-GISEL-NEXT: v_min_u32_e32 v3, v3, v11
-; GFX10-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
; GFX10-GISEL-NEXT: v_min_u32_e32 v5, v5, v13
-; GFX10-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
; GFX10-GISEL-NEXT: v_min_u32_e32 v7, v7, v15
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
-; GFX10-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
-; GFX10-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
+; GFX10-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
+; GFX10-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
+; GFX10-GISEL-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX10-GISEL-NEXT: v_min3_u32 v3, v3, v11, v7
+; GFX10-GISEL-NEXT: v_min3_u32 v0, v0, v8, v4
+; GFX10-GISEL-NEXT: v_min3_u32 v2, v2, v10, v6
; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: test_vector_reduce_umin_v16i32:
@@ -2697,25 +2567,19 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v16i32:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX11-GISEL-NEXT: v_min_u32_e32 v1, v1, v9
-; GFX11-GISEL-NEXT: v_min_u32_e32 v2, v2, v10
-; GFX11-GISEL-NEXT: v_min_u32_e32 v3, v3, v11
-; GFX11-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
; GFX11-GISEL-NEXT: v_min_u32_e32 v5, v5, v13
-; GFX11-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
; GFX11-GISEL-NEXT: v_min_u32_e32 v7, v7, v15
+; GFX11-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
+; GFX11-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX11-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
+; GFX11-GISEL-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX11-GISEL-NEXT: v_min3_u32 v3, v3, v11, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
-; GFX11-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
+; GFX11-GISEL-NEXT: v_min3_u32 v0, v0, v8, v4
+; GFX11-GISEL-NEXT: v_min3_u32 v2, v2, v10, v6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_umin_v16i32:
@@ -2746,25 +2610,19 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX12-GISEL-NEXT: v_min_u32_e32 v1, v1, v9
-; GFX12-GISEL-NEXT: v_min_u32_e32 v2, v2, v10
-; GFX12-GISEL-NEXT: v_min_u32_e32 v3, v3, v11
-; GFX12-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
; GFX12-GISEL-NEXT: v_min_u32_e32 v5, v5, v13
-; GFX12-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
; GFX12-GISEL-NEXT: v_min_u32_e32 v7, v7, v15
+; GFX12-GISEL-NEXT: v_min_u32_e32 v4, v4, v12
+; GFX12-GISEL-NEXT: v_min_u32_e32 v6, v6, v14
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v4
-; GFX12-GISEL-NEXT: v_min_u32_e32 v1, v1, v5
+; GFX12-GISEL-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_min3_u32 v3, v3, v11, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_min_u32_e32 v2, v2, v6
-; GFX12-GISEL-NEXT: v_min_u32_e32 v3, v3, v7
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v2
+; GFX12-GISEL-NEXT: v_min3_u32 v0, v0, v8, v4
+; GFX12-GISEL-NEXT: v_min3_u32 v2, v2, v10, v6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_u32_e32 v1, v1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %v)
>From cf65c2e6ef987ae242789f2f76ebdd0b47dec1d4 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 00:25:56 +0800
Subject: [PATCH 07/13] cttz cclz changes
---
llvm/test/CodeGen/AMDGPU/ctlz.ll | 17 +++++++----------
llvm/test/CodeGen/AMDGPU/cttz.ll | 8 +++-----
2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll
index f0827bc60483e..f16e5f1eedb47 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -862,11 +862,10 @@ define amdgpu_kernel void @v_ctlz_i64(ptr addrspace(1) noalias %out, ptr addrspa
; GFX10-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v0, v0
-; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1
-; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v3, v1
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 64, v0
+; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp
+; GFX10-GISEL-NEXT: v_min3_u32 v0, v3, v0, 64
; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
;
@@ -992,8 +991,7 @@ define amdgpu_kernel void @v_ctlz_i64_trunc(ptr addrspace(1) noalias %out, ptr a
; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1
; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v2, v2
; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v1, v1, 32 clamp
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v2, v1
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 64, v1
+; GFX10-GISEL-NEXT: v_min3_u32 v1, v2, v1, 64
; GFX10-GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
;
@@ -1744,11 +1742,10 @@ define amdgpu_kernel void @v_ctlz_i64_sel_ne_bitwidth(ptr addrspace(1) noalias %
; GFX10-GISEL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v0, v0
-; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v1, v1
-; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_ffbh_u32_e32 v2, v1
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 64, v0
+; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp
+; GFX10-GISEL-NEXT: v_min3_u32 v0, v2, v0, 64
; GFX10-GISEL-NEXT: v_cmp_ne_u64_e32 vcc_lo, 64, v[0:1]
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v3, -1, 0, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/cttz.ll b/llvm/test/CodeGen/AMDGPU/cttz.ll
index bdad7e61f032f..919b175a3a3eb 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz.ll
@@ -750,10 +750,9 @@ define amdgpu_kernel void @v_cttz_i64(ptr addrspace(1) noalias %out, ptr addrspa
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v1
; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v0, v0
-; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v1, v1, 32 clamp
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v3, v1, 32 clamp
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-GISEL-NEXT: v_min_u32_e32 v0, 64, v0
+; GFX10-GISEL-NEXT: v_min3_u32 v0, v0, v3, 64
; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -861,8 +860,7 @@ define amdgpu_kernel void @v_cttz_i64_trunc(ptr addrspace(1) noalias %out, ptr a
; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v2, v2
; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v1
; GFX10-GISEL-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, v1, v2
-; GFX10-GISEL-NEXT: v_min_u32_e32 v1, 64, v1
+; GFX10-GISEL-NEXT: v_min3_u32 v1, v1, v2, 64
; GFX10-GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
>From b3aaed6023f3ef08402ef7a31a3b4cb5ffe19570 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 03:48:06 +0800
Subject: [PATCH 08/13] update target gfx1200 for integer minmax
---
.../AMDGPU/GlobalISel/min3-max3-combine.ll | 154 +++++++++++++++++-
1 file changed, 153 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
index 855f904554986..ecc3ffb2ca672 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
@@ -1,12 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
-
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
define i32 @test_smin3(i32 %a, i32 %b, i32 %c) {
; GFX10-LABEL: test_smin3:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min3_i32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_smin3:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_i32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
%min2 = call i32 @llvm.smin.i32(i32 %min1, i32 %c)
ret i32 %min2
@@ -18,6 +28,16 @@ define i32 @test_smin3_with_constants(i32 %a, i32 %b) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min3_i32 v0, v0, v1, 7
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_smin3_with_constants:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_i32 v0, v0, v1, 7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
%min2 = call i32 @llvm.smin.i32(i32 %min1, i32 7)
ret i32 %min2
@@ -30,6 +50,18 @@ define i32 @test_smin3_smin_umin(i32 %a, i32 %b) {
; GFX10-NEXT: v_min_i32_e32 v0, v0, v1
; GFX10-NEXT: v_min_u32_e32 v0, 7, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_smin3_smin_umin:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_min_u32_e32 v0, 7, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i32 @llvm.smin.i32(i32 %a, i32 %b)
%min2 = call i32 @llvm.umin.i32(i32 %min1, i32 7)
ret i32 %min2
@@ -42,6 +74,18 @@ define <2 x i16> @test_smin3_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GFX10-NEXT: v_pk_min_i16 v0, v0, v1
; GFX10-NEXT: v_pk_min_i16 v0, v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_smin3_v2i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_i16 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_i16 v0, v0, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call <2 x i16> @llvm.smin.v2i16(<2 x i16> %a, <2 x i16> %b)
%min2 = call <2 x i16> @llvm.smin.v2i16(<2 x i16> %min1, <2 x i16> %c)
ret <2 x i16> %min2
@@ -53,6 +97,16 @@ define i32 @test_smax3(i32 %a, i32 %b, i32 %c) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max3_i32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_smax3:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_i32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
%max2 = call i32 @llvm.smax.i32(i32 %max1, i32 %c)
ret i32 %max2
@@ -64,6 +118,16 @@ define i32 @test_smax3_with_constants(i32 %a, i32 %b) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max3_i32 v0, v0, v1, 7
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_smax3_with_constants:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_i32 v0, v0, v1, 7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
%min2 = call i32 @llvm.smax.i32(i32 %min1, i32 7)
ret i32 %min2
@@ -76,6 +140,18 @@ define i32 @test_smin3_smax_umax(i32 %a, i32 %b) {
; GFX10-NEXT: v_max_i32_e32 v0, v0, v1
; GFX10-NEXT: v_max_u32_e32 v0, 7, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_smin3_smax_umax:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_max_u32_e32 v0, 7, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
%min2 = call i32 @llvm.umax.i32(i32 %min1, i32 7)
ret i32 %min2
@@ -88,6 +164,18 @@ define <2 x i16> @test_smax3_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GFX10-NEXT: v_pk_max_i16 v0, v0, v1
; GFX10-NEXT: v_pk_max_i16 v0, v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_smax3_v2i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_i16 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_i16 v0, v0, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %a, <2 x i16> %b)
%max2 = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %max1, <2 x i16> %c)
ret <2 x i16> %max2
@@ -99,6 +187,16 @@ define i32 @test_umin3(i32 %a, i32 %b, i32 %c) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min3_u32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_umin3:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_u32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
%min2 = call i32 @llvm.umin.i32(i32 %min1, i32 %c)
ret i32 %min2
@@ -110,6 +208,16 @@ define i32 @test_umin3_with_constants(i32 %a, i32 %b) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_min3_u32 v0, v0, v1, 7
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_umin3_with_constants:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_min3_u32 v0, v0, v1, 7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
%min2 = call i32 @llvm.umin.i32(i32 %min1, i32 7)
ret i32 %min2
@@ -122,6 +230,18 @@ define <2 x i16> @test_umin3_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GFX10-NEXT: v_pk_min_u16 v0, v0, v1
; GFX10-NEXT: v_pk_min_u16 v0, v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_umin3_v2i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_min_u16 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_min_u16 v0, v0, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call <2 x i16> @llvm.umin.v2i16(<2 x i16> %a, <2 x i16> %b)
%min2 = call <2 x i16> @llvm.umin.v2i16(<2 x i16> %min1, <2 x i16> %c)
ret <2 x i16> %min2
@@ -133,6 +253,16 @@ define i32 @test_umax3(i32 %a, i32 %b, i32 %c) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max3_u32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_umax3:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_u32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
%max2 = call i32 @llvm.umax.i32(i32 %max1, i32 %c)
ret i32 %max2
@@ -144,6 +274,16 @@ define i32 @test_umax3_with_constants(i32 %a, i32 %b) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max3_u32 v0, v0, v1, 7
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_umax3_with_constants:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_max3_u32 v0, v0, v1, 7
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call i32 @llvm.umax.i32(i32 %a, i32 %b)
%max2 = call i32 @llvm.umax.i32(i32 %max1, i32 7)
ret i32 %max2
@@ -156,6 +296,18 @@ define <2 x i16> @test_umax3_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GFX10-NEXT: v_pk_max_u16 v0, v0, v1
; GFX10-NEXT: v_pk_max_u16 v0, v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: test_umax3_v2i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_u16 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_pk_max_u16 v0, v0, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call <2 x i16> @llvm.umax.v2i16(<2 x i16> %a, <2 x i16> %b)
%max2 = call <2 x i16> @llvm.umax.v2i16(<2 x i16> %max1, <2 x i16> %c)
ret <2 x i16> %max2
>From 11e8ca6807cc0892c6d6f7fb34d1b26480c07bc3 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 20:35:51 +0800
Subject: [PATCH 09/13] don't support vector
---
llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 6eab272c54e7c..f23cfcc886d1d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -511,9 +511,7 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
LLT t = MRI.getType(dst);
bool IsSupportedTy = t == LLT::scalar(32) ||
- (t == LLT::scalar(16) && STI.hasMin3Max3_16()) ||
- (t.isVector() && t.getScalarSizeInBits() == 32);
-
+ (t == LLT::scalar(16) && STI.hasMin3Max3_16());
if (!IsSupportedTy)
return false;
>From 55b7c35f211a8f8c7c3fd2f04e2a6a76fe5861a6 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 20:39:11 +0800
Subject: [PATCH 10/13] vector: only support v2f32
---
.../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 50 ++++++++++---------
.../AMDGPU/GlobalISel/fmin3-fmax3-combine.ll | 4 --
2 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index f23cfcc886d1d..32d94e009d96f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -501,37 +501,39 @@ void AMDGPURegBankCombinerImpl::applyMinMaxToMinMax3(
bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
MachineInstr &MI, MinMaxToMinMax3MatchInfo &MatchInfo) const {
- Register dst = MI.getOperand(0).getReg();
- Register src1 = MI.getOperand(1).getReg();
- Register src2 = MI.getOperand(2).getReg();
- // if the register is SGPR, don't optimize it.
- if (!(isVgprRegBank(dst) && isVgprRegBank(src1) && isVgprRegBank(src2))) {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src1 = MI.getOperand(1).getReg();
+ Register Src2 = MI.getOperand(2).getReg();
+ // If the register is SGPR, don't optimize it.
+ if (!(isVgprRegBank(Dst) && isVgprRegBank(Src1) && isVgprRegBank(Src2))) {
return false;
}
-
- LLT t = MRI.getType(dst);
- bool IsSupportedTy = t == LLT::scalar(32) ||
- (t == LLT::scalar(16) && STI.hasMin3Max3_16());
+ unsigned Opc = MI.getOpcode();
+ LLT Ty = MRI.getType(Dst);
+ bool IsFPOp = Opc == AMDGPU::G_FMAXNUM || Opc == AMDGPU::G_FMAXNUM_IEEE ||
+ Opc == AMDGPU::G_FMINNUM || Opc == AMDGPU::G_FMINNUM_IEEE;
+ bool IsSupportedTy = Ty == LLT::scalar(32) ||
+ (Ty == LLT::scalar(16) && STI.hasMin3Max3_16()) ||
+ (IsFPOp && Ty == LLT::fixed_vector(2, 32));
if (!IsSupportedTy)
return false;
Register R0, R1, R2;
- unsigned opc = MI.getOpcode();
- auto matchMinOrMax3 = [&](MachineInstr &MI, MachineRegisterInfo &MRI,
- unsigned op, Register &r0, Register &r1,
- Register &r2) {
- auto p1 = m_BinOp(op, m_OneNonDBGUse(m_BinOp(op, m_Reg(r0), m_Reg(r1))),
- m_Reg(r2));
- auto p2 = m_BinOp(op, m_Reg(r0),
- m_OneNonDBGUse(m_BinOp(op, m_Reg(r1), m_Reg(r2))));
-
- return mi_match(MI, MRI, m_any_of(p1, p2));
+ auto MatchMinOrMax3 = [&](MachineInstr &MI, MachineRegisterInfo &MRI,
+ unsigned Op, Register &R0, Register &R1,
+ Register &R2) {
+ auto P1 = m_BinOp(Op, m_OneNonDBGUse(m_BinOp(Op, m_Reg(R0), m_Reg(R1))),
+ m_Reg(R2));
+ auto P2 = m_BinOp(Op, m_Reg(R0),
+ m_OneNonDBGUse(m_BinOp(Op, m_Reg(R1), m_Reg(R2))));
+
+ return mi_match(MI, MRI, m_any_of(P1, P2));
};
- if (!matchMinOrMax3(MI, MRI, opc, R0, R1, R2)) {
+ if (!MatchMinOrMax3(MI, MRI, Opc, R0, R1, R2)) {
return false;
}
- auto getAMDGPUOp = [](unsigned Opc) -> unsigned {
+ auto GetAMDGPUOp = [](unsigned Opc) -> unsigned {
switch (Opc) {
case AMDGPU::G_SMAX:
return AMDGPU::G_AMDGPU_SMAX3;
@@ -551,10 +553,10 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
return 0;
}
};
- unsigned amdgpuOpc = getAMDGPUOp(opc);
- if (!amdgpuOpc)
+ unsigned AMDGPUOpc = GetAMDGPUOp(Opc);
+ if (!AMDGPUOpc)
return false;
- MatchInfo = {getAMDGPUOp(opc), R0, R1, R2};
+ MatchInfo = {GetAMDGPUOp(Opc), R0, R1, R2};
return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
index 959bb04100fa5..b1083518de977 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
@@ -553,7 +553,3 @@ declare float @llvm.minnum.f32(float, float)
declare float @llvm.maxnum.f32(float, float)
declare double @llvm.minnum.f64(double, double)
declare double @llvm.maxnum.f64(double, double)
-declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
-declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
-declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
-declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
>From fbf20d0a8c6aff31ba32e0129ebf784e14e653d4 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 20:58:59 +0800
Subject: [PATCH 11/13] inline matchMinOrMax3
---
llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp | 16 +++++-----------
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 32d94e009d96f..315e2c1a0b9ad 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -519,17 +519,11 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
return false;
Register R0, R1, R2;
- auto MatchMinOrMax3 = [&](MachineInstr &MI, MachineRegisterInfo &MRI,
- unsigned Op, Register &R0, Register &R1,
- Register &R2) {
- auto P1 = m_BinOp(Op, m_OneNonDBGUse(m_BinOp(Op, m_Reg(R0), m_Reg(R1))),
- m_Reg(R2));
- auto P2 = m_BinOp(Op, m_Reg(R0),
- m_OneNonDBGUse(m_BinOp(Op, m_Reg(R1), m_Reg(R2))));
-
- return mi_match(MI, MRI, m_any_of(P1, P2));
- };
- if (!MatchMinOrMax3(MI, MRI, Opc, R0, R1, R2)) {
+ auto P1 = m_BinOp(Opc, m_OneNonDBGUse(m_BinOp(Opc, m_Reg(R0), m_Reg(R1))),
+ m_Reg(R2));
+ auto P2 = m_BinOp(Opc, m_Reg(R0),
+ m_OneNonDBGUse(m_BinOp(Opc, m_Reg(R1), m_Reg(R2))));
+ if (!mi_match(MI, MRI, m_any_of(P1, P2))) {
return false;
}
>From 88ecb07bc01ce6a4c63132a7ac4566d051295f4c Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 21:01:41 +0800
Subject: [PATCH 12/13] use commutative binop instead of binop
---
llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp | 6 +++---
llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll | 4 ++++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 315e2c1a0b9ad..02b7ef7f52381 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -519,10 +519,10 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
return false;
Register R0, R1, R2;
- auto P1 = m_BinOp(Opc, m_OneNonDBGUse(m_BinOp(Opc, m_Reg(R0), m_Reg(R1))),
+ auto P1 = m_CommutativeBinOp(Opc, m_OneNonDBGUse(m_CommutativeBinOp(Opc, m_Reg(R0), m_Reg(R1))),
m_Reg(R2));
- auto P2 = m_BinOp(Opc, m_Reg(R0),
- m_OneNonDBGUse(m_BinOp(Opc, m_Reg(R1), m_Reg(R2))));
+ auto P2 = m_CommutativeBinOp(Opc, m_Reg(R0),
+ m_OneNonDBGUse(m_CommutativeBinOp(Opc, m_Reg(R1), m_Reg(R2))));
if (!mi_match(MI, MRI, m_any_of(P1, P2))) {
return false;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
index b1083518de977..959bb04100fa5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
@@ -553,3 +553,7 @@ declare float @llvm.minnum.f32(float, float)
declare float @llvm.maxnum.f32(float, float)
declare double @llvm.minnum.f64(double, double)
declare double @llvm.maxnum.f64(double, double)
+declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
+declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
+declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
+declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
>From df0ac7e40c1f0963bd3ff88fa33b25e3e85eea5c Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile at bytedance.com>
Date: Thu, 4 Jun 2026 22:41:01 +0800
Subject: [PATCH 13/13] support maximum and minimum
---
llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 8 +-
llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 3 +
.../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 17 ++-
llvm/lib/Target/AMDGPU/SIInstructions.td | 12 ++
.../AMDGPU/GlobalISel/fmin3-fmax3-combine.ll | 112 ++++++++++++++++--
5 files changed, 136 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index f9b0e0956b13f..620cefceda189 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -171,6 +171,8 @@ def umax_to_minmax3 : minmax_to_minmax3_opcodes<G_UMAX>;
def umin_to_minmax3 : minmax_to_minmax3_opcodes<G_UMIN>;
def fmax_to_minmax3 : minmax_to_minmax3_opcodes<G_FMAXNUM>;
def fmin_to_minmax3 : minmax_to_minmax3_opcodes<G_FMINNUM>;
+def fmaximum_to_minmax3 : minmax_to_minmax3_opcodes<G_FMAXIMUM>;
+def fminimum_to_minmax3 : minmax_to_minmax3_opcodes<G_FMINIMUM>;
def fmax_ieee_to_minmax3 : minmax_to_minmax3_opcodes<G_FMAXNUM_IEEE>;
def fmin_ieee_to_minmax3 : minmax_to_minmax3_opcodes<G_FMINNUM_IEEE>;
@@ -256,7 +258,7 @@ def AMDGPURegBankCombiner : GICombiner<
fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp,
identity_combines, redundant_and, constant_fold_cast_op,
cast_of_cast_combines, sext_trunc, zext_of_shift_amount_combines,
- d16_load, smax_to_minmax3, smin_to_minmax3, umax_to_minmax3,
- umin_to_minmax3, fmax_to_minmax3, fmin_to_minmax3, fmax_ieee_to_minmax3,
- fmin_ieee_to_minmax3]> {
+ d16_load, smax_to_minmax3, smin_to_minmax3, umax_to_minmax3,
+ umin_to_minmax3, fmax_to_minmax3, fmin_to_minmax3, fmaximum_to_minmax3,
+ fminimum_to_minmax3, fmax_ieee_to_minmax3, fmin_ieee_to_minmax3]> {
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
index 97957f5100067..a88322df79036 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -277,6 +277,9 @@ def : GINodeEquiv<G_AMDGPU_FMAX3, AMDGPUfmax3>;
def : GINodeEquiv<G_AMDGPU_SMIN3, AMDGPUsmin3>;
def : GINodeEquiv<G_AMDGPU_UMIN3, AMDGPUumin3>;
def : GINodeEquiv<G_AMDGPU_FMIN3, AMDGPUfmin3>;
+def : GINodeEquiv<G_AMDGPU_FMAXIMUM3, AMDGPUfmaximum3>;
+def : GINodeEquiv<G_AMDGPU_FMINIMUM3, AMDGPUfminimum3>;
+
def : GINodeEquiv<G_AMDGPU_CLAMP, AMDGPUclamp>;
def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index 02b7ef7f52381..3602b44212a02 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -508,8 +508,9 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
if (!(isVgprRegBank(Dst) && isVgprRegBank(Src1) && isVgprRegBank(Src2))) {
return false;
}
- unsigned Opc = MI.getOpcode();
+
LLT Ty = MRI.getType(Dst);
+ unsigned Opc = MI.getOpcode();
bool IsFPOp = Opc == AMDGPU::G_FMAXNUM || Opc == AMDGPU::G_FMAXNUM_IEEE ||
Opc == AMDGPU::G_FMINNUM || Opc == AMDGPU::G_FMINNUM_IEEE;
bool IsSupportedTy = Ty == LLT::scalar(32) ||
@@ -519,10 +520,12 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
return false;
Register R0, R1, R2;
- auto P1 = m_CommutativeBinOp(Opc, m_OneNonDBGUse(m_CommutativeBinOp(Opc, m_Reg(R0), m_Reg(R1))),
- m_Reg(R2));
- auto P2 = m_CommutativeBinOp(Opc, m_Reg(R0),
- m_OneNonDBGUse(m_CommutativeBinOp(Opc, m_Reg(R1), m_Reg(R2))));
+ auto P1 = m_CommutativeBinOp(
+ Opc, m_OneNonDBGUse(m_CommutativeBinOp(Opc, m_Reg(R0), m_Reg(R1))),
+ m_Reg(R2));
+ auto P2 = m_CommutativeBinOp(
+ Opc, m_Reg(R0),
+ m_OneNonDBGUse(m_CommutativeBinOp(Opc, m_Reg(R1), m_Reg(R2))));
if (!mi_match(MI, MRI, m_any_of(P1, P2))) {
return false;
}
@@ -543,6 +546,10 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
case AMDGPU::G_FMINNUM:
case AMDGPU::G_FMINNUM_IEEE:
return AMDGPU::G_AMDGPU_FMIN3;
+ case AMDGPU::G_FMAXIMUM:
+ return AMDGPU::G_AMDGPU_FMAXIMUM3;
+ case AMDGPU::G_FMINIMUM:
+ return AMDGPU::G_AMDGPU_FMINIMUM3;
default:
return 0;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 96068037197d1..2186f9303a192 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4756,6 +4756,18 @@ def G_AMDGPU_FMAX3 : AMDGPUGenericInstruction {
let hasSideEffects = 0;
}
+def G_AMDGPU_FMAXIMUM3 : AMDGPUGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+def G_AMDGPU_FMINIMUM3 : AMDGPUGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
def G_AMDGPU_CLAMP : AMDGPUGenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
index 959bb04100fa5..cd51af7f4993e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
@@ -549,11 +549,107 @@ define <2 x float> @test_fmax3_v2f32_nnan(<2 x float> %a, <2 x float> %b, <2 x f
ret <2 x float> %max2
}
-declare float @llvm.minnum.f32(float, float)
-declare float @llvm.maxnum.f32(float, float)
-declare double @llvm.minnum.f64(double, double)
-declare double @llvm.maxnum.f64(double, double)
-declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
-declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
-declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
-declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
+define float @fmaximum3_f32(float %a, float %b, float %c) {
+; GFX10-LABEL: fmaximum3_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f32_e32 v3, v0, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
+; GFX10-NEXT: v_max_f32_e32 v1, v0, v2
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fmaximum3_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_maximum3_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %m1 = call float @llvm.maximum.f32(float %a, float %b)
+ %m2 = call float @llvm.maximum.f32(float %m1, float %c)
+ ret float %m2
+}
+
+define float @fminimum3_f32(float %a, float %b, float %c) {
+; GFX10-LABEL: fminimum3_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min_f32_e32 v3, v0, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
+; GFX10-NEXT: v_min_f32_e32 v1, v0, v2
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fminimum3_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_minimum3_f32 v0, v0, v1, v2
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %m1 = call float @llvm.minimum.f32(float %a, float %b)
+ %m2 = call float @llvm.minimum.f32(float %m1, float %c)
+ ret float %m2
+}
+
+define half @fmaximum3_f16(half %a, half %b, half %c) {
+; GFX10-LABEL: fmaximum3_f16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_max_f16_e32 v3, v0, v1
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX10-NEXT: v_max_f16_e32 v1, v0, v2
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fmaximum3_f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_maximum3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %m1 = call half @llvm.maximum.f16(half %a, half %b)
+ %m2 = call half @llvm.maximum.f16(half %m1, half %c)
+ ret half %m2
+}
+
+define half @fminimum3_f16(half %a, half %b, half %c) {
+; GFX10-LABEL: fminimum3_f16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_min_f16_e32 v3, v0, v1
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX10-NEXT: v_min_f16_e32 v1, v0, v2
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fminimum3_f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_minimum3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %m1 = call half @llvm.minimum.f16(half %a, half %b)
+ %m2 = call half @llvm.minimum.f16(half %m1, half %c)
+ ret half %m2
+}
+
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