[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[Jonathan Thackray via llvm-commits]

jthackray wrote:

> I was wondering if you could review this as well. We made some change in order to allow to create more sub register-class, but this will impact other architectures and could create an unwanted impact.

@kosarev - forgot to tag you. Any comments you've got would be appreciated. Thanks :) 

https://github.com/llvm/llvm-project/pull/200751