[llvm] [SelectionDAG] Remove the remained `NoSignedZerosFPMath` use (PR #201535)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 4 03:15:55 PDT 2026
https://github.com/paperchalice updated https://github.com/llvm/llvm-project/pull/201535
>From 9c47b14e511a24b469748d523ee822e43d7ef52c Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Jun 2026 17:01:56 +0800
Subject: [PATCH 1/3] [SelectionDAG] Propagate fast-math flags from {u,s}itofp
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index eca5bb1598ae0..19472f3dd2cb9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4054,6 +4054,8 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) {
SDNodeFlags Flags;
if (auto *PNI = dyn_cast<PossiblyNonNegInst>(&I))
Flags.setNonNeg(PNI->hasNonNeg());
+ if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
+ Flags.copyFMF(*FPOp);
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
@@ -4063,7 +4065,11 @@ void SelectionDAGBuilder::visitSIToFP(const User &I) {
SDValue N = getValue(I.getOperand(0));
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
I.getType());
- setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
+ SDNodeFlags Flags;
+ if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
+ Flags.copyFMF(*FPOp);
+
+ setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N, Flags));
}
void SelectionDAGBuilder::visitPtrToAddr(const User &I) {
>From c718940cc775278aaeadeacf70f01525a1c0e2f6 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Jun 2026 17:02:58 +0800
Subject: [PATCH 2/3] [SelectionDAG] Remove NoSignedZerosFPMath uses
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6cb9ae5fa7803..7b2a35b10c318 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19962,8 +19962,7 @@ static SDValue foldFPToIntToFP(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
TLI.isOperationLegal(IntToFPOp, VT))
return SDValue();
- bool IsSignedZeroSafe = DAG.getTarget().Options.NoSignedZerosFPMath ||
- DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
+ bool IsSignedZeroSafe = DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
// For signed conversions: The optimization changes signed zero behavior.
if (IsSigned && !IsSignedZeroSafe)
return SDValue();
>From 9a65d2f81521f44fb6bf1ceeb3165b82c10f256f Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Jun 2026 18:05:28 +0800
Subject: [PATCH 3/3] fix tests
---
llvm/test/CodeGen/AArch64/ftrunc.ll | 18 +++--
.../CodeGen/PowerPC/fp-int128-fp-combine.ll | 6 +-
llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll | 13 ++--
llvm/test/CodeGen/PowerPC/ftrunc-vec.ll | 18 +++--
.../CodeGen/PowerPC/no-extra-fp-conv-ldst.ll | 26 ++++---
llvm/test/CodeGen/X86/ftrunc.ll | 71 +++++++++----------
6 files changed, 71 insertions(+), 81 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/ftrunc.ll b/llvm/test/CodeGen/AArch64/ftrunc.ll
index c7bf514e902be..093262160af97 100644
--- a/llvm/test/CodeGen/AArch64/ftrunc.ll
+++ b/llvm/test/CodeGen/AArch64/ftrunc.ll
@@ -1,45 +1,43 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
-define float @trunc_unsigned_f32(float %x) #0 {
+define float @trunc_unsigned_f32(float %x) {
; CHECK-LABEL: trunc_unsigned_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz s0, s0
; CHECK-NEXT: ret
%i = fptoui float %x to i32
- %r = uitofp i32 %i to float
+ %r = uitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_unsigned_f64(double %x) #0 {
+define double @trunc_unsigned_f64(double %x) {
; CHECK-LABEL: trunc_unsigned_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz d0, d0
; CHECK-NEXT: ret
%i = fptoui double %x to i64
- %r = uitofp i64 %i to double
+ %r = uitofp nsz i64 %i to double
ret double %r
}
-define float @trunc_signed_f32(float %x) #0 {
+define float @trunc_signed_f32(float %x) {
; CHECK-LABEL: trunc_signed_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz s0, s0
; CHECK-NEXT: ret
%i = fptosi float %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_signed_f64(double %x) #0 {
+define double @trunc_signed_f64(double %x) {
; CHECK-LABEL: trunc_signed_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz d0, d0
; CHECK-NEXT: ret
%i = fptosi double %x to i64
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
-attributes #0 = { "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll b/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
index 8ebf54a3dc489..9af6443d85230 100644
--- a/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
@@ -26,16 +26,14 @@ entry:
; NSZ, so it's safe to friz.
-define float @f_i128_fi_nsz(float %v) #0 {
+define float @f_i128_fi_nsz(float %v) {
; CHECK-LABEL: f_i128_fi_nsz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsrdpiz 1, 1
; CHECK-NEXT: blr
entry:
%a = fptosi float %v to i128
- %b = sitofp i128 %a to float
+ %b = sitofp nsz i128 %a to float
ret float %b
}
-attributes #0 = { "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
index 11460349c90fb..de6b381275b4b 100644
--- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
@@ -25,7 +25,7 @@ define float @fool(float %X) #0 {
; PWR9-NEXT: blr
entry:
%conv = fptosi float %X to i64
- %conv1 = sitofp i64 %conv to float
+ %conv1 = sitofp nsz i64 %conv to float
ret float %conv1
@@ -50,7 +50,7 @@ define double @foodl(double %X) #0 {
; PWR9-NEXT: blr
entry:
%conv = fptosi double %X to i64
- %conv1 = sitofp i64 %conv to double
+ %conv1 = sitofp nsz i64 %conv to double
ret double %conv1
@@ -132,7 +132,7 @@ define float @fooul(float %X) #0 {
; PWR9-NEXT: blr
entry:
%conv = fptoui float %X to i64
- %conv1 = uitofp i64 %conv to float
+ %conv1 = uitofp nsz i64 %conv to float
ret float %conv1
}
@@ -188,7 +188,7 @@ define double @fooudl(double %X) #0 {
; PWR9-NEXT: blr
entry:
%conv = fptoui double %X to i64
- %conv1 = uitofp i64 %conv to double
+ %conv1 = uitofp nsz i64 %conv to double
ret double %conv1
}
@@ -288,7 +288,7 @@ define double @si1_to_f64(i1 %X) #0 {
; PWR9-NEXT: xscvsxddp 1, 0
; PWR9-NEXT: blr
entry:
- %conv = sitofp i1 %X to double
+ %conv = sitofp nsz i1 %X to double
ret double %conv
}
@@ -319,9 +319,8 @@ define double @ui1_to_f64(i1 %X) #0 {
; PWR9-NEXT: xscvsxddp 1, 0
; PWR9-NEXT: blr
entry:
- %conv = uitofp i1 %X to double
+ %conv = uitofp nsz i1 %X to double
ret double %conv
}
-attributes #0 = { nounwind readnone "no-signed-zeros-fp-math"="true" }
diff --git a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
index ecad35d22e859..b0faf1430b8fa 100644
--- a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
+++ b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
@@ -2,45 +2,43 @@
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -verify-machineinstrs < %s | FileCheck %s
-define <4 x float> @truncf32(<4 x float> %a) #0 {
+define <4 x float> @truncf32(<4 x float> %a) {
; CHECK-LABEL: truncf32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrspiz 34, 34
; CHECK-NEXT: blr
%t0 = fptosi <4 x float> %a to <4 x i32>
- %t1 = sitofp <4 x i32> %t0 to <4 x float>
+ %t1 = sitofp nsz <4 x i32> %t0 to <4 x float>
ret <4 x float> %t1
}
-define <2 x double> @truncf64(<2 x double> %a) #0 {
+define <2 x double> @truncf64(<2 x double> %a) {
; CHECK-LABEL: truncf64:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrdpiz 34, 34
; CHECK-NEXT: blr
%t0 = fptosi <2 x double> %a to <2 x i64>
- %t1 = sitofp <2 x i64> %t0 to <2 x double>
+ %t1 = sitofp nsz <2 x i64> %t0 to <2 x double>
ret <2 x double> %t1
}
-define <4 x float> @truncf32u(<4 x float> %a) #0 {
+define <4 x float> @truncf32u(<4 x float> %a) {
; CHECK-LABEL: truncf32u:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrspiz 34, 34
; CHECK-NEXT: blr
%t0 = fptoui <4 x float> %a to <4 x i32>
- %t1 = uitofp <4 x i32> %t0 to <4 x float>
+ %t1 = uitofp nsz <4 x i32> %t0 to <4 x float>
ret <4 x float> %t1
}
-define <2 x double> @truncf64u(<2 x double> %a) #0 {
+define <2 x double> @truncf64u(<2 x double> %a) {
; CHECK-LABEL: truncf64u:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrdpiz 34, 34
; CHECK-NEXT: blr
%t0 = fptoui <2 x double> %a to <2 x i64>
- %t1 = uitofp <2 x i64> %t0 to <2 x double>
+ %t1 = uitofp nsz <2 x i64> %t0 to <2 x double>
ret <2 x double> %t1
}
-attributes #0 = { "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll b/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
index 3ce14d35c4aea..eead1e932eeb6 100644
--- a/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
@@ -3,10 +3,10 @@ target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readonly
-define double @test1(ptr nocapture readonly %x) #0 {
+define double @test1(ptr nocapture readonly %x) {
entry:
%0 = load i64, ptr %x, align 8
- %conv = sitofp i64 %0 to double
+ %conv = sitofp nsz i64 %0 to double
ret double %conv
; CHECK-LABEL: @test1
@@ -16,10 +16,10 @@ entry:
}
; Function Attrs: nounwind readonly
-define double @test2(ptr nocapture readonly %x) #0 {
+define double @test2(ptr nocapture readonly %x) {
entry:
%0 = load i32, ptr %x, align 4
- %conv = sitofp i32 %0 to double
+ %conv = sitofp nsz i32 %0 to double
ret double %conv
; CHECK-LABEL: @test2
@@ -29,10 +29,10 @@ entry:
}
; Function Attrs: nounwind readnone
-define float @foo(float %X) #0 {
+define float @foo(float %X) {
entry:
%conv = fptosi float %X to i32
- %conv1 = sitofp i32 %conv to float
+ %conv1 = sitofp nsz i32 %conv to float
ret float %conv1
; CHECK-LABEL: @foo
@@ -41,10 +41,10 @@ entry:
}
; Function Attrs: nounwind readnone
-define double @food(double %X) #0 {
+define double @food(double %X) {
entry:
%conv = fptosi double %X to i32
- %conv1 = sitofp i32 %conv to double
+ %conv1 = sitofp nsz i32 %conv to double
ret double %conv1
; CHECK-LABEL: @food
@@ -53,10 +53,10 @@ entry:
}
; Function Attrs: nounwind readnone
-define float @foou(float %X) #0 {
+define float @foou(float %X) {
entry:
%conv = fptoui float %X to i32
- %conv1 = uitofp i32 %conv to float
+ %conv1 = uitofp nsz i32 %conv to float
ret float %conv1
; CHECK-LABEL: @foou
@@ -65,10 +65,10 @@ entry:
}
; Function Attrs: nounwind readnone
-define double @fooud(double %X) #0 {
+define double @fooud(double %X) {
entry:
%conv = fptoui double %X to i32
- %conv1 = uitofp i32 %conv to double
+ %conv1 = uitofp nsz i32 %conv to double
ret double %conv1
; CHECK-LABEL: @fooud
@@ -76,5 +76,3 @@ entry:
; CHECK: blr
}
-attributes #0 = { nounwind readonly "no-signed-zeros-fp-math"="true" }
-
diff --git a/llvm/test/CodeGen/X86/ftrunc.ll b/llvm/test/CodeGen/X86/ftrunc.ll
index 9095fb1550e70..0d2aa86b398c0 100644
--- a/llvm/test/CodeGen/X86/ftrunc.ll
+++ b/llvm/test/CodeGen/X86/ftrunc.ll
@@ -7,7 +7,7 @@
declare i32 @llvm.fptoui.sat.i32.f32(float)
declare i64 @llvm.fptosi.sat.i64.f64(double)
-define float @trunc_unsigned_f32(float %x) #0 {
+define float @trunc_unsigned_f32(float %x) {
; SSE2-LABEL: trunc_unsigned_f32:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttss2si %xmm0, %rax
@@ -36,11 +36,11 @@ define float @trunc_unsigned_f32(float %x) #0 {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptoui float %x to i32
- %r = uitofp i32 %i to float
+ %r = uitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_unsigned_f64(double %x) #0 {
+define double @trunc_unsigned_f64(double %x) {
; SSE2-LABEL: trunc_unsigned_f64:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttsd2si %xmm0, %rax
@@ -82,11 +82,11 @@ define double @trunc_unsigned_f64(double %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptoui double %x to i64
- %r = uitofp i64 %i to double
+ %r = uitofp nsz i64 %i to double
ret double %r
}
-define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) #0 {
+define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) {
; SSE2-LABEL: trunc_unsigned_v4f32:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttps2dq %xmm0, %xmm1
@@ -115,11 +115,11 @@ define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) #0 {
; AVX-NEXT: vroundps $11, %xmm0, %xmm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptoui <4 x float> %x to <4 x i32>
- %r = uitofp <4 x i32> %i to <4 x float>
+ %r = uitofp nsz <4 x i32> %i to <4 x float>
ret <4 x float> %r
}
-define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 {
+define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) {
; SSE2-LABEL: trunc_unsigned_v2f64:
; SSE2: # %bb.0:
; SSE2-NEXT: movsd {{.*#+}} xmm2 = [9.2233720368547758E+18,0.0E+0]
@@ -162,11 +162,11 @@ define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 {
; AVX-NEXT: vroundpd $11, %xmm0, %xmm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptoui <2 x double> %x to <2 x i64>
- %r = uitofp <2 x i64> %i to <2 x double>
+ %r = uitofp nsz <2 x i64> %i to <2 x double>
ret <2 x double> %r
}
-define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 {
+define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) {
; SSE2-LABEL: trunc_unsigned_v4f64:
; SSE2: # %bb.0:
; SSE2-NEXT: movapd %xmm1, %xmm2
@@ -239,7 +239,7 @@ define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 {
; AVX-NEXT: vroundpd $11, %ymm0, %ymm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptoui <4 x double> %x to <4 x i64>
- %r = uitofp <4 x i64> %i to <4 x double>
+ %r = uitofp nsz <4 x i64> %i to <4 x double>
ret <4 x double> %r
}
@@ -267,13 +267,13 @@ define float @trunc_signed_f32_no_fast_math(float %x) nounwind {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptosi float %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
; Without -0.0, it is ok to use roundss if it is available.
-define float @trunc_signed_f32_nsz(float %x) #0 {
+define float @trunc_signed_f32_nsz(float %x) {
; SSE2-LABEL: trunc_signed_f32_nsz:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttps2dq %xmm0, %xmm0
@@ -300,7 +300,7 @@ define float @trunc_signed_f32_nsz(float %x) #0 {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptosi float %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
@@ -332,11 +332,11 @@ define double @trunc_signed32_f64_no_fast_math(double %x) nounwind {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i32
- %r = sitofp i32 %i to double
+ %r = sitofp nsz i32 %i to double
ret double %r
}
-define double @trunc_signed32_f64_nsz(double %x) #0 {
+define double @trunc_signed32_f64_nsz(double %x) {
; SSE2-LABEL: trunc_signed32_f64_nsz:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttpd2dq %xmm0, %xmm0
@@ -367,7 +367,7 @@ define double @trunc_signed32_f64_nsz(double %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i32
- %r = sitofp i32 %i to double
+ %r = sitofp nsz i32 %i to double
ret double %r
}
@@ -399,11 +399,11 @@ define double @trunc_f32_signed32_f64_no_fast_math(float %x) nounwind {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi float %x to i32
- %r = sitofp i32 %i to double
+ %r = sitofp nsz i32 %i to double
ret double %r
}
-define double @trunc_f32_signed32_f64_nsz(float %x) #0 {
+define double @trunc_f32_signed32_f64_nsz(float %x) {
; SSE-LABEL: trunc_f32_signed32_f64_nsz:
; SSE: # %bb.0:
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
@@ -431,7 +431,7 @@ define double @trunc_f32_signed32_f64_nsz(float %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi float %x to i32
- %r = sitofp i32 %i to double
+ %r = sitofp nsz i32 %i to double
ret double %r
}
@@ -459,11 +459,11 @@ define float @trunc_f64_signed32_f32_no_fast_math(double %x) nounwind {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
-define float @trunc_f64_signed32_f32_nsz(double %x) #0 {
+define float @trunc_f64_signed32_f32_nsz(double %x) {
; SSE-LABEL: trunc_f64_signed32_f32_nsz:
; SSE: # %bb.0:
; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
@@ -487,7 +487,7 @@ define float @trunc_f64_signed32_f32_nsz(double %x) #0 {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i32
- %r = sitofp i32 %i to float
+ %r = sitofp nsz i32 %i to float
ret float %r
}
@@ -524,11 +524,11 @@ define double @trunc_signed_f64_no_fast_math(double %x) nounwind {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i64
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
-define double @trunc_signed_f64_nsz(double %x) #0 {
+define double @trunc_signed_f64_nsz(double %x) {
; SSE2-LABEL: trunc_signed_f64_nsz:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttsd2si %xmm0, %rax
@@ -560,11 +560,11 @@ define double @trunc_signed_f64_nsz(double %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = fptosi double %x to i64
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
-define <4 x float> @trunc_signed_v4f32_nsz(<4 x float> %x) #0 {
+define <4 x float> @trunc_signed_v4f32_nsz(<4 x float> %x) {
; SSE2-LABEL: trunc_signed_v4f32_nsz:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttps2dq %xmm0, %xmm0
@@ -581,11 +581,11 @@ define <4 x float> @trunc_signed_v4f32_nsz(<4 x float> %x) #0 {
; AVX-NEXT: vroundps $11, %xmm0, %xmm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptosi <4 x float> %x to <4 x i32>
- %r = sitofp <4 x i32> %i to <4 x float>
+ %r = sitofp nsz <4 x i32> %i to <4 x float>
ret <4 x float> %r
}
-define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 {
+define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) {
; SSE2-LABEL: trunc_signed_v2f64_nsz:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttsd2si %xmm0, %rax
@@ -607,11 +607,11 @@ define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 {
; AVX-NEXT: vroundpd $11, %xmm0, %xmm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptosi <2 x double> %x to <2 x i64>
- %r = sitofp <2 x i64> %i to <2 x double>
+ %r = sitofp nsz <2 x i64> %i to <2 x double>
ret <2 x double> %r
}
-define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 {
+define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) {
; SSE2-LABEL: trunc_signed_v4f64_nsz:
; SSE2: # %bb.0:
; SSE2-NEXT: cvttsd2si %xmm1, %rax
@@ -642,7 +642,7 @@ define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 {
; AVX-NEXT: vroundpd $11, %ymm0, %ymm0
; AVX-NEXT: ret{{[l|q]}}
%i = fptosi <4 x double> %x to <4 x i64>
- %r = sitofp <4 x i64> %i to <4 x double>
+ %r = sitofp nsz <4 x i64> %i to <4 x double>
ret <4 x double> %r
}
@@ -654,7 +654,7 @@ define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 {
; Now, we expect a front-end to use IR intrinsics if it wants to avoid this
; transform.
-define float @trunc_unsigned_f32_disable_via_intrinsic(float %x) #0 {
+define float @trunc_unsigned_f32_disable_via_intrinsic(float %x) {
; SSE-LABEL: trunc_unsigned_f32_disable_via_intrinsic:
; SSE: # %bb.0:
; SSE-NEXT: cvttss2si %xmm0, %rax
@@ -709,11 +709,11 @@ define float @trunc_unsigned_f32_disable_via_intrinsic(float %x) #0 {
; X86-AVX1-NEXT: popl %eax
; X86-AVX1-NEXT: retl
%i = call i32 @llvm.fptoui.sat.i32.f32(float %x)
- %r = uitofp i32 %i to float
+ %r = uitofp nsz i32 %i to float
ret float %r
}
-define double @trunc_signed_f64_disable_via_intrinsic(double %x) #0 {
+define double @trunc_signed_f64_disable_via_intrinsic(double %x) {
; SSE-LABEL: trunc_signed_f64_disable_via_intrinsic:
; SSE: # %bb.0:
; SSE-NEXT: cvttsd2si %xmm0, %rax
@@ -778,8 +778,7 @@ define double @trunc_signed_f64_disable_via_intrinsic(double %x) #0 {
; X86-AVX1-NEXT: popl %ebp
; X86-AVX1-NEXT: retl
%i = call i64 @llvm.fptosi.sat.i64.f64(double %x)
- %r = sitofp i64 %i to double
+ %r = sitofp nsz i64 %i to double
ret double %r
}
-attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" }
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