[llvm] Prefer fp (PR #201541)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 4 03:01:03 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Garvit Gupta (quic-garvgupt)
<details>
<summary>Changes</summary>
---
Patch is 256.64 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/201541.diff
25 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+43-3)
- (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp (+7-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll (+241-246)
- (modified) llvm/test/CodeGen/RISCV/callee-saved-gprs.ll (+316-316)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll (+47-47)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll (+44-44)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-lp64.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll (+24-24)
- (modified) llvm/test/CodeGen/RISCV/frame.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/ipra.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/large-stack.ll (+1-3)
- (modified) llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll (+4-5)
- (modified) llvm/test/CodeGen/RISCV/push-pop-popret.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll (+224-224)
- (modified) llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/stack-probing-dynamic.ll (+2-4)
- (modified) llvm/test/CodeGen/RISCV/vararg-ilp32e.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/vararg.ll (+295-303)
- (modified) llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll (+128-128)
- (modified) llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll (+75-75)
- (modified) llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll (+15-15)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 46e4a8b959ef6..644dd5798ae07 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1518,8 +1518,32 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
assert(!MFI.hasVarSizedObjects());
FrameReg = SPReg;
}
+ } else if (!RI->hasStackRealignment(MF)) {
+ // Note: Keeping the following as multiple 'if' statements rather than
+ // merging to a single expression for readability.
+ if (!hasFP(MF)) {
+ // No FP available, must use SP.
+ FrameReg = SPReg;
+ } else {
+ FrameReg = FPReg;
+ if (RVFI->getRVVStackSize() == 0 && !MFI.hasVarSizedObjects() &&
+ hasReservedCallFrame(MF)) {
+ // Both FP and SP are candidates.
+ // Prefer SP when the SP-relative offset fits in the compressed
+ // instruction immediate range.
+ int64_t SPOff = Offset.getFixed() + MFI.getStackSize();
+ int64_t CLWSPMaxOffset = 252;
+ int64_t CLDSPMaxOffset = 504;
+ int64_t SPThreshold = STI.is64Bit() ? CLDSPMaxOffset : CLWSPMaxOffset;
+ if (SPOff >= 0 && SPOff <= SPThreshold)
+ FrameReg = SPReg;
+ }
+ }
} else {
- FrameReg = RI->getFrameRegister(MF);
+ assert(RI->hasStackRealignment(MF) && MFI.isFixedObjectIndex(FI) &&
+ "Expected fixed object with stack realignment");
+ assert(hasFP(MF) && "Re-aligned stack must have frame pointer");
+ FrameReg = FPReg;
}
if (FrameReg == FPReg) {
@@ -1968,8 +1992,24 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
// by the frame pointer.
// Let eliminateCallFramePseudoInstr preserve stack space for it.
bool RISCVFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
- return !MF.getFrameInfo().hasVarSizedObjects() &&
- !(hasFP(MF) && hasRVVFrameObject(MF));
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ if (MFI.hasVarSizedObjects())
+ return false;
+
+ // Check if there are actual scalable vector objects on the stack.
+ // Unlike hasRVVFrameObject() which conservatively returns hasVInstructions(),
+ // this is precise because hasReservedCallFrame is only called post-RA when
+ // all spill slots have been created.
+ if (hasFP(MF)) {
+ for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd();
+ i != e; ++i) {
+ if (MFI.getStackID(i) == TargetStackID::ScalableVector &&
+ !MFI.isDeadObjectIndex(i))
+ return false;
+ }
+ }
+
+ return true;
}
// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 81f76a5d58a0f..57b10686d8a1f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -729,7 +729,13 @@ bool RISCVRegisterInfo::needsFrameBaseReg(MachineInstr *MI,
}
int64_t MaxFPOffset = Offset - CalleeSavedSize;
- return !isFrameOffsetLegal(MI, RISCV::X8, MaxFPOffset);
+ if (isFrameOffsetLegal(MI, RISCV::X8, MaxFPOffset))
+ return false;
+
+ // If the FP-relative offset doesn't fit, fall through to check the
+ // SP-relative offset. getFrameIndexReference may select SP over FP when
+ // the SP offset fits in the compressed instruction immediate range, so a
+ // base register might not be needed.
}
// Assume 128 bytes spill slots size to estimate the maximum possible
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
index 6345011e3d9ce..3d2ec63096251 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
@@ -96,18 +96,18 @@ define i32 @va1(ptr %fmt, ...) {
; RV32-WITHFP-NEXT: .cfi_offset s0, -40
; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 32
-; RV32-WITHFP-NEXT: sw a1, 4(s0)
-; RV32-WITHFP-NEXT: sw a2, 8(s0)
-; RV32-WITHFP-NEXT: sw a3, 12(s0)
-; RV32-WITHFP-NEXT: sw a4, 16(s0)
-; RV32-WITHFP-NEXT: addi a0, s0, 4
-; RV32-WITHFP-NEXT: sw a0, -12(s0)
-; RV32-WITHFP-NEXT: lw a0, -12(s0)
-; RV32-WITHFP-NEXT: sw a5, 20(s0)
-; RV32-WITHFP-NEXT: sw a6, 24(s0)
-; RV32-WITHFP-NEXT: sw a7, 28(s0)
+; RV32-WITHFP-NEXT: sw a1, 20(sp)
+; RV32-WITHFP-NEXT: sw a2, 24(sp)
+; RV32-WITHFP-NEXT: sw a3, 28(sp)
+; RV32-WITHFP-NEXT: sw a4, 32(sp)
+; RV32-WITHFP-NEXT: addi a0, sp, 20
+; RV32-WITHFP-NEXT: sw a0, 4(sp)
+; RV32-WITHFP-NEXT: lw a0, 4(sp)
+; RV32-WITHFP-NEXT: sw a5, 36(sp)
+; RV32-WITHFP-NEXT: sw a6, 40(sp)
+; RV32-WITHFP-NEXT: sw a7, 44(sp)
; RV32-WITHFP-NEXT: addi a1, a0, 4
-; RV32-WITHFP-NEXT: sw a1, -12(s0)
+; RV32-WITHFP-NEXT: sw a1, 4(sp)
; RV32-WITHFP-NEXT: lw a0, 0(a0)
; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 48
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -128,24 +128,24 @@ define i32 @va1(ptr %fmt, ...) {
; RV64-WITHFP-NEXT: .cfi_offset s0, -80
; RV64-WITHFP-NEXT: addi s0, sp, 32
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 64
-; RV64-WITHFP-NEXT: sd a1, 8(s0)
-; RV64-WITHFP-NEXT: sd a2, 16(s0)
-; RV64-WITHFP-NEXT: sd a3, 24(s0)
-; RV64-WITHFP-NEXT: sd a4, 32(s0)
-; RV64-WITHFP-NEXT: addi a0, s0, -24
-; RV64-WITHFP-NEXT: addi a1, s0, 8
-; RV64-WITHFP-NEXT: sd a1, -24(s0)
+; RV64-WITHFP-NEXT: sd a1, 40(sp)
+; RV64-WITHFP-NEXT: sd a2, 48(sp)
+; RV64-WITHFP-NEXT: sd a3, 56(sp)
+; RV64-WITHFP-NEXT: sd a4, 64(sp)
+; RV64-WITHFP-NEXT: addi a0, sp, 8
+; RV64-WITHFP-NEXT: addi a1, sp, 40
+; RV64-WITHFP-NEXT: sd a1, 8(sp)
; RV64-WITHFP-NEXT: lw a0, 4(a0)
-; RV64-WITHFP-NEXT: lwu a1, -24(s0)
-; RV64-WITHFP-NEXT: sd a5, 40(s0)
-; RV64-WITHFP-NEXT: sd a6, 48(s0)
-; RV64-WITHFP-NEXT: sd a7, 56(s0)
+; RV64-WITHFP-NEXT: lwu a1, 8(sp)
+; RV64-WITHFP-NEXT: sd a5, 72(sp)
+; RV64-WITHFP-NEXT: sd a6, 80(sp)
+; RV64-WITHFP-NEXT: sd a7, 88(sp)
; RV64-WITHFP-NEXT: slli a0, a0, 32
; RV64-WITHFP-NEXT: or a0, a0, a1
; RV64-WITHFP-NEXT: addi a1, a0, 4
; RV64-WITHFP-NEXT: srli a2, a1, 32
-; RV64-WITHFP-NEXT: sw a1, -24(s0)
-; RV64-WITHFP-NEXT: sw a2, -20(s0)
+; RV64-WITHFP-NEXT: sw a1, 8(sp)
+; RV64-WITHFP-NEXT: sw a2, 12(sp)
; RV64-WITHFP-NEXT: lw a0, 0(a0)
; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 96
; RV64-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -214,20 +214,20 @@ define iXLen @va1_va_arg(ptr %fmt, ...) nounwind {
; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 16
-; RV32-WITHFP-NEXT: sw a1, 4(s0)
-; RV32-WITHFP-NEXT: sw a2, 8(s0)
-; RV32-WITHFP-NEXT: sw a3, 12(s0)
-; RV32-WITHFP-NEXT: sw a4, 16(s0)
-; RV32-WITHFP-NEXT: sw a5, 20(s0)
-; RV32-WITHFP-NEXT: sw a6, 24(s0)
-; RV32-WITHFP-NEXT: sw a7, 28(s0)
-; RV32-WITHFP-NEXT: addi a0, s0, 4
-; RV32-WITHFP-NEXT: sw a0, -12(s0)
-; RV32-WITHFP-NEXT: lw a0, -12(s0)
+; RV32-WITHFP-NEXT: sw a1, 20(sp)
+; RV32-WITHFP-NEXT: sw a2, 24(sp)
+; RV32-WITHFP-NEXT: sw a3, 28(sp)
+; RV32-WITHFP-NEXT: sw a4, 32(sp)
+; RV32-WITHFP-NEXT: sw a5, 36(sp)
+; RV32-WITHFP-NEXT: sw a6, 40(sp)
+; RV32-WITHFP-NEXT: sw a7, 44(sp)
+; RV32-WITHFP-NEXT: addi a0, sp, 20
+; RV32-WITHFP-NEXT: sw a0, 4(sp)
+; RV32-WITHFP-NEXT: lw a0, 4(sp)
; RV32-WITHFP-NEXT: addi a0, a0, 3
; RV32-WITHFP-NEXT: andi a0, a0, -4
; RV32-WITHFP-NEXT: addi a1, a0, 4
-; RV32-WITHFP-NEXT: sw a1, -12(s0)
+; RV32-WITHFP-NEXT: sw a1, 4(sp)
; RV32-WITHFP-NEXT: lw a0, 0(a0)
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -240,20 +240,20 @@ define iXLen @va1_va_arg(ptr %fmt, ...) nounwind {
; RV64-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: addi s0, sp, 32
-; RV64-WITHFP-NEXT: sd a1, 8(s0)
-; RV64-WITHFP-NEXT: sd a2, 16(s0)
-; RV64-WITHFP-NEXT: sd a3, 24(s0)
-; RV64-WITHFP-NEXT: sd a4, 32(s0)
-; RV64-WITHFP-NEXT: sd a5, 40(s0)
-; RV64-WITHFP-NEXT: sd a6, 48(s0)
-; RV64-WITHFP-NEXT: sd a7, 56(s0)
-; RV64-WITHFP-NEXT: addi a0, s0, 8
-; RV64-WITHFP-NEXT: sd a0, -24(s0)
-; RV64-WITHFP-NEXT: ld a0, -24(s0)
+; RV64-WITHFP-NEXT: sd a1, 40(sp)
+; RV64-WITHFP-NEXT: sd a2, 48(sp)
+; RV64-WITHFP-NEXT: sd a3, 56(sp)
+; RV64-WITHFP-NEXT: sd a4, 64(sp)
+; RV64-WITHFP-NEXT: sd a5, 72(sp)
+; RV64-WITHFP-NEXT: sd a6, 80(sp)
+; RV64-WITHFP-NEXT: sd a7, 88(sp)
+; RV64-WITHFP-NEXT: addi a0, sp, 40
+; RV64-WITHFP-NEXT: sd a0, 8(sp)
+; RV64-WITHFP-NEXT: ld a0, 8(sp)
; RV64-WITHFP-NEXT: addi a0, a0, 7
; RV64-WITHFP-NEXT: andi a0, a0, -8
; RV64-WITHFP-NEXT: addi a1, a0, 8
-; RV64-WITHFP-NEXT: sd a1, -24(s0)
+; RV64-WITHFP-NEXT: sd a1, 8(sp)
; RV64-WITHFP-NEXT: ld a0, 0(a0)
; RV64-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@@ -628,20 +628,20 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 16
-; RV32-WITHFP-NEXT: sw a1, 4(s0)
-; RV32-WITHFP-NEXT: sw a2, 8(s0)
-; RV32-WITHFP-NEXT: sw a3, 12(s0)
-; RV32-WITHFP-NEXT: sw a4, 16(s0)
-; RV32-WITHFP-NEXT: addi a0, s0, 4
-; RV32-WITHFP-NEXT: sw a0, -12(s0)
-; RV32-WITHFP-NEXT: lw a0, -12(s0)
-; RV32-WITHFP-NEXT: sw a5, 20(s0)
-; RV32-WITHFP-NEXT: sw a6, 24(s0)
-; RV32-WITHFP-NEXT: sw a7, 28(s0)
+; RV32-WITHFP-NEXT: sw a1, 20(sp)
+; RV32-WITHFP-NEXT: sw a2, 24(sp)
+; RV32-WITHFP-NEXT: sw a3, 28(sp)
+; RV32-WITHFP-NEXT: sw a4, 32(sp)
+; RV32-WITHFP-NEXT: addi a0, sp, 20
+; RV32-WITHFP-NEXT: sw a0, 4(sp)
+; RV32-WITHFP-NEXT: lw a0, 4(sp)
+; RV32-WITHFP-NEXT: sw a5, 36(sp)
+; RV32-WITHFP-NEXT: sw a6, 40(sp)
+; RV32-WITHFP-NEXT: sw a7, 44(sp)
; RV32-WITHFP-NEXT: addi a1, a0, 7
; RV32-WITHFP-NEXT: addi a0, a0, 15
; RV32-WITHFP-NEXT: andi a1, a1, -8
-; RV32-WITHFP-NEXT: sw a0, -12(s0)
+; RV32-WITHFP-NEXT: sw a0, 4(sp)
; RV32-WITHFP-NEXT: lw a0, 0(a1)
; RV32-WITHFP-NEXT: lw a1, 4(a1)
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -655,20 +655,20 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; RV64-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: addi s0, sp, 32
-; RV64-WITHFP-NEXT: sd a1, 8(s0)
-; RV64-WITHFP-NEXT: sd a2, 16(s0)
-; RV64-WITHFP-NEXT: sd a3, 24(s0)
-; RV64-WITHFP-NEXT: sd a4, 32(s0)
-; RV64-WITHFP-NEXT: addi a0, s0, 8
-; RV64-WITHFP-NEXT: sd a0, -24(s0)
-; RV64-WITHFP-NEXT: ld a0, -24(s0)
-; RV64-WITHFP-NEXT: sd a5, 40(s0)
-; RV64-WITHFP-NEXT: sd a6, 48(s0)
-; RV64-WITHFP-NEXT: sd a7, 56(s0)
+; RV64-WITHFP-NEXT: sd a1, 40(sp)
+; RV64-WITHFP-NEXT: sd a2, 48(sp)
+; RV64-WITHFP-NEXT: sd a3, 56(sp)
+; RV64-WITHFP-NEXT: sd a4, 64(sp)
+; RV64-WITHFP-NEXT: addi a0, sp, 40
+; RV64-WITHFP-NEXT: sd a0, 8(sp)
+; RV64-WITHFP-NEXT: ld a0, 8(sp)
+; RV64-WITHFP-NEXT: sd a5, 72(sp)
+; RV64-WITHFP-NEXT: sd a6, 80(sp)
+; RV64-WITHFP-NEXT: sd a7, 88(sp)
; RV64-WITHFP-NEXT: addi a1, a0, 7
; RV64-WITHFP-NEXT: addi a0, a0, 15
; RV64-WITHFP-NEXT: andi a1, a1, -8
-; RV64-WITHFP-NEXT: sd a0, -24(s0)
+; RV64-WITHFP-NEXT: sd a0, 8(sp)
; RV64-WITHFP-NEXT: ld a0, 0(a1)
; RV64-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@@ -742,20 +742,20 @@ define iXLen @va2_va_arg(ptr %fmt, ...) nounwind {
; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 16
-; RV32-WITHFP-NEXT: sw a1, 4(s0)
-; RV32-WITHFP-NEXT: sw a2, 8(s0)
-; RV32-WITHFP-NEXT: sw a3, 12(s0)
-; RV32-WITHFP-NEXT: sw a4, 16(s0)
-; RV32-WITHFP-NEXT: sw a5, 20(s0)
-; RV32-WITHFP-NEXT: sw a6, 24(s0)
-; RV32-WITHFP-NEXT: sw a7, 28(s0)
-; RV32-WITHFP-NEXT: addi a0, s0, 4
-; RV32-WITHFP-NEXT: sw a0, -12(s0)
-; RV32-WITHFP-NEXT: lw a0, -12(s0)
+; RV32-WITHFP-NEXT: sw a1, 20(sp)
+; RV32-WITHFP-NEXT: sw a2, 24(sp)
+; RV32-WITHFP-NEXT: sw a3, 28(sp)
+; RV32-WITHFP-NEXT: sw a4, 32(sp)
+; RV32-WITHFP-NEXT: sw a5, 36(sp)
+; RV32-WITHFP-NEXT: sw a6, 40(sp)
+; RV32-WITHFP-NEXT: sw a7, 44(sp)
+; RV32-WITHFP-NEXT: addi a0, sp, 20
+; RV32-WITHFP-NEXT: sw a0, 4(sp)
+; RV32-WITHFP-NEXT: lw a0, 4(sp)
; RV32-WITHFP-NEXT: addi a0, a0, 3
; RV32-WITHFP-NEXT: andi a0, a0, -4
; RV32-WITHFP-NEXT: addi a1, a0, 4
-; RV32-WITHFP-NEXT: sw a1, -12(s0)
+; RV32-WITHFP-NEXT: sw a1, 4(sp)
; RV32-WITHFP-NEXT: lw a0, 0(a0)
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -768,20 +768,20 @@ define iXLen @va2_va_arg(ptr %fmt, ...) nounwind {
; RV64-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: addi s0, sp, 32
-; RV64-WITHFP-NEXT: sd a1, 8(s0)
-; RV64-WITHFP-NEXT: sd a2, 16(s0)
-; RV64-WITHFP-NEXT: sd a3, 24(s0)
-; RV64-WITHFP-NEXT: sd a4, 32(s0)
-; RV64-WITHFP-NEXT: sd a5, 40(s0)
-; RV64-WITHFP-NEXT: sd a6, 48(s0)
-; RV64-WITHFP-NEXT: sd a7, 56(s0)
-; RV64-WITHFP-NEXT: addi a0, s0, 8
-; RV64-WITHFP-NEXT: sd a0, -24(s0)
-; RV64-WITHFP-NEXT: ld a0, -24(s0)
+; RV64-WITHFP-NEXT: sd a1, 40(sp)
+; RV64-WITHFP-NEXT: sd a2, 48(sp)
+; RV64-WITHFP-NEXT: sd a3, 56(sp)
+; RV64-WITHFP-NEXT: sd a4, 64(sp)
+; RV64-WITHFP-NEXT: sd a5, 72(sp)
+; RV64-WITHFP-NEXT: sd a6, 80(sp)
+; RV64-WITHFP-NEXT: sd a7, 88(sp)
+; RV64-WITHFP-NEXT: addi a0, sp, 40
+; RV64-WITHFP-NEXT: sd a0, 8(sp)
+; RV64-WITHFP-NEXT: ld a0, 8(sp)
; RV64-WITHFP-NEXT: addi a0, a0, 7
; RV64-WITHFP-NEXT: andi a0, a0, -8
; RV64-WITHFP-NEXT: addi a1, a0, 8
-; RV64-WITHFP-NEXT: sd a1, -24(s0)
+; RV64-WITHFP-NEXT: sd a1, 8(sp)
; RV64-WITHFP-NEXT: ld a0, 0(a0)
; RV64-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@@ -977,18 +977,18 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV32-WITHFP-NEXT: sw ra, 20(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 16(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 24
-; RV32-WITHFP-NEXT: addi a0, s0, 4
-; RV32-WITHFP-NEXT: sw a0, -12(s0)
-; RV32-WITHFP-NEXT: lw a0, -12(s0)
-; RV32-WITHFP-NEXT: sw a3, 4(s0)
-; RV32-WITHFP-NEXT: sw a4, 8(s0)
-; RV32-WITHFP-NEXT: sw a5, 12(s0)
-; RV32-WITHFP-NEXT: sw a6, 16(s0)
-; RV32-WITHFP-NEXT: sw a7, 20(s0)
+; RV32-WITHFP-NEXT: addi a0, sp, 28
+; RV32-WITHFP-NEXT: sw a0, 12(sp)
+; RV32-WITHFP-NEXT: lw a0, 12(sp)
+; RV32-WITHFP-NEXT: sw a3, 28(sp)
+; RV32-WITHFP-NEXT: sw a4, 32(sp)
+; RV32-WITHFP-NEXT: sw a5, 36(sp)
+; RV32-WITHFP-NEXT: sw a6, 40(sp)
+; RV32-WITHFP-NEXT: sw a7, 44(sp)
; RV32-WITHFP-NEXT: addi a3, a0, 7
; RV32-WITHFP-NEXT: addi a0, a0, 15
; RV32-WITHFP-NEXT: andi a3, a3, -8
-; RV32-WITHFP-NEXT: sw a0, -12(s0)
+; RV32-WITHFP-NEXT: sw a0, 12(sp)
; RV32-WITHFP-NEXT: lw a4, 0(a3)
; RV32-WITHFP-NEXT: lw a3, 4(a3)
; RV32-WITHFP-NEXT: add a0, a1, a4
@@ -1006,19 +1006,19 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV64-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: addi s0, sp, 32
-; RV64-WITHFP-NEXT: mv a0, s0
-; RV64-WITHFP-NEXT: sd a0, -24(s0)
-; RV64-WITHFP-NEXT: ld a0, -24(s0)
-; RV64-WITHFP-NEXT: sd a2, 0(s0)
-; RV64-WITHFP-NEXT: sd a3, 8(s0)
-; RV64-WITHFP-NEXT: sd a4, 16(s0)
-; RV64-WITHFP-NEXT: sd a5, 24(s0)
-; RV64-WITHFP-NEXT: sd a6, 32(s0)
-; RV64-WITHFP-NEXT: sd a7, 40(s0)
+; RV64-WITHFP-NEXT: addi a0, sp, 32
+; RV64-WITHFP-NEXT: sd a0, 8(sp)
+; RV64-WITHFP-NEXT: ld a0, 8(sp)
+; RV64-WITHFP-NEXT: sd a2, 32(sp)
+; RV64-WITHFP-NEXT: sd a3, 40(sp)
+; RV64-WITHFP-NEXT: sd a4, 48(sp)
+; RV64-WITHFP-NEXT: sd a5, 56(sp)
+; RV64-WITHFP-NEXT: sd a6, 64(sp)
+; RV64-WITHFP-NEXT: sd a7, 72(sp)
; RV64-WITHFP-NEXT: addi a2, a0, 7
; RV64-WITHFP-NEXT: addi a0, a0, 15
; RV64-WITHFP-NEXT: andi a2, a2, -8
-; RV64-WITHFP-NEXT: sd a0, -24(s0)
+; RV64-WITHFP-NEXT: sd a0, 8(sp)
; RV64-WITHFP-NEXT: ld a0, 0(a2)
; RV64-WITHFP-NEXT: add a0, a1, a0
; RV64-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -1094,19 +1094,19 @@ define iXLen @va3_va_arg(iXLen %a, iXLen %b, ...) nounwind {
; RV32-WITHFP-NEXT: sw ra, 20(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 16(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 24
-; RV32-WITHFP-NEXT: sw a2, 0(s0)
-; RV32-WITHFP-NEXT: sw a3, 4(s0)
-; RV32-WITHFP-NEXT: sw a4, 8(s0)
-; RV32-WITHFP-NEXT: sw a5, 12(s0)
-; RV32-WITHFP-NEXT: sw a6, 16(s0)
-; RV32-WITHFP-NEXT: sw a7, 20(s0)
-; RV32-WITHFP-NEXT: mv a0, s0
-; RV32-WITHFP-NEXT: sw a0, -12(s0)
-; RV32-WITHFP-NEXT: lw a0, -12(s0)
+; RV32-WITHFP-NEXT: sw a2, 24(sp)
+; RV32-WITHFP-NEXT: sw a3, 28(sp)
+; RV32-WITHFP-NEXT: sw a4, 32(sp)
+; RV32-WITHFP-NEXT: sw a5, 36(sp)
+; RV32-WITHFP-NEXT: sw a6, 40(sp)
+; RV32-WITHFP-NEXT: sw a7, 44(sp)
+; RV32-WITHFP-NEXT: addi a0, sp, 24
+; RV32-WITHFP-NEXT: sw a0, 12(sp)
+; RV32-WITHFP-NEXT: lw a0, 12(sp)
; RV32-WITHFP-NEXT: addi a0, a0, 3
; RV32-WITHFP-NEXT: andi a0, a0, -4
; RV32-WITHFP-NEXT: addi a2, a0, 4
-; RV32-WITHFP-NEXT: sw a2, -12(s0)
+; RV32-WITHFP-NEXT: sw a2, 12(sp)
; RV32-WITHFP-NEXT: lw a0, 0(a0)
; RV32-WITHFP-NEXT: add a0, a1, a0
; RV32-WITHFP-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
@@ -1120,19 +1120,19 @@ define iXLen @va3_va_arg(iXLen %a, iXLen %b, ...) nounwind {
; RV64-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: addi s0, sp, 32
-; RV64-WITHFP-NEXT: sd a2, 0(s0)
-; RV64-WITHFP-NEXT: sd a3, 8(s0)
-; RV64-WITHFP-NEXT: sd a4, 16(s0)
-; RV64-WITHFP-NEXT: sd a5, 24(s0)
-; RV64-WITHFP-NEXT: sd a6, 32(s0)
-; RV64-WITHFP-NEXT: sd a7, 40(s0)
-; RV64-WITHFP-NEXT: mv a0, s0
-; RV64-WITHFP-NEXT: sd a0, -24(s0)
-; RV64-WITHFP-NEXT: ld a0, -24(s0)
+; RV64-WITHFP-NEXT: sd a2, 32(sp)
+; RV64-WITHFP-NEXT: sd a3, 40(sp)
+; RV64-WITHFP-NEXT: sd a4, 48(sp)
+; RV64-WITHFP-NEXT: sd a5, 56(sp)
+; RV64-WITHFP-NEXT: sd a6, 64(sp)
+; RV64-WITHFP-NEXT: sd a7, 72(sp)
+; RV64-WITHFP-NEXT: addi a0, sp, 32
+; RV64-WITHFP-NEXT: sd a0, 8(sp)
+; RV64-WITHFP-NEXT: ld a0, 8(sp)
; RV64-WITHFP-NEXT: addi a0, a0, 7
; RV64-WITHFP-NEXT: andi a0, a0, -8
; RV64-WITHFP-NEXT: addi a2, a0, 8
-; RV64-WITHFP-NEXT: sd a2, -24(s0)
+; RV64-WITHFP-NEXT: sd a2, 8(sp)
; RV64-WITHFP-NEXT: ld a0, 0(a0)
; RV64-WITHFP-NEXT: add a0, a1, a0
; RV64-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -1329,43 +1329,43 @@ define iXLen @va4_va_copy(i32 %argno, ...) nounwind {
; RV32-WITHFP-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 32
-; RV32-WITHFP-NEXT: sw a1, 4(s0)
-; RV32-WITHFP-NEXT: sw a2, 8(s0)
-; RV32-WITHFP-NEXT: sw a3, 12(s0)
-; RV32-WITHFP-NEXT: sw a4, 16(s0)
-; RV32-WITHFP-NEXT: sw a5, 20(s0)
-; RV32-WITHFP-NEXT: sw a6, 24(s0)
-; RV32-WITHFP-NEXT: sw a7, 28(s0)
-; RV32-WITHFP-NEXT: addi a0, s0, 4
-; RV32-WITHFP-NEXT: sw a0, -20(s0)
-; RV32-WITHFP-NEXT: lw a0, -20(s0)
+; RV32-WITHFP-NEXT: sw a1, 36(sp)
+; RV32-WITHFP-NEXT: sw a2, 40(sp)
+; RV32-WITHFP-NEXT: sw a3, 44(sp)
+; RV32-WITHFP-NEXT: sw a4, 48(sp)
+; RV32-WITHFP-NEXT: sw a5, 52(sp)
+; RV32-WITHFP-NEXT: sw a6, 56(sp)
+; RV32-WITHFP-NEXT: sw a7, 60(sp)
+; RV32-WITHFP-NEXT: addi a0, sp, 36
+; RV32-WITHFP-NEXT: sw a0, 12(sp)
+; RV...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/201541
More information about the llvm-commits
mailing list