[llvm] 808b9e5 - [GlobalISel] Combine sext(load), zext(load) patterns when the load has multiple uses (#182831)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 4 01:34:34 PDT 2026
Author: KRM7
Date: 2026-06-04T08:34:29Z
New Revision: 808b9e58c651486eee2e297b8814de90254082a2
URL: https://github.com/llvm/llvm-project/commit/808b9e58c651486eee2e297b8814de90254082a2
DIFF: https://github.com/llvm/llvm-project/commit/808b9e58c651486eee2e297b8814de90254082a2.diff
LOG: [GlobalISel] Combine sext(load), zext(load) patterns when the load has multiple uses (#182831)
Extend the existing combiners for sext(load), zext(load) patterns to also work when the load has multiple uses.
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
llvm/test/CodeGen/AMDGPU/ctlz.ll
llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
llvm/test/CodeGen/AMDGPU/cttz.ll
llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index a910a900e775f..6331d2d04cd60 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -994,19 +994,23 @@ bool CombinerHelper::matchCombineLoadWithAndMask(MachineInstr &MI,
// Don't use getOpcodeDef() here since intermediate instructions may have
// multiple users.
GAnyLoad *LoadMI = dyn_cast<GAnyLoad>(MRI.getVRegDef(SrcReg));
- if (!LoadMI || !MRI.hasOneNonDBGUse(LoadMI->getDstReg()))
+ if (!LoadMI)
return false;
Register LoadReg = LoadMI->getDstReg();
LLT RegTy = MRI.getType(LoadReg);
Register PtrReg = LoadMI->getPointerReg();
unsigned RegSize = RegTy.getSizeInBits();
- LocationSize LoadSizeBits = LoadMI->getMemSizeInBits();
+ unsigned LoadSizeBits = LoadMI->getMemSizeInBits().getValue();
unsigned MaskSizeBits = MaskVal.countr_one();
+ if ((isa<GSExtLoad>(LoadMI) || MaskSizeBits < LoadSizeBits) &&
+ !MRI.hasOneNonDBGUse(LoadReg))
+ return false;
+
// The mask may not be larger than the in-memory type, as it might cover sign
// extended bits
- if (MaskSizeBits > LoadSizeBits.getValue())
+ if (MaskSizeBits > LoadSizeBits)
return false;
// If the mask covers the whole destination register, there's nothing to
@@ -1026,8 +1030,7 @@ bool CombinerHelper::matchCombineLoadWithAndMask(MachineInstr &MI,
// still adjust the opcode to indicate the high bit behavior.
if (LoadMI->isSimple())
MemDesc.MemoryTy = LLT::scalar(MaskSizeBits);
- else if (LoadSizeBits.getValue() > MaskSizeBits ||
- LoadSizeBits.getValue() == RegSize)
+ else if (LoadSizeBits > MaskSizeBits || LoadSizeBits == RegSize)
return false;
// TODO: Could check if it's legal with the reduced or original memory size.
@@ -1041,6 +1044,7 @@ bool CombinerHelper::matchCombineLoadWithAndMask(MachineInstr &MI,
auto PtrInfo = MMO.getPointerInfo();
auto *NewMMO = MF.getMachineMemOperand(&MMO, PtrInfo, MemDesc.MemoryTy);
B.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, Dst, PtrReg, *NewMMO);
+ replaceRegWith(MRI, LoadReg, Dst);
LoadMI->eraseFromParent();
};
return true;
@@ -1119,16 +1123,20 @@ bool CombinerHelper::matchSextInRegOfLoad(
return false;
Register SrcReg = MI.getOperand(1).getReg();
- auto *LoadDef = getOpcodeDef<GLoad>(SrcReg, MRI);
- if (!LoadDef || !MRI.hasOneNonDBGUse(SrcReg))
+ auto *LoadDef = dyn_cast<GLoad>(MRI.getVRegDef(SrcReg));
+ if (!LoadDef)
return false;
uint64_t MemBits = LoadDef->getMemSizeInBits().getValue();
+ uint64_t ExtFrom = MI.getOperand(2).getImm();
+
+ if (MemBits > ExtFrom && !MRI.hasOneNonDBGUse(SrcReg))
+ return false;
// If the sign extend extends from a narrower width than the load's width,
// then we can narrow the load width when we combine to a G_SEXTLOAD.
// Avoid widening the load at all.
- unsigned NewSizeBits = std::min((uint64_t)MI.getOperand(2).getImm(), MemBits);
+ unsigned NewSizeBits = std::min(ExtFrom, MemBits);
// Don't generate G_SEXTLOADs with a < 1 byte width.
if (NewSizeBits < 8)
@@ -1180,6 +1188,7 @@ void CombinerHelper::applySextInRegOfLoad(
auto *NewMMO = MF.getMachineMemOperand(&MMO, PtrInfo, ScalarSizeBits / 8);
Builder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, MI.getOperand(0).getReg(),
LoadDef->getPointerReg(), *NewMMO);
+ replaceRegWith(MRI, LoadReg, MI.getOperand(0).getReg());
MI.eraseFromParent();
// Not all loads can be deleted, so make sure the old one is removed.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
index a7809f276c53f..15cefc50faa29 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
@@ -368,3 +368,125 @@ body: |
$w1 = COPY %v
$w0 = COPY %3
...
+
+---
+name: test_multi_use_load
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_multi_use_load
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: G_STORE [[ZEXTLOAD]](s32), [[COPY1]](p0) :: (store (s8))
+ ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_CONSTANT i32 255
+ %3:_(s32) = G_LOAD %0 :: (load (s8))
+ G_STORE %3, %1 :: (store (s8))
+ %4:_(s32) = G_AND %3, %2
+ $w0 = COPY %4
+...
+
+---
+name: test_multi_use_zextload
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_multi_use_zextload
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: G_STORE [[ZEXTLOAD]](s32), [[COPY1]](p0) :: (store (s8))
+ ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_CONSTANT i32 255
+ %3:_(s32) = G_ZEXTLOAD %0 :: (load (s8))
+ G_STORE %3, %1 :: (store (s8))
+ %4:_(s32) = G_AND %3, %2
+ $w0 = COPY %4
+...
+
+---
+name: test_multi_use_sextload
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_multi_use_sextload
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: G_STORE [[SEXTLOAD]](s32), [[COPY1]](p0) :: (store (s32))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_CONSTANT i32 255
+ %3:_(s32) = G_SEXTLOAD %0 :: (load (s8))
+ G_STORE %3, %1 :: (store (s32))
+ %4:_(s32) = G_AND %3, %2
+ $w0 = COPY %4
+...
+
+---
+name: test_multi_use_load_large_mask
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_multi_use_load_large_mask
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: G_STORE [[LOAD]](s32), [[COPY1]](p0) :: (store (s32))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_CONSTANT i32 65535
+ %3:_(s32) = G_LOAD %0 :: (load (s8))
+ G_STORE %3, %1 :: (store (s32))
+ %4:_(s32) = G_AND %3, %2
+ $w0 = COPY %4
+...
+
+---
+name: test_multi_use_sextload_large_mask
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_multi_use_sextload_large_mask
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: G_STORE [[SEXTLOAD]](s32), [[COPY1]](p0) :: (store (s32))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_CONSTANT i32 65535
+ %3:_(s32) = G_SEXTLOAD %0 :: (load (s8))
+ G_STORE %3, %1 :: (store (s32))
+ %4:_(s32) = G_AND %3, %2
+ $w0 = COPY %4
+...
+
+---
+name: test_multi_use_load_small_mask
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_multi_use_load_small_mask
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: G_STORE [[LOAD]](s32), [[COPY1]](p0) :: (store (s32))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_CONSTANT i32 255
+ %3:_(s32) = G_LOAD %0 :: (load (s16))
+ G_STORE %3, %1 :: (store (s32))
+ %4:_(s32) = G_AND %3, %2
+ $w0 = COPY %4
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
index e827341e909d9..662f21be2033a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -aarch64prelegalizercombiner-only-enable-rule="sext_inreg_of_load" -verify-machineinstrs %s -o - | FileCheck %s
---
name: sextload_from_inreg
alignment: 4
@@ -134,3 +134,61 @@ body: |
RET_ReallyLR implicit $w0
...
+
+---
+name: test_one_use_copy_multi_use_load
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_one_use_copy_multi_use_load
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: G_STORE [[LOAD]](s32), [[COPY1]](p0) :: (store (s16))
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; CHECK-NEXT: $w0 = COPY [[SEXT_INREG]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_LOAD %0 :: (load (s16))
+ G_STORE %2, %1 :: (store (s16))
+ %3:_(s32) = COPY %2
+ %4:_(s32) = G_SEXT_INREG %3, 8
+ $w0 = COPY %4
+...
+
+---
+name: test_multi_use_load
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_multi_use_load
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: G_STORE [[SEXTLOAD]](s32), [[COPY1]](p0) :: (store (s8))
+ ; CHECK-NEXT: $w0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_LOAD %0 :: (load (s8))
+ G_STORE %2, %1 :: (store (s8))
+ %3:_(s32) = G_SEXT_INREG %2, 8
+ $w0 = COPY %3
+...
+
+---
+name: test_multi_use_load_large_memsize
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_multi_use_load_large_memsize
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: G_STORE [[LOAD]](s32), [[COPY1]](p0) :: (store (s16))
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
+ ; CHECK-NEXT: $w0 = COPY [[SEXT_INREG]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s32) = G_LOAD %0 :: (load (s16))
+ G_STORE %2, %1 :: (store (s16))
+ %3:_(s32) = G_SEXT_INREG %2, 8
+ $w0 = COPY %3
+...
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll
index f0827bc60483e..8c3b5be0b0ae0 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -2171,8 +2171,8 @@ define amdgpu_kernel void @v_ctlz_i8_sel_eq_neg1(ptr addrspace(1) noalias %out,
; GFX10-GISEL-NEXT: global_load_ushort v1, v0, s[2:3]
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s2, v1
-; GFX10-GISEL-NEXT: s_and_b32 s2, s2, 0xffff
; GFX10-GISEL-NEXT: s_flbit_i32_b32 s3, s2
+; GFX10-GISEL-NEXT: s_and_b32 s2, 0xffff, s2
; GFX10-GISEL-NEXT: s_min_u32 s3, s3, 32
; GFX10-GISEL-NEXT: s_add_i32 s3, s3, 0xfff0
; GFX10-GISEL-NEXT: s_cmp_eq_u32 s2, 0
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
index 8c288ec551063..867bd8ee26227 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
@@ -658,7 +658,7 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i8_with_select(ptr addrspace(1) no
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_lshl_b32 s3, s2, 24
; GFX9-GISEL-NEXT: s_flbit_i32_b32 s3, s3
-; GFX9-GISEL-NEXT: s_and_b32 s2, s2, 0xff
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s3, 32
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX9-GISEL-NEXT: global_store_byte v0, v1, s[0:1]
@@ -1733,13 +1733,13 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i8_sel_eq_neg1(ptr addrspace(1) no
; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v1, v0
; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v3, vcc
; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0xffff
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v3, 24, v0
-; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v3, v3
-; GFX9-GISEL-NEXT: v_cmp_eq_u32_sdwa vcc, v0, v1 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v0
+; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v2, v2
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX9-GISEL-NEXT: global_store_byte v1, v0, s[0:1]
; GFX9-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/cttz.ll b/llvm/test/CodeGen/AMDGPU/cttz.ll
index bdad7e61f032f..974e7179988e5 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz.ll
@@ -1355,14 +1355,14 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s3
; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v1, v0
; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v2, v3, vcc_lo
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, 0x100, v0
-; GFX10-GISEL-NEXT: v_cmp_eq_u32_sdwa s2, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-GISEL-NEXT: v_ffbl_b32_e32 v1, v1
-; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0xffff, s2
-; GFX10-GISEL-NEXT: global_store_byte v2, v0, s[0:1]
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0xffff, vcc_lo
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-GISEL-NEXT: global_store_byte v1, v0, s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%valptr.gep = getelementptr i8, ptr addrspace(1) %valptr, i32 %tid
diff --git a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
index 0f5ee9d407f25..60d87fe22f208 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
@@ -630,7 +630,7 @@ define amdgpu_kernel void @v_cttz_zero_poison_i8_with_select(ptr addrspace(1) no
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_ff1_i32_b32 s3, s2
-; GFX9-GISEL-NEXT: s_and_b32 s2, s2, 0xff
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, s3, 32
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s2
; GFX9-GISEL-NEXT: global_store_byte v0, v1, s[0:1]
@@ -1551,7 +1551,6 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-GISEL-NEXT: s_or_b32 s3, s2, 0x100
-; GFX9-GISEL-NEXT: s_and_b32 s2, s2, 0xff
; GFX9-GISEL-NEXT: s_ff1_i32_b32 s3, s3
; GFX9-GISEL-NEXT: s_cmp_eq_u32 s2, 0
; GFX9-GISEL-NEXT: s_cselect_b32 s2, 0xffff, s3
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