[llvm] [SelectionDAG] Pre-commit tests for dagcombine improvements (PR #201270)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 4 00:56:06 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/201270
>From 7f971784663f29ac8b61d4585ff5bff981834fa3 Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Tue, 2 Jun 2026 16:51:34 +0000
Subject: [PATCH 1/3] [SelectionDAG] Pre-commit tests for dagcombine
improvements
I've got a stack of dagcombine improvements that together make an
infinite cycle relating to freeze insertion in vector-manipulation IR.
Here we have
- Handling freeze(undef) in demanded-elts for shufflevector
- Improvements to noundef checks for bitcast, concat, and select
- Improvements to extract(concat), extract(extract), and
- extract(insert) nadling
---
.../CodeGen/X86/dagcombine-extract-concat.ll | 25 ++++++
.../CodeGen/X86/dagcombine-extract-insert.ll | 51 +++++++++++
...dagcombine-freeze-bitcast-demanded-elts.ll | 56 +++++++++++++
.../dagcombine-freeze-concat-demanded-elts.ll | 20 +++++
.../dagcombine-freeze-select-demanded-elts.ll | 84 +++++++++++++++++++
.../dagcombine-freeze-undef-demanded-elts.ll | 36 ++++++++
.../CodeGen/X86/dagcombine-insert-concat.ll | 38 +++++++++
7 files changed, 310 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/dagcombine-extract-concat.ll
create mode 100644 llvm/test/CodeGen/X86/dagcombine-extract-insert.ll
create mode 100644 llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll
create mode 100644 llvm/test/CodeGen/X86/dagcombine-freeze-concat-demanded-elts.ll
create mode 100644 llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll
create mode 100644 llvm/test/CodeGen/X86/dagcombine-freeze-undef-demanded-elts.ll
create mode 100644 llvm/test/CodeGen/X86/dagcombine-insert-concat.ll
diff --git a/llvm/test/CodeGen/X86/dagcombine-extract-concat.ll b/llvm/test/CodeGen/X86/dagcombine-extract-concat.ll
new file mode 100644
index 0000000000000..9d203b0eb3d17
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dagcombine-extract-concat.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
+
+define <16 x i32> @extract_concat_pmaddwd(<32 x i16> %a, <32 x i16> %b) {
+; CHECK-LABEL: extract_concat_pmaddwd:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm4
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm5
+; CHECK-NEXT: vpmaddwd %xmm4, %xmm5, %xmm4
+; CHECK-NEXT: vpmaddwd %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; CHECK-NEXT: vextractf128 $1, %ymm3, %xmm2
+; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm4
+; CHECK-NEXT: vpmaddwd %xmm2, %xmm4, %xmm2
+; CHECK-NEXT: vpmaddwd %xmm3, %xmm1, %xmm1
+; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; CHECK-NEXT: retq
+ %a.ext = sext <32 x i16> %a to <32 x i32>
+ %b.ext = sext <32 x i16> %b to <32 x i32>
+ %m = mul nsw <32 x i32> %a.ext, %b.ext
+ %odd = shufflevector <32 x i32> %m, <32 x i32> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+ %even = shufflevector <32 x i32> %m, <32 x i32> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+ %ret = add <16 x i32> %odd, %even
+ ret <16 x i32> %ret
+}
diff --git a/llvm/test/CodeGen/X86/dagcombine-extract-insert.ll b/llvm/test/CodeGen/X86/dagcombine-extract-insert.ll
new file mode 100644
index 0000000000000..c0595fce4117d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dagcombine-extract-insert.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512bw < %s | FileCheck %s
+
+define void @extract_insert_interleaved_store(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecptr2, ptr %in.vecptr3, ptr %in.vecptr4, ptr %in.vecptr5, ptr %out.vec) {
+; CHECK-LABEL: extract_insert_interleaved_store:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; CHECK-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; CHECK-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; CHECK-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; CHECK-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
+; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm3
+; CHECK-NEXT: vmovdqa {{.*#+}} ymm4 = [0,8,0,8,u,u,1,9,1,9,u,u,2,10,2,10,u,u,3,11,3,11,u,u,4,12,4,12,u,u,5,13]
+; CHECK-NEXT: vpshufb %ymm4, %ymm3, %ymm5
+; CHECK-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,3,0,1]
+; CHECK-NEXT: vpshufb %ymm4, %ymm3, %ymm3
+; CHECK-NEXT: vpblendw {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2,3],ymm3[4],ymm5[5,6],ymm3[7],ymm5[8],ymm3[9],ymm5[10,11],ymm3[12],ymm5[13,14],ymm3[15]
+; CHECK-NEXT: vpshufb {{.*#+}} xmm4 = xmm2[2,10,1,9,0,8,3,11,u,u,u,u,4,12,u,u]
+; CHECK-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,0,1]
+; CHECK-NEXT: vpmovsxbw {{.*#+}} ymm5 = [65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535]
+; CHECK-NEXT: vpblendvb %ymm5, %ymm3, %ymm4, %ymm3
+; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,xmm0[u,u,6,14],zero,zero,xmm0[u,u,7,15],zero,zero,xmm0[u,u]
+; CHECK-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[5,13,u,u],zero,zero,xmm1[6,14,u,u],zero,zero,xmm1[7,15,u,u]
+; CHECK-NEXT: vpor %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vpshufb {{.*#+}} xmm1 = xmm2[u,u,5,13,u,u,u,u,6,14,u,u,u,u,7,15]
+; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4],xmm0[5,6],xmm1[7]
+; CHECK-NEXT: vmovdqa %xmm0, 32(%rax)
+; CHECK-NEXT: vmovdqa %ymm3, (%rax)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %in.vec0 = load <8 x i8>, ptr %in.vecptr0, align 64
+ %in.vec1 = load <8 x i8>, ptr %in.vecptr1, align 64
+ %in.vec2 = load <8 x i8>, ptr %in.vecptr2, align 64
+ %in.vec3 = load <8 x i8>, ptr %in.vecptr3, align 64
+ %in.vec4 = load <8 x i8>, ptr %in.vecptr4, align 64
+ %in.vec5 = load <8 x i8>, ptr %in.vecptr5, align 64
+ %1 = shufflevector <8 x i8> %in.vec0, <8 x i8> %in.vec1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %2 = shufflevector <8 x i8> %in.vec2, <8 x i8> %in.vec3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %3 = shufflevector <8 x i8> %in.vec4, <8 x i8> %in.vec5, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %4 = shufflevector <16 x i8> %1, <16 x i8> %2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ %5 = shufflevector <16 x i8> %3, <16 x i8> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+ %6 = shufflevector <32 x i8> %4, <32 x i8> %5, <48 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47>
+ %interleaved.vec = shufflevector <48 x i8> %6, <48 x i8> poison, <48 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 40, i32 1, i32 9, i32 17, i32 25, i32 33, i32 41, i32 2, i32 10, i32 18, i32 26, i32 34, i32 42, i32 3, i32 11, i32 19, i32 27, i32 35, i32 43, i32 4, i32 12, i32 20, i32 28, i32 36, i32 44, i32 5, i32 13, i32 21, i32 29, i32 37, i32 45, i32 6, i32 14, i32 22, i32 30, i32 38, i32 46, i32 7, i32 15, i32 23, i32 31, i32 39, i32 47>
+ store <48 x i8> %interleaved.vec, ptr %out.vec, align 64
+ ret void
+}
diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll
new file mode 100644
index 0000000000000..aa619567c56af
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx2 < %s | FileCheck %s
+
+declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64 immarg)
+declare <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64>, i64 immarg)
+
+define <4 x i32> @freeze_extract_bitcast_high_demanded(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: freeze_extract_bitcast_high_demanded:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %poisonable = add nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807>
+ %wide = shufflevector <2 x i64> %poisonable, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %bc = bitcast <4 x i64> %wide to <8 x i32>
+ %shifted = lshr <8 x i32> %bc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %fr = freeze <8 x i32> %shifted
+ %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
+ ret <4 x i32> %ext
+}
+
+define <2 x i64> @freeze_extract_bitcast_low_width_high_demanded(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: freeze_extract_bitcast_low_width_high_demanded:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: vpsrlq $1, %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %poisonable = add nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %wide = shufflevector <4 x i32> %poisonable, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %bc = bitcast <8 x i32> %wide to <4 x i64>
+ %shifted = lshr <4 x i64> %bc, <i64 1, i64 1, i64 1, i64 1>
+ %fr = freeze <4 x i64> %shifted
+ %ext = call <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64> %fr, i64 2)
+ ret <2 x i64> %ext
+}
+
+define <4 x i32> @freeze_extract_bitcast_equal_width_high_demanded(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: freeze_extract_bitcast_equal_width_high_demanded:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %poisonable = fadd nnan <4 x float> %a, zeroinitializer
+ %wide = shufflevector <4 x float> %poisonable, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %bc = bitcast <8 x float> %wide to <8 x i32>
+ %shifted = lshr <8 x i32> %bc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %fr = freeze <8 x i32> %shifted
+ %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
+ ret <4 x i32> %ext
+}
diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-concat-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-concat-demanded-elts.ll
new file mode 100644
index 0000000000000..5988e1b6150df
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dagcombine-freeze-concat-demanded-elts.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx2 < %s | FileCheck %s
+
+declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64 immarg)
+
+define <4 x i32> @freeze_lshr_extract_concat_high_demanded(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: freeze_lshr_extract_concat_high_demanded:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %poisonable = add nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %wide = shufflevector <4 x i32> %poisonable, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %shifted = lshr <8 x i32> %wide, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %fr = freeze <8 x i32> %shifted
+ %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
+ ret <4 x i32> %ext
+}
diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll
new file mode 100644
index 0000000000000..21241af18a3c9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s
+
+declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64 immarg)
+
+define i32 @freeze_select_scalar_demanded(i1 %c, <2 x i32> %a, <2 x i32> %b, <2 x i32> %d) {
+; CHECK-LABEL: freeze_select_scalar_demanded:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: jne .LBB0_1
+; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: movd %xmm0, %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: .LBB0_1:
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [2147483647,2147483647,u,u]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT: movd %xmm0, %eax
+; CHECK-NEXT: retq
+ %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
+ %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
+ %lhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %rhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %sel = select i1 %c, <4 x i32> %lhs, <4 x i32> %rhs
+ %fr = freeze <4 x i32> %sel
+ %ext = extractelement <4 x i32> %fr, i64 0
+ ret i32 %ext
+}
+
+define <2 x i32> @freeze_vselect_high_demanded(<4 x i32> %csrc, <2 x i32> %a, <2 x i32> %b, <2 x i32> %e, <2 x i32> %d) {
+; CHECK-LABEL: freeze_vselect_high_demanded:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa {{.*#+}} xmm5 = [2147483647,2147483647,2147483647,2147483647]
+; CHECK-NEXT: paddd %xmm0, %xmm5
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm0[2,3]
+; CHECK-NEXT: pxor %xmm0, %xmm0
+; CHECK-NEXT: pcmpgtd %xmm0, %xmm5
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [2147483647,2147483647,u,u]
+; CHECK-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
+; CHECK-NEXT: pand %xmm5, %xmm2
+; CHECK-NEXT: pandn %xmm4, %xmm5
+; CHECK-NEXT: por %xmm2, %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm5[2,3,2,3]
+; CHECK-NEXT: retq
+ %poisonable.c.val = add nsw <4 x i32> %csrc, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %poisonable.c = icmp sgt <4 x i32> %poisonable.c.val, zeroinitializer
+ %safe.c = icmp sgt <4 x i32> %csrc, zeroinitializer
+ %cond = shufflevector <4 x i1> %poisonable.c, <4 x i1> %safe.c, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
+ %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
+ %lhs = shufflevector <2 x i32> %poisonable.b, <2 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %rhs = shufflevector <2 x i32> %poisonable.d, <2 x i32> %e, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %sel = select <4 x i1> %cond, <4 x i32> %lhs, <4 x i32> %rhs
+ %fr = freeze <4 x i32> %sel
+ %ext = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %fr, i64 2)
+ ret <2 x i32> %ext
+}
+
+define i32 @freeze_vselect_demanded(<4 x i32> %csrc, <2 x i32> %a, <2 x i32> %b, <2 x i32> %e, <2 x i32> %d) {
+; CHECK-LABEL: freeze_vselect_demanded:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pxor %xmm2, %xmm2
+; CHECK-NEXT: pcmpgtd %xmm2, %xmm0
+; CHECK-NEXT: pand %xmm0, %xmm1
+; CHECK-NEXT: pandn %xmm3, %xmm0
+; CHECK-NEXT: por %xmm1, %xmm0
+; CHECK-NEXT: movd %xmm0, %eax
+; CHECK-NEXT: retq
+ %safe.c = icmp sgt <4 x i32> %csrc, zeroinitializer
+ %poisonable.c.val = add nsw <4 x i32> %csrc, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %poisonable.c = icmp sgt <4 x i32> %poisonable.c.val, zeroinitializer
+ %cond = shufflevector <4 x i1> %safe.c, <4 x i1> %poisonable.c, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+ %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
+ %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
+ %lhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %rhs = shufflevector <2 x i32> %e, <2 x i32> %poisonable.d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %sel = select <4 x i1> %cond, <4 x i32> %lhs, <4 x i32> %rhs
+ %fr = freeze <4 x i32> %sel
+ %ext = extractelement <4 x i32> %fr, i64 0
+ ret i32 %ext
+}
diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-undef-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-undef-demanded-elts.ll
new file mode 100644
index 0000000000000..fbf9945a73cb9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dagcombine-freeze-undef-demanded-elts.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s | FileCheck %s
+
+define void @freeze_undef_demanded_elts(ptr %p) minsize {
+; CHECK-LABEL: freeze_undef_demanded_elts:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testb %al, %al
+; CHECK-NEXT: je .LBB0_2
+; CHECK-NEXT: # %bb.1: # %bb
+; CHECK-NEXT: movl $31744, %eax # imm = 0x7C00
+; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vpcmpeqw %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpinsrw $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vcvtps2ph $4, %xmm0, %xmm0
+; CHECK-NEXT: vpextrw $0, %xmm0, (%rdi)
+; CHECK-NEXT: .LBB0_2: # %ret
+; CHECK-NEXT: retq
+ %poison.as.i16 = bitcast <2 x half> poison to <2 x i16>
+ %cmp = icmp eq <2 x i16> %poison.as.i16, <i16 31744, i16 31744>
+ br i1 poison, label %bb, label %ret
+
+ret:
+ ret void
+
+bb:
+ %sel = select <2 x i1> %cmp, <2 x half> <half 0xH3C00, half 0xH3C00>, <2 x half> zeroinitializer
+ %mul = fmul <2 x half> %sel, zeroinitializer
+ %sub = fsub <2 x half> %mul, zeroinitializer
+ %elt = extractelement <2 x half> %sub, i64 0
+ store half %elt, ptr %p, align 2
+ br label %ret
+}
diff --git a/llvm/test/CodeGen/X86/dagcombine-insert-concat.ll b/llvm/test/CodeGen/X86/dagcombine-insert-concat.ll
new file mode 100644
index 0000000000000..a143b85ec74d6
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dagcombine-insert-concat.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512bw < %s | FileCheck %s
+
+declare <32 x i16> @llvm.vector.insert.v32i16.v4i16(<32 x i16>, <4 x i16>, i64 immarg)
+
+define <32 x i16> @insert_concat_select(i1 %cond, <16 x i16> %a, <16 x i16> %b, <4 x i16> %sub, <32 x i16> %alt) {
+; CHECK-LABEL: insert_concat_select:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: je .LBB0_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm3
+; CHECK-NEXT: vmovd %xmm2, %eax
+; CHECK-NEXT: movl $65536, %ecx # imm = 0x10000
+; CHECK-NEXT: kmovd %ecx, %k1
+; CHECK-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
+; CHECK-NEXT: vpextrw $1, %xmm2, %eax
+; CHECK-NEXT: movl $131072, %ecx # imm = 0x20000
+; CHECK-NEXT: kmovd %ecx, %k1
+; CHECK-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
+; CHECK-NEXT: vpextrw $2, %xmm2, %eax
+; CHECK-NEXT: movl $262144, %ecx # imm = 0x40000
+; CHECK-NEXT: kmovd %ecx, %k1
+; CHECK-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
+; CHECK-NEXT: vpextrw $3, %xmm2, %eax
+; CHECK-NEXT: movl $524288, %ecx # imm = 0x80000
+; CHECK-NEXT: kmovd %ecx, %k1
+; CHECK-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
+; CHECK-NEXT: .LBB0_2: # %entry
+; CHECK-NEXT: vmovdqa64 %zmm3, %zmm0
+; CHECK-NEXT: retq
+entry:
+ %wide = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ %ins = call <32 x i16> @llvm.vector.insert.v32i16.v4i16(<32 x i16> %wide, <4 x i16> %sub, i64 16)
+ %sel = select i1 %cond, <32 x i16> %ins, <32 x i16> %alt
+ ret <32 x i16> %sel
+}
>From 0f2ebc784311266a7e3fd2a7fc8d0b2966d07224 Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Wed, 3 Jun 2026 17:22:52 +0000
Subject: [PATCH 2/3] Move tests around per review feedback
---
.../CodeGen/X86/dagcombine-extract-concat.ll | 25 --
.../CodeGen/X86/dagcombine-extract-insert.ll | 51 ----
...dagcombine-freeze-bitcast-demanded-elts.ll | 56 -----
.../dagcombine-freeze-concat-demanded-elts.ll | 20 --
.../dagcombine-freeze-select-demanded-elts.ll | 84 -------
.../CodeGen/X86/dagcombine-insert-concat.ll | 38 ---
llvm/test/CodeGen/X86/freeze-vector.ll | 230 ++++++++++++++++++
llvm/test/CodeGen/X86/madd.ll | 64 +++++
.../vector-shuffle-combining-avx512bwvl.ll | 73 ++++++
9 files changed, 367 insertions(+), 274 deletions(-)
delete mode 100644 llvm/test/CodeGen/X86/dagcombine-extract-concat.ll
delete mode 100644 llvm/test/CodeGen/X86/dagcombine-extract-insert.ll
delete mode 100644 llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll
delete mode 100644 llvm/test/CodeGen/X86/dagcombine-freeze-concat-demanded-elts.ll
delete mode 100644 llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll
delete mode 100644 llvm/test/CodeGen/X86/dagcombine-insert-concat.ll
diff --git a/llvm/test/CodeGen/X86/dagcombine-extract-concat.ll b/llvm/test/CodeGen/X86/dagcombine-extract-concat.ll
deleted file mode 100644
index 9d203b0eb3d17..0000000000000
--- a/llvm/test/CodeGen/X86/dagcombine-extract-concat.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
-
-define <16 x i32> @extract_concat_pmaddwd(<32 x i16> %a, <32 x i16> %b) {
-; CHECK-LABEL: extract_concat_pmaddwd:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm4
-; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm5
-; CHECK-NEXT: vpmaddwd %xmm4, %xmm5, %xmm4
-; CHECK-NEXT: vpmaddwd %xmm2, %xmm0, %xmm0
-; CHECK-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
-; CHECK-NEXT: vextractf128 $1, %ymm3, %xmm2
-; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm4
-; CHECK-NEXT: vpmaddwd %xmm2, %xmm4, %xmm2
-; CHECK-NEXT: vpmaddwd %xmm3, %xmm1, %xmm1
-; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; CHECK-NEXT: retq
- %a.ext = sext <32 x i16> %a to <32 x i32>
- %b.ext = sext <32 x i16> %b to <32 x i32>
- %m = mul nsw <32 x i32> %a.ext, %b.ext
- %odd = shufflevector <32 x i32> %m, <32 x i32> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
- %even = shufflevector <32 x i32> %m, <32 x i32> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
- %ret = add <16 x i32> %odd, %even
- ret <16 x i32> %ret
-}
diff --git a/llvm/test/CodeGen/X86/dagcombine-extract-insert.ll b/llvm/test/CodeGen/X86/dagcombine-extract-insert.ll
deleted file mode 100644
index c0595fce4117d..0000000000000
--- a/llvm/test/CodeGen/X86/dagcombine-extract-insert.ll
+++ /dev/null
@@ -1,51 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512bw < %s | FileCheck %s
-
-define void @extract_insert_interleaved_store(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecptr2, ptr %in.vecptr3, ptr %in.vecptr4, ptr %in.vecptr5, ptr %out.vec) {
-; CHECK-LABEL: extract_insert_interleaved_store:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; CHECK-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; CHECK-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; CHECK-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
-; CHECK-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
-; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm3
-; CHECK-NEXT: vmovdqa {{.*#+}} ymm4 = [0,8,0,8,u,u,1,9,1,9,u,u,2,10,2,10,u,u,3,11,3,11,u,u,4,12,4,12,u,u,5,13]
-; CHECK-NEXT: vpshufb %ymm4, %ymm3, %ymm5
-; CHECK-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,3,0,1]
-; CHECK-NEXT: vpshufb %ymm4, %ymm3, %ymm3
-; CHECK-NEXT: vpblendw {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2,3],ymm3[4],ymm5[5,6],ymm3[7],ymm5[8],ymm3[9],ymm5[10,11],ymm3[12],ymm5[13,14],ymm3[15]
-; CHECK-NEXT: vpshufb {{.*#+}} xmm4 = xmm2[2,10,1,9,0,8,3,11,u,u,u,u,4,12,u,u]
-; CHECK-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,0,0,1]
-; CHECK-NEXT: vpmovsxbw {{.*#+}} ymm5 = [65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535]
-; CHECK-NEXT: vpblendvb %ymm5, %ymm3, %ymm4, %ymm3
-; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,xmm0[u,u,6,14],zero,zero,xmm0[u,u,7,15],zero,zero,xmm0[u,u]
-; CHECK-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[5,13,u,u],zero,zero,xmm1[6,14,u,u],zero,zero,xmm1[7,15,u,u]
-; CHECK-NEXT: vpor %xmm0, %xmm1, %xmm0
-; CHECK-NEXT: vpshufb {{.*#+}} xmm1 = xmm2[u,u,5,13,u,u,u,u,6,14,u,u,u,u,7,15]
-; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4],xmm0[5,6],xmm1[7]
-; CHECK-NEXT: vmovdqa %xmm0, 32(%rax)
-; CHECK-NEXT: vmovdqa %ymm3, (%rax)
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %in.vec0 = load <8 x i8>, ptr %in.vecptr0, align 64
- %in.vec1 = load <8 x i8>, ptr %in.vecptr1, align 64
- %in.vec2 = load <8 x i8>, ptr %in.vecptr2, align 64
- %in.vec3 = load <8 x i8>, ptr %in.vecptr3, align 64
- %in.vec4 = load <8 x i8>, ptr %in.vecptr4, align 64
- %in.vec5 = load <8 x i8>, ptr %in.vecptr5, align 64
- %1 = shufflevector <8 x i8> %in.vec0, <8 x i8> %in.vec1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %2 = shufflevector <8 x i8> %in.vec2, <8 x i8> %in.vec3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %3 = shufflevector <8 x i8> %in.vec4, <8 x i8> %in.vec5, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %4 = shufflevector <16 x i8> %1, <16 x i8> %2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- %5 = shufflevector <16 x i8> %3, <16 x i8> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
- %6 = shufflevector <32 x i8> %4, <32 x i8> %5, <48 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47>
- %interleaved.vec = shufflevector <48 x i8> %6, <48 x i8> poison, <48 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 40, i32 1, i32 9, i32 17, i32 25, i32 33, i32 41, i32 2, i32 10, i32 18, i32 26, i32 34, i32 42, i32 3, i32 11, i32 19, i32 27, i32 35, i32 43, i32 4, i32 12, i32 20, i32 28, i32 36, i32 44, i32 5, i32 13, i32 21, i32 29, i32 37, i32 45, i32 6, i32 14, i32 22, i32 30, i32 38, i32 46, i32 7, i32 15, i32 23, i32 31, i32 39, i32 47>
- store <48 x i8> %interleaved.vec, ptr %out.vec, align 64
- ret void
-}
diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll
deleted file mode 100644
index aa619567c56af..0000000000000
--- a/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll
+++ /dev/null
@@ -1,56 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx2 < %s | FileCheck %s
-
-declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64 immarg)
-declare <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64>, i64 immarg)
-
-define <4 x i32> @freeze_extract_bitcast_high_demanded(<2 x i64> %a, <2 x i64> %b) {
-; CHECK-LABEL: freeze_extract_bitcast_high_demanded:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0
-; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %poisonable = add nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807>
- %wide = shufflevector <2 x i64> %poisonable, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %bc = bitcast <4 x i64> %wide to <8 x i32>
- %shifted = lshr <8 x i32> %bc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
- %fr = freeze <8 x i32> %shifted
- %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
- ret <4 x i32> %ext
-}
-
-define <2 x i64> @freeze_extract_bitcast_low_width_high_demanded(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-LABEL: freeze_extract_bitcast_low_width_high_demanded:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT: vpsrlq $1, %ymm0, %ymm0
-; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %poisonable = add nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
- %wide = shufflevector <4 x i32> %poisonable, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- %bc = bitcast <8 x i32> %wide to <4 x i64>
- %shifted = lshr <4 x i64> %bc, <i64 1, i64 1, i64 1, i64 1>
- %fr = freeze <4 x i64> %shifted
- %ext = call <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64> %fr, i64 2)
- ret <2 x i64> %ext
-}
-
-define <4 x i32> @freeze_extract_bitcast_equal_width_high_demanded(<4 x float> %a, <4 x float> %b) {
-; CHECK-LABEL: freeze_extract_bitcast_equal_width_high_demanded:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0
-; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %poisonable = fadd nnan <4 x float> %a, zeroinitializer
- %wide = shufflevector <4 x float> %poisonable, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- %bc = bitcast <8 x float> %wide to <8 x i32>
- %shifted = lshr <8 x i32> %bc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
- %fr = freeze <8 x i32> %shifted
- %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
- ret <4 x i32> %ext
-}
diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-concat-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-concat-demanded-elts.ll
deleted file mode 100644
index 5988e1b6150df..0000000000000
--- a/llvm/test/CodeGen/X86/dagcombine-freeze-concat-demanded-elts.ll
+++ /dev/null
@@ -1,20 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx2 < %s | FileCheck %s
-
-declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64 immarg)
-
-define <4 x i32> @freeze_lshr_extract_concat_high_demanded(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-LABEL: freeze_lshr_extract_concat_high_demanded:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0
-; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
- %poisonable = add nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
- %wide = shufflevector <4 x i32> %poisonable, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- %shifted = lshr <8 x i32> %wide, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
- %fr = freeze <8 x i32> %shifted
- %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
- ret <4 x i32> %ext
-}
diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll
deleted file mode 100644
index 21241af18a3c9..0000000000000
--- a/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll
+++ /dev/null
@@ -1,84 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s
-
-declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64 immarg)
-
-define i32 @freeze_select_scalar_demanded(i1 %c, <2 x i32> %a, <2 x i32> %b, <2 x i32> %d) {
-; CHECK-LABEL: freeze_select_scalar_demanded:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: jne .LBB0_1
-; CHECK-NEXT: # %bb.2:
-; CHECK-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; CHECK-NEXT: movd %xmm0, %eax
-; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB0_1:
-; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [2147483647,2147483647,u,u]
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT: movd %xmm0, %eax
-; CHECK-NEXT: retq
- %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
- %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
- %lhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %rhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %sel = select i1 %c, <4 x i32> %lhs, <4 x i32> %rhs
- %fr = freeze <4 x i32> %sel
- %ext = extractelement <4 x i32> %fr, i64 0
- ret i32 %ext
-}
-
-define <2 x i32> @freeze_vselect_high_demanded(<4 x i32> %csrc, <2 x i32> %a, <2 x i32> %b, <2 x i32> %e, <2 x i32> %d) {
-; CHECK-LABEL: freeze_vselect_high_demanded:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movdqa {{.*#+}} xmm5 = [2147483647,2147483647,2147483647,2147483647]
-; CHECK-NEXT: paddd %xmm0, %xmm5
-; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm0[2,3]
-; CHECK-NEXT: pxor %xmm0, %xmm0
-; CHECK-NEXT: pcmpgtd %xmm0, %xmm5
-; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [2147483647,2147483647,u,u]
-; CHECK-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
-; CHECK-NEXT: pand %xmm5, %xmm2
-; CHECK-NEXT: pandn %xmm4, %xmm5
-; CHECK-NEXT: por %xmm2, %xmm5
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm5[2,3,2,3]
-; CHECK-NEXT: retq
- %poisonable.c.val = add nsw <4 x i32> %csrc, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
- %poisonable.c = icmp sgt <4 x i32> %poisonable.c.val, zeroinitializer
- %safe.c = icmp sgt <4 x i32> %csrc, zeroinitializer
- %cond = shufflevector <4 x i1> %poisonable.c, <4 x i1> %safe.c, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
- %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
- %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
- %lhs = shufflevector <2 x i32> %poisonable.b, <2 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %rhs = shufflevector <2 x i32> %poisonable.d, <2 x i32> %e, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %sel = select <4 x i1> %cond, <4 x i32> %lhs, <4 x i32> %rhs
- %fr = freeze <4 x i32> %sel
- %ext = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %fr, i64 2)
- ret <2 x i32> %ext
-}
-
-define i32 @freeze_vselect_demanded(<4 x i32> %csrc, <2 x i32> %a, <2 x i32> %b, <2 x i32> %e, <2 x i32> %d) {
-; CHECK-LABEL: freeze_vselect_demanded:
-; CHECK: # %bb.0:
-; CHECK-NEXT: pxor %xmm2, %xmm2
-; CHECK-NEXT: pcmpgtd %xmm2, %xmm0
-; CHECK-NEXT: pand %xmm0, %xmm1
-; CHECK-NEXT: pandn %xmm3, %xmm0
-; CHECK-NEXT: por %xmm1, %xmm0
-; CHECK-NEXT: movd %xmm0, %eax
-; CHECK-NEXT: retq
- %safe.c = icmp sgt <4 x i32> %csrc, zeroinitializer
- %poisonable.c.val = add nsw <4 x i32> %csrc, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
- %poisonable.c = icmp sgt <4 x i32> %poisonable.c.val, zeroinitializer
- %cond = shufflevector <4 x i1> %safe.c, <4 x i1> %poisonable.c, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
- %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
- %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
- %lhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %rhs = shufflevector <2 x i32> %e, <2 x i32> %poisonable.d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %sel = select <4 x i1> %cond, <4 x i32> %lhs, <4 x i32> %rhs
- %fr = freeze <4 x i32> %sel
- %ext = extractelement <4 x i32> %fr, i64 0
- ret i32 %ext
-}
diff --git a/llvm/test/CodeGen/X86/dagcombine-insert-concat.ll b/llvm/test/CodeGen/X86/dagcombine-insert-concat.ll
deleted file mode 100644
index a143b85ec74d6..0000000000000
--- a/llvm/test/CodeGen/X86/dagcombine-insert-concat.ll
+++ /dev/null
@@ -1,38 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512bw < %s | FileCheck %s
-
-declare <32 x i16> @llvm.vector.insert.v32i16.v4i16(<32 x i16>, <4 x i16>, i64 immarg)
-
-define <32 x i16> @insert_concat_select(i1 %cond, <16 x i16> %a, <16 x i16> %b, <4 x i16> %sub, <32 x i16> %alt) {
-; CHECK-LABEL: insert_concat_select:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: je .LBB0_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm3
-; CHECK-NEXT: vmovd %xmm2, %eax
-; CHECK-NEXT: movl $65536, %ecx # imm = 0x10000
-; CHECK-NEXT: kmovd %ecx, %k1
-; CHECK-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
-; CHECK-NEXT: vpextrw $1, %xmm2, %eax
-; CHECK-NEXT: movl $131072, %ecx # imm = 0x20000
-; CHECK-NEXT: kmovd %ecx, %k1
-; CHECK-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
-; CHECK-NEXT: vpextrw $2, %xmm2, %eax
-; CHECK-NEXT: movl $262144, %ecx # imm = 0x40000
-; CHECK-NEXT: kmovd %ecx, %k1
-; CHECK-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
-; CHECK-NEXT: vpextrw $3, %xmm2, %eax
-; CHECK-NEXT: movl $524288, %ecx # imm = 0x80000
-; CHECK-NEXT: kmovd %ecx, %k1
-; CHECK-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
-; CHECK-NEXT: .LBB0_2: # %entry
-; CHECK-NEXT: vmovdqa64 %zmm3, %zmm0
-; CHECK-NEXT: retq
-entry:
- %wide = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- %ins = call <32 x i16> @llvm.vector.insert.v32i16.v4i16(<32 x i16> %wide, <4 x i16> %sub, i64 16)
- %sel = select i1 %cond, <32 x i16> %ins, <32 x i16> %alt
- ret <32 x i16> %sel
-}
diff --git a/llvm/test/CodeGen/X86/freeze-vector.ll b/llvm/test/CodeGen/X86/freeze-vector.ll
index b24ca513ebb54..76295cc6c737c 100644
--- a/llvm/test/CodeGen/X86/freeze-vector.ll
+++ b/llvm/test/CodeGen/X86/freeze-vector.ll
@@ -165,6 +165,72 @@ define void @freeze_bitcast_to_wider_elt_escape(ptr %origin, ptr %escape, ptr %d
ret void
}
+define <4 x i32> @freeze_extract_bitcast_high_demanded(<2 x i64> %a, <2 x i64> %b) {
+; X86-LABEL: freeze_extract_bitcast_high_demanded:
+; X86: # %bb.0:
+; X86-NEXT: vpsrld $1, %xmm1, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_extract_bitcast_high_demanded:
+; X64: # %bb.0:
+; X64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; X64-NEXT: vpsrld $1, %ymm0, %ymm0
+; X64-NEXT: vextracti128 $1, %ymm0, %xmm0
+; X64-NEXT: vzeroupper
+; X64-NEXT: retq
+ %poisonable = add nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807>
+ %wide = shufflevector <2 x i64> %poisonable, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %bc = bitcast <4 x i64> %wide to <8 x i32>
+ %shifted = lshr <8 x i32> %bc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %fr = freeze <8 x i32> %shifted
+ %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
+ ret <4 x i32> %ext
+}
+
+define <2 x i64> @freeze_extract_bitcast_low_width_high_demanded(<4 x i32> %a, <4 x i32> %b) {
+; X86-LABEL: freeze_extract_bitcast_low_width_high_demanded:
+; X86: # %bb.0:
+; X86-NEXT: vpsrlq $1, %xmm1, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_extract_bitcast_low_width_high_demanded:
+; X64: # %bb.0:
+; X64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; X64-NEXT: vpsrlq $1, %ymm0, %ymm0
+; X64-NEXT: vextracti128 $1, %ymm0, %xmm0
+; X64-NEXT: vzeroupper
+; X64-NEXT: retq
+ %poisonable = add nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %wide = shufflevector <4 x i32> %poisonable, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %bc = bitcast <8 x i32> %wide to <4 x i64>
+ %shifted = lshr <4 x i64> %bc, <i64 1, i64 1, i64 1, i64 1>
+ %fr = freeze <4 x i64> %shifted
+ %ext = call <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64> %fr, i64 2)
+ ret <2 x i64> %ext
+}
+
+define <4 x i32> @freeze_extract_bitcast_equal_width_high_demanded(<4 x float> %a, <4 x float> %b) {
+; X86-LABEL: freeze_extract_bitcast_equal_width_high_demanded:
+; X86: # %bb.0:
+; X86-NEXT: vpsrld $1, %xmm1, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_extract_bitcast_equal_width_high_demanded:
+; X64: # %bb.0:
+; X64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; X64-NEXT: vpsrld $1, %ymm0, %ymm0
+; X64-NEXT: vextracti128 $1, %ymm0, %xmm0
+; X64-NEXT: vzeroupper
+; X64-NEXT: retq
+ %poisonable = fadd nnan <4 x float> %a, zeroinitializer
+ %wide = shufflevector <4 x float> %poisonable, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %bc = bitcast <8 x float> %wide to <8 x i32>
+ %shifted = lshr <8 x i32> %bc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %fr = freeze <8 x i32> %shifted
+ %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
+ ret <4 x i32> %ext
+}
+
define void @freeze_extractelement(ptr %origin0, ptr %origin1, ptr %dst) nounwind {
; X86-LABEL: freeze_extractelement:
; X86: # %bb.0:
@@ -699,3 +765,167 @@ define void @freeze_buildvector_not_simple_type(ptr %dst) nounwind {
store <5 x i8> %i0, ptr %dst
ret void
}
+
+define <4 x i32> @freeze_lshr_extract_concat_high_demanded(<4 x i32> %a, <4 x i32> %b) {
+; X86-LABEL: freeze_lshr_extract_concat_high_demanded:
+; X86: # %bb.0:
+; X86-NEXT: vpsrld $1, %xmm1, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_lshr_extract_concat_high_demanded:
+; X64: # %bb.0:
+; X64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; X64-NEXT: vpsrld $1, %ymm0, %ymm0
+; X64-NEXT: vextracti128 $1, %ymm0, %xmm0
+; X64-NEXT: vzeroupper
+; X64-NEXT: retq
+ %poisonable = add nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %wide = shufflevector <4 x i32> %poisonable, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %shifted = lshr <8 x i32> %wide, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %fr = freeze <8 x i32> %shifted
+ %ext = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %fr, i64 4)
+ ret <4 x i32> %ext
+}
+
+define i32 @freeze_select_scalar_demanded(i1 %c, <2 x i32> %a, <2 x i32> %b, <2 x i32> %d) {
+; X86-LABEL: freeze_select_scalar_demanded:
+; X86: # %bb.0:
+; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
+; X86-NEXT: jne .LBB27_1
+; X86-NEXT: # %bb.2:
+; X86-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm1
+; X86-NEXT: jmp .LBB27_3
+; X86-NEXT: .LBB27_1:
+; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # [2147483647,2147483647,u,u]
+; X86-NEXT: .LBB27_3:
+; X86-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X86-NEXT: vmovd %xmm0, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_select_scalar_demanded:
+; X64: # %bb.0:
+; X64-NEXT: testb $1, %dil
+; X64-NEXT: jne .LBB27_1
+; X64-NEXT: # %bb.2:
+; X64-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
+; X64-NEXT: vpsubd %xmm1, %xmm2, %xmm1
+; X64-NEXT: jmp .LBB27_3
+; X64-NEXT: .LBB27_1:
+; X64-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
+; X64-NEXT: vpaddd %xmm2, %xmm1, %xmm1
+; X64-NEXT: .LBB27_3:
+; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-NEXT: vmovd %xmm0, %eax
+; X64-NEXT: retq
+ %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
+ %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
+ %lhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %rhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %sel = select i1 %c, <4 x i32> %lhs, <4 x i32> %rhs
+ %fr = freeze <4 x i32> %sel
+ %ext = extractelement <4 x i32> %fr, i64 0
+ ret i32 %ext
+}
+
+define <2 x i32> @freeze_vselect_high_demanded(<4 x i32> %csrc, <2 x i32> %a, <2 x i32> %b, <2 x i32> %e, <2 x i32> %d) {
+; X86-LABEL: freeze_vselect_high_demanded:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %ebp, -8
+; X86-NEXT: movl %esp, %ebp
+; X86-NEXT: .cfi_def_cfa_register %ebp
+; X86-NEXT: andl $-16, %esp
+; X86-NEXT: subl $16, %esp
+; X86-NEXT: vmovdqa 24(%ebp), %xmm3
+; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm4 # [2147483647,2147483647,2147483647,2147483647]
+; X86-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm4[0,1,2,3],xmm0[4,5,6,7]
+; X86-NEXT: vpcmpgtd %xmm5, %xmm0, %xmm0
+; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2 # [2147483647,2147483647,u,u]
+; X86-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
+; X86-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; X86-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],mem[0]
+; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; X86-NEXT: movl %ebp, %esp
+; X86-NEXT: popl %ebp
+; X86-NEXT: .cfi_def_cfa %esp, 4
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_vselect_high_demanded:
+; X64: # %bb.0:
+; X64-NEXT: vpbroadcastd {{.*#+}} xmm5 = [2147483647,2147483647,2147483647,2147483647]
+; X64-NEXT: vpaddd %xmm5, %xmm0, %xmm6
+; X64-NEXT: vpxor %xmm7, %xmm7, %xmm7
+; X64-NEXT: vpblendd {{.*#+}} xmm0 = xmm6[0,1],xmm0[2,3]
+; X64-NEXT: vpcmpgtd %xmm7, %xmm0, %xmm0
+; X64-NEXT: vpaddd %xmm5, %xmm2, %xmm2
+; X64-NEXT: vpbroadcastd {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
+; X64-NEXT: vpsubd %xmm5, %xmm4, %xmm4
+; X64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; X64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm4[0],xmm3[0]
+; X64-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; X64-NEXT: retq
+ %poisonable.c.val = add nsw <4 x i32> %csrc, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %poisonable.c = icmp sgt <4 x i32> %poisonable.c.val, zeroinitializer
+ %safe.c = icmp sgt <4 x i32> %csrc, zeroinitializer
+ %cond = shufflevector <4 x i1> %poisonable.c, <4 x i1> %safe.c, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
+ %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
+ %lhs = shufflevector <2 x i32> %poisonable.b, <2 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %rhs = shufflevector <2 x i32> %poisonable.d, <2 x i32> %e, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %sel = select <4 x i1> %cond, <4 x i32> %lhs, <4 x i32> %rhs
+ %fr = freeze <4 x i32> %sel
+ %ext = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %fr, i64 2)
+ ret <2 x i32> %ext
+}
+
+define i32 @freeze_vselect_demanded(<4 x i32> %csrc, <2 x i32> %a, <2 x i32> %b, <2 x i32> %e, <2 x i32> %d) {
+; X86-LABEL: freeze_vselect_demanded:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %ebp, -8
+; X86-NEXT: movl %esp, %ebp
+; X86-NEXT: .cfi_def_cfa_register %ebp
+; X86-NEXT: andl $-16, %esp
+; X86-NEXT: subl $16, %esp
+; X86-NEXT: vmovdqa 8(%ebp), %xmm3
+; X86-NEXT: vmovdqa 24(%ebp), %xmm4
+; X86-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm6 # [2147483647,2147483647,2147483647,2147483647]
+; X86-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
+; X86-NEXT: vpcmpgtd %xmm5, %xmm0, %xmm0
+; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2 # [2147483647,2147483647,u,u]
+; X86-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4, %xmm4
+; X86-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
+; X86-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm3, %xmm0
+; X86-NEXT: vmovd %xmm0, %eax
+; X86-NEXT: movl %ebp, %esp
+; X86-NEXT: popl %ebp
+; X86-NEXT: .cfi_def_cfa %esp, 4
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_vselect_demanded:
+; X64: # %bb.0:
+; X64-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; X64-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm0
+; X64-NEXT: vblendvps %xmm0, %xmm1, %xmm3, %xmm0
+; X64-NEXT: vmovd %xmm0, %eax
+; X64-NEXT: retq
+ %safe.c = icmp sgt <4 x i32> %csrc, zeroinitializer
+ %poisonable.c.val = add nsw <4 x i32> %csrc, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+ %poisonable.c = icmp sgt <4 x i32> %poisonable.c.val, zeroinitializer
+ %cond = shufflevector <4 x i1> %safe.c, <4 x i1> %poisonable.c, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+ %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
+ %poisonable.d = sub nsw <2 x i32> %d, <i32 -2147483648, i32 -2147483648>
+ %lhs = shufflevector <2 x i32> %a, <2 x i32> %poisonable.b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %rhs = shufflevector <2 x i32> %e, <2 x i32> %poisonable.d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %sel = select <4 x i1> %cond, <4 x i32> %lhs, <4 x i32> %rhs
+ %fr = freeze <4 x i32> %sel
+ %ext = extractelement <4 x i32> %fr, i64 0
+ ret i32 %ext
+}
diff --git a/llvm/test/CodeGen/X86/madd.ll b/llvm/test/CodeGen/X86/madd.ll
index fd67fdcbabadf..afa2ca55a644c 100644
--- a/llvm/test/CodeGen/X86/madd.ll
+++ b/llvm/test/CodeGen/X86/madd.ll
@@ -3143,3 +3143,67 @@ afterloop:
%sum = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %.lcssa)
ret i32 %sum
}
+
+define <16 x i32> @extract_concat_pmaddwd(<32 x i16> %a, <32 x i16> %b) {
+; CHECK-LABEL: extract_concat_pmaddwd:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm4
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm5
+; CHECK-NEXT: vpmaddwd %xmm4, %xmm5, %xmm4
+; CHECK-NEXT: vpmaddwd %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; CHECK-NEXT: vextractf128 $1, %ymm3, %xmm2
+; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm4
+; CHECK-NEXT: vpmaddwd %xmm2, %xmm4, %xmm2
+; CHECK-NEXT: vpmaddwd %xmm3, %xmm1, %xmm1
+; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; CHECK-NEXT: retq
+; SSE2-LABEL: extract_concat_pmaddwd:
+; SSE2: # %bb.0:
+; SSE2-NEXT: pmaddwd %xmm4, %xmm0
+; SSE2-NEXT: pmaddwd %xmm5, %xmm1
+; SSE2-NEXT: pmaddwd %xmm6, %xmm2
+; SSE2-NEXT: pmaddwd %xmm7, %xmm3
+; SSE2-NEXT: retq
+;
+; AVX1-LABEL: extract_concat_pmaddwd:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
+; AVX1-NEXT: vpmaddwd %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpmaddwd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
+; AVX1-NEXT: vpmaddwd %xmm2, %xmm4, %xmm2
+; AVX1-NEXT: vpmaddwd %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: extract_concat_pmaddwd:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpmaddwd %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpmaddwd %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: extract_concat_pmaddwd:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2
+; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT: vpmaddwd %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX512F-NEXT: retq
+;
+; AVX512BW-LABEL: extract_concat_pmaddwd:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vpmaddwd %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: retq
+ %a.ext = sext <32 x i16> %a to <32 x i32>
+ %b.ext = sext <32 x i16> %b to <32 x i32>
+ %m = mul nsw <32 x i32> %a.ext, %b.ext
+ %odd = shufflevector <32 x i32> %m, <32 x i32> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+ %even = shufflevector <32 x i32> %m, <32 x i32> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+ %ret = add <16 x i32> %odd, %even
+ ret <16 x i32> %ret
+}
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
index d33507e1a5bb9..cc84738ed3915 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
@@ -303,3 +303,76 @@ exit:
declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
+
+
+define <32 x i16> @insert_concat_select(i1 %cond, <16 x i16> %a, <16 x i16> %b, <4 x i16> %sub, <32 x i16> %alt) {
+; X86-LABEL: insert_concat_select:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %ebp, -8
+; X86-NEXT: movl %esp, %ebp
+; X86-NEXT: .cfi_def_cfa_register %ebp
+; X86-NEXT: andl $-64, %esp
+; X86-NEXT: subl $64, %esp
+; X86-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; X86-NEXT: testb $1, 8(%ebp)
+; X86-NEXT: jne .LBB16_1
+; X86-NEXT: # %bb.2:
+; X86-NEXT: vmovdqa64 72(%ebp), %zmm0
+; X86-NEXT: jmp .LBB16_3
+; X86-NEXT: .LBB16_1:
+; X86-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; X86-NEXT: vmovd %xmm2, %eax
+; X86-NEXT: movl $65536, %ecx # imm = 0x10000
+; X86-NEXT: kmovd %ecx, %k1
+; X86-NEXT: vpbroadcastw %eax, %zmm0 {%k1}
+; X86-NEXT: vpextrw $1, %xmm2, %eax
+; X86-NEXT: movl $131072, %ecx # imm = 0x20000
+; X86-NEXT: kmovd %ecx, %k1
+; X86-NEXT: vpbroadcastw %eax, %zmm0 {%k1}
+; X86-NEXT: vpextrw $2, %xmm2, %eax
+; X86-NEXT: movl $262144, %ecx # imm = 0x40000
+; X86-NEXT: kmovd %ecx, %k1
+; X86-NEXT: vpbroadcastw %eax, %zmm0 {%k1}
+; X86-NEXT: vpextrw $3, %xmm2, %eax
+; X86-NEXT: movl $524288, %ecx # imm = 0x80000
+; X86-NEXT: kmovd %ecx, %k1
+; X86-NEXT: vpbroadcastw %eax, %zmm0 {%k1}
+; X86-NEXT: .LBB16_3:
+; X86-NEXT: movl %ebp, %esp
+; X86-NEXT: popl %ebp
+; X86-NEXT: .cfi_def_cfa %esp, 4
+; X86-NEXT: retl
+;
+; X64-LABEL: insert_concat_select:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; X64-NEXT: testb $1, %dil
+; X64-NEXT: je .LBB16_2
+; X64-NEXT: # %bb.1:
+; X64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm3
+; X64-NEXT: vmovd %xmm2, %eax
+; X64-NEXT: movl $65536, %ecx # imm = 0x10000
+; X64-NEXT: kmovd %ecx, %k1
+; X64-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
+; X64-NEXT: vpextrw $1, %xmm2, %eax
+; X64-NEXT: movl $131072, %ecx # imm = 0x20000
+; X64-NEXT: kmovd %ecx, %k1
+; X64-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
+; X64-NEXT: vpextrw $2, %xmm2, %eax
+; X64-NEXT: movl $262144, %ecx # imm = 0x40000
+; X64-NEXT: kmovd %ecx, %k1
+; X64-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
+; X64-NEXT: vpextrw $3, %xmm2, %eax
+; X64-NEXT: movl $524288, %ecx # imm = 0x80000
+; X64-NEXT: kmovd %ecx, %k1
+; X64-NEXT: vpbroadcastw %eax, %zmm3 {%k1}
+; X64-NEXT: .LBB16_2:
+; X64-NEXT: vmovdqa64 %zmm3, %zmm0
+; X64-NEXT: retq
+ %wide = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ %ins = call <32 x i16> @llvm.vector.insert.v32i16.v4i16(<32 x i16> %wide, <4 x i16> %sub, i64 16)
+ %sel = select i1 %cond, <32 x i16> %ins, <32 x i16> %alt
+ ret <32 x i16> %sel
+}
>From a8afdd43413b26be376e4636c872f7ac67c9732d Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Wed, 3 Jun 2026 22:10:45 +0000
Subject: [PATCH 3/3] File rename per review
---
.../{dagcombine-freeze-undef-demanded-elts.ll => freeze-fp.ll} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename llvm/test/CodeGen/X86/{dagcombine-freeze-undef-demanded-elts.ll => freeze-fp.ll} (100%)
diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-undef-demanded-elts.ll b/llvm/test/CodeGen/X86/freeze-fp.ll
similarity index 100%
rename from llvm/test/CodeGen/X86/dagcombine-freeze-undef-demanded-elts.ll
rename to llvm/test/CodeGen/X86/freeze-fp.ll
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