[llvm] [NFC][AMDGPU] Introduce SIInstrFlags predicates for TSFlag access (PR #201512)
Valery Pykhtin via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 3 22:58:09 PDT 2026
https://github.com/vpykhtin created https://github.com/llvm/llvm-project/pull/201512
https://github.com/llvm/llvm-project/pull/201411 was too large, so this is the first part from it.
Add inline predicate templates to SIDefines.h for each TSFlag bit (isSALU, isVOP3, isFLAT, isMaybeAtomic, hasFPClamp, ...) plus compound predicates (isAtomic, isSegmentSpecificFLAT, isImage, isVMEM). A getTSFlags() shim dispatches over MCInstrDesc; SIInstrInfo.h adds a MachineInstr overload in namespace llvm, found via ADL when predicates are instantiated with MachineInstr.
Route all SIInstrInfo.h thin wrapper bodies through the new predicates instead of reading TSFlags bits directly. SIInstrInfo class methods could be replaced by direct SIInstrFlags predicate calls at their call sites, but that is outside the scope of this series.
>From a58137163d9e1a8cb243f16b95668d2a8f53e775 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at amd.com>
Date: Thu, 4 Jun 2026 05:41:42 +0000
Subject: [PATCH] [NFC][AMDGPU] Introduce SIInstrFlags predicates for TSFlag
access
First commit in a series that eliminates raw TSFlag accesses from the
AMDGPU backend.
Add inline predicate templates to SIDefines.h for each TSFlag bit (isSALU,
isVOP3, isFLAT, isMaybeAtomic, hasFPClamp, ...) plus compound predicates
(isAtomic, isSegmentSpecificFLAT, isImage, isVMEM). A getTSFlags() shim
dispatches over MCInstrDesc; SIInstrInfo.h adds a MachineInstr overload in
namespace llvm, found via ADL when predicates are instantiated with
MachineInstr.
Route all SIInstrInfo.h thin wrapper bodies through the new predicates
instead of reading TSFlags bits directly. SIInstrInfo class methods could
be replaced by direct SIInstrFlags predicate calls at their call sites, but
that is outside the scope of this series.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
llvm/lib/Target/AMDGPU/SIDefines.h | 204 +++++++++++++++++++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 261 ++++++++++++-------------
3 files changed, 326 insertions(+), 143 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 09740d531e456..552fbcde1532d 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -182,6 +182,210 @@ enum : uint64_t {
IsSWMMAC = UINT64_C(1) << 63,
};
+// Inline predicates for TSFlags — the single place where raw TSFlags bit
+// tests are written. All callers (SIInstrInfo methods, MC-level code) go
+// through these functions to make bit layout changes easier.
+//
+// getTSFlags extracts the TSFlags value from different argument types.
+// SIInstrInfo.h adds a MachineInstr overload in namespace llvm (found via ADL
+// when predicates are instantiated with MachineInstr). Later commits in this
+// series add (MCInstrInfo, unsigned Opcode) and (MCInstrInfo, MCInst) overloads
+// so that MC-layer callers can write e.g. isFLAT(MII, Inst) without extracting
+// a descriptor first.
+
+inline uint64_t getTSFlags(const MCInstrDesc &Desc) { return Desc.TSFlags; }
+
+template <typename... T> inline bool isSALU(const T &...O) {
+ return getTSFlags(O...) & SALU;
+}
+template <typename... T> inline bool isVALU(const T &...O) {
+ return getTSFlags(O...) & VALU;
+}
+template <typename... T> inline bool isSOP1(const T &...O) {
+ return getTSFlags(O...) & SOP1;
+}
+template <typename... T> inline bool isSOP2(const T &...O) {
+ return getTSFlags(O...) & SOP2;
+}
+template <typename... T> inline bool isSOPC(const T &...O) {
+ return getTSFlags(O...) & SOPC;
+}
+template <typename... T> inline bool isSOPK(const T &...O) {
+ return getTSFlags(O...) & SOPK;
+}
+template <typename... T> inline bool isSOPP(const T &...O) {
+ return getTSFlags(O...) & SOPP;
+}
+template <typename... T> inline bool isVOP1(const T &...O) {
+ return getTSFlags(O...) & VOP1;
+}
+template <typename... T> inline bool isVOP2(const T &...O) {
+ return getTSFlags(O...) & VOP2;
+}
+template <typename... T> inline bool isVOPC(const T &...O) {
+ return getTSFlags(O...) & VOPC;
+}
+template <typename... T> inline bool isVOP3(const T &...O) {
+ return getTSFlags(O...) & VOP3;
+}
+template <typename... T> inline bool isVOP3P(const T &...O) {
+ return getTSFlags(O...) & VOP3P;
+}
+template <typename... T> inline bool isVINTRP(const T &...O) {
+ return getTSFlags(O...) & VINTRP;
+}
+template <typename... T> inline bool isSDWA(const T &...O) {
+ return getTSFlags(O...) & SDWA;
+}
+template <typename... T> inline bool isDPP(const T &...O) {
+ return getTSFlags(O...) & DPP;
+}
+template <typename... T> inline bool isTRANS(const T &...O) {
+ return getTSFlags(O...) & TRANS;
+}
+template <typename... T> inline bool isMUBUF(const T &...O) {
+ return getTSFlags(O...) & MUBUF;
+}
+template <typename... T> inline bool isMTBUF(const T &...O) {
+ return getTSFlags(O...) & MTBUF;
+}
+template <typename... T> inline bool isSMRD(const T &...O) {
+ return getTSFlags(O...) & SMRD;
+}
+template <typename... T> inline bool isMIMG(const T &...O) {
+ return getTSFlags(O...) & MIMG;
+}
+template <typename... T> inline bool isVIMAGE(const T &...O) {
+ return getTSFlags(O...) & VIMAGE;
+}
+template <typename... T> inline bool isVSAMPLE(const T &...O) {
+ return getTSFlags(O...) & VSAMPLE;
+}
+template <typename... T> inline bool isEXP(const T &...O) {
+ return getTSFlags(O...) & EXP;
+}
+template <typename... T> inline bool isFLAT(const T &...O) {
+ return getTSFlags(O...) & FLAT;
+}
+template <typename... T> inline bool isDS(const T &...O) {
+ return getTSFlags(O...) & DS;
+}
+template <typename... T> inline bool isSpill(const T &...O) {
+ return getTSFlags(O...) & Spill;
+}
+template <typename... T> inline bool isLDSDIR(const T &...O) {
+ return getTSFlags(O...) & LDSDIR;
+}
+template <typename... T> inline bool isVINTERP(const T &...O) {
+ return getTSFlags(O...) & VINTERP;
+}
+template <typename... T> inline bool isWQM(const T &...O) {
+ return getTSFlags(O...) & WQM;
+}
+template <typename... T> inline bool isDisableWQM(const T &...O) {
+ return getTSFlags(O...) & DisableWQM;
+}
+template <typename... T> inline bool isGather4(const T &...O) {
+ return getTSFlags(O...) & Gather4;
+}
+template <typename... T> inline bool usesTENSOR_CNT(const T &...O) {
+ return getTSFlags(O...) & TENSOR_CNT;
+}
+template <typename... T> inline bool isScalarStore(const T &...O) {
+ return getTSFlags(O...) & SCALAR_STORE;
+}
+template <typename... T> inline bool isFixedSize(const T &...O) {
+ return getTSFlags(O...) & FIXED_SIZE;
+}
+template <typename... T> inline bool usesASYNC_CNT(const T &...O) {
+ return getTSFlags(O...) & ASYNC_CNT;
+}
+template <typename... T> inline bool hasVOP3OpSel(const T &...O) {
+ return getTSFlags(O...) & VOP3_OPSEL;
+}
+template <typename... T> inline bool isMaybeAtomic(const T &...O) {
+ return getTSFlags(O...) & maybeAtomic;
+}
+template <typename... T> inline bool hasFPClamp(const T &...O) {
+ return getTSFlags(O...) & FPClamp;
+}
+template <typename... T> inline bool hasIntClamp(const T &...O) {
+ return getTSFlags(O...) & IntClamp;
+}
+template <typename... T> inline bool hasClampLo(const T &...O) {
+ return getTSFlags(O...) & ClampLo;
+}
+template <typename... T> inline bool hasClampHi(const T &...O) {
+ return getTSFlags(O...) & ClampHi;
+}
+template <typename... T> inline bool isPacked(const T &...O) {
+ return getTSFlags(O...) & IsPacked;
+}
+template <typename... T> inline bool isD16Buf(const T &...O) {
+ return getTSFlags(O...) & D16Buf;
+}
+template <typename... T> inline bool isFlatGlobal(const T &...O) {
+ return getTSFlags(O...) & FlatGlobal;
+}
+template <typename... T> inline bool usesFPDPRounding(const T &...O) {
+ return getTSFlags(O...) & FPDPRounding;
+}
+template <typename... T> inline bool isFPAtomic(const T &...O) {
+ return getTSFlags(O...) & FPAtomic;
+}
+template <typename... T> inline bool isMAI(const T &...O) {
+ return getTSFlags(O...) & IsMAI;
+}
+template <typename... T> inline bool isDOT(const T &...O) {
+ return getTSFlags(O...) & IsDOT;
+}
+template <typename... T> inline bool isFlatScratch(const T &...O) {
+ return getTSFlags(O...) & FlatScratch;
+}
+template <typename... T> inline bool isAtomicNoRet(const T &...O) {
+ return getTSFlags(O...) & IsAtomicNoRet;
+}
+template <typename... T> inline bool isAtomicRet(const T &...O) {
+ return getTSFlags(O...) & IsAtomicRet;
+}
+template <typename... T> inline bool isWMMA(const T &...O) {
+ return getTSFlags(O...) & IsWMMA;
+}
+template <typename... T> inline bool isTiedSourceNotRead(const T &...O) {
+ return getTSFlags(O...) & TiedSourceNotRead;
+}
+template <typename... T> inline bool isNeverUniform(const T &...O) {
+ return getTSFlags(O...) & IsNeverUniform;
+}
+template <typename... T> inline bool isGWS(const T &...O) {
+ return getTSFlags(O...) & GWS;
+}
+template <typename... T> inline bool isSWMMAC(const T &...O) {
+ return getTSFlags(O...) & IsSWMMAC;
+}
+template <typename... T> inline bool usesVM_CNT(const T &...O) {
+ return getTSFlags(O...) & VM_CNT;
+}
+template <typename... T> inline bool usesLGKM_CNT(const T &...O) {
+ return getTSFlags(O...) & LGKM_CNT;
+}
+
+// Compound predicates.
+template <typename... T> inline bool isAtomic(const T &...O) {
+ return isAtomicNoRet(O...) || isAtomicRet(O...);
+}
+template <typename... T> inline bool isSegmentSpecificFLAT(const T &...O) {
+ return isFlatGlobal(O...) || isFlatScratch(O...);
+}
+// Any image-family instruction: pre-gfx11 MIMG, gfx11+ VIMAGE or VSAMPLE.
+template <typename... T> inline bool isImage(const T &...O) {
+ return isMIMG(O...) || isVIMAGE(O...) || isVSAMPLE(O...);
+}
+// Vector memory: buffer + image + flat.
+template <typename... T> inline bool isVMEM(const T &...O) {
+ return isMUBUF(O...) || isMTBUF(O...) || isImage(O...) || isFLAT(O...);
+}
+
// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
// The result is true if any of these tests are true.
enum ClassFlags : unsigned {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index a544f1380e53d..0f9e1b10fcd17 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -10574,10 +10574,10 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
// Adjust the encoding family to GFX80 for D16 buffer instructions when the
// subtarget has UnpackedD16VMem feature.
// TODO: remove this when we discard GFX80 encoding.
- if (ST.hasUnpackedD16VMem() && (get(Opcode).TSFlags & SIInstrFlags::D16Buf))
+ if (ST.hasUnpackedD16VMem() && SIInstrFlags::isD16Buf(get(Opcode)))
Gen = SIEncodingFamily::GFX80;
- if (get(Opcode).TSFlags & SIInstrFlags::SDWA) {
+ if (SIInstrFlags::isSDWA(get(Opcode))) {
switch (ST.getGeneration()) {
default:
Gen = SIEncodingFamily::SDWA;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 20ab23df208f8..1e5d8383fa023 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -98,6 +98,12 @@ struct SIInstrWorklist {
SetVector<MachineInstr *> DeferredList;
};
+// In namespace llvm so ADL finds it when SIInstrFlags predicates are
+// instantiated with MachineInstr (MachineInstr is in namespace llvm).
+inline uint64_t getTSFlags(const MachineInstr &MI) {
+ return MI.getDesc().TSFlags;
+}
+
class SIInstrInfo final : public AMDGPUGenInstrInfo {
struct ThreeAddressUpdates;
@@ -484,107 +490,106 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
const MachineFunction &MF) const override;
static bool isSALU(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SALU;
+ return SIInstrFlags::isSALU(MI);
}
bool isSALU(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SALU;
+ return SIInstrFlags::isSALU(get(Opcode));
}
static bool isVALU(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VALU;
+ return SIInstrFlags::isVALU(MI);
}
bool isVALU(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VALU;
+ return SIInstrFlags::isVALU(get(Opcode));
}
static bool isImage(const MachineInstr &MI) {
- return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
+ return SIInstrFlags::isImage(MI);
}
bool isImage(uint32_t Opcode) const {
- return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
+ return SIInstrFlags::isImage(get(Opcode));
}
static bool isVMEM(const MachineInstr &MI) {
- return isMUBUF(MI) || isMTBUF(MI) || isImage(MI) || isFLAT(MI);
+ return SIInstrFlags::isVMEM(MI);
}
bool isVMEM(uint32_t Opcode) const {
- return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode) ||
- isFLAT(Opcode);
+ return SIInstrFlags::isVMEM(get(Opcode));
}
/// True if MI implicitly drains XCNT.
static bool isXcntDrain(const MachineInstr &MI);
static bool isSOP1(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
+ return SIInstrFlags::isSOP1(MI);
}
bool isSOP1(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SOP1;
+ return SIInstrFlags::isSOP1(get(Opcode));
}
static bool isSOP2(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
+ return SIInstrFlags::isSOP2(MI);
}
bool isSOP2(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SOP2;
+ return SIInstrFlags::isSOP2(get(Opcode));
}
static bool isSOPC(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
+ return SIInstrFlags::isSOPC(MI);
}
bool isSOPC(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SOPC;
+ return SIInstrFlags::isSOPC(get(Opcode));
}
static bool isSOPK(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
+ return SIInstrFlags::isSOPK(MI);
}
bool isSOPK(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SOPK;
+ return SIInstrFlags::isSOPK(get(Opcode));
}
static bool isSOPP(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
+ return SIInstrFlags::isSOPP(MI);
}
bool isSOPP(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SOPP;
+ return SIInstrFlags::isSOPP(get(Opcode));
}
static bool isPacked(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
+ return SIInstrFlags::isPacked(MI);
}
bool isPacked(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
+ return SIInstrFlags::isPacked(get(Opcode));
}
static bool isVOP1(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
+ return SIInstrFlags::isVOP1(MI);
}
bool isVOP1(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VOP1;
+ return SIInstrFlags::isVOP1(get(Opcode));
}
static bool isVOP2(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
+ return SIInstrFlags::isVOP2(MI);
}
bool isVOP2(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VOP2;
+ return SIInstrFlags::isVOP2(get(Opcode));
}
static bool isVOP3(const MCInstrDesc &Desc) {
- return Desc.TSFlags & SIInstrFlags::VOP3;
+ return SIInstrFlags::isVOP3(Desc);
}
static bool isVOP3(const MachineInstr &MI) { return isVOP3(MI.getDesc()); }
@@ -592,35 +597,35 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool isVOP3(uint32_t Opcode) const { return isVOP3(get(Opcode)); }
static bool isSDWA(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
+ return SIInstrFlags::isSDWA(MI);
}
bool isSDWA(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SDWA;
+ return SIInstrFlags::isSDWA(get(Opcode));
}
static bool isVOPC(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
+ return SIInstrFlags::isVOPC(MI);
}
bool isVOPC(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VOPC;
+ return SIInstrFlags::isVOPC(get(Opcode));
}
static bool isMUBUF(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
+ return SIInstrFlags::isMUBUF(MI);
}
bool isMUBUF(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
+ return SIInstrFlags::isMUBUF(get(Opcode));
}
static bool isMTBUF(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
+ return SIInstrFlags::isMTBUF(MI);
}
bool isMTBUF(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
+ return SIInstrFlags::isMTBUF(get(Opcode));
}
static bool isBUF(const MachineInstr &MI) {
@@ -628,110 +633,100 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
static bool isSMRD(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
+ return SIInstrFlags::isSMRD(MI);
}
bool isSMRD(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SMRD;
+ return SIInstrFlags::isSMRD(get(Opcode));
}
bool isBufferSMRD(const MachineInstr &MI) const;
- static bool isDS(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::DS;
- }
+ static bool isDS(const MachineInstr &MI) { return SIInstrFlags::isDS(MI); }
- bool isDS(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::DS;
- }
+ bool isDS(uint32_t Opcode) const { return SIInstrFlags::isDS(get(Opcode)); }
static bool isLDSDMA(const MachineInstr &MI) {
return (isVALU(MI) && (isMUBUF(MI) || isFLAT(MI))) ||
- (MI.getDesc().TSFlags & SIInstrFlags::TENSOR_CNT);
+ (SIInstrFlags::usesTENSOR_CNT(MI));
}
bool isLDSDMA(uint32_t Opcode) {
return (isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode))) ||
- (get(Opcode).TSFlags & SIInstrFlags::TENSOR_CNT);
+ (SIInstrFlags::usesTENSOR_CNT(get(Opcode)));
}
- static bool isGWS(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::GWS;
- }
+ static bool isGWS(const MachineInstr &MI) { return SIInstrFlags::isGWS(MI); }
- bool isGWS(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::GWS;
- }
+ bool isGWS(uint32_t Opcode) const { return SIInstrFlags::isGWS(get(Opcode)); }
bool isAlwaysGDS(uint32_t Opcode) const;
static bool isMIMG(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
+ return SIInstrFlags::isMIMG(MI);
}
bool isMIMG(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::MIMG;
+ return SIInstrFlags::isMIMG(get(Opcode));
}
static bool isVIMAGE(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
+ return SIInstrFlags::isVIMAGE(MI);
}
bool isVIMAGE(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
+ return SIInstrFlags::isVIMAGE(get(Opcode));
}
static bool isVSAMPLE(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
+ return SIInstrFlags::isVSAMPLE(MI);
}
bool isVSAMPLE(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
+ return SIInstrFlags::isVSAMPLE(get(Opcode));
}
static bool isGather4(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
+ return SIInstrFlags::isGather4(MI);
}
bool isGather4(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::Gather4;
+ return SIInstrFlags::isGather4(get(Opcode));
}
static bool isFLAT(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
+ return SIInstrFlags::isFLAT(MI);
}
// Is a FLAT encoded instruction which accesses a specific segment,
// i.e. global_* or scratch_*.
static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
- auto Flags = MI.getDesc().TSFlags;
- return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
+ return SIInstrFlags::isSegmentSpecificFLAT(MI);
}
bool isSegmentSpecificFLAT(uint32_t Opcode) const {
- auto Flags = get(Opcode).TSFlags;
- return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
+ return SIInstrFlags::isSegmentSpecificFLAT(get(Opcode));
}
static bool isFLATGlobal(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
+ return SIInstrFlags::isFlatGlobal(MI);
}
bool isFLATGlobal(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
+ return SIInstrFlags::isFlatGlobal(get(Opcode));
}
static bool isFLATScratch(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
+ return SIInstrFlags::isFlatScratch(MI);
}
bool isFLATScratch(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
+ return SIInstrFlags::isFlatScratch(get(Opcode));
}
// Any FLAT encoded instruction, including global_* and scratch_*.
bool isFLAT(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::FLAT;
+ return SIInstrFlags::isFLAT(get(Opcode));
}
/// \returns true for SCRATCH_ instructions, or FLAT/BUF instructions unless
@@ -807,9 +802,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
}
- static bool isEXP(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::EXP;
- }
+ static bool isEXP(const MachineInstr &MI) { return SIInstrFlags::isEXP(MI); }
static bool isDualSourceBlendEXP(const MachineInstr &MI) {
if (!isEXP(MI))
@@ -819,34 +812,30 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND1;
}
- bool isEXP(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::EXP;
- }
+ bool isEXP(uint32_t Opcode) const { return SIInstrFlags::isEXP(get(Opcode)); }
static bool isAtomicNoRet(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
+ return SIInstrFlags::isAtomicNoRet(MI);
}
bool isAtomicNoRet(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
+ return SIInstrFlags::isAtomicNoRet(get(Opcode));
}
static bool isAtomicRet(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
+ return SIInstrFlags::isAtomicRet(MI);
}
bool isAtomicRet(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
+ return SIInstrFlags::isAtomicRet(get(Opcode));
}
static bool isAtomic(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
- SIInstrFlags::IsAtomicNoRet);
+ return SIInstrFlags::isAtomic(MI);
}
bool isAtomic(uint32_t Opcode) const {
- return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
- SIInstrFlags::IsAtomicNoRet);
+ return SIInstrFlags::isAtomic(get(Opcode));
}
static bool mayWriteLDSThroughDMA(const MachineInstr &MI) {
@@ -869,20 +858,16 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
!MI.getOperand(1).isUndef();
}
- static bool isWQM(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::WQM;
- }
+ static bool isWQM(const MachineInstr &MI) { return SIInstrFlags::isWQM(MI); }
- bool isWQM(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::WQM;
- }
+ bool isWQM(uint32_t Opcode) const { return SIInstrFlags::isWQM(get(Opcode)); }
static bool isDisableWQM(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
+ return SIInstrFlags::isDisableWQM(MI);
}
bool isDisableWQM(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
+ return SIInstrFlags::isDisableWQM(get(Opcode));
}
// SI_SPILL_S32_TO_VGPR and SI_RESTORE_S32_FROM_VGPR form a special case of
@@ -915,11 +900,11 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
bool isSpill(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::Spill;
+ return SIInstrFlags::isSpill(get(Opcode));
}
static bool isSpill(const MCInstrDesc &Desc) {
- return Desc.TSFlags & SIInstrFlags::Spill;
+ return SIInstrFlags::isSpill(Desc);
}
static bool isSpill(const MachineInstr &MI) { return isSpill(MI.getDesc()); }
@@ -936,28 +921,24 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
Opcode == AMDGPU::SI_CS_CHAIN_TC_W64;
}
- static bool isDPP(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::DPP;
- }
+ static bool isDPP(const MachineInstr &MI) { return SIInstrFlags::isDPP(MI); }
- bool isDPP(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::DPP;
- }
+ bool isDPP(uint32_t Opcode) const { return SIInstrFlags::isDPP(get(Opcode)); }
static bool isTRANS(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
+ return SIInstrFlags::isTRANS(MI);
}
bool isTRANS(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::TRANS;
+ return SIInstrFlags::isTRANS(get(Opcode));
}
static bool isVOP3P(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
+ return SIInstrFlags::isVOP3P(MI);
}
bool isVOP3P(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
+ return SIInstrFlags::isVOP3P(get(Opcode));
}
bool isVOP3PMix(const MachineInstr &MI) const {
@@ -979,15 +960,15 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
static bool isVINTRP(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
+ return SIInstrFlags::isVINTRP(MI);
}
bool isVINTRP(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
+ return SIInstrFlags::isVINTRP(get(Opcode));
}
static bool isMAI(const MCInstrDesc &Desc) {
- return Desc.TSFlags & SIInstrFlags::IsMAI;
+ return SIInstrFlags::isMAI(Desc);
}
static bool isMAI(const MachineInstr &MI) { return isMAI(MI.getDesc()); }
@@ -1004,16 +985,14 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
Opcode != AMDGPU::V_ACCVGPR_READ_B32_e64;
}
- static bool isDOT(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
- }
+ static bool isDOT(const MachineInstr &MI) { return SIInstrFlags::isDOT(MI); }
static bool isWMMA(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
+ return SIInstrFlags::isWMMA(MI);
}
bool isWMMA(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
+ return SIInstrFlags::isWMMA(get(Opcode));
}
static bool isMFMAorWMMA(const MachineInstr &MI) {
@@ -1025,16 +1004,14 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
static bool isSWMMAC(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
+ return SIInstrFlags::isSWMMAC(MI);
}
bool isSWMMAC(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC;
+ return SIInstrFlags::isSWMMAC(get(Opcode));
}
- bool isDOT(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
- }
+ bool isDOT(uint32_t Opcode) const { return SIInstrFlags::isDOT(get(Opcode)); }
bool isXDLWMMA(const MachineInstr &MI) const;
@@ -1043,39 +1020,39 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isDGEMM(unsigned Opcode) { return AMDGPU::getMAIIsDGEMM(Opcode); }
static bool isLDSDIR(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
+ return SIInstrFlags::isLDSDIR(MI);
}
bool isLDSDIR(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
+ return SIInstrFlags::isLDSDIR(get(Opcode));
}
static bool isVINTERP(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
+ return SIInstrFlags::isVINTERP(MI);
}
bool isVINTERP(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
+ return SIInstrFlags::isVINTERP(get(Opcode));
}
static bool isScalarUnit(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
+ return SIInstrFlags::isSALU(MI) || SIInstrFlags::isSMRD(MI);
}
static bool usesVM_CNT(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
+ return SIInstrFlags::usesVM_CNT(MI);
}
static bool usesLGKM_CNT(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
+ return SIInstrFlags::usesLGKM_CNT(MI);
}
static bool usesASYNC_CNT(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::ASYNC_CNT;
+ return SIInstrFlags::usesASYNC_CNT(MI);
}
bool usesASYNC_CNT(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::ASYNC_CNT;
+ return SIInstrFlags::usesASYNC_CNT(get(Opcode));
}
// Most sopk treat the immediate as a signed 16-bit, however some
@@ -1091,57 +1068,59 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// \returns true if this is an s_store_dword* instruction. This is more
/// specific than isSMEM && mayStore.
static bool isScalarStore(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
+ return SIInstrFlags::isScalarStore(MI);
}
bool isScalarStore(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
+ return SIInstrFlags::isScalarStore(get(Opcode));
}
static bool isFixedSize(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
+ return SIInstrFlags::isFixedSize(MI);
}
bool isFixedSize(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
+ return SIInstrFlags::isFixedSize(get(Opcode));
}
static bool hasFPClamp(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
+ return SIInstrFlags::hasFPClamp(MI);
}
bool hasFPClamp(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
+ return SIInstrFlags::hasFPClamp(get(Opcode));
}
static bool hasIntClamp(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
+ return SIInstrFlags::hasIntClamp(MI);
}
static bool hasSameClamp(const MachineInstr &A, const MachineInstr &B) {
- const uint64_t Mask = SIInstrFlags::FPClamp | SIInstrFlags::IntClamp |
- SIInstrFlags::ClampLo | SIInstrFlags::ClampHi;
- return (A.getDesc().TSFlags & Mask) == (B.getDesc().TSFlags & Mask);
+ const MCInstrDesc &DA = A.getDesc(), &DB = B.getDesc();
+ return SIInstrFlags::hasFPClamp(DA) == SIInstrFlags::hasFPClamp(DB) &&
+ SIInstrFlags::hasIntClamp(DA) == SIInstrFlags::hasIntClamp(DB) &&
+ SIInstrFlags::hasClampLo(DA) == SIInstrFlags::hasClampLo(DB) &&
+ SIInstrFlags::hasClampHi(DA) == SIInstrFlags::hasClampHi(DB);
}
static bool usesFPDPRounding(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
+ return SIInstrFlags::usesFPDPRounding(MI);
}
bool usesFPDPRounding(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
+ return SIInstrFlags::usesFPDPRounding(get(Opcode));
}
static bool isFPAtomic(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
+ return SIInstrFlags::isFPAtomic(MI);
}
bool isFPAtomic(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
+ return SIInstrFlags::isFPAtomic(get(Opcode));
}
static bool isNeverUniform(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::IsNeverUniform;
+ return SIInstrFlags::isNeverUniform(MI);
}
// Check to see if opcode is for a barrier start. Pre gfx12 this is just the
@@ -1178,11 +1157,11 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
static bool doesNotReadTiedSource(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
+ return SIInstrFlags::isTiedSourceNotRead(MI);
}
bool doesNotReadTiedSource(uint32_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
+ return SIInstrFlags::isTiedSourceNotRead(get(Opcode));
}
bool isIGLP(unsigned Opcode) const {
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