[llvm] [LoongArch][NFC] Add horizontal widening add/sub tests (PR #201487)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 3 18:14:03 PDT 2026
https://github.com/heiher created https://github.com/llvm/llvm-project/pull/201487
None
>From a18d5492b28109b7938e17115bc27060ee9f7d8d Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Wed, 3 Jun 2026 15:12:43 +0800
Subject: [PATCH] [LoongArch][NFC] Add horizontal widening add/sub tests
---
llvm/test/CodeGen/LoongArch/lasx/vhaddw.ll | 359 +++++++++++++++++++++
llvm/test/CodeGen/LoongArch/lasx/vhsubw.ll | 359 +++++++++++++++++++++
llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll | 144 +++++++++
llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll | 144 +++++++++
4 files changed, 1006 insertions(+)
create mode 100644 llvm/test/CodeGen/LoongArch/lasx/vhaddw.ll
create mode 100644 llvm/test/CodeGen/LoongArch/lasx/vhsubw.ll
create mode 100644 llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll
create mode 100644 llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vhaddw.ll b/llvm/test/CodeGen/LoongArch/lasx/vhaddw.ll
new file mode 100644
index 0000000000000..1e2b681bd9917
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/vhaddw.ll
@@ -0,0 +1,359 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define <16 x i16> @xvhaddw_h_b(<32 x i8> %a, <32 x i8> %b) nounwind {
+; CHECK-LABEL: xvhaddw_h_b:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 7
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 9
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 10
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 11
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 12
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 13
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 15
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 8
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 10
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 12
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 14
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 7
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 9
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 10
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 11
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 8
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 12
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 10
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 13
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 12
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 14
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 15
+; CHECK-NEXT: vext2xv.h.b $xr1, $xr2
+; CHECK-NEXT: vext2xv.h.b $xr0, $xr0
+; CHECK-NEXT: xvadd.h $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <32 x i8> %a, <32 x i8> poison,
+ <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15,
+ i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+
+ %1 = shufflevector <32 x i8> %b, <32 x i8> poison,
+ <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14,
+ i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+
+ %2 = sext <16 x i8> %0 to <16 x i16>
+ %3 = sext <16 x i8> %1 to <16 x i16>
+
+ %4 = add <16 x i16> %2, %3
+ ret <16 x i16> %4
+}
+
+define <8 x i32> @xvhaddw_w_h(<16 x i16> %a, <16 x i16> %b) nounwind {
+; CHECK-LABEL: xvhaddw_w_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 3
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 7
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 3
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 14
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 4
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 5
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 6
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
+; CHECK-NEXT: vext2xv.w.h $xr1, $xr2
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: xvadd.w $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <16 x i16> %a, <16 x i16> poison,
+ <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+
+ %1 = shufflevector <16 x i16> %b, <16 x i16> poison,
+ <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+
+ %2 = sext <8 x i16> %0 to <8 x i32>
+ %3 = sext <8 x i16> %1 to <8 x i32>
+
+ %4 = add <8 x i32> %2, %3
+ ret <8 x i32> %4
+}
+
+define <4 x i64> @xvhaddw_d_w(<8 x i32> %a, <8 x i32> %b) nounwind {
+; CHECK-LABEL: xvhaddw_d_w:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 1
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 5
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 7
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 2
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 4
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 6
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; CHECK-NEXT: vext2xv.d.w $xr1, $xr2
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %1 = shufflevector <8 x i32> %b, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+
+ %2 = sext <4 x i32> %0 to <4 x i64>
+ %3 = sext <4 x i32> %1 to <4 x i64>
+
+ %4 = add <4 x i64> %2, %3
+ ret <4 x i64> %4
+}
+
+define <16 x i16> @xvhaddw_hu_bu(<32 x i8> %a, <32 x i8> %b) nounwind {
+; CHECK-LABEL: xvhaddw_hu_bu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 7
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 9
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 10
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 11
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 12
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 13
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 15
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 8
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 10
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 12
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 14
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 7
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 9
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 10
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 11
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 8
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 12
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 10
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 13
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 12
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 14
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 15
+; CHECK-NEXT: vext2xv.hu.bu $xr1, $xr2
+; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr0
+; CHECK-NEXT: xvadd.h $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <32 x i8> %a, <32 x i8> poison,
+ <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15,
+ i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+
+ %1 = shufflevector <32 x i8> %b, <32 x i8> poison,
+ <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14,
+ i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+
+ %2 = zext <16 x i8> %0 to <16 x i16>
+ %3 = zext <16 x i8> %1 to <16 x i16>
+
+ %4 = add <16 x i16> %2, %3
+ ret <16 x i16> %4
+}
+
+define <8 x i32> @xvhaddw_wu_hu(<16 x i16> %a, <16 x i16> %b) nounwind {
+; CHECK-LABEL: xvhaddw_wu_hu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 3
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 7
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 3
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 14
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 4
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 5
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 6
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
+; CHECK-NEXT: vext2xv.wu.hu $xr1, $xr2
+; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0
+; CHECK-NEXT: xvadd.w $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <16 x i16> %a, <16 x i16> poison,
+ <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+
+ %1 = shufflevector <16 x i16> %b, <16 x i16> poison,
+ <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+
+ %2 = zext <8 x i16> %0 to <8 x i32>
+ %3 = zext <8 x i16> %1 to <8 x i32>
+
+ %4 = add <8 x i32> %2, %3
+ ret <8 x i32> %4
+}
+
+define <4 x i64> @xvhaddw_du_wu(<8 x i32> %a, <8 x i32> %b) nounwind {
+; CHECK-LABEL: xvhaddw_du_wu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 1
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 5
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 7
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 2
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 4
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 6
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; CHECK-NEXT: vext2xv.du.wu $xr1, $xr2
+; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
+; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %1 = shufflevector <8 x i32> %b, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+
+ %2 = zext <4 x i32> %0 to <4 x i64>
+ %3 = zext <4 x i32> %1 to <4 x i64>
+
+ %4 = add <4 x i64> %2, %3
+ ret <4 x i64> %4
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vhsubw.ll b/llvm/test/CodeGen/LoongArch/lasx/vhsubw.ll
new file mode 100644
index 0000000000000..2664c51c13837
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/vhsubw.ll
@@ -0,0 +1,359 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define <16 x i16> @xvhsubw_h_b(<32 x i8> %a, <32 x i8> %b) nounwind {
+; CHECK-LABEL: xvhsubw_h_b:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 7
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 9
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 10
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 11
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 12
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 13
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 15
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 8
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 10
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 12
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 14
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 7
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 9
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 10
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 11
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 8
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 12
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 10
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 13
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 12
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 14
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 15
+; CHECK-NEXT: vext2xv.h.b $xr1, $xr2
+; CHECK-NEXT: vext2xv.h.b $xr0, $xr0
+; CHECK-NEXT: xvsub.h $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <32 x i8> %a, <32 x i8> poison,
+ <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15,
+ i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+
+ %1 = shufflevector <32 x i8> %b, <32 x i8> poison,
+ <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14,
+ i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+
+ %2 = sext <16 x i8> %0 to <16 x i16>
+ %3 = sext <16 x i8> %1 to <16 x i16>
+
+ %4 = sub <16 x i16> %2, %3
+ ret <16 x i16> %4
+}
+
+define <8 x i32> @xvhsubw_w_h(<16 x i16> %a, <16 x i16> %b) nounwind {
+; CHECK-LABEL: xvhsubw_w_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 3
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 7
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 3
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 14
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 4
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 5
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 6
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
+; CHECK-NEXT: vext2xv.w.h $xr1, $xr2
+; CHECK-NEXT: vext2xv.w.h $xr0, $xr0
+; CHECK-NEXT: xvsub.w $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <16 x i16> %a, <16 x i16> poison,
+ <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+
+ %1 = shufflevector <16 x i16> %b, <16 x i16> poison,
+ <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+
+ %2 = sext <8 x i16> %0 to <8 x i32>
+ %3 = sext <8 x i16> %1 to <8 x i32>
+
+ %4 = sub <8 x i32> %2, %3
+ ret <8 x i32> %4
+}
+
+define <4 x i64> @xvhsubw_d_w(<8 x i32> %a, <8 x i32> %b) nounwind {
+; CHECK-LABEL: xvhsubw_d_w:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 1
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 5
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 7
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 2
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 4
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 6
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; CHECK-NEXT: vext2xv.d.w $xr1, $xr2
+; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
+; CHECK-NEXT: xvsub.d $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %1 = shufflevector <8 x i32> %b, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+
+ %2 = sext <4 x i32> %0 to <4 x i64>
+ %3 = sext <4 x i32> %1 to <4 x i64>
+
+ %4 = sub <4 x i64> %2, %3
+ ret <4 x i64> %4
+}
+
+define <16 x i16> @xvhsubw_hu_bu(<32 x i8> %a, <32 x i8> %b) nounwind {
+; CHECK-LABEL: xvhsubw_hu_bu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 7
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 9
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 10
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 11
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 12
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 13
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.b $vr2, $a0, 15
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 8
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 10
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 12
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 14
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 7
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 9
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 10
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 11
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 8
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 12
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 10
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 13
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 12
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 14
+; CHECK-NEXT: vpickve2gr.b $a0, $vr1, 14
+; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 15
+; CHECK-NEXT: vext2xv.hu.bu $xr1, $xr2
+; CHECK-NEXT: vext2xv.hu.bu $xr0, $xr0
+; CHECK-NEXT: xvsub.h $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <32 x i8> %a, <32 x i8> poison,
+ <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15,
+ i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+
+ %1 = shufflevector <32 x i8> %b, <32 x i8> poison,
+ <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14,
+ i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+
+ %2 = zext <16 x i8> %0 to <16 x i16>
+ %3 = zext <16 x i8> %1 to <16 x i16>
+
+ %4 = sub <16 x i16> %2, %3
+ ret <16 x i16> %4
+}
+
+define <8 x i32> @xvhsubw_wu_hu(<16 x i16> %a, <16 x i16> %b) nounwind {
+; CHECK-LABEL: xvhsubw_wu_hu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 3
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 7
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 3
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 14
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 4
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 5
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 6
+; CHECK-NEXT: vpickve2gr.h $a0, $vr1, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
+; CHECK-NEXT: vext2xv.wu.hu $xr1, $xr2
+; CHECK-NEXT: vext2xv.wu.hu $xr0, $xr0
+; CHECK-NEXT: xvsub.w $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <16 x i16> %a, <16 x i16> poison,
+ <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+
+ %1 = shufflevector <16 x i16> %b, <16 x i16> poison,
+ <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+
+ %2 = zext <8 x i16> %0 to <8 x i32>
+ %3 = zext <8 x i16> %1 to <8 x i32>
+
+ %4 = sub <8 x i32> %2, %3
+ ret <8 x i32> %4
+}
+
+define <4 x i64> @xvhsubw_du_wu(<8 x i32> %a, <8 x i32> %b) nounwind {
+; CHECK-LABEL: xvhsubw_du_wu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 1
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 5
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 7
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 2
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 4
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr1, 6
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; CHECK-NEXT: vext2xv.du.wu $xr1, $xr2
+; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
+; CHECK-NEXT: xvsub.d $xr0, $xr1, $xr0
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %1 = shufflevector <8 x i32> %b, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+
+ %2 = zext <4 x i32> %0 to <4 x i64>
+ %3 = zext <4 x i32> %1 to <4 x i64>
+
+ %4 = sub <4 x i64> %2, %3
+ ret <4 x i64> %4
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll b/llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll
new file mode 100644
index 0000000000000..6c313a850ad34
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll
@@ -0,0 +1,144 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <8 x i16> @vhaddw_h_b(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: vhaddw_h_b:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickod.b $vr0, $vr0, $vr0
+; CHECK-NEXT: vpickev.b $vr1, $vr1, $vr1
+; CHECK-NEXT: vslti.b $vr2, $vr0, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr2, $vr0
+; CHECK-NEXT: vslti.b $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.b $vr1, $vr2, $vr1
+; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <16 x i8> %a, <16 x i8> poison,
+ <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+
+ %1 = shufflevector <16 x i8> %b, <16 x i8> poison,
+ <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+
+ %2 = sext <8 x i8> %0 to <8 x i16>
+ %3 = sext <8 x i8> %1 to <8 x i16>
+
+ %4 = add <8 x i16> %2, %3
+ ret <8 x i16> %4
+}
+
+define <4 x i32> @vhaddw_w_h(<8 x i16> %a, <8 x i16> %b) nounwind {
+; CHECK-LABEL: vhaddw_w_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickod.h $vr0, $vr0, $vr0
+; CHECK-NEXT: vpickev.h $vr1, $vr1, $vr1
+; CHECK-NEXT: vslti.h $vr2, $vr0, 0
+; CHECK-NEXT: vilvl.h $vr0, $vr2, $vr0
+; CHECK-NEXT: vslti.h $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.h $vr1, $vr2, $vr1
+; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i16> %a, <8 x i16> poison,
+ <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+
+ %1 = shufflevector <8 x i16> %b, <8 x i16> poison,
+ <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+
+ %2 = sext <4 x i16> %0 to <4 x i32>
+ %3 = sext <4 x i16> %1 to <4 x i32>
+
+ %4 = add <4 x i32> %2, %3
+ ret <4 x i32> %4
+}
+
+define <2 x i64> @vhaddw_d_w(<4 x i32> %a, <4 x i32> %b) nounwind {
+; CHECK-LABEL: vhaddw_d_w:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vshuf4i.w $vr0, $vr0, 13
+; CHECK-NEXT: vshuf4i.w $vr1, $vr1, 8
+; CHECK-NEXT: vslti.w $vr2, $vr0, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr0
+; CHECK-NEXT: vslti.w $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.w $vr1, $vr2, $vr1
+; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
+ %1 = shufflevector <4 x i32> %b, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+
+ %2 = sext <2 x i32> %0 to <2 x i64>
+ %3 = sext <2 x i32> %1 to <2 x i64>
+
+ %4 = add <2 x i64> %2, %3
+ ret <2 x i64> %4
+}
+
+define <8 x i16> @vhaddw_hu_bu(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: vhaddw_hu_bu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT: vrepli.b $vr3, 0
+; CHECK-NEXT: vpackod.b $vr0, $vr3, $vr0
+; CHECK-NEXT: vshuf.b $vr1, $vr3, $vr1, $vr2
+; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <16 x i8> %a, <16 x i8> poison,
+ <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+
+ %1 = shufflevector <16 x i8> %b, <16 x i8> poison,
+ <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+
+ %2 = zext <8 x i8> %0 to <8 x i16>
+ %3 = zext <8 x i8> %1 to <8 x i16>
+
+ %4 = add <8 x i16> %2, %3
+ ret <8 x i16> %4
+}
+
+define <4 x i32> @vhaddw_wu_hu(<8 x i16> %a, <8 x i16> %b) nounwind {
+; CHECK-LABEL: vhaddw_wu_hu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: vrepli.b $vr3, 0
+; CHECK-NEXT: vpackod.h $vr0, $vr3, $vr0
+; CHECK-NEXT: vshuf.h $vr2, $vr3, $vr1
+; CHECK-NEXT: vadd.w $vr0, $vr0, $vr2
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i16> %a, <8 x i16> poison,
+ <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+
+ %1 = shufflevector <8 x i16> %b, <8 x i16> poison,
+ <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+
+ %2 = zext <4 x i16> %0 to <4 x i32>
+ %3 = zext <4 x i16> %1 to <4 x i32>
+
+ %4 = add <4 x i32> %2, %3
+ ret <4 x i32> %4
+}
+
+define <2 x i64> @vhaddw_du_wu(<4 x i32> %a, <4 x i32> %b) nounwind {
+; CHECK-LABEL: vhaddw_du_wu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT: vrepli.b $vr3, 0
+; CHECK-NEXT: vpackod.w $vr0, $vr3, $vr0
+; CHECK-NEXT: vshuf.w $vr2, $vr3, $vr1
+; CHECK-NEXT: vadd.d $vr0, $vr0, $vr2
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
+ %1 = shufflevector <4 x i32> %b, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+
+ %2 = zext <2 x i32> %0 to <2 x i64>
+ %3 = zext <2 x i32> %1 to <2 x i64>
+
+ %4 = add <2 x i64> %2, %3
+ ret <2 x i64> %4
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll b/llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll
new file mode 100644
index 0000000000000..5ace2a9ed48fb
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll
@@ -0,0 +1,144 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <8 x i16> @vhsubw_h_b(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: vhsubw_h_b:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickod.b $vr0, $vr0, $vr0
+; CHECK-NEXT: vpickev.b $vr1, $vr1, $vr1
+; CHECK-NEXT: vslti.b $vr2, $vr0, 0
+; CHECK-NEXT: vilvl.b $vr0, $vr2, $vr0
+; CHECK-NEXT: vslti.b $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.b $vr1, $vr2, $vr1
+; CHECK-NEXT: vsub.h $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <16 x i8> %a, <16 x i8> poison,
+ <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+
+ %1 = shufflevector <16 x i8> %b, <16 x i8> poison,
+ <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+
+ %2 = sext <8 x i8> %0 to <8 x i16>
+ %3 = sext <8 x i8> %1 to <8 x i16>
+
+ %4 = sub <8 x i16> %2, %3
+ ret <8 x i16> %4
+}
+
+define <4 x i32> @vhsubw_w_h(<8 x i16> %a, <8 x i16> %b) nounwind {
+; CHECK-LABEL: vhsubw_w_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vpickod.h $vr0, $vr0, $vr0
+; CHECK-NEXT: vpickev.h $vr1, $vr1, $vr1
+; CHECK-NEXT: vslti.h $vr2, $vr0, 0
+; CHECK-NEXT: vilvl.h $vr0, $vr2, $vr0
+; CHECK-NEXT: vslti.h $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.h $vr1, $vr2, $vr1
+; CHECK-NEXT: vsub.w $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i16> %a, <8 x i16> poison,
+ <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+
+ %1 = shufflevector <8 x i16> %b, <8 x i16> poison,
+ <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+
+ %2 = sext <4 x i16> %0 to <4 x i32>
+ %3 = sext <4 x i16> %1 to <4 x i32>
+
+ %4 = sub <4 x i32> %2, %3
+ ret <4 x i32> %4
+}
+
+define <2 x i64> @vhsubw_d_w(<4 x i32> %a, <4 x i32> %b) nounwind {
+; CHECK-LABEL: vhsubw_d_w:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vshuf4i.w $vr0, $vr0, 13
+; CHECK-NEXT: vshuf4i.w $vr1, $vr1, 8
+; CHECK-NEXT: vslti.w $vr2, $vr0, 0
+; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr0
+; CHECK-NEXT: vslti.w $vr2, $vr1, 0
+; CHECK-NEXT: vilvl.w $vr1, $vr2, $vr1
+; CHECK-NEXT: vsub.d $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
+ %1 = shufflevector <4 x i32> %b, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+
+ %2 = sext <2 x i32> %0 to <2 x i64>
+ %3 = sext <2 x i32> %1 to <2 x i64>
+
+ %4 = sub <2 x i64> %2, %3
+ ret <2 x i64> %4
+}
+
+define <8 x i16> @vhsubw_hu_bu(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: vhsubw_hu_bu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT: vrepli.b $vr3, 0
+; CHECK-NEXT: vpackod.b $vr0, $vr3, $vr0
+; CHECK-NEXT: vshuf.b $vr1, $vr3, $vr1, $vr2
+; CHECK-NEXT: vsub.h $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <16 x i8> %a, <16 x i8> poison,
+ <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+
+ %1 = shufflevector <16 x i8> %b, <16 x i8> poison,
+ <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+
+ %2 = zext <8 x i8> %0 to <8 x i16>
+ %3 = zext <8 x i8> %1 to <8 x i16>
+
+ %4 = sub <8 x i16> %2, %3
+ ret <8 x i16> %4
+}
+
+define <4 x i32> @vhsubw_wu_hu(<8 x i16> %a, <8 x i16> %b) nounwind {
+; CHECK-LABEL: vhsubw_wu_hu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: vrepli.b $vr3, 0
+; CHECK-NEXT: vpackod.h $vr0, $vr3, $vr0
+; CHECK-NEXT: vshuf.h $vr2, $vr3, $vr1
+; CHECK-NEXT: vsub.w $vr0, $vr0, $vr2
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i16> %a, <8 x i16> poison,
+ <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+
+ %1 = shufflevector <8 x i16> %b, <8 x i16> poison,
+ <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+
+ %2 = zext <4 x i16> %0 to <4 x i32>
+ %3 = zext <4 x i16> %1 to <4 x i32>
+
+ %4 = sub <4 x i32> %2, %3
+ ret <4 x i32> %4
+}
+
+define <2 x i64> @vhsubw_du_wu(<4 x i32> %a, <4 x i32> %b) nounwind {
+; CHECK-LABEL: vhsubw_du_wu:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT: vrepli.b $vr3, 0
+; CHECK-NEXT: vpackod.w $vr0, $vr3, $vr0
+; CHECK-NEXT: vshuf.w $vr2, $vr3, $vr1
+; CHECK-NEXT: vsub.d $vr0, $vr0, $vr2
+; CHECK-NEXT: ret
+entry:
+ %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
+ %1 = shufflevector <4 x i32> %b, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+
+ %2 = zext <2 x i32> %0 to <2 x i64>
+ %3 = zext <2 x i32> %1 to <2 x i64>
+
+ %4 = sub <2 x i64> %2, %3
+ ret <2 x i64> %4
+}
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