[llvm] [LFI][AArch64] Add rewrites for memory accesses (PR #195167)

[Peter Smith via llvm-commits]

================
@@ -269,3 +721,540 @@ bool AArch64MCLFIRewriter::rewriteInst(const MCInst &Inst, MCStreamer &Out,
   Guard = false;
   return true;
 }
+
+// Opcode X-macro Tables
+//
+// These macros define groups of related opcodes and are used to generate
+// multiple switch tables without repetition. Each macro takes a callback X and
+// invokes X(NAME, VALUE) for each entry.
+
+// Scalar memory ops that have ui, pre, post, roX, and roW variants.
+// PRFM is excluded because it has no pre/post forms.
+// The second column is the log2 element size (shift for scaled addressing).
+#define SCALAR_MEM_OPS(X)                                                      \
+  X(LDRBB, 0)                                                                  \
+  X(LDRB, 0)                                                                   \
+  X(LDRSBW, 0)                                                                 \
+  X(LDRSBX, 0)                                                                 \
+  X(STRBB, 0)                                                                  \
+  X(STRB, 0)                                                                   \
+  X(LDRHH, 1)                                                                  \
+  X(LDRH, 1)                                                                   \
+  X(LDRSHW, 1)                                                                 \
+  X(LDRSHX, 1)                                                                 \
+  X(STRHH, 1)                                                                  \
+  X(STRH, 1)                                                                   \
+  X(LDRSW, 2)                                                                  \
+  X(LDRS, 2)                                                                   \
+  X(LDRW, 2)                                                                   \
+  X(STRS, 2)                                                                   \
+  X(STRW, 2)                                                                   \
+  X(LDRD, 3)                                                                   \
+  X(LDRX, 3)                                                                   \
+  X(STRD, 3)                                                                   \
+  X(STRX, 3)                                                                   \
+  X(LDRQ, 4)                                                                   \
+  X(STRQ, 4)
----------------
smithp35 wrote:

I've had a chance to look through Nick's proposed TableGen alternatives.

I agree with Nick that https://github.com/lfi-project/llvm-project/pull/6 is the better of the two alternatives. I don't think the additional changes in AArch64InstrFormats.td are significantly more complex than https://github.com/lfi-project/llvm-project/pull/5

I found it difficult to compare 3 implementations across the size of the diffs. I think it would likely be simpler for a non LFI expert to have a [NFC] refactoring and put that to a wider audience to see if there are any objections. The feeling I get is that an overall simpler more robust solution is preferred to keeping LFI isolated.

One small comment on the TableGen, there were some classes with parameters that didn't look like they were used. There could be some inheritance that I'm missing though.
```
class LFILoadStoreRO<bits<2> sz, bit V> : LFIInstruction
  let LFIInst = !cast<Instruction>(NAME);
  let IsLFIMem = 1;
  let BaseIdx = 1;
  let OffsetIdx = 2;
  let HasOffset = 1;
}
```



https://github.com/llvm/llvm-project/pull/195167