[llvm] [AArch64][llvm] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[Jonathan Thackray via llvm-commits]

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@@ -1429,6 +1425,16 @@ class ZPRVectorListMul<int ElementWidth, int NumRegs, string RegClassSuffix = ""
                                  # "AArch64::ZPR" # RegClassSuffix # "RegClassID" # ">";
 }
 
+class ZPRVectorList_3b<int ElementWidth, int NumRegs>
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jthackray wrote:

Thanks, good idea. Fixed.

https://github.com/llvm/llvm-project/pull/200751