[llvm] [AArch64][GlobalISel] Treat vector select as legal (PR #197111)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,73 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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arsenm wrote:

```suggestion
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
```

https://github.com/llvm/llvm-project/pull/197111