[llvm] [AArch64][GlobalISel] Treat vector select as legal (PR #197111)

[Matt Arsenault via llvm-commits]

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@@ -6260,6 +6260,24 @@ def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
 def : Pat<(AArch64bsp (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
           (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
 
+def : Pat<(v8i8 (select (v8i8 V64:$Rd), V64:$Rn, V64:$Rm)),
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arsenm wrote:

These can also trigger for SDAG, so why weren't they already here?

https://github.com/llvm/llvm-project/pull/197111