[llvm] [AMDGPU] Defer emitting AMDGPUAsmPrinter local Resource Usage comments until the end (PR #198233)
Janek van Oirschot via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 3 05:18:21 PDT 2026
https://github.com/JanekvO updated https://github.com/llvm/llvm-project/pull/198233
>From 64a045dd450c85567e9ac1d37962122b05eae630 Mon Sep 17 00:00:00 2001
From: Janek van Oirschot <janek.vanoirschot at amd.com>
Date: Mon, 11 May 2026 13:39:46 +0100
Subject: [PATCH 1/4] [AMDGPU] Defer emitting AMDGPUAsmPrinter comments until
the end
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 266 +++++----
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h | 11 +-
.../Target/AMDGPU/AMDGPUMCResourceInfo.cpp | 22 +-
llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h | 3 +
.../AMDGPU/GlobalISel/flat-scratch-init.ll | 22 +-
.../GlobalISel/llvm.amdgcn.workgroup.id.ll | 40 +-
.../AMDGPU/GlobalISel/non-entry-alloca.ll | 13 +-
llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 7 +-
.../CodeGen/AMDGPU/agpr-register-count.ll | 180 +++---
.../AMDGPU/amdgpu-no-agprs-violations.ll | 24 +-
.../amdhsa-kernarg-preload-num-sgprs.ll | 21 +-
.../amdpal-metadata-agpr-register-count.ll | 24 +-
...-amdgpu-flat-work-group-size-vgpr-limit.ll | 58 +-
.../attr-amdgpu-flat-work-group-size.ll | 37 +-
.../AMDGPU/attr-amdgpu-waves-per-eu.ll | 118 ++--
.../AMDGPU/call-graph-register-usage.ll | 125 ++--
.../callee-special-input-vgprs-packed.ll | 4 +-
.../AMDGPU/callee-special-input-vgprs.ll | 4 +-
.../AMDGPU/code-size-estimate-gfx1250.ll | 7 +-
.../test/CodeGen/AMDGPU/code-size-estimate.ll | 171 +++---
.../CodeGen/AMDGPU/code-size-estimate.mir | 22 +-
llvm/test/CodeGen/AMDGPU/default-fp-mode.ll | 91 +--
llvm/test/CodeGen/AMDGPU/empty-function.ll | 7 +-
llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll | 138 +++--
.../CodeGen/AMDGPU/function-resource-usage.ll | 248 ++++----
.../AMDGPU/gfx11-user-sgpr-init16-bug.ll | 20 +-
.../AMDGPU/greedy-liverange-priority.mir | 11 +-
llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll | 28 +-
llvm/test/CodeGen/AMDGPU/hsa-func.ll | 9 +-
.../CodeGen/AMDGPU/hsa-metadata-agpr-small.ll | 50 +-
llvm/test/CodeGen/AMDGPU/inline-asm.ll | 50 +-
.../AMDGPU/insert-subvector-unused-scratch.ll | 7 +-
.../test/CodeGen/AMDGPU/inst-prefetch-hint.ll | 12 +-
llvm/test/CodeGen/AMDGPU/ipra.ll | 26 +-
.../CodeGen/AMDGPU/kernarg-stack-alignment.ll | 16 +-
.../CodeGen/AMDGPU/large-alloca-graphics.ll | 7 +-
.../CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll | 19 +-
.../CodeGen/AMDGPU/lds-size-hsa-gfx950.ll | 7 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll | 1 +
.../AMDGPU/llvm.amdgcn.workgroup.id.ll | 39 +-
llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll | 40 +-
llvm/test/CodeGen/AMDGPU/merge-stores.ll | 13 +-
.../AMDGPU/module-lds-false-sharing.ll | 9 +-
llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll | 15 +-
llvm/test/CodeGen/AMDGPU/occupancy-levels.ll | 541 ++++++++++--------
llvm/test/CodeGen/AMDGPU/perfhint.ll | 44 +-
.../AMDGPU/promote-alloca-calling-conv.ll | 20 +-
.../promote-alloca-stored-pointer-value.ll | 1 +
.../CodeGen/AMDGPU/ps-shader-arg-count.ll | 58 +-
llvm/test/CodeGen/AMDGPU/recursion.ll | 7 +-
.../CodeGen/AMDGPU/register-count-comments.ll | 13 +-
.../CodeGen/AMDGPU/sgpr-count-graphics.ll | 13 +-
llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll | 7 +-
llvm/test/CodeGen/AMDGPU/spill-agpr.ll | 13 +-
.../test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll | 19 +-
llvm/test/CodeGen/AMDGPU/spill-vgpr.ll | 61 +-
llvm/test/CodeGen/AMDGPU/stack-realign.ll | 9 +
llvm/test/CodeGen/AMDGPU/trap.ll | 9 +-
.../CodeGen/AMDGPU/unaligned-load-store.ll | 7 +-
.../CodeGen/AMDGPU/vector-alloca-bitcast.ll | 31 +-
.../CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll | 163 +++---
.../test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll | 20 +-
.../CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir | 42 +-
63 files changed, 1836 insertions(+), 1284 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index f1c015312d9a7..830bb251411d1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -724,6 +724,9 @@ bool AMDGPUAsmPrinter::doFinalization(Module &M) {
// known.
RI.finalize(OutContext);
+ if (isVerbose())
+ emitDeferredComments();
+
// Switch section and emit all GPR maximums within the processed module.
OutStreamer->pushSection();
MCSectionELF *MaxGPRSection =
@@ -763,7 +766,7 @@ SmallString<128> AMDGPUAsmPrinter::getMCExprStr(const MCExpr *Value) {
void AMDGPUAsmPrinter::emitCommonFunctionComments(
const MCExpr *NumVGPR, const MCExpr *NumAGPR, const MCExpr *TotalNumVGPR,
const MCExpr *NumSGPR, const MCExpr *ScratchSize, uint64_t CodeSize,
- const AMDGPUMachineFunctionInfo *MFI) {
+ bool IsMemoryBound) {
OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
OutStreamer->emitRawComment(" TotalNumSgprs: " + getMCExprStr(NumSGPR),
false);
@@ -775,8 +778,139 @@ void AMDGPUAsmPrinter::emitCommonFunctionComments(
}
OutStreamer->emitRawComment(" ScratchSize: " + getMCExprStr(ScratchSize),
false);
- OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
- false);
+ OutStreamer->emitRawComment(" MemoryBound: " + Twine(IsMemoryBound), false);
+}
+
+void AMDGPUAsmPrinter::emitDeferredComments() {
+ for (const auto &Info : DeferredComments) {
+ const Function &F = *Info.F;
+ const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F);
+ MCSymbol *FnSym = TM.getSymbol(&F);
+ StringRef FuncName = FnSym->getName();
+ bool IsMemoryBound = F.getFnAttribute("amdgpu-memory-bound").getValueAsBool();
+
+ MCSectionELF *CommentSection = OutContext.getELFSection(
+ ".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
+ OutStreamer->switchSection(CommentSection);
+
+ if (!AMDGPU::isEntryFunctionCC(F.getCallingConv())) {
+ using RIK = MCResourceInfo::ResourceInfoKind;
+ OutStreamer->emitRawComment(" " + Twine(FuncName) + " Function info:",
+ false);
+
+ emitCommonFunctionComments(
+ RI.getSymbol(FuncName, RIK::RIK_NumVGPR, OutContext)
+ ->getVariableValue(),
+ STM.hasMAIInsts()
+ ? RI.getSymbol(FuncName, RIK::RIK_NumAGPR, OutContext)
+ ->getVariableValue()
+ : nullptr,
+ RI.createTotalNumVGPRs(FuncName, OutContext),
+ RI.createTotalNumSGPRs(
+ FuncName,
+ STM.getTargetID().isXnackOnOrAny(), OutContext),
+ RI.getSymbol(FuncName, RIK::RIK_PrivateSegSize, OutContext)
+ ->getVariableValue(),
+ Info.CodeSize, IsMemoryBound);
+ continue;
+ }
+
+ const SIProgramInfo &PI = Info.ProgInfo;
+ OutStreamer->emitRawComment(" " + Twine(FuncName) + " Kernel info:", false);
+ emitCommonFunctionComments(
+ PI.NumArchVGPR,
+ STM.hasMAIInsts() ? PI.NumAccVGPR : nullptr,
+ PI.NumVGPR, PI.NumSGPR, PI.ScratchSize,
+ Info.CodeSize, IsMemoryBound);
+
+ OutStreamer->emitRawComment(
+ " FloatMode: " + Twine(PI.FloatMode), false);
+ OutStreamer->emitRawComment(
+ " IeeeMode: " + Twine(PI.IEEEMode), false);
+ OutStreamer->emitRawComment(
+ " LDSByteSize: " + Twine(PI.LDSSize) +
+ " bytes/workgroup (compile time only)",
+ false);
+
+ OutStreamer->emitRawComment(
+ " SGPRBlocks: " + getMCExprStr(PI.SGPRBlocks), false);
+ OutStreamer->emitRawComment(
+ " VGPRBlocks: " + getMCExprStr(PI.VGPRBlocks), false);
+
+ OutStreamer->emitRawComment(
+ " NumSGPRsForWavesPerEU: " +
+ getMCExprStr(PI.NumSGPRsForWavesPerEU),
+ false);
+ OutStreamer->emitRawComment(
+ " NumVGPRsForWavesPerEU: " +
+ getMCExprStr(PI.NumVGPRsForWavesPerEU),
+ false);
+
+ if (STM.hasGFX90AInsts()) {
+ const MCExpr *AdjustedAccum = MCBinaryExpr::createAdd(
+ PI.AccumOffset, MCConstantExpr::create(1, OutContext), OutContext);
+ AdjustedAccum = MCBinaryExpr::createMul(
+ AdjustedAccum, MCConstantExpr::create(4, OutContext), OutContext);
+ OutStreamer->emitRawComment(
+ " AccumOffset: " + getMCExprStr(AdjustedAccum), false);
+ }
+
+ if (STM.hasGFX1250Insts())
+ OutStreamer->emitRawComment(
+ " NamedBarCnt: " + getMCExprStr(PI.NamedBarCnt), false);
+
+ OutStreamer->emitRawComment(
+ " Occupancy: " + getMCExprStr(PI.Occupancy), false);
+
+ bool NeedsWaveLimiter =
+ F.getFnAttribute("amdgpu-wave-limiter").getValueAsBool();
+ OutStreamer->emitRawComment(
+ " WaveLimiterHint : " + Twine(NeedsWaveLimiter), false);
+
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC2:SCRATCH_EN: " +
+ getMCExprStr(PI.ScratchEnable),
+ false);
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC2:USER_SGPR: " + Twine(PI.UserSGPR), false);
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
+ Twine(PI.TrapHandlerEnable),
+ false);
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC2:TGID_X_EN: " + Twine(PI.TGIdXEnable), false);
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC2:TGID_Y_EN: " + Twine(PI.TGIdYEnable), false);
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC2:TGID_Z_EN: " + Twine(PI.TGIdZEnable), false);
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " + Twine(PI.TIdIGCompCount),
+ false);
+
+ [[maybe_unused]] int64_t PGMRSrc3;
+ assert(STM.getGeneration() >= AMDGPUSubtarget::GFX10 ||
+ STM.hasGFX90AInsts() || STM.hasGFX1250Insts() ||
+ (PI.ComputePGMRSrc3->evaluateAsAbsolute(PGMRSrc3) &&
+ static_cast<uint64_t>(PGMRSrc3) == 0));
+ if (STM.hasGFX90AInsts()) {
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: " +
+ getMCExprStr(MCKernelDescriptor::bits_get(
+ PI.ComputePGMRSrc3,
+ amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
+ amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, OutContext)),
+ false);
+ OutStreamer->emitRawComment(
+ " COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: " +
+ getMCExprStr(MCKernelDescriptor::bits_get(
+ PI.ComputePGMRSrc3,
+ amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
+ amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, OutContext)),
+ false);
+ }
+ }
+
+ DeferredComments.clear();
}
const MCExpr *AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
@@ -884,7 +1018,6 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
const AMDGPUMachineFunctionInfo *MFI =
MF.getInfo<AMDGPUMachineFunctionInfo>();
- MCContext &Ctx = MF.getContext();
// The starting address of all shader programs must be 256 bytes aligned.
// Regular functions just need the basic required instruction alignment.
@@ -973,129 +1106,12 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
emitDVgprSymbol(MF);
if (isVerbose()) {
- MCSectionELF *CommentSection =
- Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
- OutStreamer->switchSection(CommentSection);
-
- if (!MFI->isEntryFunction()) {
- using RIK = MCResourceInfo::ResourceInfoKind;
- OutStreamer->emitRawComment(" Function info:", false);
+ DeferredComments.push_back(
+ {&MF.getFunction(), CurrentProgramInfo,
+ CurrentProgramInfo.getFunctionCodeSize(MF)});
- emitCommonFunctionComments(
- RI.getSymbol(CurrentFnSym->getName(), RIK::RIK_NumVGPR, OutContext)
- ->getVariableValue(),
- STM.hasMAIInsts() ? RI.getSymbol(CurrentFnSym->getName(),
- RIK::RIK_NumAGPR, OutContext)
- ->getVariableValue()
- : nullptr,
- RI.createTotalNumVGPRs(MF, Ctx),
- RI.createTotalNumSGPRs(
- MF,
- MF.getSubtarget<GCNSubtarget>().getTargetID().isXnackOnOrAny(),
- Ctx),
- RI.getSymbol(CurrentFnSym->getName(), RIK::RIK_PrivateSegSize,
- OutContext)
- ->getVariableValue(),
- CurrentProgramInfo.getFunctionCodeSize(MF), MFI);
+ if (!MFI->isEntryFunction())
return false;
- }
-
- OutStreamer->emitRawComment(" Kernel info:", false);
- emitCommonFunctionComments(
- CurrentProgramInfo.NumArchVGPR,
- STM.hasMAIInsts() ? CurrentProgramInfo.NumAccVGPR : nullptr,
- CurrentProgramInfo.NumVGPR, CurrentProgramInfo.NumSGPR,
- CurrentProgramInfo.ScratchSize,
- CurrentProgramInfo.getFunctionCodeSize(MF), MFI);
-
- OutStreamer->emitRawComment(
- " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
- OutStreamer->emitRawComment(
- " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
- OutStreamer->emitRawComment(
- " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
- " bytes/workgroup (compile time only)",
- false);
-
- OutStreamer->emitRawComment(
- " SGPRBlocks: " + getMCExprStr(CurrentProgramInfo.SGPRBlocks), false);
-
- OutStreamer->emitRawComment(
- " VGPRBlocks: " + getMCExprStr(CurrentProgramInfo.VGPRBlocks), false);
-
- OutStreamer->emitRawComment(
- " NumSGPRsForWavesPerEU: " +
- getMCExprStr(CurrentProgramInfo.NumSGPRsForWavesPerEU),
- false);
- OutStreamer->emitRawComment(
- " NumVGPRsForWavesPerEU: " +
- getMCExprStr(CurrentProgramInfo.NumVGPRsForWavesPerEU),
- false);
-
- if (STM.hasGFX90AInsts()) {
- const MCExpr *AdjustedAccum = MCBinaryExpr::createAdd(
- CurrentProgramInfo.AccumOffset, MCConstantExpr::create(1, Ctx), Ctx);
- AdjustedAccum = MCBinaryExpr::createMul(
- AdjustedAccum, MCConstantExpr::create(4, Ctx), Ctx);
- OutStreamer->emitRawComment(
- " AccumOffset: " + getMCExprStr(AdjustedAccum), false);
- }
-
- if (STM.hasGFX1250Insts())
- OutStreamer->emitRawComment(
- " NamedBarCnt: " + getMCExprStr(CurrentProgramInfo.NamedBarCnt),
- false);
-
- OutStreamer->emitRawComment(
- " Occupancy: " + getMCExprStr(CurrentProgramInfo.Occupancy), false);
-
- OutStreamer->emitRawComment(
- " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
-
- OutStreamer->emitRawComment(
- " COMPUTE_PGM_RSRC2:SCRATCH_EN: " +
- getMCExprStr(CurrentProgramInfo.ScratchEnable),
- false);
- OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
- Twine(CurrentProgramInfo.UserSGPR),
- false);
- OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
- Twine(CurrentProgramInfo.TrapHandlerEnable),
- false);
- OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
- Twine(CurrentProgramInfo.TGIdXEnable),
- false);
- OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
- Twine(CurrentProgramInfo.TGIdYEnable),
- false);
- OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
- Twine(CurrentProgramInfo.TGIdZEnable),
- false);
- OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
- Twine(CurrentProgramInfo.TIdIGCompCount),
- false);
-
- [[maybe_unused]] int64_t PGMRSrc3;
- assert(STM.getGeneration() >= AMDGPUSubtarget::GFX10 ||
- STM.hasGFX90AInsts() || STM.hasGFX1250Insts() ||
- (CurrentProgramInfo.ComputePGMRSrc3->evaluateAsAbsolute(PGMRSrc3) &&
- static_cast<uint64_t>(PGMRSrc3) == 0));
- if (STM.hasGFX90AInsts()) {
- OutStreamer->emitRawComment(
- " COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: " +
- getMCExprStr(MCKernelDescriptor::bits_get(
- CurrentProgramInfo.ComputePGMRSrc3,
- amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
- amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, Ctx)),
- false);
- OutStreamer->emitRawComment(
- " COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: " +
- getMCExprStr(MCKernelDescriptor::bits_get(
- CurrentProgramInfo.ComputePGMRSrc3,
- amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
- amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Ctx)),
- false);
- }
}
if (DumpCodeInstEmitter) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
index 9066b2d419f89..89580387f462d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
@@ -53,6 +53,13 @@ class AMDGPUAsmPrinter final : public AsmPrinter {
SIProgramInfo CurrentProgramInfo;
+ struct DeferredResourceCommentInfo {
+ const Function *F;
+ SIProgramInfo ProgInfo;
+ uint64_t CodeSize;
+ };
+ SmallVector<DeferredResourceCommentInfo, 8> DeferredComments;
+
std::unique_ptr<AMDGPU::HSAMD::MetadataStreamer> HSAMetadataStream;
MCCodeEmitter *DumpCodeInstEmitter = nullptr;
@@ -76,7 +83,7 @@ class AMDGPUAsmPrinter final : public AsmPrinter {
const MCExpr *TotalNumVGPR,
const MCExpr *NumSGPR,
const MCExpr *ScratchSize, uint64_t CodeSize,
- const AMDGPUMachineFunctionInfo *MFI);
+ bool IsMemoryBound);
void emitResourceUsageRemarks(const MachineFunction &MF,
const SIProgramInfo &CurrentProgramInfo,
bool isModuleEntryFunction, bool hasMAIInsts);
@@ -98,6 +105,8 @@ class AMDGPUAsmPrinter final : public AsmPrinter {
SmallString<128> getMCExprStr(const MCExpr *Value);
+ void emitDeferredComments();
+
/// Attempts to replace the validation that is missed in getSIProgramInfo due
/// to MCExpr being unknown. Invoked during doFinalization such that the
/// MCResourceInfo symbols are known.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
index 2d43019a8d66b..efe6b6ccc5e87 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
@@ -400,9 +400,14 @@ const MCExpr *MCResourceInfo::createTotalNumVGPRs(const MachineFunction &MF,
MCContext &Ctx) {
const TargetMachine &TM = MF.getTarget();
MCSymbol *FnSym = TM.getSymbol(&MF.getFunction());
+ return createTotalNumVGPRs(FnSym->getName(), Ctx);
+}
+
+const MCExpr *MCResourceInfo::createTotalNumVGPRs(StringRef FuncName,
+ MCContext &Ctx) {
return AMDGPUMCExpr::createTotalNumVGPR(
- getSymRefExpr(FnSym->getName(), RIK_NumAGPR, Ctx),
- getSymRefExpr(FnSym->getName(), RIK_NumVGPR, Ctx), Ctx);
+ getSymRefExpr(FuncName, RIK_NumAGPR, Ctx),
+ getSymRefExpr(FuncName, RIK_NumVGPR, Ctx), Ctx);
}
const MCExpr *MCResourceInfo::createTotalNumSGPRs(const MachineFunction &MF,
@@ -410,11 +415,16 @@ const MCExpr *MCResourceInfo::createTotalNumSGPRs(const MachineFunction &MF,
MCContext &Ctx) {
const TargetMachine &TM = MF.getTarget();
MCSymbol *FnSym = TM.getSymbol(&MF.getFunction());
+ return createTotalNumSGPRs(FnSym->getName(), hasXnack, Ctx);
+}
+
+const MCExpr *MCResourceInfo::createTotalNumSGPRs(StringRef FuncName,
+ bool hasXnack,
+ MCContext &Ctx) {
return MCBinaryExpr::createAdd(
- getSymRefExpr(FnSym->getName(), RIK_NumSGPR, Ctx),
+ getSymRefExpr(FuncName, RIK_NumSGPR, Ctx),
AMDGPUMCExpr::createExtraSGPRs(
- getSymRefExpr(FnSym->getName(), RIK_UsesVCC, Ctx),
- getSymRefExpr(FnSym->getName(), RIK_UsesFlatScratch, Ctx), hasXnack,
- Ctx),
+ getSymRefExpr(FuncName, RIK_UsesVCC, Ctx),
+ getSymRefExpr(FuncName, RIK_UsesFlatScratch, Ctx), hasXnack, Ctx),
Ctx);
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h
index 3cb063ef8e962..ac2eb2c902ea3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h
@@ -112,8 +112,11 @@ class MCResourceInfo {
MCContext &OutContext);
const MCExpr *createTotalNumVGPRs(const MachineFunction &MF, MCContext &Ctx);
+ const MCExpr *createTotalNumVGPRs(StringRef FuncName, MCContext &Ctx);
const MCExpr *createTotalNumSGPRs(const MachineFunction &MF, bool hasXnack,
MCContext &Ctx);
+ const MCExpr *createTotalNumSGPRs(StringRef FuncName, bool hasXnack,
+ MCContext &Ctx);
};
} // namespace llvm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
index e207d95287783..6e50ae0fbeb32 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
@@ -18,9 +18,6 @@ target triple = "amdgcn-amd-amdhsa"
; RW-FLAT-NOT: .amdhsa_enable_private_segment
; RO-FLAT-NOT: .amdhsa_system_sgpr_private_segment_wavefront_offset
; RO-FLAT: .amdhsa_enable_private_segment 1
-; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
-; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
define amdgpu_kernel void @stack_object_addrspacecast_in_kernel_no_calls() {
%alloca = alloca i32, addrspace(5)
%cast = addrspacecast ptr addrspace(5) %alloca to ptr
@@ -42,9 +39,6 @@ define amdgpu_kernel void @stack_object_addrspacecast_in_kernel_no_calls() {
; RO-FLAT-NOT: .amdhsa_system_sgpr_private_segment_wavefront_offset
; RO-FLAT: .amdhsa_enable_private_segment 1
; RW-FLAT: .amdhsa_reserve_flat_scratch 0
-; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
-; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 4
-; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
define amdgpu_kernel void @stack_object_in_kernel_no_calls() {
%alloca = alloca i32, addrspace(5)
store volatile i32 0, ptr addrspace(5) %alloca
@@ -62,9 +56,19 @@ define amdgpu_kernel void @stack_object_in_kernel_no_calls() {
; RO-FLAT-NOT: .amdhsa_system_sgpr_private_segment_wavefront_offset
; RO-FLAT: .amdhsa_enable_private_segment 0
; RW-FLAT: .amdhsa_reserve_flat_scratch 0
-; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
-; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 4
-; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
define amdgpu_kernel void @kernel_no_calls_no_stack() {
ret void
}
+
+; GCN: ; stack_object_addrspacecast_in_kernel_no_calls Kernel info:
+; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
+; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 6
+; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
+; GCN: ; stack_object_in_kernel_no_calls Kernel info:
+; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
+; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 4
+; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
+; GCN: ; kernel_no_calls_no_stack Kernel info:
+; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
+; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 4
+; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
index f491df8448a7a..dac3d10116b66 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
@@ -27,12 +27,6 @@ declare i32 @llvm.amdgcn.workgroup.id.z() #0
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
-; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
-; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
-; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
-; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
-; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
%id = call i32 @llvm.amdgcn.workgroup.id.x()
store i32 %id, ptr addrspace(1) %out
@@ -54,12 +48,6 @@ define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
-; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
-; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
-; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
-; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
-; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
%id = call i32 @llvm.amdgcn.workgroup.id.y()
store i32 %id, ptr addrspace(1) %out
@@ -89,12 +77,6 @@ define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
-; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
-; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
-; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
-; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
-; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
%id = call i32 @llvm.amdgcn.workgroup.id.z()
store i32 %id, ptr addrspace(1) %out
@@ -104,5 +86,27 @@ define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
+; ALL: ; test_workgroup_id_x Kernel info:
+; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
+; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
+; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
+; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
+; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
+; ALL: ; test_workgroup_id_y Kernel info:
+; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
+; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
+; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
+; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
+; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
+; ALL: ; test_workgroup_id_z Kernel info:
+; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
+; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
+; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
+; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
+; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
+
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
index 8bef60523e9a7..1359910d01da2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
@@ -77,10 +77,8 @@ bb.2:
ret void
}
; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 16
-; DEFAULTSIZE: ; ScratchSize: 16
; ASSUME1024: .amdhsa_private_segment_fixed_size 1040
-; ASSUME1024: ; ScratchSize: 1040
define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) #1 {
; GCN-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
@@ -140,10 +138,8 @@ bb.1:
}
; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 64
-; DEFAULTSIZE: ; ScratchSize: 64
; ASSUME1024: .amdhsa_private_segment_fixed_size 1088
-; ASSUME1024: ; ScratchSize: 1088
define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) #1 {
@@ -277,3 +273,12 @@ attributes #1 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; ASSUME1024: {{.*}}
; DEFAULTSIZE: {{.*}}
+
+; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4 Kernel info:
+; DEFAULTSIZE: ; ScratchSize: 16
+; ASSUME1024: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4 Kernel info:
+; ASSUME1024: ; ScratchSize: 1040
+; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64 Kernel info:
+; DEFAULTSIZE: ; ScratchSize: 64
+; ASSUME1024: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64 Kernel info:
+; ASSUME1024: ; ScratchSize: 1088
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 4652d0ae60fd0..333cd8abd66a5 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -33,7 +33,6 @@ target triple = "amdgcn-amd-amdhsa"
; At most 2 digits. Make sure src_shared_base is not counted as a high
; number SGPR.
-; HSA: NumSgprs: {{[0-9]+}}
define amdgpu_kernel void @use_group_to_flat_addrspacecast(ptr addrspace(3) %ptr) #0 {
%stof = addrspacecast ptr addrspace(3) %ptr to ptr
store volatile i32 7, ptr %stof
@@ -92,7 +91,6 @@ define void @use_group_to_flat_addrspacecast_func(ptr addrspace(3) %ptr) #0 {
; CI: .amdhsa_user_sgpr_queue_ptr 1
; GFX9: .amdhsa_user_sgpr_queue_ptr 0
-; HSA: NumSgprs: {{[0-9]+}}
define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
%stof = addrspacecast ptr addrspace(5) %ptr to ptr
store volatile i32 7, ptr %stof
@@ -1598,3 +1596,8 @@ attributes #3 = { nounwind "amdgpu-32bit-address-high-bits"="0xffff8000" }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
+
+; HSA: ; use_group_to_flat_addrspacecast Kernel info:
+; HSA: NumSgprs: {{[0-9]+}}
+; HSA: ; use_private_to_flat_addrspacecast Kernel info:
+; HSA: NumSgprs: {{[0-9]+}}
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
index dffde8d25c5f6..e364ba97ee3d7 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
@@ -5,17 +5,6 @@
; GFX908: .amdhsa_next_free_vgpr 32
; GFX90A: .amdhsa_next_free_vgpr 44
; GFX90A: .amdhsa_accum_offset 12
-; GCN: NumVgprs: 9
-; GCN: NumAgprs: 32
-; GFX908: TotalNumVgprs: 32
-; GFX90A: TotalNumVgprs: 44
-; GFX908: VGPRBlocks: 7
-; GFX90A: VGPRBlocks: 5
-; GFX908: NumVGPRsForWavesPerEU: 32
-; GFX90A: NumVGPRsForWavesPerEU: 44
-; GFX90A: AccumOffset: 12
-; GCN: Occupancy: 8
-; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2
define amdgpu_kernel void @kernel_32_agprs() #0 {
bb:
call void asm sideeffect "", "~{v8}" ()
@@ -26,15 +15,6 @@ bb:
; GCN-LABEL: {{^}}kernel_0_agprs:
; GCN: .amdhsa_next_free_vgpr 1
; GFX90A: .amdhsa_accum_offset 4
-; GCN: NumVgprs: 1
-; GCN: NumAgprs: 0
-; GCN: TotalNumVgprs: 1
-; GCN: VGPRBlocks: 0
-; GCN: NumVGPRsForWavesPerEU: 1
-; GFX90A: AccumOffset: 4
-; GFX908: Occupancy: 10
-; GFX90A: Occupancy: 8
-; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 0
define amdgpu_kernel void @kernel_0_agprs() #0 {
bb:
call void asm sideeffect "", "~{v0}" ()
@@ -45,18 +25,6 @@ bb:
; GFX908: .amdhsa_next_free_vgpr 40
; GFX90A: .amdhsa_next_free_vgpr 56
; GFX90A: .amdhsa_accum_offset 40
-; GCN: NumVgprs: 40
-; GCN: NumAgprs: 16
-; GFX908: TotalNumVgprs: 40
-; GFX90A: TotalNumVgprs: 56
-; GFX908: VGPRBlocks: 9
-; GFX90A: VGPRBlocks: 6
-; GFX908: NumVGPRsForWavesPerEU: 40
-; GFX90A: NumVGPRsForWavesPerEU: 56
-; GFX90A: AccumOffset: 40
-; GFX908: Occupancy: 6
-; GFX90A: Occupancy: 8
-; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 9
define amdgpu_kernel void @kernel_40_vgprs() #0 {
bb:
call void asm sideeffect "", "~{v39}" ()
@@ -65,10 +33,6 @@ bb:
}
; GCN-LABEL: {{^}}func_32_agprs:
-; GCN: NumVgprs: 9
-; GCN: NumAgprs: 32
-; GFX908: TotalNumVgprs: 32
-; GFX90A: TotalNumVgprs: 44
define void @func_32_agprs() #0 {
bb:
call void asm sideeffect "", "~{v8}" ()
@@ -77,10 +41,6 @@ bb:
}
; GCN-LABEL: {{^}}func_32_vgprs:
-; GCN: NumVgprs: 32
-; GCN: NumAgprs: 9
-; GFX908: TotalNumVgprs: 32
-; GFX90A: TotalNumVgprs: 41
define void @func_32_vgprs() #0 {
bb:
call void asm sideeffect "", "~{v31}" ()
@@ -89,9 +49,6 @@ bb:
}
; GCN-LABEL: {{^}}func_0_agprs:
-; GCN: NumVgprs: 1
-; GCN: NumAgprs: 0
-; GCN: TotalNumVgprs: 1
define amdgpu_kernel void @func_0_agprs() #0 {
bb:
call void asm sideeffect "", "~{v0}" ()
@@ -102,17 +59,6 @@ bb:
; GFX908: .amdhsa_next_free_vgpr 256
; GFX90A: .amdhsa_next_free_vgpr 512
; GFX90A: .amdhsa_accum_offset 256
-; GCN: NumVgprs: 256
-; GCN: NumAgprs: 256
-; GFX908: TotalNumVgprs: 256
-; GFX90A: TotalNumVgprs: 512
-; GFX908: VGPRBlocks: 63
-; GFX90A: VGPRBlocks: 63
-; GFX908: NumVGPRsForWavesPerEU: 256
-; GFX90A: NumVGPRsForWavesPerEU: 512
-; GFX90A: AccumOffset: 256
-; GCN: Occupancy: 1
-; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63
define amdgpu_kernel void @kernel_max_gprs() #0 {
bb:
call void asm sideeffect "", "~{v255}" ()
@@ -123,17 +69,6 @@ bb:
; GCN-LABEL: {{^}}kernel_call_func_32_agprs:
; GFX908: .amdhsa_next_free_vgpr 32
; GFX90A: .amdhsa_accum_offset 12
-; GCN: NumVgprs: 9
-; GCN: NumAgprs: 32
-; GFX908: TotalNumVgprs: 32
-; GFX90A: TotalNumVgprs: 44
-; GFX908: VGPRBlocks: 7
-; GFX90A: VGPRBlocks: 5
-; GFX908: NumVGPRsForWavesPerEU: 32
-; GFX90A: NumVGPRsForWavesPerEU: 44
-; GFX90A: AccumOffset: 12
-; GCN: Occupancy: 8
-; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2
define amdgpu_kernel void @kernel_call_func_32_agprs() #0 {
bb:
call void @func_32_agprs() #0
@@ -141,10 +76,6 @@ bb:
}
; GCN-LABEL: {{^}}func_call_func_32_agprs:
-; GCN: NumVgprs: 9
-; GCN: NumAgprs: 32
-; GFX908: TotalNumVgprs: 32
-; GFX90A: TotalNumVgprs: 44
define void @func_call_func_32_agprs() #0 {
bb:
call void @func_32_agprs() #0
@@ -158,22 +89,113 @@ declare void @undef_func()
; GFX90A: .amdhsa_accum_offset (((((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1)&~65536)&63)+1)*4
; GCN: .set .Lkernel_call_undef_func.num_vgpr, max(32, amdgpu.max_num_vgpr)
; GCN: .set .Lkernel_call_undef_func.num_agpr, max(0, amdgpu.max_num_agpr)
-; GCN: NumVgprs: .Lkernel_call_undef_func.num_vgpr
-; GCN: NumAgprs: .Lkernel_call_undef_func.num_agpr
-; GCN: TotalNumVgprs: totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr)
-; GFX908: VGPRBlocks: (alignto(max(max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 1), 4)/4)-1
-; GFX90A: VGPRBlocks: (alignto(max(max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 1), 8)/8)-1
-; GCN: NumVGPRsForWavesPerEU: max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0)
-; GFX90A: AccumOffset: ((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1+1)*4
-; GFX908: Occupancy: occupancy(10, 4, 256, 8, 10, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0))
-; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 8, max(.Lkernel_call_undef_func.numbered_sgpr+extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0))
-; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: (((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4)/4)-1)&~65536)&63
define amdgpu_kernel void @kernel_call_undef_func() #0 {
bb:
call void @undef_func()
ret void
}
+; GCN: ; kernel_32_agprs Kernel info:
+; GCN: NumVgprs: 9
+; GCN: NumAgprs: 32
+; GFX908: TotalNumVgprs: 32
+; GFX90A: TotalNumVgprs: 44
+; GFX908: VGPRBlocks: 7
+; GFX90A: VGPRBlocks: 5
+; GFX908: NumVGPRsForWavesPerEU: 32
+; GFX90A: NumVGPRsForWavesPerEU: 44
+; GFX90A: AccumOffset: 12
+; GCN: Occupancy: 8
+; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2
+
+; GCN: ; kernel_0_agprs Kernel info:
+; GCN: NumVgprs: 1
+; GCN: NumAgprs: 0
+; GCN: TotalNumVgprs: 1
+; GCN: VGPRBlocks: 0
+; GCN: NumVGPRsForWavesPerEU: 1
+; GFX90A: AccumOffset: 4
+; GFX908: Occupancy: 10
+; GFX90A: Occupancy: 8
+; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 0
+
+; GCN: ; kernel_40_vgprs Kernel info:
+; GCN: NumVgprs: 40
+; GCN: NumAgprs: 16
+; GFX908: TotalNumVgprs: 40
+; GFX90A: TotalNumVgprs: 56
+; GFX908: VGPRBlocks: 9
+; GFX90A: VGPRBlocks: 6
+; GFX908: NumVGPRsForWavesPerEU: 40
+; GFX90A: NumVGPRsForWavesPerEU: 56
+; GFX90A: AccumOffset: 40
+; GFX908: Occupancy: 6
+; GFX90A: Occupancy: 8
+; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 9
+
+; GCN: ; func_32_agprs Function info:
+; GCN: NumVgprs: 9
+; GCN: NumAgprs: 32
+; GFX908: TotalNumVgprs: 32
+; GFX90A: TotalNumVgprs: 44
+
+; GCN: ; func_32_vgprs Function info:
+; GCN: NumVgprs: 32
+; GCN: NumAgprs: 9
+; GFX908: TotalNumVgprs: 32
+; GFX90A: TotalNumVgprs: 41
+
+; GCN: ; func_0_agprs Kernel info:
+; GCN: NumVgprs: 1
+; GCN: NumAgprs: 0
+; GCN: TotalNumVgprs: 1
+
+; GCN: ; kernel_max_gprs Kernel info:
+; GCN: NumVgprs: 256
+; GCN: NumAgprs: 256
+; GFX908: TotalNumVgprs: 256
+; GFX90A: TotalNumVgprs: 512
+; GFX908: VGPRBlocks: 63
+; GFX90A: VGPRBlocks: 63
+; GFX908: NumVGPRsForWavesPerEU: 256
+; GFX90A: NumVGPRsForWavesPerEU: 512
+; GFX90A: AccumOffset: 256
+; GCN: Occupancy: 1
+; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63
+
+; GCN: ; kernel_call_func_32_agprs Kernel info:
+; GCN: NumVgprs: 9
+; GCN: NumAgprs: 32
+; GFX908: TotalNumVgprs: 32
+; GFX90A: TotalNumVgprs: 44
+; GFX908: VGPRBlocks: 7
+; GFX90A: VGPRBlocks: 5
+; GFX908: NumVGPRsForWavesPerEU: 32
+; GFX90A: NumVGPRsForWavesPerEU: 44
+; GFX90A: AccumOffset: 12
+; GCN: Occupancy: 8
+; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2
+
+; GCN: ; func_call_func_32_agprs Function info:
+; GCN: NumVgprs: 9
+; GCN: NumAgprs: 32
+; GFX908: TotalNumVgprs: 32
+; GFX90A: TotalNumVgprs: 44
+
+; GCN: ; kernel_call_undef_func Kernel info:
+; GCN: NumVgprs: 32
+; GCN: NumAgprs: 32
+; GFX908: TotalNumVgprs: 32
+; GFX90A: TotalNumVgprs: 64
+; GFX908: VGPRBlocks: 7
+; GFX90A: VGPRBlocks: 7
+; GFX908: NumVGPRsForWavesPerEU: 32
+; GFX90A: NumVGPRsForWavesPerEU: 64
+; GFX90A: AccumOffset: 32
+; GFX908: Occupancy: 8
+; GFX90A: Occupancy: 8
+; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 7
+
; GCN: .set amdgpu.max_num_vgpr, 32
; GCN-NEXT: .set amdgpu.max_num_agpr, 32
; GCN-NEXT: .set amdgpu.max_num_sgpr, 34
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll
index 7bf9a29e9ff44..a02f2b779c5bf 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll
@@ -12,9 +12,6 @@
; CHECK: {{^}}kernel_illegal_agpr_use_asm:
; CHECK: ; use a0
-
-; CHECK: NumVgprs: 0
-; CHECK: NumAgprs: 1
define amdgpu_kernel void @kernel_illegal_agpr_use_asm() #0 {
call void asm sideeffect "; use $0", "a"(i32 poison)
ret void
@@ -22,9 +19,6 @@ define amdgpu_kernel void @kernel_illegal_agpr_use_asm() #0 {
; CHECK: {{^}}func_illegal_agpr_use_asm:
; CHECK: ; use a0
-
-; CHECK: NumVgprs: 0
-; CHECK: NumAgprs: 1
define void @func_illegal_agpr_use_asm() #0 {
call void asm sideeffect "; use $0", "a"(i32 poison)
ret void
@@ -34,6 +28,19 @@ define void @func_illegal_agpr_use_asm() #0 {
; GFX908: v_accvgpr_write_b32
; GFX90A-NOT: v_accvgpr_write_b32
+define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32(ptr addrspace(1) %out, float %a, float %b, <32 x float> %c) #0 {
+ %result = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %a, float %b, <32 x float> %c, i32 0, i32 0, i32 0)
+ store <32 x float> %result, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: ; kernel_illegal_agpr_use_asm Kernel info:
+; CHECK: NumVgprs: 0
+; CHECK: NumAgprs: 1
+; CHECK: ; func_illegal_agpr_use_asm Function info:
+; CHECK: NumVgprs: 0
+; CHECK: NumAgprs: 1
+; CHECK: ; kernel_calls_mfma.f32.32x32x1f32 Kernel info:
; GFX908: NumVgprs: 5
; GFX908: NumAgprs: 32
; GFX90A: NumVgprs: 35
@@ -41,10 +48,5 @@ define void @func_illegal_agpr_use_asm() #0 {
; GFX908: TotalNumVgprs: 32
; GFX90A: TotalNumVgprs: 35
-define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32(ptr addrspace(1) %out, float %a, float %b, <32 x float> %c) #0 {
- %result = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %a, float %b, <32 x float> %c, i32 0, i32 0, i32 0)
- store <32 x float> %result, ptr addrspace(1) %out
- ret void
-}
attributes #0 = { "amdgpu-agpr-alloc"="0" }
diff --git a/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll b/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
index 933f81c279341..bf1befc4bcd7c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
@@ -13,8 +13,6 @@
; ASM-LABEL: amdhsa_kernarg_preload_4_implicit_6:
; ASM: .amdhsa_user_sgpr_count 12
; ASM: .amdhsa_next_free_sgpr 12
-; ASM: ; TotalNumSgprs: 18
-; ASM: ; NumSGPRsForWavesPerEU: 18
; Test that we include preloaded SGPRs in the GRANULATED_WAVEFRONT_SGPR_COUNT
; feild that are not explicitly referenced in the kernel. This test has 6 implicit
@@ -33,8 +31,6 @@ define amdgpu_kernel void @amdhsa_kernarg_preload_4_implicit_6(i128 inreg) { ret
; ASM-LABEL: amdhsa_kernarg_preload_8_implicit_2:
; ASM: .amdhsa_user_sgpr_count 10
; ASM: .amdhsa_next_free_sgpr 10
-; ASM: ; TotalNumSgprs: 16
-; ASM: ; NumSGPRsForWavesPerEU: 16
; Only the kernarg_ptr is enabled so we should have 8 preload kernarg SGPRs, 2
; implicit, and 6 extra.
@@ -49,8 +45,6 @@ define amdgpu_kernel void @amdhsa_kernarg_preload_8_implicit_2(i256 inreg) #0 {
; ASM-LABEL: amdhsa_kernarg_preload_1_implicit_2:
; ASM: .amdhsa_user_sgpr_count 3
; ASM: .amdhsa_next_free_sgpr 3
-; ASM: ; TotalNumSgprs: 9
-; ASM: ; NumSGPRsForWavesPerEU: 9
; 1 preload, 2 implicit, 6 extra. Rounds up to 16 SGPRs in the KD.
@@ -64,8 +58,6 @@ define amdgpu_kernel void @amdhsa_kernarg_preload_1_implicit_2(i32 inreg) #0 { r
; ASM-LABEL: amdhsa_kernarg_preload_0_implicit_2:
; ASM: .amdhsa_user_sgpr_count 2
; ASM: .amdhsa_next_free_sgpr 0
-; ASM: ; TotalNumSgprs: 6
-; ASM: ; NumSGPRsForWavesPerEU: 6
; 0 preload kernarg SGPRs, 2 implicit, 6 extra. Rounds up to 8 SGPRs in the KD.
; Encoded like '00'.
@@ -92,3 +84,16 @@ define amdgpu_kernel void @many__i32(
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
+
+; ASM: ; amdhsa_kernarg_preload_4_implicit_6 Kernel info:
+; ASM: ; TotalNumSgprs: 18
+; ASM: ; NumSGPRsForWavesPerEU: 18
+; ASM: ; amdhsa_kernarg_preload_8_implicit_2 Kernel info:
+; ASM: ; TotalNumSgprs: 16
+; ASM: ; NumSGPRsForWavesPerEU: 16
+; ASM: ; amdhsa_kernarg_preload_1_implicit_2 Kernel info:
+; ASM: ; TotalNumSgprs: 9
+; ASM: ; NumSGPRsForWavesPerEU: 9
+; ASM: ; amdhsa_kernarg_preload_0_implicit_2 Kernel info:
+; ASM: ; TotalNumSgprs: 6
+; ASM: ; NumSGPRsForWavesPerEU: 6
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll b/llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
index b05c65e73d734..e1c685522d192 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
@@ -6,7 +6,6 @@
; CHECK: .type kernel_32_agprs
-; CHECK: NumAgprs: 32
define amdgpu_kernel void @kernel_32_agprs() #0 {
bb:
call void asm sideeffect "", "~{v8}" ()
@@ -15,7 +14,6 @@ bb:
}
; CHECK: .type kernel_0_agprs
-; CHECK: NumAgprs: 0
define amdgpu_kernel void @kernel_0_agprs() #0 {
bb:
call void asm sideeffect "", "~{v0}" ()
@@ -23,7 +21,6 @@ bb:
}
; CHECK: .type kernel_40_vgprs
-; CHECK: NumAgprs: 16
define amdgpu_kernel void @kernel_40_vgprs() #0 {
bb:
call void asm sideeffect "", "~{v39}" ()
@@ -32,7 +29,6 @@ bb:
}
; CHECK: .type kernel_max_gprs
-; CHECK: NumAgprs: 256
define amdgpu_kernel void @kernel_max_gprs() #0 {
bb:
call void asm sideeffect "", "~{v255}" ()
@@ -41,7 +37,6 @@ bb:
}
; CHECK: .type func_32_agprs
-; CHECK: NumAgprs: 32
define void @func_32_agprs() #0 {
bb:
call void asm sideeffect "", "~{v8}" ()
@@ -50,7 +45,6 @@ bb:
}
; CHECK: .type kernel_call_func_32_agprs
-; CHECK: NumAgprs: 32
define amdgpu_kernel void @kernel_call_func_32_agprs() #0 {
bb:
call void @func_32_agprs() #0
@@ -61,14 +55,28 @@ declare void @undef_func()
; CHECK: .type kernel_call_undef_func
; CHECK: .set .Lkernel_call_undef_func.num_agpr, max(0, amdgpu.max_num_agpr)
-; CHECK: NumAgprs: .Lkernel_call_undef_func.num_agpr
-; CHECK: .set amdgpu.max_num_agpr, 32
define amdgpu_kernel void @kernel_call_undef_func() #0 {
bb:
call void @undef_func()
ret void
}
+; CHECK: ; kernel_32_agprs Kernel info:
+; CHECK: NumAgprs: 32
+; CHECK: ; kernel_0_agprs Kernel info:
+; CHECK: NumAgprs: 0
+; CHECK: ; kernel_40_vgprs Kernel info:
+; CHECK: NumAgprs: 16
+; CHECK: ; kernel_max_gprs Kernel info:
+; CHECK: NumAgprs: 256
+; CHECK: ; func_32_agprs Function info:
+; CHECK: NumAgprs: 32
+; CHECK: ; kernel_call_func_32_agprs Kernel info:
+; CHECK: NumAgprs: 32
+; CHECK: ; kernel_call_undef_func Kernel info:
+; CHECK: NumAgprs: 32
+; CHECK: .set amdgpu.max_num_agpr, 32
+
; CHECK: ---
; CHECK: amdpal.pipelines:
; GFX90A: agpr_count: 0x20
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
index 57784651591b8..7dcfdf2cedbb7 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
@@ -528,18 +528,6 @@ define internal void @use256vgprs() {
}
; GCN-LABEL: {{^}}f256:
-; GFX9: NumVgprs: 256
-; GFX90A: NumVgprs: 256
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 256
-; GFX10WGP-WAVE32: NumVgprs: 256
-; GFX10WGP-WAVE64: NumVgprs: 256
-; GFX10CU-WAVE32: NumVgprs: 256
-; GFX10CU-WAVE64: NumVgprs: 256
-; GFX11WGP-WAVE32: NumVgprs: 256
-; GFX11WGP-WAVE64: NumVgprs: 256
-; GFX11CU-WAVE32: NumVgprs: 256
-; GFX11CU-WAVE64: NumVgprs: 256
define amdgpu_kernel void @f256() #256 {
call void @use256vgprs()
ret void
@@ -558,9 +546,6 @@ attributes #256 = { nounwind "amdgpu-flat-work-group-size"="256,256" }
; GFX11WGP-WAVE64: .set .Lf512.num_vgpr, max(256, amdgpu.max_num_vgpr)
; GFX11CU-WAVE32: .set .Lf512.num_vgpr, max(192, amdgpu.max_num_vgpr)
; GFX11CU-WAVE64: .set .Lf512.num_vgpr, max(192, amdgpu.max_num_vgpr)
-; GCN: NumVgprs: .Lf512.num_vgpr
-; GFX90A: NumAgprs: .Lf512.num_agpr
-; GFX90A: TotalNumVgprs: totalnumvgprs(.Lf512.num_agpr, .Lf512.num_vgpr)
define amdgpu_kernel void @f512() #512 {
call void @foo()
call void @use256vgprs()
@@ -580,9 +565,6 @@ attributes #512 = { nounwind "amdgpu-flat-work-group-size"="512,512" }
; GFX11WGP-WAVE64: .set .Lf1024.num_vgpr, max(192, amdgpu.max_num_vgpr)
; GFX11CU-WAVE32: .set .Lf1024.num_vgpr, max(96, amdgpu.max_num_vgpr)
; GFX11CU-WAVE64: .set .Lf1024.num_vgpr, max(96, amdgpu.max_num_vgpr)
-; GCN: NumVgprs: .Lf1024.num_vgpr
-; GFX90A: NumAgprs: .Lf1024.num_agpr
-; GFX90A: TotalNumVgprs: totalnumvgprs(.Lf1024.num_agpr, .Lf1024.num_vgpr)
define amdgpu_kernel void @f1024() #1024 {
call void @foo()
call void @use256vgprs()
@@ -592,3 +574,43 @@ define amdgpu_kernel void @f1024() #1024 {
attributes #1024 = { nounwind "amdgpu-flat-work-group-size"="1024,1024" }
declare void @foo()
+
+; GCN: ; f256 Kernel info:
+; GFX9: NumVgprs: 256
+; GFX90A: NumVgprs: 256
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 256
+; GFX10WGP-WAVE32: NumVgprs: 256
+; GFX10WGP-WAVE64: NumVgprs: 256
+; GFX10CU-WAVE32: NumVgprs: 256
+; GFX10CU-WAVE64: NumVgprs: 256
+; GFX11WGP-WAVE32: NumVgprs: 256
+; GFX11WGP-WAVE64: NumVgprs: 256
+; GFX11CU-WAVE32: NumVgprs: 256
+; GFX11CU-WAVE64: NumVgprs: 256
+; GCN: ; f512 Kernel info:
+; GFX9: NumVgprs: 128
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 128
+; GFX90A: TotalNumVgprs: 256
+; GFX10WGP-WAVE32: NumVgprs: 256
+; GFX10WGP-WAVE64: NumVgprs: 256
+; GFX10CU-WAVE32: NumVgprs: 128
+; GFX10CU-WAVE64: NumVgprs: 128
+; GFX11WGP-WAVE32: NumVgprs: 256
+; GFX11WGP-WAVE64: NumVgprs: 256
+; GFX11CU-WAVE32: NumVgprs: 192
+; GFX11CU-WAVE64: NumVgprs: 192
+; GCN: ; f1024 Kernel info:
+; GFX9: NumVgprs: 64
+; GFX90A: NumVgprs: 64
+; GFX90A: NumAgprs: 64
+; GFX90A: TotalNumVgprs: 128
+; GFX10WGP-WAVE32: NumVgprs: 128
+; GFX10WGP-WAVE64: NumVgprs: 128
+; GFX10CU-WAVE32: NumVgprs: 64
+; GFX10CU-WAVE64: NumVgprs: 64
+; GFX11WGP-WAVE32: NumVgprs: 192
+; GFX11WGP-WAVE64: NumVgprs: 192
+; GFX11CU-WAVE32: NumVgprs: 96
+; GFX11CU-WAVE64: NumVgprs: 96
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
index 0a02be9c5b358..1c5290422f917 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
@@ -2,10 +2,6 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=HSAMD %s
; CHECK-LABEL: {{^}}min_64_max_64:
-; CHECK: SGPRBlocks: 0
-; CHECK: VGPRBlocks: 0
-; CHECK: NumSGPRsForWavesPerEU: 1
-; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @min_64_max_64() #0 {
entry:
ret void
@@ -13,10 +9,6 @@ entry:
attributes #0 = {"amdgpu-flat-work-group-size"="64,64"}
; CHECK-LABEL: {{^}}min_64_max_128:
-; CHECK: SGPRBlocks: 0
-; CHECK: VGPRBlocks: 0
-; CHECK: NumSGPRsForWavesPerEU: 1
-; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @min_64_max_128() #1 {
entry:
ret void
@@ -24,10 +16,6 @@ entry:
attributes #1 = {"amdgpu-flat-work-group-size"="64,128"}
; CHECK-LABEL: {{^}}min_128_max_128:
-; CHECK: SGPRBlocks: 8
-; CHECK: VGPRBlocks: 7
-; CHECK: NumSGPRsForWavesPerEU: 65
-; CHECK: NumVGPRsForWavesPerEU: 29
define amdgpu_kernel void @min_128_max_128() #2 {
entry:
ret void
@@ -35,10 +23,6 @@ entry:
attributes #2 = {"amdgpu-flat-work-group-size"="128,128"}
; CHECK-LABEL: {{^}}min_1024_max_1024
-; CHECK: SGPRBlocks: 8
-; CHECK: VGPRBlocks: 10
-; CHECK: NumSGPRsForWavesPerEU: 65
-; CHECK: NumVGPRsForWavesPerEU: 43
@var = addrspace(1) global float 0.0
define amdgpu_kernel void @min_1024_max_1024() #3 {
%val0 = load volatile float, ptr addrspace(1) @var
@@ -141,3 +125,24 @@ attributes #3 = {"amdgpu-flat-work-group-size"="1024,1024"}
; HSAMD: .name: min_128_max_128
; HSAMD: .max_flat_workgroup_size: 1024
; HSAMD: .name: min_1024_max_1024
+
+; CHECK: ; min_64_max_64 Kernel info:
+; CHECK: SGPRBlocks: 0
+; CHECK: VGPRBlocks: 0
+; CHECK: NumSGPRsForWavesPerEU: 1
+; CHECK: NumVGPRsForWavesPerEU: 1
+; CHECK: ; min_64_max_128 Kernel info:
+; CHECK: SGPRBlocks: 0
+; CHECK: VGPRBlocks: 0
+; CHECK: NumSGPRsForWavesPerEU: 1
+; CHECK: NumVGPRsForWavesPerEU: 1
+; CHECK: ; min_128_max_128 Kernel info:
+; CHECK: SGPRBlocks: 8
+; CHECK: VGPRBlocks: 7
+; CHECK: NumSGPRsForWavesPerEU: 65
+; CHECK: NumVGPRsForWavesPerEU: 29
+; CHECK: ; min_1024_max_1024 Kernel info:
+; CHECK: SGPRBlocks: 8
+; CHECK: VGPRBlocks: 10
+; CHECK: NumSGPRsForWavesPerEU: 65
+; CHECK: NumVGPRsForWavesPerEU: 43
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
index 41bce31c6ebc0..cae517a5c4460 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
@@ -2,10 +2,6 @@
; Exactly 1 wave per execution unit.
; CHECK-LABEL: {{^}}empty_exactly_1:
-; CHECK: SGPRBlocks: 12
-; CHECK: VGPRBlocks: 32
-; CHECK: NumSGPRsForWavesPerEU: 102
-; CHECK: NumVGPRsForWavesPerEU: 129
define amdgpu_kernel void @empty_exactly_1() #0 {
entry:
ret void
@@ -14,10 +10,6 @@ attributes #0 = {"amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="1,64
; Exactly 5 waves per execution unit.
; CHECK-LABEL: {{^}}empty_exactly_5:
-; CHECK: SGPRBlocks: 12
-; CHECK: VGPRBlocks: 10
-; CHECK: NumSGPRsForWavesPerEU: 102
-; CHECK: NumVGPRsForWavesPerEU: 41
define amdgpu_kernel void @empty_exactly_5() #1 {
entry:
ret void
@@ -26,10 +18,6 @@ attributes #1 = {"amdgpu-waves-per-eu"="5,5"}
; Exactly 10 waves per execution unit.
; CHECK-LABEL: {{^}}empty_exactly_10:
-; CHECK: SGPRBlocks: 0
-; CHECK: VGPRBlocks: 0
-; CHECK: NumSGPRsForWavesPerEU: 1
-; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @empty_exactly_10() #2 {
entry:
ret void
@@ -38,10 +26,6 @@ attributes #2 = {"amdgpu-waves-per-eu"="10,10"}
; At least 1 wave per execution unit.
; CHECK-LABEL: {{^}}empty_at_least_1:
-; CHECK: SGPRBlocks: 0
-; CHECK: VGPRBlocks: 0
-; CHECK: NumSGPRsForWavesPerEU: 1
-; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @empty_at_least_1() #3 {
entry:
ret void
@@ -50,10 +34,6 @@ attributes #3 = {"amdgpu-waves-per-eu"="1"}
; At least 5 waves per execution unit.
; CHECK-LABEL: {{^}}empty_at_least_5:
-; CHECK: SGPRBlocks: 0
-; CHECK: VGPRBlocks: 0
-; CHECK: NumSGPRsForWavesPerEU: 1
-; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @empty_at_least_5() #4 {
entry:
ret void
@@ -62,10 +42,6 @@ attributes #4 = {"amdgpu-waves-per-eu"="5"}
; At least 10 waves per execution unit.
; CHECK-LABEL: {{^}}empty_at_least_10:
-; CHECK: SGPRBlocks: 0
-; CHECK: VGPRBlocks: 0
-; CHECK: NumSGPRsForWavesPerEU: 1
-; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @empty_at_least_10() #5 {
entry:
ret void
@@ -76,10 +52,6 @@ attributes #5 = {"amdgpu-waves-per-eu"="10"}
; At most 5 waves per execution unit.
; CHECK-LABEL: {{^}}empty_at_most_5:
-; CHECK: SGPRBlocks: 12
-; CHECK: VGPRBlocks: 10
-; CHECK: NumSGPRsForWavesPerEU: 102
-; CHECK: NumVGPRsForWavesPerEU: 41
define amdgpu_kernel void @empty_at_most_5() #6 {
entry:
ret void
@@ -88,10 +60,6 @@ attributes #6 = {"amdgpu-waves-per-eu"="1,5" "amdgpu-flat-work-group-size"="1,64
; At most 10 waves per execution unit.
; CHECK-LABEL: {{^}}empty_at_most_10:
-; CHECK: SGPRBlocks: 0
-; CHECK: VGPRBlocks: 0
-; CHECK: NumSGPRsForWavesPerEU: 1
-; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @empty_at_most_10() #7 {
entry:
ret void
@@ -102,10 +70,6 @@ attributes #7 = {"amdgpu-waves-per-eu"="1,10"}
; Between 5 and 10 waves per execution unit.
; CHECK-LABEL: {{^}}empty_between_5_and_10:
-; CHECK: SGPRBlocks: 0
-; CHECK: VGPRBlocks: 0
-; CHECK: NumSGPRsForWavesPerEU: 1
-; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @empty_between_5_and_10() #8 {
entry:
ret void
@@ -116,10 +80,6 @@ attributes #8 = {"amdgpu-waves-per-eu"="5,10"}
; Exactly 10 waves per execution unit.
; CHECK-LABEL: {{^}}exactly_10:
-; CHECK: SGPRBlocks: 3
-; CHECK: VGPRBlocks: 5
-; CHECK: NumSGPRsForWavesPerEU: 30
-; CHECK: NumVGPRsForWavesPerEU: 24
define amdgpu_kernel void @exactly_10() #9 {
%val0 = load volatile float, ptr addrspace(1) @var
%val1 = load volatile float, ptr addrspace(1) @var
@@ -191,10 +151,6 @@ attributes #9 = {"amdgpu-waves-per-eu"="10,10"}
; Exactly 256 workitems and exactly 2 waves.
; CHECK-LABEL: {{^}}empty_workitems_exactly_256_waves_exactly_2:
-; CHECK: SGPRBlocks: 12
-; CHECK: VGPRBlocks: 21
-; CHECK: NumSGPRsForWavesPerEU: 102
-; CHECK: NumVGPRsForWavesPerEU: 85
define amdgpu_kernel void @empty_workitems_exactly_256_waves_exactly_2() #10 {
entry:
ret void
@@ -203,10 +159,6 @@ attributes #10 = {"amdgpu-flat-work-group-size"="256,256" "amdgpu-waves-per-eu"=
; Minimum 2 waves, maximum limited by LDS usage.
; CHECK-LABEL: {{^}}empty_at_least_2_lds_limited:
-; CHECK: SGPRBlocks: 12
-; CHECK: VGPRBlocks: 12
-; CHECK: NumSGPRsForWavesPerEU: 102
-; CHECK: NumVGPRsForWavesPerEU: 49
define amdgpu_kernel void @empty_at_least_2_lds_limited() #11 {
entry:
ret void
@@ -216,12 +168,74 @@ attributes #11 = {"amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="2
; Minimum 2 waves, maximum limited by LDS usage. Requested maximum within spec
; but above achievable occupancy has no effect.
; CHECK-LABEL: {{^}}empty_at_least_2_lds_limited_max_above_achievable:
-; CHECK: SGPRBlocks: 12
-; CHECK: VGPRBlocks: 12
-; CHECK: NumSGPRsForWavesPerEU: 102
-; CHECK: NumVGPRsForWavesPerEU: 49
define amdgpu_kernel void @empty_at_least_2_lds_limited_max_above_achievable() #12 {
entry:
ret void
}
attributes #12 = {"amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="2,10" "amdgpu-lds-size"="16384"}
+
+; CHECK: ; empty_exactly_1 Kernel info:
+; CHECK: SGPRBlocks: 12
+; CHECK: VGPRBlocks: 32
+; CHECK: NumSGPRsForWavesPerEU: 102
+; CHECK: NumVGPRsForWavesPerEU: 129
+; CHECK: ; empty_exactly_5 Kernel info:
+; CHECK: SGPRBlocks: 12
+; CHECK: VGPRBlocks: 10
+; CHECK: NumSGPRsForWavesPerEU: 102
+; CHECK: NumVGPRsForWavesPerEU: 41
+; CHECK: ; empty_exactly_10 Kernel info:
+; CHECK: SGPRBlocks: 0
+; CHECK: VGPRBlocks: 0
+; CHECK: NumSGPRsForWavesPerEU: 1
+; CHECK: NumVGPRsForWavesPerEU: 1
+; CHECK: ; empty_at_least_1 Kernel info:
+; CHECK: SGPRBlocks: 0
+; CHECK: VGPRBlocks: 0
+; CHECK: NumSGPRsForWavesPerEU: 1
+; CHECK: NumVGPRsForWavesPerEU: 1
+; CHECK: ; empty_at_least_5 Kernel info:
+; CHECK: SGPRBlocks: 0
+; CHECK: VGPRBlocks: 0
+; CHECK: NumSGPRsForWavesPerEU: 1
+; CHECK: NumVGPRsForWavesPerEU: 1
+; CHECK: ; empty_at_least_10 Kernel info:
+; CHECK: SGPRBlocks: 0
+; CHECK: VGPRBlocks: 0
+; CHECK: NumSGPRsForWavesPerEU: 1
+; CHECK: NumVGPRsForWavesPerEU: 1
+; CHECK: ; empty_at_most_5 Kernel info:
+; CHECK: SGPRBlocks: 12
+; CHECK: VGPRBlocks: 10
+; CHECK: NumSGPRsForWavesPerEU: 102
+; CHECK: NumVGPRsForWavesPerEU: 41
+; CHECK: ; empty_at_most_10 Kernel info:
+; CHECK: SGPRBlocks: 0
+; CHECK: VGPRBlocks: 0
+; CHECK: NumSGPRsForWavesPerEU: 1
+; CHECK: NumVGPRsForWavesPerEU: 1
+; CHECK: ; empty_between_5_and_10 Kernel info:
+; CHECK: SGPRBlocks: 0
+; CHECK: VGPRBlocks: 0
+; CHECK: NumSGPRsForWavesPerEU: 1
+; CHECK: NumVGPRsForWavesPerEU: 1
+; CHECK: ; exactly_10 Kernel info:
+; CHECK: SGPRBlocks: 3
+; CHECK: VGPRBlocks: 5
+; CHECK: NumSGPRsForWavesPerEU: 30
+; CHECK: NumVGPRsForWavesPerEU: 24
+; CHECK: ; empty_workitems_exactly_256_waves_exactly_2 Kernel info:
+; CHECK: SGPRBlocks: 12
+; CHECK: VGPRBlocks: 21
+; CHECK: NumSGPRsForWavesPerEU: 102
+; CHECK: NumVGPRsForWavesPerEU: 85
+; CHECK: ; empty_at_least_2_lds_limited Kernel info:
+; CHECK: SGPRBlocks: 12
+; CHECK: VGPRBlocks: 12
+; CHECK: NumSGPRsForWavesPerEU: 102
+; CHECK: NumVGPRsForWavesPerEU: 49
+; CHECK: ; empty_at_least_2_lds_limited_max_above_achievable Kernel info:
+; CHECK: SGPRBlocks: 12
+; CHECK: VGPRBlocks: 12
+; CHECK: NumSGPRsForWavesPerEU: 102
+; CHECK: NumVGPRsForWavesPerEU: 49
diff --git a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
index 1d6299b5fc177..f4d0a1274b9fe 100644
--- a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
@@ -12,8 +12,6 @@
; Make sure to run a GPU with the SGPR allocation bug.
; GCN-LABEL: {{^}}use_vcc:
-; GCN: ; TotalNumSgprs: 34
-; GCN: ; NumVgprs: 0
define void @use_vcc() #1 {
call void asm sideeffect "", "~{vcc}" () #0
ret void
@@ -30,53 +28,36 @@ define void @use_vcc() #1 {
; GCN: v_readlane_b32 s4, v40, 2
; GCN: s_mov_b32 s33, s4
; GCN: s_setpc_b64 s[30:31]
-; GCN: ; TotalNumSgprs: 36
-; GCN: ; NumVgprs: 41
define void @indirect_use_vcc() #1 {
call void @use_vcc()
ret void
}
; GCN-LABEL: {{^}}indirect_2level_use_vcc_kernel:
-; CI: ; TotalNumSgprs: 38
-; VI-NOBUG: ; TotalNumSgprs: 40
-; VI-BUG: ; TotalNumSgprs: 96
-; GCN: ; NumVgprs: 41
define amdgpu_kernel void @indirect_2level_use_vcc_kernel(ptr addrspace(1) %out) #0 {
call void @indirect_use_vcc()
ret void
}
; GCN-LABEL: {{^}}use_flat_scratch:
-; CI: ; TotalNumSgprs: 36
-; VI: ; TotalNumSgprs: 38
-; GCN: ; NumVgprs: 0
define void @use_flat_scratch() #1 {
call void asm sideeffect "", "~{flat_scratch}" () #0
ret void
}
; GCN-LABEL: {{^}}indirect_use_flat_scratch:
-; CI: ; TotalNumSgprs: 38
-; VI: ; TotalNumSgprs: 40
-; GCN: ; NumVgprs: 41
define void @indirect_use_flat_scratch() #1 {
call void @use_flat_scratch()
ret void
}
; GCN-LABEL: {{^}}indirect_2level_use_flat_scratch_kernel:
-; CI: ; TotalNumSgprs: 38
-; VI-NOBUG: ; TotalNumSgprs: 40
-; VI-BUG: ; TotalNumSgprs: 96
-; GCN: ; NumVgprs: 41
define amdgpu_kernel void @indirect_2level_use_flat_scratch_kernel(ptr addrspace(1) %out) #0 {
call void @indirect_use_flat_scratch()
ret void
}
; GCN-LABEL: {{^}}use_10_vgpr:
-; GCN: ; NumVgprs: 10
define void @use_10_vgpr() #1 {
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4}"() #0
call void asm sideeffect "", "~{v5},~{v6},~{v7},~{v8},~{v9}"() #0
@@ -84,51 +65,42 @@ define void @use_10_vgpr() #1 {
}
; GCN-LABEL: {{^}}indirect_use_10_vgpr:
-; GCN: ; NumVgprs: 41
define void @indirect_use_10_vgpr() #0 {
call void @use_10_vgpr()
ret void
}
; GCN-LABEL: {{^}}indirect_2_level_use_10_vgpr:
-; GCN: ; NumVgprs: 41
define amdgpu_kernel void @indirect_2_level_use_10_vgpr() #0 {
call void @indirect_use_10_vgpr()
ret void
}
; GCN-LABEL: {{^}}use_50_vgpr:
-; GCN: ; NumVgprs: 50
define void @use_50_vgpr() #1 {
call void asm sideeffect "", "~{v49}"() #0
ret void
}
; GCN-LABEL: {{^}}indirect_use_50_vgpr:
-; GCN: ; NumVgprs: 50
define void @indirect_use_50_vgpr() #0 {
call void @use_50_vgpr()
ret void
}
; GCN-LABEL: {{^}}use_80_sgpr:
-; GCN: ; TotalNumSgprs: 80
define void @use_80_sgpr() #1 {
call void asm sideeffect "", "~{s79}"() #0
ret void
}
; GCN-LABEL: {{^}}indirect_use_80_sgpr:
-; GCN: ; TotalNumSgprs: 82
define void @indirect_use_80_sgpr() #1 {
call void @use_80_sgpr()
ret void
}
; GCN-LABEL: {{^}}indirect_2_level_use_80_sgpr:
-; CI: ; TotalNumSgprs: 84
-; VI-NOBUG: ; TotalNumSgprs: 86
-; VI-BUG: ; TotalNumSgprs: 96
define amdgpu_kernel void @indirect_2_level_use_80_sgpr() #0 {
call void @indirect_use_80_sgpr()
ret void
@@ -136,7 +108,6 @@ define amdgpu_kernel void @indirect_2_level_use_80_sgpr() #0 {
; GCN-LABEL: {{^}}use_stack0:
-; GCN: ScratchSize: 2052
define void @use_stack0() #1 {
%alloca = alloca [512 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
@@ -144,7 +115,6 @@ define void @use_stack0() #1 {
}
; GCN-LABEL: {{^}}use_stack1:
-; GCN: ScratchSize: 404
define void @use_stack1() #1 {
%alloca = alloca [100 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
@@ -152,7 +122,6 @@ define void @use_stack1() #1 {
}
; GCN-LABEL: {{^}}indirect_use_stack:
-; GCN: ScratchSize: 2132
define void @indirect_use_stack() #1 {
%alloca = alloca [16 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
@@ -161,7 +130,6 @@ define void @indirect_use_stack() #1 {
}
; GCN-LABEL: {{^}}indirect_2_level_use_stack:
-; GCN: ScratchSize: 2132
define amdgpu_kernel void @indirect_2_level_use_stack() #0 {
call void @indirect_use_stack()
ret void
@@ -170,7 +138,6 @@ define amdgpu_kernel void @indirect_2_level_use_stack() #0 {
; Should be maximum of callee usage
; GCN-LABEL: {{^}}multi_call_use_use_stack:
-; GCN: ScratchSize: 2052
define amdgpu_kernel void @multi_call_use_use_stack() #0 {
call void @use_stack0()
call void @use_stack1()
@@ -183,10 +150,8 @@ declare void @external() #0
; GCN-LABEL: {{^}}usage_external:
; TotalNumSgprs: 48
; NumVgprs: 24
-; GCN: ScratchSize: 16384
;
; GCN-V5-LABEL: {{^}}usage_external:
-; GCN-V5: ScratchSize: 0
define amdgpu_kernel void @usage_external() #0 {
call void @external()
ret void
@@ -197,20 +162,16 @@ declare void @external_recurse() #2
; GCN-LABEL: {{^}}usage_external_recurse:
; TotalNumSgprs: 48
; NumVgprs: 24
-; GCN: ScratchSize: 16384
;
; GCN-V5-LABEL: {{^}}usage_external_recurse:
-; GCN-V5: ScratchSize: 0
define amdgpu_kernel void @usage_external_recurse() #0 {
call void @external_recurse()
ret void
}
; GCN-LABEL: {{^}}direct_recursion_use_stack:
-; GCN: ScratchSize: 18448{{$}}
;
; GCN-V5-LABEL: {{^}}direct_recursion_use_stack:
-; GCN-V5: ScratchSize: 2064{{$}}
define void @direct_recursion_use_stack(i32 %val) #2 {
%alloca = alloca [512 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
@@ -241,9 +202,6 @@ define amdgpu_kernel void @usage_direct_recursion(i32 %n) #0 {
; GCN: ; sgpr96 s[{{[0-9]+}}:{{[0-9]+}}]
; GCN: .set .Lcount_use_sgpr96_external_call.num_vgpr, max(0, amdgpu.max_num_vgpr)
; GCN: .set .Lcount_use_sgpr96_external_call.numbered_sgpr, max(33, amdgpu.max_num_sgpr)
-; CI: TotalNumSgprs: .Lcount_use_sgpr96_external_call.numbered_sgpr+4
-; VI-BUG: TotalNumSgprs: 96
-; GCN: NumVgprs: .Lcount_use_sgpr96_external_call.num_vgpr
define amdgpu_kernel void @count_use_sgpr96_external_call() {
entry:
tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1
@@ -256,9 +214,6 @@ entry:
; GCN: ; sgpr160 s[{{[0-9]+}}:{{[0-9]+}}]
; GCN: .set .Lcount_use_sgpr160_external_call.num_vgpr, max(0, amdgpu.max_num_vgpr)
; GCN: .set .Lcount_use_sgpr160_external_call.numbered_sgpr, max(33, amdgpu.max_num_sgpr)
-; CI: TotalNumSgprs: .Lcount_use_sgpr160_external_call.numbered_sgpr+4
-; VI-BUG: TotalNumSgprs: 96
-; GCN: NumVgprs: .Lcount_use_sgpr160_external_call.num_vgpr
define amdgpu_kernel void @count_use_sgpr160_external_call() {
entry:
tail call void asm sideeffect "; sgpr160 $0", "s"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
@@ -271,9 +226,6 @@ entry:
; GCN: ; vgpr160 v[{{[0-9]+}}:{{[0-9]+}}]
; GCN: .set .Lcount_use_vgpr160_external_call.num_vgpr, max(5, amdgpu.max_num_vgpr)
; GCN: .set .Lcount_use_vgpr160_external_call.numbered_sgpr, max(33, amdgpu.max_num_sgpr)
-; CI: TotalNumSgprs: .Lcount_use_vgpr160_external_call.numbered_sgpr+4
-; VI-BUG: TotalNumSgprs: 96
-; GCN: NumVgprs: .Lcount_use_vgpr160_external_call.num_vgpr
define amdgpu_kernel void @count_use_vgpr160_external_call() {
entry:
tail call void asm sideeffect "; vgpr160 $0", "v"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
@@ -281,6 +233,83 @@ entry:
ret void
}
+; GCN: ; use_vcc Function info:
+; GCN: ; TotalNumSgprs: 34
+; GCN: ; NumVgprs: 0
+; GCN: ; indirect_use_vcc Function info:
+; GCN: ; TotalNumSgprs: 36
+; GCN: ; NumVgprs: 41
+; GCN: ; indirect_2level_use_vcc_kernel Kernel info:
+; CI: ; TotalNumSgprs: 38
+; VI-NOBUG: ; TotalNumSgprs: 40
+; VI-BUG: ; TotalNumSgprs: 96
+; GCN: ; NumVgprs: 41
+; GCN: ; use_flat_scratch Function info:
+; CI: ; TotalNumSgprs: 36
+; VI: ; TotalNumSgprs: 38
+; GCN: ; NumVgprs: 0
+; GCN: ; indirect_use_flat_scratch Function info:
+; CI: ; TotalNumSgprs: 38
+; VI: ; TotalNumSgprs: 40
+; GCN: ; NumVgprs: 41
+; GCN: ; indirect_2level_use_flat_scratch_kernel Kernel info:
+; CI: ; TotalNumSgprs: 38
+; VI-NOBUG: ; TotalNumSgprs: 40
+; VI-BUG: ; TotalNumSgprs: 96
+; GCN: ; NumVgprs: 41
+; GCN: ; use_10_vgpr Function info:
+; GCN: ; NumVgprs: 10
+; GCN: ; indirect_use_10_vgpr Function info:
+; GCN: ; NumVgprs: 41
+; GCN: ; indirect_2_level_use_10_vgpr Kernel info:
+; GCN: ; NumVgprs: 41
+; GCN: ; use_50_vgpr Function info:
+; GCN: ; NumVgprs: 50
+; GCN: ; indirect_use_50_vgpr Function info:
+; GCN: ; NumVgprs: 50
+; GCN: ; use_80_sgpr Function info:
+; GCN: ; TotalNumSgprs: 80
+; GCN: ; indirect_use_80_sgpr Function info:
+; GCN: ; TotalNumSgprs: 82
+; GCN: ; indirect_2_level_use_80_sgpr Kernel info:
+; CI: ; TotalNumSgprs: 84
+; VI-NOBUG: ; TotalNumSgprs: 86
+; VI-BUG: ; TotalNumSgprs: 96
+; GCN: ; use_stack0 Function info:
+; GCN: ScratchSize: 2052
+; GCN: ; use_stack1 Function info:
+; GCN: ScratchSize: 404
+; GCN: ; indirect_use_stack Function info:
+; GCN: ScratchSize: 2132
+; GCN: ; indirect_2_level_use_stack Kernel info:
+; GCN: ScratchSize: 2132
+; GCN: ; multi_call_use_use_stack Kernel info:
+; GCN: ScratchSize: 2052
+; GCN: ; usage_external Kernel info:
+; GCN: ScratchSize: 16384
+;
+; GCN-V5: ScratchSize: 0
+; GCN: ; usage_external_recurse Kernel info:
+; GCN: ScratchSize: 16384
+;
+; GCN-V5: ScratchSize: 0
+; GCN: ; direct_recursion_use_stack Function info:
+; GCN: ScratchSize: 18448{{$}}
+;
+; GCN-V5: ScratchSize: 2064{{$}}
+; GCN: ; count_use_sgpr96_external_call Kernel info:
+; CI: TotalNumSgprs: 84
+; VI-BUG: TotalNumSgprs: 96
+; GCN: NumVgprs: 50
+; GCN: ; count_use_sgpr160_external_call Kernel info:
+; CI: TotalNumSgprs: 84
+; VI-BUG: TotalNumSgprs: 96
+; GCN: NumVgprs: 50
+; GCN: ; count_use_vgpr160_external_call Kernel info:
+; CI: TotalNumSgprs: 84
+; VI-BUG: TotalNumSgprs: 96
+; GCN: NumVgprs: 50
+
; GCN: .set amdgpu.max_num_vgpr, 50
; GCN: .set amdgpu.max_num_agpr, 0
; GCN: .set amdgpu.max_num_sgpr, 80
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
index a7009c4d20e33..ab0cea0ce12ca 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
@@ -1992,7 +1992,6 @@ define void @too_many_args_use_workitem_id_x_stack_yz(
ret void
}
-; GCN: ScratchSize: 0
define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_stack_yz() #1 {
; GFX7-LABEL: kern_call_too_many_args_use_workitem_id_x_stack_yz:
@@ -2106,3 +2105,6 @@ declare i32 @llvm.amdgcn.workitem.id.z() #0
attributes #0 = { nounwind readnone speculatable "amdgpu-flat-work-group-size"="1,512" }
attributes #1 = { nounwind noinline "amdgpu-flat-work-group-size"="1,512" }
+
+; GCN: ; too_many_args_use_workitem_id_x_stack_yz Function info:
+; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
index 718140f82887e..b764faa52c2c4 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
@@ -1363,7 +1363,6 @@ define void @too_many_args_use_workitem_id_x_stack_yz(
ret void
}
-; GCN: ScratchSize: 0
define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_stack_yz() #1 {
; GCN-LABEL: kern_call_too_many_args_use_workitem_id_x_stack_yz:
@@ -1519,3 +1518,6 @@ attributes #2 = { nounwind "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
+
+; GCN: ; use_workitem_id_x Function info:
+; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
index 5f82bec69a6b3..5e8e6b70be7ce 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
@@ -20,7 +20,6 @@ define i16 @cvt_pk_bf8_f16_v(ptr addrspace(1) %out) {
ret i16 %cvt
}
-; GFX1250: codeLenInByte = 24
define i16 @cvt_pk_fp8_f16_v(ptr addrspace(1) %out) {
; FAKE16-LABEL: cvt_pk_fp8_f16_v:
@@ -40,6 +39,10 @@ define i16 @cvt_pk_fp8_f16_v(ptr addrspace(1) %out) {
ret i16 %cvt
}
-; GFX1250: codeLenInByte = 24
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1250: {{.*}}
+
+; GFX1250: ; cvt_pk_bf8_f16_v Function info:
+; GFX1250: codeLenInByte = 24
+; GFX1250: ; cvt_pk_fp8_f16_v Function info:
+; GFX1250: codeLenInByte = 24
diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll b/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
index b59bcb7967af2..ec5222f4b7596 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
@@ -1,10 +1,9 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9,NOT-GFX12 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10,NOT-GFX12 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX1100,NOT-GFX12 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX1150,NOT-GFX12 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX1200 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX1250 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX9,NOT-GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX10,NOT-GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX11,GFX1100,NOT-GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX11,GFX1150,NOT-GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX1200 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -show-mc-encoding < %s | FileCheck -check-prefixes=CHECK,GFX1250 %s
declare float @llvm.fabs.f32(float)
declare float @llvm.fma.f32(float, float, float)
@@ -47,9 +46,6 @@ define float @v_mul_f32_vop2(float %x, float %y) {
%mul = fmul float %x, %y
ret float %mul
}
-; NOT-GFX12: codeLenInByte = 12
-; GFX1200: codeLenInByte = 28
-; GFX1250: codeLenInByte = 16
define float @v_mul_f32_vop2_inline_imm(float %x) {
; GFX9-LABEL: v_mul_f32_vop2_inline_imm:
@@ -89,9 +85,6 @@ define float @v_mul_f32_vop2_inline_imm(float %x) {
%mul = fmul float %x, 4.0
ret float %mul
}
-; NOT-GFX12: codeLenInByte = 12
-; GFX1200: codeLenInByte = 28
-; GFX1250: codeLenInByte = 16
define float @v_mul_f32_vop2_literal(float %x) {
; GFX9-LABEL: v_mul_f32_vop2_literal:
@@ -131,9 +124,6 @@ define float @v_mul_f32_vop2_literal(float %x) {
%mul = fmul float %x, 123.0
ret float %mul
}
-; NOT-GFX12: codeLenInByte = 16
-; GFX1200: codeLenInByte = 32
-; GFX1250: codeLenInByte = 20
define float @v_mul_f32_vop3_src_mods(float %x, float %y) {
; GFX9-LABEL: v_mul_f32_vop3_src_mods:
@@ -174,9 +164,6 @@ define float @v_mul_f32_vop3_src_mods(float %x, float %y) {
%mul = fmul float %fabs.x, %y
ret float %mul
}
-; NOT-GFX12: codeLenInByte = 16
-; GFX1200: codeLenInByte = 32
-; GFX1250: codeLenInByte = 20
define float @v_mul_f32_vop3_src_mods_inline_imm(float %x, float %y) {
; GFX9-LABEL: v_mul_f32_vop3_src_mods_inline_imm:
@@ -218,9 +205,6 @@ define float @v_mul_f32_vop3_src_mods_inline_imm(float %x, float %y) {
ret float %mul
}
-; NOT-GFX12: codeLenInByte = 16
-; GFX1200: codeLenInByte = 32
-; GFX1250: codeLenInByte = 20
define float @v_mul_f32_vop3_src_mods_literal(float %x, float %y) {
; GFX9-LABEL: v_mul_f32_vop3_src_mods_literal:
@@ -263,11 +247,6 @@ define float @v_mul_f32_vop3_src_mods_literal(float %x, float %y) {
ret float %mul
}
-; GFX9: codeLenInByte = 24
-; GFX10: codeLenInByte = 20
-; GFX11: codeLenInByte = 20
-; GFX1200: codeLenInByte = 36
-; GFX1250: codeLenInByte = 24
define float @v_mul_f32_vop2_frame_index(float %x) {
; GFX9-LABEL: v_mul_f32_vop2_frame_index:
@@ -313,11 +292,6 @@ define float @v_mul_f32_vop2_frame_index(float %x) {
ret float %mul
}
-; GFX9: codeLenInByte = 20
-; GFX10: codeLenInByte = 20
-; GFX11: codeLenInByte = 12
-; GFX1200: codeLenInByte = 28
-; GFX1250: codeLenInByte = 16
define float @v_fma_f32(float %x, float %y, float %z) {
; GFX9-LABEL: v_fma_f32:
@@ -358,9 +332,6 @@ define float @v_fma_f32(float %x, float %y, float %z) {
ret float %fma
}
-; NOT-GFX12: codeLenInByte = 16
-; GFX1200: codeLenInByte = 32
-; GFX1250: codeLenInByte = 20
define float @v_fma_f32_src_mods(float %x, float %y, float %z) {
; GFX9-LABEL: v_fma_f32_src_mods:
@@ -402,9 +373,6 @@ define float @v_fma_f32_src_mods(float %x, float %y, float %z) {
ret float %fma
}
-; NOT-GFX12: codeLenInByte = 16
-; GFX1200: codeLenInByte = 32
-; GFX1250: codeLenInByte = 20
define float @v_fmac_f32(float %x, float %y) {
; GFX9-LABEL: v_fmac_f32:
@@ -445,11 +413,6 @@ define float @v_fmac_f32(float %x, float %y) {
ret float %fma
}
-; GFX9: codeLenInByte = 16
-; GFX10: codeLenInByte = 12
-; GFX11: codeLenInByte = 12
-; GFX1200: codeLenInByte = 28
-; GFX1250: codeLenInByte = 16
define float @v_fmaak_f32(float %x, float %y) {
; GFX9-LABEL: v_fmaak_f32:
@@ -491,11 +454,6 @@ define float @v_fmaak_f32(float %x, float %y) {
ret float %fma
}
-; GFX9: codeLenInByte = 24
-; GFX10: codeLenInByte = 16
-; GFX11: codeLenInByte = 16
-; GFX1200: codeLenInByte = 32
-; GFX1250: codeLenInByte = 20
define float @v_fma_k_f32_src_mods(float %x, float %y) {
; GFX9-LABEL: v_fma_k_f32_src_mods:
@@ -538,11 +496,6 @@ define float @v_fma_k_f32_src_mods(float %x, float %y) {
ret float %fma
}
-; GFX9: codeLenInByte = 24
-; GFX10: codeLenInByte = 20
-; GFX11: codeLenInByte = 20
-; GFX1200: codeLenInByte = 36
-; GFX1250: codeLenInByte = 24
define amdgpu_ps float @s_fmaak_f32(float inreg %x, float inreg %y) {
; GFX9-LABEL: s_fmaak_f32:
@@ -591,12 +544,6 @@ define amdgpu_ps float @s_fmaak_f32(float inreg %x, float inreg %y) {
ret float %fma
}
-; GFX9: codeLenInByte = 20
-; GFX10: codeLenInByte = 12
-; GFX1100: codeLenInByte = 16
-; GFX1150: codeLenInByte = 16
-; GFX1200: codeLenInByte = 16
-; GFX1250: codeLenInByte = 24
define double @v_mul_f64_vop2_literal_32(double %x) {
; GFX9-LABEL: v_mul_f64_vop2_literal_32:
@@ -639,11 +586,6 @@ define double @v_mul_f64_vop2_literal_32(double %x) {
ret double %mul
}
-; GFX9: codeLenInByte = 28
-; GFX10: codeLenInByte = 20
-; GFX1100: codeLenInByte = 20
-; GFX1150: codeLenInByte = 20
-; GFX1250: codeLenInByte = 20
define double @v_mul_f64_vop2_literal_64(double %x) {
; GFX9-LABEL: v_mul_f64_vop2_literal_64:
@@ -694,11 +636,6 @@ define double @v_mul_f64_vop2_literal_64(double %x) {
ret double %mul
}
-; GFX9: codeLenInByte = 32
-; GFX10: codeLenInByte = 32
-; GFX1100: codeLenInByte = 36
-; GFX1150: codeLenInByte = 36
-; GFX1250: codeLenInByte = 24
define i64 @v_add_u64_vop2_literal_32(i64 %x) {
; GFX9-LABEL: v_add_u64_vop2_literal_32:
@@ -745,11 +682,6 @@ define i64 @v_add_u64_vop2_literal_32(i64 %x) {
ret i64 %add
}
-; GFX9: codeLenInByte = 20
-; GFX10: codeLenInByte = 28
-; GFX1100: codeLenInByte = 32
-; GFX1150: codeLenInByte = 32
-; GFX1250: codeLenInByte = 20
define i64 @v_add_u64_vop2_literal_64(i64 %x) {
; GFX9-LABEL: v_add_u64_vop2_literal_64:
@@ -796,10 +728,97 @@ define i64 @v_add_u64_vop2_literal_64(i64 %x) {
ret i64 %add
}
+; CHECK: ; v_mul_f32_vop2 Function info:
+; NOT-GFX12: codeLenInByte = 12
+; GFX1200: codeLenInByte = 28
+; GFX1250: codeLenInByte = 16
+; CHECK: ; v_mul_f32_vop2_inline_imm Function info:
+; NOT-GFX12: codeLenInByte = 12
+; GFX1200: codeLenInByte = 28
+; GFX1250: codeLenInByte = 16
+; CHECK: ; v_mul_f32_vop2_literal Function info:
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
+; GFX1250: codeLenInByte = 20
+; CHECK: ; v_mul_f32_vop3_src_mods Function info:
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
+; GFX1250: codeLenInByte = 20
+; CHECK: ; v_mul_f32_vop3_src_mods_inline_imm Function info:
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
+; GFX1250: codeLenInByte = 20
+; CHECK: ; v_mul_f32_vop3_src_mods_literal Function info:
+; GFX9: codeLenInByte = 24
+; GFX10: codeLenInByte = 20
+; GFX11: codeLenInByte = 20
+; GFX1200: codeLenInByte = 36
+; GFX1250: codeLenInByte = 24
+; CHECK: ; v_mul_f32_vop2_frame_index Function info:
+; GFX9: codeLenInByte = 20
+; GFX10: codeLenInByte = 20
+; GFX11: codeLenInByte = 12
+; GFX1200: codeLenInByte = 28
+; GFX1250: codeLenInByte = 16
+; CHECK: ; v_fma_f32 Function info:
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
+; GFX1250: codeLenInByte = 20
+; CHECK: ; v_fma_f32_src_mods Function info:
+; NOT-GFX12: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
+; GFX1250: codeLenInByte = 20
+; CHECK: ; v_fmac_f32 Function info:
+; GFX9: codeLenInByte = 16
+; GFX10: codeLenInByte = 12
+; GFX11: codeLenInByte = 12
+; GFX1200: codeLenInByte = 28
+; GFX1250: codeLenInByte = 16
+; CHECK: ; v_fmaak_f32 Function info:
+; GFX9: codeLenInByte = 24
+; GFX10: codeLenInByte = 16
+; GFX11: codeLenInByte = 16
+; GFX1200: codeLenInByte = 32
+; GFX1250: codeLenInByte = 20
+; CHECK: ; v_fma_k_f32_src_mods Function info:
+; GFX9: codeLenInByte = 24
+; GFX10: codeLenInByte = 20
+; GFX1100: codeLenInByte = 20
+; GFX1150: codeLenInByte = 20
+; GFX1200: codeLenInByte = 36
+; GFX1250: codeLenInByte = 24
+; CHECK: ; s_fmaak_f32 Kernel info:
+; GFX9: codeLenInByte = 20
+; GFX10: codeLenInByte = 12
+; GFX1100: codeLenInByte = 16
+; GFX1150: codeLenInByte = 16
+; GFX1200: codeLenInByte = 16
+; GFX1250: codeLenInByte = 24
+; CHECK: ; v_mul_f64_vop2_literal_32 Function info:
+; GFX9: codeLenInByte = 28
+; GFX10: codeLenInByte = 20
+; GFX1100: codeLenInByte = 20
+; GFX1150: codeLenInByte = 20
+; GFX1200: codeLenInByte = 32
+; GFX1250: codeLenInByte = 20
+; CHECK: ; v_mul_f64_vop2_literal_64 Function info:
+; GFX9: codeLenInByte = 32
+; GFX10: codeLenInByte = 32
+; GFX1100: codeLenInByte = 36
+; GFX1150: codeLenInByte = 36
+; GFX1200: codeLenInByte = 48
+; GFX1250: codeLenInByte = 24
+; CHECK: ; v_add_u64_vop2_literal_32 Function info:
+; GFX9: codeLenInByte = 20
+; GFX10: codeLenInByte = 28
+; GFX1100: codeLenInByte = 32
+; GFX1150: codeLenInByte = 32
+; GFX1200: codeLenInByte = 48
+; GFX1250: codeLenInByte = 20
+; CHECK: ; v_add_u64_vop2_literal_64 Function info:
; GFX9: codeLenInByte = 20
; GFX10: codeLenInByte = 28
; GFX1100: codeLenInByte = 32
; GFX1150: codeLenInByte = 32
+; GFX1200: codeLenInByte = 48
; GFX1250: codeLenInByte = 24
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; NOT-GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir b/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
index 3ad963b0f723c..adabbd11aa07b 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
@@ -6,7 +6,6 @@
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
# CHECK: v_mov_b32_e32 v16, v1 ; encoding: [0x01,0x03,0x20,0x7e]
# CHECK: v_mov_b32_e32 v0, v3 ; encoding: [0x03,0x03,0x00,0x7e]
-# CHECK: ; codeLenInByte = 12
---
name: indirect_mov
@@ -22,7 +21,6 @@ body: |
# CHECK: meta: ; @meta
# CHECK: ; wave barrier
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
-# CHECK: ; codeLenInByte = 4
---
name: meta
tracksRegLiveness: true
@@ -37,7 +35,6 @@ body: |
# CHECK: wait_asyncmark_meta: ; @wait_asyncmark_meta
# CHECK: ; wait_asyncmark(1)
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
-# CHECK: ; codeLenInByte = 4
---
name: wait_asyncmark_meta
tracksRegLiveness: true
@@ -53,7 +50,6 @@ body: |
# CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align 2
# CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
-# CHECK: ; codeLenInByte = 16
---
name: align4
@@ -76,7 +72,6 @@ body: |
# CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align 3
# CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
-# CHECK: ; codeLenInByte = 20
---
name: align8
tracksRegLiveness: true
@@ -98,7 +93,6 @@ body: |
# CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align 4
# CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
-# CHECK: ; codeLenInByte = 20
---
name: align16
tracksRegLiveness: true
@@ -120,7 +114,6 @@ body: |
# CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align 5
# CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
-# CHECK: ; codeLenInByte = 36
---
name: align32
tracksRegLiveness: true
@@ -135,3 +128,18 @@ body: |
bb.2 (align 32):
S_ENDPGM 0
...
+
+# CHECK: ; indirect_mov Function info:
+# CHECK: ; codeLenInByte = 12
+# CHECK: ; meta Function info:
+# CHECK: ; codeLenInByte = 4
+# CHECK: ; wait_asyncmark_meta Function info:
+# CHECK: ; codeLenInByte = 4
+# CHECK: ; align4 Function info:
+# CHECK: ; codeLenInByte = 16
+# CHECK: ; align8 Function info:
+# CHECK: ; codeLenInByte = 20
+# CHECK: ; align16 Function info:
+# CHECK: ; codeLenInByte = 20
+# CHECK: ; align32 Function info:
+# CHECK: ; codeLenInByte = 36
diff --git a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
index e9146c0d241ba..d0696ec1c99a5 100644
--- a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
@@ -1,8 +1,6 @@
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_default_si:
-; GCN: FloatMode: 240
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_default_si(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #0 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -10,8 +8,6 @@ define amdgpu_kernel void @test_default_si(ptr addrspace(1) %out0, ptr addrspace
}
; GCN-LABEL: {{^}}test_default_vi:
-; GCN: FloatMode: 240
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_default_vi(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #1 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -19,8 +15,6 @@ define amdgpu_kernel void @test_default_vi(ptr addrspace(1) %out0, ptr addrspace
}
; GCN-LABEL: {{^}}test_f64_denormals:
-; GCN: FloatMode: 240
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #2 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -28,8 +22,6 @@ define amdgpu_kernel void @test_f64_denormals(ptr addrspace(1) %out0, ptr addrsp
}
; GCN-LABEL: {{^}}test_f32_denormals:
-; GCNL: FloatMode: 48
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_f32_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #3 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -37,8 +29,6 @@ define amdgpu_kernel void @test_f32_denormals(ptr addrspace(1) %out0, ptr addrsp
}
; GCN-LABEL: {{^}}test_f32_f64_denormals:
-; GCN: FloatMode: 240
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_f32_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #4 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -46,8 +36,6 @@ define amdgpu_kernel void @test_f32_f64_denormals(ptr addrspace(1) %out0, ptr ad
}
; GCN-LABEL: {{^}}test_no_denormals
-; GCN: FloatMode: 0
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_no_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #5 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -55,8 +43,6 @@ define amdgpu_kernel void @test_no_denormals(ptr addrspace(1) %out0, ptr addrspa
}
; GCN-LABEL: {{^}}test_f16_f64_denormals:
-; GCN: FloatMode: 240
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_f16_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #6 {
store half 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -64,8 +50,6 @@ define amdgpu_kernel void @test_f16_f64_denormals(ptr addrspace(1) %out0, ptr ad
}
; GCN-LABEL: {{^}}test_no_f16_f64_denormals:
-; GCN: FloatMode: 48
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_no_f16_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #7 {
store half 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -73,8 +57,6 @@ define amdgpu_kernel void @test_no_f16_f64_denormals(ptr addrspace(1) %out0, ptr
}
; GCN-LABEL: {{^}}test_f32_f16_f64_denormals:
-; GCN: FloatMode: 240
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_f32_f16_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %out2) #8 {
store half 0.0, ptr addrspace(1) %out0
store float 0.0, ptr addrspace(1) %out1
@@ -83,8 +65,6 @@ define amdgpu_kernel void @test_f32_f16_f64_denormals(ptr addrspace(1) %out0, pt
}
; GCN-LABEL: {{^}}test_just_f32_attr_flush
-; GCN: FloatMode: 192
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_just_f32_attr_flush(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #9 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -92,8 +72,6 @@ define amdgpu_kernel void @test_just_f32_attr_flush(ptr addrspace(1) %out0, ptr
}
; GCN-LABEL: {{^}}test_flush_all_outputs:
-; GCN: FloatMode: 80
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_flush_all_outputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #10 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -101,8 +79,6 @@ define amdgpu_kernel void @test_flush_all_outputs(ptr addrspace(1) %out0, ptr ad
}
; GCN-LABEL: {{^}}test_flush_all_inputs:
-; GCN: FloatMode: 160
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_flush_all_inputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #11 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -110,8 +86,6 @@ define amdgpu_kernel void @test_flush_all_inputs(ptr addrspace(1) %out0, ptr add
}
; GCN-LABEL: {{^}}test_flush_f32_inputs:
-; GCN: FloatMode: 224
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_flush_f32_inputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #12 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -119,8 +93,6 @@ define amdgpu_kernel void @test_flush_f32_inputs(ptr addrspace(1) %out0, ptr add
}
; GCN-LABEL: {{^}}test_flush_f32_outputs:
-; GCN: FloatMode: 208
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_flush_f32_outputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #13 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -128,8 +100,6 @@ define amdgpu_kernel void @test_flush_f32_outputs(ptr addrspace(1) %out0, ptr ad
}
; GCN-LABEL: {{^}}test_flush_f64_inputs:
-; GCN: FloatMode: 176
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_flush_f64_inputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #14 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -137,8 +107,6 @@ define amdgpu_kernel void @test_flush_f64_inputs(ptr addrspace(1) %out0, ptr add
}
; GCN-LABEL: {{^}}test_flush_f64_outputs:
-; GCN: FloatMode: 112
-; GCN: IeeeMode: 1
define amdgpu_kernel void @test_flush_f64_outputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #15 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -146,8 +114,6 @@ define amdgpu_kernel void @test_flush_f64_outputs(ptr addrspace(1) %out0, ptr ad
}
; GCN-LABEL: {{^}}kill_gs_const:
-; GCN: FloatMode: 240
-; GCN: IeeeMode: 0
define amdgpu_gs void @kill_gs_const() {
main_body:
%cmp0 = icmp ule i32 0, 3
@@ -158,8 +124,6 @@ main_body:
}
; GCN-LABEL: {{^}}kill_vcc_implicit_def:
-; GCN: FloatMode: 240
-; GCN: IeeeMode: 0
define amdgpu_ps float @kill_vcc_implicit_def(ptr addrspace(4) inreg, ptr addrspace(4) inreg, ptr addrspace(4) inreg, ptr addrspace(4) inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
entry:
%tmp0 = fcmp olt float %13, 0.0
@@ -187,3 +151,58 @@ attributes #12 = { nounwind denormal_fpenv(ieee, float:ieee|preservesign) }
attributes #13 = { nounwind denormal_fpenv(ieee, float:preservesign|ieee) }
attributes #14 = { nounwind denormal_fpenv(ieee|preservesign, float:ieee) }
attributes #15 = { nounwind denormal_fpenv(preservesign|ieee, float:ieee) }
+
+; GCN: ; test_default_si Kernel info:
+; GCN: FloatMode: 240
+; GCN: IeeeMode: 1
+; GCN: ; test_default_vi Kernel info:
+; GCN: FloatMode: 240
+; GCN: IeeeMode: 1
+; GCN: ; test_f64_denormals Kernel info:
+; GCN: FloatMode: 240
+; GCN: IeeeMode: 1
+; GCNL: ; test_f32_denormals Kernel info:
+; GCNL: FloatMode: 48
+; GCN: IeeeMode: 1
+; GCN: ; test_f32_f64_denormals Kernel info:
+; GCN: FloatMode: 240
+; GCN: IeeeMode: 1
+; GCN: ; test_no_denormals Kernel info:
+; GCN: FloatMode: 0
+; GCN: IeeeMode: 1
+; GCN: ; test_f16_f64_denormals Kernel info:
+; GCN: FloatMode: 240
+; GCN: IeeeMode: 1
+; GCN: ; test_no_f16_f64_denormals Kernel info:
+; GCN: FloatMode: 48
+; GCN: IeeeMode: 1
+; GCN: ; test_f32_f16_f64_denormals Kernel info:
+; GCN: FloatMode: 240
+; GCN: IeeeMode: 1
+; GCN: ; test_just_f32_attr_flush Kernel info:
+; GCN: FloatMode: 192
+; GCN: IeeeMode: 1
+; GCN: ; test_flush_all_outputs Kernel info:
+; GCN: FloatMode: 80
+; GCN: IeeeMode: 1
+; GCN: ; test_flush_all_inputs Kernel info:
+; GCN: FloatMode: 160
+; GCN: IeeeMode: 1
+; GCN: ; test_flush_f32_inputs Kernel info:
+; GCN: FloatMode: 224
+; GCN: IeeeMode: 1
+; GCN: ; test_flush_f32_outputs Kernel info:
+; GCN: FloatMode: 208
+; GCN: IeeeMode: 1
+; GCN: ; test_flush_f64_inputs Kernel info:
+; GCN: FloatMode: 176
+; GCN: IeeeMode: 1
+; GCN: ; test_flush_f64_outputs Kernel info:
+; GCN: FloatMode: 112
+; GCN: IeeeMode: 1
+; GCN: ; kill_gs_const Kernel info:
+; GCN: FloatMode: 240
+; GCN: IeeeMode: 0
+; GCN: ; kill_vcc_implicit_def Kernel info:
+; GCN: FloatMode: 240
+; GCN: IeeeMode: 0
diff --git a/llvm/test/CodeGen/AMDGPU/empty-function.ll b/llvm/test/CodeGen/AMDGPU/empty-function.ll
index 088effce57fd1..62099ffecd0b8 100644
--- a/llvm/test/CodeGen/AMDGPU/empty-function.ll
+++ b/llvm/test/CodeGen/AMDGPU/empty-function.ll
@@ -6,16 +6,19 @@
; SI: .text
; SI-LABEL: {{^}}empty_function_ret:
; SI: s_endpgm
-; SI: codeLenInByte = 4
define amdgpu_kernel void @empty_function_ret() #0 {
ret void
}
; SI: .text
; SI-LABEL: {{^}}empty_function_unreachable:
-; SI: codeLenInByte = 0
define amdgpu_kernel void @empty_function_unreachable() #0 {
unreachable
}
attributes #0 = { nounwind }
+
+; SI: ; empty_function_ret Kernel info:
+; SI: codeLenInByte = 4
+; SI: ; empty_function_unreachable Kernel info:
+; SI: codeLenInByte = 0
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
index a59382ba20dc5..60ef3eb9532ef 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
@@ -27,15 +27,6 @@
; GFX9-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
; GFX10-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
-; CI: ; TotalNumSgprs: 8
-; VI-NOXNACK: ; TotalNumSgprs: 8
-; HSA-VI-NOXNACK: ; TotalNumSgprs: 8
-; VI-XNACK: ; TotalNumSgprs: 12
-; HSA-VI-XNACK: ; TotalNumSgprs: 12
-; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 14
-; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 14
-; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 8
-; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 8
define amdgpu_kernel void @no_vcc_no_flat() {
entry:
call void asm sideeffect "", "~{s7}"()
@@ -50,15 +41,6 @@ entry:
; GFX9-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
; GFX10-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
-; CI: ; TotalNumSgprs: 10
-; VI-NOXNACK: ; TotalNumSgprs: 10
-; HSA-VI-NOXNACK: ; TotalNumSgprs: 10
-; VI-XNACK: ; TotalNumSgprs: 12
-; HSA-VI-XNACK: ; TotalNumSgprs: 12
-; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 14
-; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 14
-; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 10
-; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 10
define amdgpu_kernel void @vcc_no_flat() {
entry:
call void asm sideeffect "", "~{s7},~{vcc}"()
@@ -73,15 +55,6 @@ entry:
; GFX9-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
; GFX10-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
-; CI: ; TotalNumSgprs: 12
-; VI-NOXNACK: ; TotalNumSgprs: 14
-; HSA-VI-NOXNACK: ; TotalNumSgprs: 24
-; VI-XNACK: ; TotalNumSgprs: 14
-; HSA-VI-XNACK: ; TotalNumSgprs: 24
-; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 14
-; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 14
-; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 8
-; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 8
define amdgpu_kernel void @no_vcc_flat() {
entry:
call void asm sideeffect "", "~{s7},~{flat_scratch}"()
@@ -96,15 +69,6 @@ entry:
; GFX9-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
; GFX10-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
-; CI: ; TotalNumSgprs: 12
-; VI-NOXNACK: ; TotalNumSgprs: 14
-; HSA-VI-NOXNACK: ; TotalNumSgprs: 24
-; VI-XNACK: ; TotalNumSgprs: 14
-; HSA-VI-XNACK: ; TotalNumSgprs: 24
-; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 14
-; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 14
-; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 10
-; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 10
define amdgpu_kernel void @vcc_flat() {
entry:
call void asm sideeffect "", "~{s7},~{vcc},~{flat_scratch}"()
@@ -122,15 +86,6 @@ entry:
; GFX9-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
; GFX10-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
-; CI: NumSgprs: 4
-; VI-NOXNACK: NumSgprs: 6
-; HSA-VI-NOXNACK: NumSgprs: 24
-; VI-XNACK: NumSgprs: 6
-; HSA-VI-XNACK: NumSgprs: 24
-; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 6
-; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 6
-; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 0
-; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 0
define amdgpu_kernel void @use_flat_scr() #0 {
entry:
call void asm sideeffect "; clobber ", "~{flat_scratch}"()
@@ -143,15 +98,6 @@ entry:
; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
-; CI: NumSgprs: 4
-; VI-NOXNACK: NumSgprs: 6
-; HSA-VI-NOXNACK: NumSgprs: 24
-; VI-XNACK: NumSgprs: 6
-; HSA-VI-XNACK: NumSgprs: 24
-; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 6
-; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 6
-; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 0
-; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 0
define amdgpu_kernel void @use_flat_scr_lo() #0 {
entry:
call void asm sideeffect "; clobber ", "~{flat_scratch_lo}"()
@@ -166,6 +112,62 @@ entry:
; GFX9-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
; GFX10-ARCH-FLAT-XNACK: .amdhsa_reserve_xnack_mask 1
+define amdgpu_kernel void @use_flat_scr_hi() #0 {
+entry:
+ call void asm sideeffect "; clobber ", "~{flat_scratch_hi}"()
+ ret void
+}
+
+attributes #0 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
+
+; GCN: ; no_vcc_no_flat Kernel info:
+; CI: ; TotalNumSgprs: 8
+; VI-NOXNACK: ; TotalNumSgprs: 8
+; HSA-VI-NOXNACK: ; TotalNumSgprs: 8
+; VI-XNACK: ; TotalNumSgprs: 12
+; HSA-VI-XNACK: ; TotalNumSgprs: 12
+; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 14
+; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 14
+; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 8
+; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 8
+
+; GCN: ; vcc_no_flat Kernel info:
+; CI: ; TotalNumSgprs: 10
+; VI-NOXNACK: ; TotalNumSgprs: 10
+; HSA-VI-NOXNACK: ; TotalNumSgprs: 10
+; VI-XNACK: ; TotalNumSgprs: 12
+; HSA-VI-XNACK: ; TotalNumSgprs: 12
+; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 14
+; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 14
+; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 10
+; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 10
+
+; GCN: ; no_vcc_flat Kernel info:
+; CI: ; TotalNumSgprs: 12
+; VI-NOXNACK: ; TotalNumSgprs: 14
+; HSA-VI-NOXNACK: ; TotalNumSgprs: 24
+; VI-XNACK: ; TotalNumSgprs: 14
+; HSA-VI-XNACK: ; TotalNumSgprs: 24
+; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 14
+; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 14
+; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 8
+; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 8
+
+; GCN: ; vcc_flat Kernel info:
+; CI: ; TotalNumSgprs: 12
+; VI-NOXNACK: ; TotalNumSgprs: 14
+; HSA-VI-NOXNACK: ; TotalNumSgprs: 24
+; VI-XNACK: ; TotalNumSgprs: 14
+; HSA-VI-XNACK: ; TotalNumSgprs: 24
+; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 14
+; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 14
+; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 10
+; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 10
+
+; GCN: ; use_flat_scr Kernel info:
; CI: NumSgprs: 4
; VI-NOXNACK: NumSgprs: 6
; HSA-VI-NOXNACK: NumSgprs: 24
@@ -175,13 +177,25 @@ entry:
; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 6
; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 0
; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 0
-define amdgpu_kernel void @use_flat_scr_hi() #0 {
-entry:
- call void asm sideeffect "; clobber ", "~{flat_scratch_hi}"()
- ret void
-}
-attributes #0 = { nounwind }
+; GCN: ; use_flat_scr_lo Kernel info:
+; CI: NumSgprs: 4
+; VI-NOXNACK: NumSgprs: 6
+; HSA-VI-NOXNACK: NumSgprs: 24
+; VI-XNACK: NumSgprs: 6
+; HSA-VI-XNACK: NumSgprs: 24
+; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 6
+; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 6
+; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 0
+; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 0
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
+; GCN: ; use_flat_scr_hi Kernel info:
+; CI: NumSgprs: 4
+; VI-NOXNACK: NumSgprs: 6
+; HSA-VI-NOXNACK: NumSgprs: 24
+; VI-XNACK: NumSgprs: 6
+; HSA-VI-XNACK: NumSgprs: 24
+; GFX9-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 6
+; GFX9-ARCH-FLAT-XNACK: ; TotalNumSgprs: 6
+; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 0
+; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 0
diff --git a/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll b/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
index 2c9778e1db5e5..a7ac8f5899b23 100644
--- a/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
@@ -13,9 +13,6 @@
; GCN: .set .Luse_vcc.has_dyn_sized_stack, 0
; GCN: .set .Luse_vcc.has_recursion, 0
; GCN: .set .Luse_vcc.has_indirect_call, 0
-; GCN: TotalNumSgprs: 36
-; GCN: NumVgprs: 0
-; GCN: ScratchSize: 0
define void @use_vcc() #1 {
call void asm sideeffect "", "~{vcc}" () #0
ret void
@@ -31,9 +28,6 @@ define void @use_vcc() #1 {
; GCN: .set .Lindirect_use_vcc.has_dyn_sized_stack, or(0, .Luse_vcc.has_dyn_sized_stack)
; GCN: .set .Lindirect_use_vcc.has_recursion, or(0, .Luse_vcc.has_recursion)
; GCN: .set .Lindirect_use_vcc.has_indirect_call, or(0, .Luse_vcc.has_indirect_call)
-; GCN: TotalNumSgprs: 38
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define void @indirect_use_vcc() #1 {
call void @use_vcc()
ret void
@@ -49,9 +43,6 @@ define void @indirect_use_vcc() #1 {
; GCN: .set .Lindirect_2level_use_vcc_kernel.has_dyn_sized_stack, or(0, .Lindirect_use_vcc.has_dyn_sized_stack)
; GCN: .set .Lindirect_2level_use_vcc_kernel.has_recursion, or(0, .Lindirect_use_vcc.has_recursion)
; GCN: .set .Lindirect_2level_use_vcc_kernel.has_indirect_call, or(0, .Lindirect_use_vcc.has_indirect_call)
-; GCN: TotalNumSgprs: 40
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define amdgpu_kernel void @indirect_2level_use_vcc_kernel(ptr addrspace(1) %out) #0 {
call void @indirect_use_vcc()
ret void
@@ -67,9 +58,6 @@ define amdgpu_kernel void @indirect_2level_use_vcc_kernel(ptr addrspace(1) %out)
; GCN: .set .Luse_flat_scratch.has_dyn_sized_stack, 0
; GCN: .set .Luse_flat_scratch.has_recursion, 0
; GCN: .set .Luse_flat_scratch.has_indirect_call, 0
-; GCN: TotalNumSgprs: 38
-; GCN: NumVgprs: 0
-; GCN: ScratchSize: 0
define void @use_flat_scratch() #1 {
call void asm sideeffect "", "~{flat_scratch}" () #0
ret void
@@ -85,9 +73,6 @@ define void @use_flat_scratch() #1 {
; GCN: .set .Lindirect_use_flat_scratch.has_dyn_sized_stack, or(0, .Luse_flat_scratch.has_dyn_sized_stack)
; GCN: .set .Lindirect_use_flat_scratch.has_recursion, or(0, .Luse_flat_scratch.has_recursion)
; GCN: .set .Lindirect_use_flat_scratch.has_indirect_call, or(0, .Luse_flat_scratch.has_indirect_call)
-; GCN: TotalNumSgprs: 40
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define void @indirect_use_flat_scratch() #1 {
call void @use_flat_scratch()
ret void
@@ -103,9 +88,6 @@ define void @indirect_use_flat_scratch() #1 {
; GCN: .set .Lindirect_2level_use_flat_scratch_kernel.has_dyn_sized_stack, or(0, .Lindirect_use_flat_scratch.has_dyn_sized_stack)
; GCN: .set .Lindirect_2level_use_flat_scratch_kernel.has_recursion, or(0, .Lindirect_use_flat_scratch.has_recursion)
; GCN: .set .Lindirect_2level_use_flat_scratch_kernel.has_indirect_call, or(0, .Lindirect_use_flat_scratch.has_indirect_call)
-; GCN: TotalNumSgprs: 40
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define amdgpu_kernel void @indirect_2level_use_flat_scratch_kernel(ptr addrspace(1) %out) #0 {
call void @indirect_use_flat_scratch()
ret void
@@ -121,9 +103,6 @@ define amdgpu_kernel void @indirect_2level_use_flat_scratch_kernel(ptr addrspace
; GCN: .set .Luse_10_vgpr.has_dyn_sized_stack, 0
; GCN: .set .Luse_10_vgpr.has_recursion, 0
; GCN: .set .Luse_10_vgpr.has_indirect_call, 0
-; GCN: TotalNumSgprs: 36
-; GCN: NumVgprs: 10
-; GCN: ScratchSize: 0
define void @use_10_vgpr() #1 {
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4}"() #0
call void asm sideeffect "", "~{v5},~{v6},~{v7},~{v8},~{v9}"() #0
@@ -140,9 +119,6 @@ define void @use_10_vgpr() #1 {
; GCN: .set .Lindirect_use_10_vgpr.has_dyn_sized_stack, or(0, .Luse_10_vgpr.has_dyn_sized_stack)
; GCN: .set .Lindirect_use_10_vgpr.has_recursion, or(0, .Luse_10_vgpr.has_recursion)
; GCN: .set .Lindirect_use_10_vgpr.has_indirect_call, or(0, .Luse_10_vgpr.has_indirect_call)
-; GCN: TotalNumSgprs: 38
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define void @indirect_use_10_vgpr() #0 {
call void @use_10_vgpr()
ret void
@@ -158,9 +134,6 @@ define void @indirect_use_10_vgpr() #0 {
; GCN: .set .Lindirect_2_level_use_10_vgpr.has_dyn_sized_stack, or(0, .Lindirect_use_10_vgpr.has_dyn_sized_stack)
; GCN: .set .Lindirect_2_level_use_10_vgpr.has_recursion, or(0, .Lindirect_use_10_vgpr.has_recursion)
; GCN: .set .Lindirect_2_level_use_10_vgpr.has_indirect_call, or(0, .Lindirect_use_10_vgpr.has_indirect_call)
-; GCN: TotalNumSgprs: 40
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define amdgpu_kernel void @indirect_2_level_use_10_vgpr() #0 {
call void @indirect_use_10_vgpr()
ret void
@@ -176,9 +149,6 @@ define amdgpu_kernel void @indirect_2_level_use_10_vgpr() #0 {
; GCN: .set .Luse_50_vgpr.has_dyn_sized_stack, 0
; GCN: .set .Luse_50_vgpr.has_recursion, 0
; GCN: .set .Luse_50_vgpr.has_indirect_call, 0
-; GCN: TotalNumSgprs: 36
-; GCN: NumVgprs: 50
-; GCN: ScratchSize: 0
define void @use_50_vgpr() #1 {
call void asm sideeffect "", "~{v49}"() #0
ret void
@@ -194,9 +164,6 @@ define void @use_50_vgpr() #1 {
; GCN: .set .Lindirect_use_50_vgpr.has_dyn_sized_stack, or(0, .Luse_50_vgpr.has_dyn_sized_stack)
; GCN: .set .Lindirect_use_50_vgpr.has_recursion, or(0, .Luse_50_vgpr.has_recursion)
; GCN: .set .Lindirect_use_50_vgpr.has_indirect_call, or(0, .Luse_50_vgpr.has_indirect_call)
-; GCN: TotalNumSgprs: 38
-; GCN: NumVgprs: 50
-; GCN: ScratchSize: 16
define void @indirect_use_50_vgpr() #0 {
call void @use_50_vgpr()
ret void
@@ -212,9 +179,6 @@ define void @indirect_use_50_vgpr() #0 {
; GCN: .set .Luse_80_sgpr.has_dyn_sized_stack, 0
; GCN: .set .Luse_80_sgpr.has_recursion, 0
; GCN: .set .Luse_80_sgpr.has_indirect_call, 0
-; GCN: TotalNumSgprs: 84
-; GCN: NumVgprs: 0
-; GCN: ScratchSize: 0
define void @use_80_sgpr() #1 {
call void asm sideeffect "", "~{s79}"() #0
ret void
@@ -230,9 +194,6 @@ define void @use_80_sgpr() #1 {
; GCN: .set .Lindirect_use_80_sgpr.has_dyn_sized_stack, or(0, .Luse_80_sgpr.has_dyn_sized_stack)
; GCN: .set .Lindirect_use_80_sgpr.has_recursion, or(0, .Luse_80_sgpr.has_recursion)
; GCN: .set .Lindirect_use_80_sgpr.has_indirect_call, or(0, .Luse_80_sgpr.has_indirect_call)
-; GCN: TotalNumSgprs: 84
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define void @indirect_use_80_sgpr() #1 {
call void @use_80_sgpr()
ret void
@@ -248,9 +209,6 @@ define void @indirect_use_80_sgpr() #1 {
; GCN: .set .Lindirect_2_level_use_80_sgpr.has_dyn_sized_stack, or(0, .Lindirect_use_80_sgpr.has_dyn_sized_stack)
; GCN: .set .Lindirect_2_level_use_80_sgpr.has_recursion, or(0, .Lindirect_use_80_sgpr.has_recursion)
; GCN: .set .Lindirect_2_level_use_80_sgpr.has_indirect_call, or(0, .Lindirect_use_80_sgpr.has_indirect_call)
-; GCN: TotalNumSgprs: 86
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define amdgpu_kernel void @indirect_2_level_use_80_sgpr() #0 {
call void @indirect_use_80_sgpr()
ret void
@@ -266,9 +224,6 @@ define amdgpu_kernel void @indirect_2_level_use_80_sgpr() #0 {
; GCN: .set .Luse_stack0.has_dyn_sized_stack, 0
; GCN: .set .Luse_stack0.has_recursion, 0
; GCN: .set .Luse_stack0.has_indirect_call, 0
-; GCN: TotalNumSgprs: 37
-; GCN: NumVgprs: 1
-; GCN: ScratchSize: 2052
define void @use_stack0() #1 {
%alloca = alloca [512 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
@@ -285,9 +240,6 @@ define void @use_stack0() #1 {
; GCN: .set .Luse_stack1.has_dyn_sized_stack, 0
; GCN: .set .Luse_stack1.has_recursion, 0
; GCN: .set .Luse_stack1.has_indirect_call, 0
-; GCN: TotalNumSgprs: 37
-; GCN: NumVgprs: 1
-; GCN: ScratchSize: 404
define void @use_stack1() #1 {
%alloca = alloca [100 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
@@ -304,9 +256,6 @@ define void @use_stack1() #1 {
; GCN: .set .Lindirect_use_stack.has_dyn_sized_stack, or(0, .Luse_stack0.has_dyn_sized_stack)
; GCN: .set .Lindirect_use_stack.has_recursion, or(0, .Luse_stack0.has_recursion)
; GCN: .set .Lindirect_use_stack.has_indirect_call, or(0, .Luse_stack0.has_indirect_call)
-; GCN: TotalNumSgprs: 38
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 2132
define void @indirect_use_stack() #1 {
%alloca = alloca [16 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
@@ -324,9 +273,6 @@ define void @indirect_use_stack() #1 {
; GCN: .set .Lindirect_2_level_use_stack.has_dyn_sized_stack, or(0, .Lindirect_use_stack.has_dyn_sized_stack)
; GCN: .set .Lindirect_2_level_use_stack.has_recursion, or(0, .Lindirect_use_stack.has_recursion)
; GCN: .set .Lindirect_2_level_use_stack.has_indirect_call, or(0, .Lindirect_use_stack.has_indirect_call)
-; GCN: TotalNumSgprs: 40
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 2132
define amdgpu_kernel void @indirect_2_level_use_stack() #0 {
call void @indirect_use_stack()
ret void
@@ -344,9 +290,6 @@ define amdgpu_kernel void @indirect_2_level_use_stack() #0 {
; GCN: .set .Lmulti_call_use_use_stack.has_dyn_sized_stack, or(0, .Luse_stack0.has_dyn_sized_stack, .Luse_stack1.has_dyn_sized_stack)
; GCN: .set .Lmulti_call_use_use_stack.has_recursion, or(0, .Luse_stack0.has_recursion, .Luse_stack1.has_recursion)
; GCN: .set .Lmulti_call_use_use_stack.has_indirect_call, or(0, .Luse_stack0.has_indirect_call, .Luse_stack1.has_indirect_call)
-; GCN: TotalNumSgprs: 58
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 2052
define amdgpu_kernel void @multi_call_use_use_stack() #0 {
call void @use_stack0()
call void @use_stack1()
@@ -365,9 +308,6 @@ declare void @external() #0
; GCN: .set .Lmulti_call_with_external.has_dyn_sized_stack, 1
; GCN: .set .Lmulti_call_with_external.has_recursion, 0
; GCN: .set .Lmulti_call_with_external.has_indirect_call, 1
-; GCN: TotalNumSgprs: .Lmulti_call_with_external.numbered_sgpr+6
-; GCN: NumVgprs: .Lmulti_call_with_external.num_vgpr
-; GCN: ScratchSize: 2052
define amdgpu_kernel void @multi_call_with_external() #0 {
call void @use_stack0()
call void @use_stack1()
@@ -385,9 +325,6 @@ define amdgpu_kernel void @multi_call_with_external() #0 {
; GCN: .set .Lmulti_call_with_external_and_duplicates.has_dyn_sized_stack, 1
; GCN: .set .Lmulti_call_with_external_and_duplicates.has_recursion, 0
; GCN: .set .Lmulti_call_with_external_and_duplicates.has_indirect_call, 1
-; GCN: TotalNumSgprs: .Lmulti_call_with_external_and_duplicates.numbered_sgpr+6
-; GCN: NumVgprs: .Lmulti_call_with_external_and_duplicates.num_vgpr
-; GCN: ScratchSize: 2052
define amdgpu_kernel void @multi_call_with_external_and_duplicates() #0 {
call void @use_stack0()
call void @use_stack0()
@@ -408,9 +345,6 @@ define amdgpu_kernel void @multi_call_with_external_and_duplicates() #0 {
; GCN: .set .Lusage_external.has_dyn_sized_stack, 1
; GCN: .set .Lusage_external.has_recursion, 0
; GCN: .set .Lusage_external.has_indirect_call, 1
-; GCN: TotalNumSgprs: .Lusage_external.numbered_sgpr+6
-; GCN: NumVgprs: .Lusage_external.num_vgpr
-; GCN: ScratchSize: 0
define amdgpu_kernel void @usage_external() #0 {
call void @external()
ret void
@@ -428,9 +362,6 @@ declare void @external_recurse() #2
; GCN: .set .Lusage_external_recurse.has_dyn_sized_stack, 1
; GCN: .set .Lusage_external_recurse.has_recursion, 1
; GCN: .set .Lusage_external_recurse.has_indirect_call, 1
-; GCN: TotalNumSgprs: .Lusage_external_recurse.numbered_sgpr+6
-; GCN: NumVgprs: .Lusage_external_recurse.num_vgpr
-; GCN: ScratchSize: 0
define amdgpu_kernel void @usage_external_recurse() #0 {
call void @external_recurse()
ret void
@@ -446,9 +377,6 @@ define amdgpu_kernel void @usage_external_recurse() #0 {
; GCN: .set .Ldirect_recursion_use_stack.has_dyn_sized_stack, 0
; GCN: .set .Ldirect_recursion_use_stack.has_recursion, 1
; GCN: .set .Ldirect_recursion_use_stack.has_indirect_call, 0
-; GCN: TotalNumSgprs: 40
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 2064
define void @direct_recursion_use_stack(i32 %val) #2 {
%alloca = alloca [512 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
@@ -474,9 +402,6 @@ ret:
; GCN: .set .Lusage_direct_recursion.has_dyn_sized_stack, or(0, .Ldirect_recursion_use_stack.has_dyn_sized_stack)
; GCN: .set .Lusage_direct_recursion.has_recursion, or(1, .Ldirect_recursion_use_stack.has_recursion)
; GCN: .set .Lusage_direct_recursion.has_indirect_call, or(0, .Ldirect_recursion_use_stack.has_indirect_call)
-; GCN: TotalNumSgprs: 42
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 2064
define amdgpu_kernel void @usage_direct_recursion(i32 %n) #0 {
call void @direct_recursion_use_stack(i32 %n)
ret void
@@ -492,9 +417,6 @@ define amdgpu_kernel void @usage_direct_recursion(i32 %n) #0 {
; GCN: .set .Lmulti_stage_recurse2.has_dyn_sized_stack, or(0, .Lmulti_stage_recurse1.has_dyn_sized_stack)
; GCN: .set .Lmulti_stage_recurse2.has_recursion, or(1, .Lmulti_stage_recurse1.has_recursion)
; GCN: .set .Lmulti_stage_recurse2.has_indirect_call, or(0, .Lmulti_stage_recurse1.has_indirect_call)
-; GCN: TotalNumSgprs: .Lmulti_stage_recurse2.numbered_sgpr+extrasgprs(.Lmulti_stage_recurse2.uses_vcc, .Lmulti_stage_recurse2.uses_flat_scratch, 1)
-; GCN: NumVgprs: max(43, .Lmulti_stage_recurse1.num_vgpr)
-; GCN: ScratchSize: 16+max(.Lmulti_stage_recurse1.private_seg_size)
; GCN-LABEL: {{^}}multi_stage_recurse1:
; GCN: .set .Lmulti_stage_recurse1.num_vgpr, max(48, 43)
; GCN: .set .Lmulti_stage_recurse1.num_agpr, max(0, 0)
@@ -505,9 +427,6 @@ define amdgpu_kernel void @usage_direct_recursion(i32 %n) #0 {
; GCN: .set .Lmulti_stage_recurse1.has_dyn_sized_stack, 0
; GCN: .set .Lmulti_stage_recurse1.has_recursion, 1
; GCN: .set .Lmulti_stage_recurse1.has_indirect_call, 0
-; GCN: TotalNumSgprs: 38
-; GCN: NumVgprs: 48
-; GCN: ScratchSize: 16
define void @multi_stage_recurse1(i32 %val) #2 {
call void @multi_stage_recurse2(i32 %val)
call void asm sideeffect "", "~{v47}"() #0
@@ -529,9 +448,6 @@ define void @multi_stage_recurse2(i32 %val) #2 {
; GCN: .set .Lusage_multi_stage_recurse.has_dyn_sized_stack, or(0, .Lmulti_stage_recurse1.has_dyn_sized_stack)
; GCN: .set .Lusage_multi_stage_recurse.has_recursion, or(1, .Lmulti_stage_recurse1.has_recursion)
; GCN: .set .Lusage_multi_stage_recurse.has_indirect_call, or(0, .Lmulti_stage_recurse1.has_indirect_call)
-; GCN: TotalNumSgprs: 40
-; GCN: NumVgprs: 48
-; GCN: ScratchSize: 16
define amdgpu_kernel void @usage_multi_stage_recurse(i32 %n) #0 {
call void @multi_stage_recurse1(i32 %n)
ret void
@@ -547,9 +463,6 @@ define amdgpu_kernel void @usage_multi_stage_recurse(i32 %n) #0 {
; GCN: .set .Lmulti_stage_recurse_noattr2.has_dyn_sized_stack, or(0, .Lmulti_stage_recurse_noattr1.has_dyn_sized_stack)
; GCN: .set .Lmulti_stage_recurse_noattr2.has_recursion, or(0, .Lmulti_stage_recurse_noattr1.has_recursion)
; GCN: .set .Lmulti_stage_recurse_noattr2.has_indirect_call, or(0, .Lmulti_stage_recurse_noattr1.has_indirect_call)
-; GCN: TotalNumSgprs: .Lmulti_stage_recurse_noattr2.numbered_sgpr+extrasgprs(.Lmulti_stage_recurse_noattr2.uses_vcc, .Lmulti_stage_recurse_noattr2.uses_flat_scratch, 1)
-; GCN: NumVgprs: max(41, .Lmulti_stage_recurse_noattr1.num_vgpr)
-; GCN: ScratchSize: 16+max(.Lmulti_stage_recurse_noattr1.private_seg_size)
; GCN-LABEL: {{^}}multi_stage_recurse_noattr1:
; GCN: .set .Lmulti_stage_recurse_noattr1.num_vgpr, max(41, 41)
; GCN: .set .Lmulti_stage_recurse_noattr1.num_agpr, max(0, 0)
@@ -560,9 +473,6 @@ define amdgpu_kernel void @usage_multi_stage_recurse(i32 %n) #0 {
; GCN: .set .Lmulti_stage_recurse_noattr1.has_dyn_sized_stack, 0
; GCN: .set .Lmulti_stage_recurse_noattr1.has_recursion, 0
; GCN: .set .Lmulti_stage_recurse_noattr1.has_indirect_call, 0
-; GCN: TotalNumSgprs: 61
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define void @multi_stage_recurse_noattr1(i32 %val) #0 {
call void @multi_stage_recurse_noattr2(i32 %val)
call void asm sideeffect "", "~{s56}"() #0
@@ -584,9 +494,6 @@ define void @multi_stage_recurse_noattr2(i32 %val) #0 {
; GCN: .set .Lusage_multi_stage_recurse_noattrs.has_dyn_sized_stack, or(0, .Lmulti_stage_recurse_noattr1.has_dyn_sized_stack)
; GCN: .set .Lusage_multi_stage_recurse_noattrs.has_recursion, or(0, .Lmulti_stage_recurse_noattr1.has_recursion)
; GCN: .set .Lusage_multi_stage_recurse_noattrs.has_indirect_call, or(0, .Lmulti_stage_recurse_noattr1.has_indirect_call)
-; GCN: TotalNumSgprs: 63
-; GCN: NumVgprs: 41
-; GCN: ScratchSize: 16
define amdgpu_kernel void @usage_multi_stage_recurse_noattrs(i32 %n) #0 {
call void @multi_stage_recurse_noattr1(i32 %n)
ret void
@@ -602,9 +509,6 @@ define amdgpu_kernel void @usage_multi_stage_recurse_noattrs(i32 %n) #0 {
; GCN: .set .Lmulti_call_with_multi_stage_recurse.has_dyn_sized_stack, or(0, .Luse_stack0.has_dyn_sized_stack, .Luse_stack1.has_dyn_sized_stack, .Lmulti_stage_recurse1.has_dyn_sized_stack)
; GCN: .set .Lmulti_call_with_multi_stage_recurse.has_recursion, or(1, .Luse_stack0.has_recursion, .Luse_stack1.has_recursion, .Lmulti_stage_recurse1.has_recursion)
; GCN: .set .Lmulti_call_with_multi_stage_recurse.has_indirect_call, or(0, .Luse_stack0.has_indirect_call, .Luse_stack1.has_indirect_call, .Lmulti_stage_recurse1.has_indirect_call)
-; GCN: TotalNumSgprs: 59
-; GCN: NumVgprs: 48
-; GCN: ScratchSize: 2052
define amdgpu_kernel void @multi_call_with_multi_stage_recurse(i32 %n) #0 {
call void @use_stack0()
call void @use_stack1()
@@ -623,9 +527,6 @@ define amdgpu_kernel void @multi_call_with_multi_stage_recurse(i32 %n) #0 {
; GCN: .set .Lcount_use_sgpr96_external_call.has_dyn_sized_stack, 1
; GCN: .set .Lcount_use_sgpr96_external_call.has_recursion, 0
; GCN: .set .Lcount_use_sgpr96_external_call.has_indirect_call, 1
-; GCN: TotalNumSgprs: .Lcount_use_sgpr96_external_call.numbered_sgpr+6
-; GCN: NumVgprs: .Lcount_use_sgpr96_external_call.num_vgpr
-; GCN: ScratchSize: 0
define amdgpu_kernel void @count_use_sgpr96_external_call() {
entry:
tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1
@@ -644,9 +545,6 @@ entry:
; GCN: .set .Lcount_use_sgpr160_external_call.has_dyn_sized_stack, 1
; GCN: .set .Lcount_use_sgpr160_external_call.has_recursion, 0
; GCN: .set .Lcount_use_sgpr160_external_call.has_indirect_call, 1
-; GCN: TotalNumSgprs: .Lcount_use_sgpr160_external_call.numbered_sgpr+6
-; GCN: NumVgprs: .Lcount_use_sgpr160_external_call.num_vgpr
-; GCN: ScratchSize: 0
define amdgpu_kernel void @count_use_sgpr160_external_call() {
entry:
tail call void asm sideeffect "; sgpr160 $0", "s"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
@@ -665,9 +563,6 @@ entry:
; GCN: .set .Lcount_use_vgpr160_external_call.has_dyn_sized_stack, 1
; GCN: .set .Lcount_use_vgpr160_external_call.has_recursion, 0
; GCN: .set .Lcount_use_vgpr160_external_call.has_indirect_call, 1
-; GCN: TotalNumSgprs: .Lcount_use_vgpr160_external_call.numbered_sgpr+6
-; GCN: NumVgprs: .Lcount_use_vgpr160_external_call.num_vgpr
-; GCN: ScratchSize: 0
define amdgpu_kernel void @count_use_vgpr160_external_call() {
entry:
tail call void asm sideeffect "; vgpr160 $0", "v"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
@@ -685,7 +580,148 @@ define internal void @ctor_func() {
ret void
}
-; Added at the of the .s are the module level maximums
+; GCN: ; use_vcc Function info:
+; GCN: TotalNumSgprs: 36
+; GCN: NumVgprs: 0
+; GCN: ScratchSize: 0
+; GCN: ; indirect_use_vcc Function info:
+; GCN: TotalNumSgprs: 38
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; indirect_2level_use_vcc_kernel Kernel info:
+; GCN: TotalNumSgprs: 40
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; use_flat_scratch Function info:
+; GCN: TotalNumSgprs: 38
+; GCN: NumVgprs: 0
+; GCN: ScratchSize: 0
+; GCN: ; indirect_use_flat_scratch Function info:
+; GCN: TotalNumSgprs: 40
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; indirect_2level_use_flat_scratch_kernel Kernel info:
+; GCN: TotalNumSgprs: 40
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; use_10_vgpr Function info:
+; GCN: TotalNumSgprs: 36
+; GCN: NumVgprs: 10
+; GCN: ScratchSize: 0
+; GCN: ; indirect_use_10_vgpr Function info:
+; GCN: TotalNumSgprs: 38
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; indirect_2_level_use_10_vgpr Kernel info:
+; GCN: TotalNumSgprs: 40
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; use_50_vgpr Function info:
+; GCN: TotalNumSgprs: 36
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 0
+; GCN: ; indirect_use_50_vgpr Function info:
+; GCN: TotalNumSgprs: 38
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 16
+; GCN: ; use_80_sgpr Function info:
+; GCN: TotalNumSgprs: 84
+; GCN: NumVgprs: 0
+; GCN: ScratchSize: 0
+; GCN: ; indirect_use_80_sgpr Function info:
+; GCN: TotalNumSgprs: 84
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; indirect_2_level_use_80_sgpr Kernel info:
+; GCN: TotalNumSgprs: 86
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; use_stack0 Function info:
+; GCN: TotalNumSgprs: 37
+; GCN: NumVgprs: 1
+; GCN: ScratchSize: 2052
+; GCN: ; use_stack1 Function info:
+; GCN: TotalNumSgprs: 37
+; GCN: NumVgprs: 1
+; GCN: ScratchSize: 404
+; GCN: ; indirect_use_stack Function info:
+; GCN: TotalNumSgprs: 38
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 2132
+; GCN: ; indirect_2_level_use_stack Kernel info:
+; GCN: TotalNumSgprs: 40
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 2132
+; GCN: ; multi_call_use_use_stack Kernel info:
+; GCN: TotalNumSgprs: 58
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 2052
+; GCN: ; multi_call_with_external Kernel info:
+; GCN: TotalNumSgprs: 86
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 2052
+; GCN: ; multi_call_with_external_and_duplicates Kernel info:
+; GCN: TotalNumSgprs: 86
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 2052
+; GCN: ; usage_external Kernel info:
+; GCN: TotalNumSgprs: 86
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 0
+; GCN: ; usage_external_recurse Kernel info:
+; GCN: TotalNumSgprs: 86
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 0
+; GCN: ; direct_recursion_use_stack Function info:
+; GCN: TotalNumSgprs: 40
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 2064
+; GCN: ; usage_direct_recursion Kernel info:
+; GCN: TotalNumSgprs: 42
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 2064
+; GCN: ; multi_stage_recurse2 Function info:
+; GCN: TotalNumSgprs: 38
+; GCN: NumVgprs: 48
+; GCN: ScratchSize: 32
+; GCN: ; multi_stage_recurse1 Function info:
+; GCN: TotalNumSgprs: 38
+; GCN: NumVgprs: 48
+; GCN: ScratchSize: 16
+; GCN: ; usage_multi_stage_recurse Kernel info:
+; GCN: TotalNumSgprs: 40
+; GCN: NumVgprs: 48
+; GCN: ScratchSize: 16
+; GCN: ; multi_stage_recurse_noattr2 Function info:
+; GCN: TotalNumSgprs: 61
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 32
+; GCN: ; multi_stage_recurse_noattr1 Function info:
+; GCN: TotalNumSgprs: 61
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; usage_multi_stage_recurse_noattrs Kernel info:
+; GCN: TotalNumSgprs: 63
+; GCN: NumVgprs: 41
+; GCN: ScratchSize: 16
+; GCN: ; multi_call_with_multi_stage_recurse Kernel info:
+; GCN: TotalNumSgprs: 59
+; GCN: NumVgprs: 48
+; GCN: ScratchSize: 2052
+; GCN: ; count_use_sgpr96_external_call Kernel info:
+; GCN: TotalNumSgprs: 86
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 0
+; GCN: ; count_use_sgpr160_external_call Kernel info:
+; GCN: TotalNumSgprs: 86
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 0
+; GCN: ; count_use_vgpr160_external_call Kernel info:
+; GCN: TotalNumSgprs: 86
+; GCN: NumVgprs: 50
+; GCN: ScratchSize: 0
+
+; Added at the end of the .s are the module level maximums
; GCN: .set amdgpu.max_num_vgpr, 50
; GCN: .set amdgpu.max_num_agpr, 0
; GCN: .set amdgpu.max_num_sgpr, 80
diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll b/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
index d42c6bad16873..748b473a7b4a5 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
@@ -47,8 +47,6 @@
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
-; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
-; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
define amdgpu_kernel void @minimal_kernel_inputs() #0 {
%id = call i32 @llvm.amdgcn.workgroup.id.x()
store volatile i32 %id, ptr addrspace(1) poison
@@ -76,8 +74,6 @@ define amdgpu_kernel void @minimal_kernel_inputs() #0 {
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
-; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
-; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
define amdgpu_kernel void @minimal_kernel_inputs_with_stack() #0 {
%alloca = alloca i32, addrspace(5)
%id = call i32 @llvm.amdgcn.workgroup.id.x()
@@ -110,8 +106,6 @@ define amdgpu_kernel void @minimal_kernel_inputs_with_stack() #0 {
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
-; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
-; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 4
define amdgpu_kernel void @queue_ptr() #1 {
%queue.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0
%load = load volatile i8, ptr addrspace(4) %queue.ptr
@@ -161,8 +155,6 @@ define amdgpu_kernel void @queue_ptr() #1 {
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
-; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13
-; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 8
define amdgpu_kernel void @all_inputs() #2 {
%alloca = alloca i32, addrspace(5)
store volatile i32 0, ptr addrspace(5) %alloca
@@ -205,3 +197,15 @@ attributes #1 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-ld
attributes #2 = { "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+; GCN: ; minimal_kernel_inputs Kernel info:
+; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
+; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
+; GCN: ; minimal_kernel_inputs_with_stack Kernel info:
+; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
+; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
+; GCN: ; queue_ptr Kernel info:
+; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
+; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 4
+; GCN: ; all_inputs Kernel info:
+; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13
+; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 8
diff --git a/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir b/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
index c4ef72416588a..de53143eee7cf 100644
--- a/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
+++ b/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
@@ -6,8 +6,6 @@
# test, from 11 down to 7.
# GCN-LABEL: test1:
-# OLD: NumVgprs: 11{{$}}
-# NEW: NumVgprs: 7{{$}}
---
name: test1
tracksRegLiveness: true
@@ -48,8 +46,6 @@ body: |
...
# GCN-LABEL: test2:
-# OLD: NumVgprs: 7{{$}}
-# NEW: NumVgprs: 11{{$}}
---
name: test2
tracksRegLiveness: true
@@ -102,3 +98,10 @@ body: |
bb.3:
S_ENDPGM 0
...
+
+# GCN: ; test1 Function info:
+# OLD: NumVgprs: 11{{$}}
+# NEW: NumVgprs: 7{{$}}
+# GCN: ; test2 Function info:
+# OLD: NumVgprs: 7{{$}}
+# NEW: NumVgprs: 11{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
index 732051972c14a..a64c95cd442e8 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
@@ -3,7 +3,6 @@
; GCN-LABEL: {{^}}test_default_ci:
; GCN: .amdhsa_dx10_clamp 1
; GCN: .amdhsa_ieee_mode 1
-; GCN: FloatMode: 240
define amdgpu_kernel void @test_default_ci(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #0 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -13,7 +12,6 @@ define amdgpu_kernel void @test_default_ci(ptr addrspace(1) %out0, ptr addrspace
; GCN-LABEL: {{^}}test_default_vi:
; GCN: .amdhsa_dx10_clamp 1
; GCN: .amdhsa_ieee_mode 1
-; GCN: FloatMode: 240
define amdgpu_kernel void @test_default_vi(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #1 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -23,7 +21,6 @@ define amdgpu_kernel void @test_default_vi(ptr addrspace(1) %out0, ptr addrspace
; GCN-LABEL: {{^}}test_f64_denormals:
; GCN: .amdhsa_dx10_clamp 1
; GCN: .amdhsa_ieee_mode 1
-; GCN: FloatMode: 192
define amdgpu_kernel void @test_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #2 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -33,7 +30,6 @@ define amdgpu_kernel void @test_f64_denormals(ptr addrspace(1) %out0, ptr addrsp
; GCN-LABEL: {{^}}test_f32_denormals:
; GCN: .amdhsa_dx10_clamp 1
; GCN: .amdhsa_ieee_mode 1
-; GCN: FloatMode: 48
define amdgpu_kernel void @test_f32_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #3 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -43,7 +39,6 @@ define amdgpu_kernel void @test_f32_denormals(ptr addrspace(1) %out0, ptr addrsp
; GCN-LABEL: {{^}}test_f32_f64_denormals:
; GCN: .amdhsa_dx10_clamp 1
; GCN: .amdhsa_ieee_mode 1
-; GCN: FloatMode: 240
define amdgpu_kernel void @test_f32_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #4 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -53,7 +48,6 @@ define amdgpu_kernel void @test_f32_f64_denormals(ptr addrspace(1) %out0, ptr ad
; GCN-LABEL: {{^}}test_no_denormals:
; GCN: .amdhsa_dx10_clamp 1
; GCN: .amdhsa_ieee_mode 1
-; GCN: FloatMode: 0
define amdgpu_kernel void @test_no_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #5 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -63,7 +57,6 @@ define amdgpu_kernel void @test_no_denormals(ptr addrspace(1) %out0, ptr addrspa
; GCN-LABEL: {{^}}test_no_dx10_clamp_vi:
; GCN: .amdhsa_dx10_clamp 0
; GCN: .amdhsa_ieee_mode 1
-; GCN: FloatMode: 240
define amdgpu_kernel void @test_no_dx10_clamp_vi(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #6 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -73,7 +66,6 @@ define amdgpu_kernel void @test_no_dx10_clamp_vi(ptr addrspace(1) %out0, ptr add
; GCN-LABEL: {{^}}test_no_ieee_mode_vi:
; GCN: .amdhsa_dx10_clamp 1
; GCN: .amdhsa_ieee_mode 0
-; GCN: FloatMode: 240
define amdgpu_kernel void @test_no_ieee_mode_vi(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #7 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -83,7 +75,6 @@ define amdgpu_kernel void @test_no_ieee_mode_vi(ptr addrspace(1) %out0, ptr addr
; GCN-LABEL: {{^}}test_no_ieee_mode_no_dx10_clamp_vi:
; GCN: .amdhsa_dx10_clamp 0
; GCN: .amdhsa_ieee_mode 0
-; GCN: FloatMode: 240
define amdgpu_kernel void @test_no_ieee_mode_no_dx10_clamp_vi(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #8 {
store float 0.0, ptr addrspace(1) %out0
store double 0.0, ptr addrspace(1) %out1
@@ -102,3 +93,22 @@ attributes #8 = { nounwind "amdgpu-dx10-clamp"="false" "amdgpu-ieee"="false" "ta
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
+
+; GCN: ; test_default_ci Kernel info:
+; GCN: FloatMode: 240
+; GCN: ; test_default_vi Kernel info:
+; GCN: FloatMode: 240
+; GCN: ; test_f64_denormals Kernel info:
+; GCN: FloatMode: 192
+; GCN: ; test_f32_denormals Kernel info:
+; GCN: FloatMode: 48
+; GCN: ; test_f32_f64_denormals Kernel info:
+; GCN: FloatMode: 240
+; GCN: ; test_no_denormals Kernel info:
+; GCN: FloatMode: 0
+; GCN: ; test_no_dx10_clamp_vi Kernel info:
+; GCN: FloatMode: 240
+; GCN: ; test_no_ieee_mode_vi Kernel info:
+; GCN: FloatMode: 240
+; GCN: ; test_no_ieee_mode_no_dx10_clamp_vi Kernel info:
+; GCN: FloatMode: 240
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-func.ll b/llvm/test/CodeGen/AMDGPU/hsa-func.ll
index b8bdacf450fb3..ce5a6299225d2 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-func.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-func.ll
@@ -33,8 +33,8 @@
; ELF: }
; HSA: .text
-; HSA-CI: .amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
-; HSA-VI: .amdgcn_target "amdgcn-unknown-amdhsa--gfx801"
+; HSA-CI: .amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
+; HSA-VI: .amdgcn_target "amdgcn-unknown-amdhsa--gfx801"
; HSA-NOT: .amdgpu_hsa_kernel simple
; HSA: .globl simple
@@ -49,8 +49,6 @@
; HSA: .Lfunc_end0:
; HSA: .size simple, .Lfunc_end0-simple
-; HSA: ; Function info:
-; HSA-NOT: COMPUTE_PGM_RSRC2
define void @simple(ptr addrspace(4) %ptr.out) {
entry:
%out = load ptr addrspace(1), ptr addrspace(4) %ptr.out
@@ -68,5 +66,8 @@ entry:
ret void
}
+; HSA: ; {{.*}} Function info:
+; HSA-NOT: COMPUTE_PGM_RSRC2
+
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
index 5ec1502899edf..5e5894992107f 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
@@ -2,30 +2,44 @@
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=CHECK,GFX90A %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx801 < %s | FileCheck -check-prefixes=CHECK,GFX801 %s
-; COM: Comments for each kernel
-; CHECK: kernel_32_agprs
+define amdgpu_kernel void @kernel_32_agprs() #0 {
+bb:
+ call void asm sideeffect "", "~{v8}" ()
+ call void asm sideeffect "", "~{a31}" ()
+ ret void
+}
+
+define amdgpu_kernel void @kernel_40_vgprs() #0 {
+bb:
+ call void asm sideeffect "", "~{v39}" ()
+ call void asm sideeffect "", "~{a15}" ()
+ ret void
+}
+
+; CHECK: .section .AMDGPU.csdata
+; CHECK: ; kernel_32_agprs Kernel info:
; GFX908: ; NumVgprs: 9
-; GFX908 ; NumAgprs: 32
-; GFX908 ; TotalNumVgprs: 32
+; GFX908: ; NumAgprs: 32
+; GFX908: ; TotalNumVgprs: 32
; GFX90A: ; NumVgprs: 9
-; GFX90A ; NumAgprs: 32
-; GFX90A ; TotalNumVgprs: 44
+; GFX90A: ; NumAgprs: 32
+; GFX90A: ; TotalNumVgprs: 44
; GFX801: ; NumVgprs: 9
-; CHECK: kernel_40_vgprs
+; CHECK: ; kernel_40_vgprs Kernel info:
; GFX908: ; NumVgprs: 40
-; GFX908 ; NumAgprs: 16
-; GFX908 ; TotalNumVgprs: 40
+; GFX908: ; NumAgprs: 16
+; GFX908: ; TotalNumVgprs: 40
; GFX90A: ; NumVgprs: 40
-; GFX90A ; NumAgprs: 16
-; GFX90A ; TotalNumVgprs: 56
+; GFX90A: ; NumAgprs: 16
+; GFX90A: ; TotalNumVgprs: 56
; GFX801: ; NumVgprs: 40
-; COM: Metadata
+; Metadata
; GFX908: - .agpr_count: 32
; GFX908: .vgpr_count: 32
@@ -33,12 +47,6 @@
; GFX90A: .vgpr_count: 44
; GFX801: .vgpr_count: 9
-define amdgpu_kernel void @kernel_32_agprs() #0 {
-bb:
- call void asm sideeffect "", "~{v8}" ()
- call void asm sideeffect "", "~{a31}" ()
- ret void
-}
; GFX908: - .agpr_count: 16
; GFX908: .vgpr_count: 40
@@ -47,11 +55,5 @@ bb:
; GFX90A: .vgpr_count: 56
; GFX801: .vgpr_count: 40
-define amdgpu_kernel void @kernel_40_vgprs() #0 {
-bb:
- call void asm sideeffect "", "~{v39}" ()
- call void asm sideeffect "", "~{a15}" ()
- ret void
-}
attributes #0 = { nounwind noinline "amdgpu-flat-work-group-size"="1,512" }
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
index 54e7d0e6b08f3..85c97fab37308 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
@@ -70,7 +70,6 @@ define amdgpu_kernel void @v_cmp_asm(ptr addrspace(1) %out, i32 %in) {
}
; CHECK-LABEL: {{^}}code_size_inline_asm:
-; CHECK: codeLenInByte = 12
define amdgpu_kernel void @code_size_inline_asm(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "v_nop_e64", ""()
@@ -79,7 +78,6 @@ entry:
; All inlineasm instructions are assumed to be the maximum size
; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst:
-; CHECK: codeLenInByte = 12
define amdgpu_kernel void @code_size_inline_asm_small_inst(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "v_nop_e32", ""()
@@ -87,7 +85,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst:
-; CHECK: codeLenInByte = 20
define amdgpu_kernel void @code_size_inline_asm_2_inst(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "
@@ -98,7 +95,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst_extra_newline:
-; CHECK: codeLenInByte = 20
define amdgpu_kernel void @code_size_inline_asm_2_inst_extra_newline(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "
@@ -110,7 +106,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_0_inst:
-; CHECK: codeLenInByte = 4
define amdgpu_kernel void @code_size_inline_asm_0_inst(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "", ""()
@@ -118,7 +113,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment:
-; CHECK: codeLenInByte = 4
define amdgpu_kernel void @code_size_inline_asm_1_comment(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "; comment", ""()
@@ -126,7 +120,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_newline_1_comment:
-; CHECK: codeLenInByte = 4
define amdgpu_kernel void @code_size_inline_asm_newline_1_comment(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "
@@ -135,7 +128,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment_newline:
-; CHECK: codeLenInByte = 4
define amdgpu_kernel void @code_size_inline_asm_1_comment_newline(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "; comment
@@ -144,7 +136,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line:
-; CHECK: codeLenInByte = 4
define amdgpu_kernel void @code_size_inline_asm_2_comments_line(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "; first comment ; second comment", ""()
@@ -152,7 +143,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line_nospace:
-; CHECK: codeLenInByte = 4
define amdgpu_kernel void @code_size_inline_asm_2_comments_line_nospace(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "; first comment;second comment", ""()
@@ -160,7 +150,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments0:
-; CHECK: codeLenInByte = 20
define amdgpu_kernel void @code_size_inline_asm_mixed_comments0(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "; comment
@@ -175,7 +164,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments1:
-; CHECK: codeLenInByte = 20
define amdgpu_kernel void @code_size_inline_asm_mixed_comments1(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "v_nop_e64 ; inline comment
@@ -189,7 +177,6 @@ entry:
}
; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments_operands:
-; CHECK: codeLenInByte = 20
define amdgpu_kernel void @code_size_inline_asm_mixed_comments_operands(ptr addrspace(1) %out) {
entry:
call void asm sideeffect "; comment
@@ -363,3 +350,40 @@ define void @mixed_def_sgpr_vgpr_def_asm() {
call void asm sideeffect "; use $0 ", "{s[4:5]}"(i64 %sgpr.add)
ret void
}
+
+; CHECK: ; inline_asm Kernel info:
+; CHECK: codeLenInByte = {{[0-9]+}}
+; CHECK: ; inline_asm_shader Kernel info:
+; CHECK: codeLenInByte = {{[0-9]+}}
+; CHECK: ; branch_on_asm_vgpr Kernel info:
+; CHECK: codeLenInByte = {{[0-9]+}}
+; CHECK: ; branch_on_asm_sgpr Kernel info:
+; CHECK: codeLenInByte = {{[0-9]+}}
+; CHECK: ; v_cmp_asm Kernel info:
+; CHECK: codeLenInByte = {{[0-9]+}}
+; CHECK: ; code_size_inline_asm Kernel info:
+; CHECK: codeLenInByte = 12
+; CHECK: ; code_size_inline_asm_small_inst Kernel info:
+; CHECK: codeLenInByte = 12
+; CHECK: ; code_size_inline_asm_2_inst Kernel info:
+; CHECK: codeLenInByte = 20
+; CHECK: ; code_size_inline_asm_2_inst_extra_newline Kernel info:
+; CHECK: codeLenInByte = 20
+; CHECK: ; code_size_inline_asm_0_inst Kernel info:
+; CHECK: codeLenInByte = 4
+; CHECK: ; code_size_inline_asm_1_comment Kernel info:
+; CHECK: codeLenInByte = 4
+; CHECK: ; code_size_inline_asm_newline_1_comment Kernel info:
+; CHECK: codeLenInByte = 4
+; CHECK: ; code_size_inline_asm_1_comment_newline Kernel info:
+; CHECK: codeLenInByte = 4
+; CHECK: ; code_size_inline_asm_2_comments_line Kernel info:
+; CHECK: codeLenInByte = 4
+; CHECK: ; code_size_inline_asm_2_comments_line_nospace Kernel info:
+; CHECK: codeLenInByte = 4
+; CHECK: ; code_size_inline_asm_mixed_comments0 Kernel info:
+; CHECK: codeLenInByte = 20
+; CHECK: ; code_size_inline_asm_mixed_comments1 Kernel info:
+; CHECK: codeLenInByte = 20
+; CHECK: ; code_size_inline_asm_mixed_comments_operands Kernel info:
+; CHECK: codeLenInByte = 20
diff --git a/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll b/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
index d6e75d0714bb5..b85f48363f759 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
@@ -6,7 +6,6 @@
; GCN-LABEL: store_v3i32:
; GCN: ds_read_b96
; GCN: ds_write_b96
-; GCN: ScratchSize: 0
define amdgpu_kernel void @store_v3i32(ptr addrspace(3) %out, <3 x i32> %a) nounwind {
%val = load <3 x i32>, ptr addrspace(3) %out
%val.1 = add <3 x i32> %a, %val
@@ -19,10 +18,14 @@ define amdgpu_kernel void @store_v3i32(ptr addrspace(3) %out, <3 x i32> %a) noun
; GCN: ds_read_b32
; GCN: ds_write_b32
; GCN: ds_write_b128
-; GCN: ScratchSize: 0
define amdgpu_kernel void @store_v5i32(ptr addrspace(3) %out, <5 x i32> %a) nounwind {
%val = load <5 x i32>, ptr addrspace(3) %out
%val.1 = add <5 x i32> %a, %val
store <5 x i32> %val.1, ptr addrspace(3) %out, align 16
ret void
}
+
+; GCN: ; store_v3i32 Kernel info:
+; GCN: ScratchSize: 0
+; GCN: ; store_v5i32 Kernel info:
+; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll b/llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
index 1509eb16d8627..114382bd7b5ad 100644
--- a/llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
+++ b/llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
@@ -24,9 +24,7 @@
; GCN-LABEL: .amdhsa_kernel large
; GFX11: .amdhsa_inst_pref_size ((instprefsize(.Lfunc_end0-large)<<4)&1008)>>4
-; GFX11: codeLenInByte = {{[0-9]+}}
; GFX12: .amdhsa_inst_pref_size ((instprefsize(.Lfunc_end0-large)<<4)&4080)>>4
-; GFX12: codeLenInByte = {{[0-9]+}}
;; Object: kernel descriptor at 0x00, COMPUTE_PGM_RSRC3 at 0x2C:
;; gfx11 pref=3 (0x30), gfx12 pref=4 (0x40)
; OBJ-GFX11: 0020 {{.*}}30000000
@@ -40,7 +38,6 @@ bb:
; GCN-LABEL: .amdhsa_kernel small
; GFX11: .amdhsa_inst_pref_size ((instprefsize(.Lfunc_end1-small)<<4)&1008)>>4
; GFX12: .amdhsa_inst_pref_size ((instprefsize(.Lfunc_end1-small)<<4)&4080)>>4
-; GCN: codeLenInByte = {{[0-9]+}}
;; Object: kernel descriptor at 0x40, COMPUTE_PGM_RSRC3 at 0x6C:
;; pref=1 (0x10) for both
; OBJ-GFX11: 0060 {{.*}}10000000
@@ -56,7 +53,6 @@ bb:
; GCN-LABEL: .amdhsa_kernel inline_asm
; GFX11: .amdhsa_inst_pref_size ((instprefsize(.Lfunc_end2-inline_asm)<<4)&1008)>>4
; GFX12: .amdhsa_inst_pref_size ((instprefsize(.Lfunc_end2-inline_asm)<<4)&4080)>>4
-; GCN: codeLenInByte = {{[0-9]+}}
;; Object: kernel descriptor at 0x80, COMPUTE_PGM_RSRC3 at 0xAC:
;; pref=9 (0x90) for both
;; (.fill 256, 4, 0 = 1024 bytes + 4 s_endpgm = 1028 -> divideCeil(1028,128) = 9)
@@ -67,3 +63,11 @@ bb:
call void asm sideeffect ".fill 256, 4, 0", ""()
ret void
}
+
+; GCN: ; large Kernel info:
+; GFX11: codeLenInByte = 3{{[0-9][0-9]$}}
+; GFX12: codeLenInByte = 4{{[0-9][0-9]$}}
+; GCN: ; small Kernel info:
+; GCN: codeLenInByte = {{[0-9]$}}
+; GCN: ; inline_asm Kernel info:
+; GCN: codeLenInByte = 24
diff --git a/llvm/test/CodeGen/AMDGPU/ipra.ll b/llvm/test/CodeGen/AMDGPU/ipra.ll
index 1e3678d278695..1ac1c281f899f 100644
--- a/llvm/test/CodeGen/AMDGPU/ipra.ll
+++ b/llvm/test/CodeGen/AMDGPU/ipra.ll
@@ -11,7 +11,6 @@ entry:
}
; GCN-LABEL: {{^}}func:
-; GCN: ; NumVgprs: 8
define hidden void @func() #1 {
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0
ret void
@@ -30,8 +29,6 @@ define hidden void @func() #1 {
; GCN-NOT: writelane
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
-; GCN: ; TotalNumSgprs: 37
-; GCN: ; NumVgprs: 9
define amdgpu_kernel void @kernel_call() #0 {
%vgpr = load volatile i32, ptr addrspace(1) poison
tail call void @func()
@@ -48,8 +45,6 @@ define amdgpu_kernel void @kernel_call() #0 {
; GCN-NOT: readlane
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
-; GCN: ; TotalNumSgprs: 34
-; GCN: ; NumVgprs: 10
define void @func_regular_call() #1 {
%vgpr = load volatile i32, ptr addrspace(1) poison
tail call void @func()
@@ -64,8 +59,6 @@ define void @func_regular_call() #1 {
; GCN-NEXT: s_addc_u32 s17,
; GCN-NEXT: s_setpc_b64 s[16:17]
-; GCN: ; TotalNumSgprs: 32
-; GCN: ; NumVgprs: 8
define void @func_tail_call() #1 {
tail call void @func()
ret void
@@ -77,8 +70,6 @@ define void @func_tail_call() #1 {
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
; GCN: s_setpc_b64
-; GCN: ; TotalNumSgprs: 34
-; GCN: ; NumVgprs: 10
define void @func_call_tail_call() #1 {
%vgpr = load volatile i32, ptr addrspace(1) poison
tail call void @func()
@@ -134,3 +125,20 @@ declare dso_local void @eggs()
attributes #0 = { nounwind }
attributes #1 = { nounwind noinline "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
attributes #2 = { norecurse }
+
+; GCN: ; kernel Kernel info:
+; GCN: ; NumVgprs: 3
+; GCN: ; func Function info:
+; GCN: ; NumVgprs: 8
+; GCN: ; kernel_call Kernel info:
+; GCN: ; TotalNumSgprs: 37
+; GCN: ; NumVgprs: 9
+; GCN: ; func_regular_call Function info:
+; GCN: ; TotalNumSgprs: 34
+; GCN: ; NumVgprs: 10
+; GCN: ; func_tail_call Function info:
+; GCN: ; TotalNumSgprs: 32
+; GCN: ; NumVgprs: 8
+; GCN: ; func_call_tail_call Function info:
+; GCN: ; TotalNumSgprs: 34
+; GCN: ; NumVgprs: 10
diff --git a/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll b/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
index 039ae1b061266..89ad5c9414124 100644
--- a/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
@@ -4,7 +4,6 @@
; alignment of the stack
; CHECK-LABEL: {{^}}no_args:
-; CHECK: ScratchSize: 8{{$}}
define amdgpu_kernel void @no_args() {
%alloca = alloca i8, addrspace(5)
store volatile i8 0, ptr addrspace(5) %alloca
@@ -12,7 +11,6 @@ define amdgpu_kernel void @no_args() {
}
; CHECK-LABEL: {{^}}force_align32:
-; CHECK: ScratchSize: 8{{$}}
define amdgpu_kernel void @force_align32(<8 x i32>) {
%alloca = alloca i8, addrspace(5)
store volatile i8 0, ptr addrspace(5) %alloca
@@ -20,7 +18,6 @@ define amdgpu_kernel void @force_align32(<8 x i32>) {
}
; CHECK-LABEL: {{^}}force_align64:
-; CHECK: ScratchSize: 8{{$}}
define amdgpu_kernel void @force_align64(<16 x i32>) {
%alloca = alloca i8, addrspace(5)
store volatile i8 0, ptr addrspace(5) %alloca
@@ -28,7 +25,6 @@ define amdgpu_kernel void @force_align64(<16 x i32>) {
}
; CHECK-LABEL: {{^}}force_align128:
-; CHECK: ScratchSize: 8{{$}}
define amdgpu_kernel void @force_align128(<32 x i32>) {
%alloca = alloca i8, addrspace(5)
store volatile i8 0, ptr addrspace(5) %alloca
@@ -36,9 +32,19 @@ define amdgpu_kernel void @force_align128(<32 x i32>) {
}
; CHECK-LABEL: {{^}}force_align256:
-; CHECK: ScratchSize: 8{{$}}
define amdgpu_kernel void @force_align256(<64 x i32>) {
%alloca = alloca i8, addrspace(5)
store volatile i8 0, ptr addrspace(5) %alloca
ret void
}
+
+; CHECK: ; no_args Kernel info:
+; CHECK: ScratchSize: 8{{$}}
+; CHECK: ; force_align32 Kernel info:
+; CHECK: ScratchSize: 8{{$}}
+; CHECK: ; force_align64 Kernel info:
+; CHECK: ScratchSize: 8{{$}}
+; CHECK: ; force_align128 Kernel info:
+; CHECK: ScratchSize: 8{{$}}
+; CHECK: ; force_align256 Kernel info:
+; CHECK: ScratchSize: 8{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll b/llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
index 5b6010376be26..1ef0d8248ecf4 100644
--- a/llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
+++ b/llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
@@ -17,7 +17,6 @@
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[4:7], 0 offen
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[4:7], 0 offen
-; ALL: ; ScratchSize: 32772
define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 {
%large = alloca [8192 x i32], align 4, addrspace(5)
%gep = getelementptr [8192 x i32], ptr addrspace(5) %large, i32 0, i32 8191
@@ -43,7 +42,6 @@ define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 {
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[4:7], 0 offen
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[4:7], 0 offen
-; ALL: ; ScratchSize: 32772
define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #0 {
%large = alloca [8192 x i32], align 4, addrspace(5)
%gep = getelementptr [8192 x i32], ptr addrspace(5) %large, i32 0, i32 8191
@@ -55,3 +53,8 @@ define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %
}
attributes #0 = { nounwind }
+
+; ALL: ; large_alloca_pixel_shader Kernel info:
+; ALL: ; ScratchSize: 32772
+; ALL: ; large_alloca_pixel_shader_inreg Kernel info:
+; ALL: ; ScratchSize: 32772
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
index 7e8d5e0f30b9e..e86cfb84dfb53 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
@@ -13,7 +13,6 @@
; GCN-LABEL: test_lds_i8:
; GCN: .amdhsa_group_segment_fixed_size 1
-; GCN: ; LDSByteSize: 1 bytes/workgroup
; MESA: granulated_lds_size = 1
define amdgpu_kernel void @test_lds_i8(i8 %val) {
store i8 %val, ptr addrspace(3) @lds.i8
@@ -22,7 +21,6 @@ define amdgpu_kernel void @test_lds_i8(i8 %val) {
; GCN-LABEL: test_lds_i16:
; GCN: .amdhsa_group_segment_fixed_size 2
-; GCN: ; LDSByteSize: 2 bytes/workgroup
; MESA: granulated_lds_size = 1
define amdgpu_kernel void @test_lds_i16(i16 %val) {
store i16 %val, ptr addrspace(3) @lds.i16
@@ -31,7 +29,6 @@ define amdgpu_kernel void @test_lds_i16(i16 %val) {
; GCN-LABEL: test_lds_i32:
; GCN: .amdhsa_group_segment_fixed_size 4
-; GCN: ; LDSByteSize: 4 bytes/workgroup
; MESA: granulated_lds_size = 1
define amdgpu_kernel void @test_lds_i32(i32 %val) {
store i32 %val, ptr addrspace(3) @lds.i32
@@ -40,7 +37,6 @@ define amdgpu_kernel void @test_lds_i32(i32 %val) {
; GCN-LABEL: test_lds_array_i8:
; GCN: .amdhsa_group_segment_fixed_size 327680
-; GCN: ; LDSByteSize: 327680 bytes/workgroup
; MESA: granulated_lds_size = 160
define amdgpu_kernel void @test_lds_array_i8() {
%gep = getelementptr inbounds [327679 x i8], ptr addrspace(3) @lds.array.i8, i32 0, i32 5
@@ -51,7 +47,6 @@ define amdgpu_kernel void @test_lds_array_i8() {
; GCN-LABEL: test_lds_array_i16:
; GCN: .amdhsa_group_segment_fixed_size 327680
-; GCN: ; LDSByteSize: 327680 bytes/workgroup
; MESA: granulated_lds_size = 160
define amdgpu_kernel void @test_lds_array_i16() {
%gep = getelementptr inbounds [163839 x i16], ptr addrspace(3) @lds.array.i16, i32 0, i32 10
@@ -62,7 +57,6 @@ define amdgpu_kernel void @test_lds_array_i16() {
; GCN-LABEL: test_lds_array_i32:
; GCN: .amdhsa_group_segment_fixed_size 327680
-; GCN: ; LDSByteSize: 327680 bytes/workgroup
; MESA: granulated_lds_size = 160
define amdgpu_kernel void @test_lds_array_i32() {
%gep = getelementptr inbounds [81919 x i32], ptr addrspace(3) @lds.array.i32, i32 0, i32 20
@@ -70,3 +64,16 @@ define amdgpu_kernel void @test_lds_array_i32() {
store i32 %val, ptr addrspace(3) @lds.i32
ret void
}
+
+; GCN: ; test_lds_i8 Kernel info:
+; GCN: ; LDSByteSize: 1 bytes/workgroup
+; GCN: ; test_lds_i16 Kernel info:
+; GCN: ; LDSByteSize: 2 bytes/workgroup
+; GCN: ; test_lds_i32 Kernel info:
+; GCN: ; LDSByteSize: 4 bytes/workgroup
+; GCN: ; test_lds_array_i8 Kernel info:
+; GCN: ; LDSByteSize: 327680 bytes/workgroup
+; GCN: ; test_lds_array_i16 Kernel info:
+; GCN: ; LDSByteSize: 327680 bytes/workgroup
+; GCN: ; test_lds_array_i32 Kernel info:
+; GCN: ; LDSByteSize: 327680 bytes/workgroup
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
index 878d204073b27..f73e95650eeb7 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
@@ -10,7 +10,6 @@
; GCN-LABEL: test_lds_array_size_131076:
; GCN: .amdhsa_group_segment_fixed_size 131076
-; GCN: ; LDSByteSize: 131076 bytes/workgroup
; MESA: granulated_lds_size = 65
define amdgpu_kernel void @test_lds_array_size_131076() {
%gep = getelementptr inbounds [32768 x i32], ptr addrspace(3) @lds.array.size.131076, i32 0, i32 20
@@ -21,7 +20,6 @@ define amdgpu_kernel void @test_lds_array_size_131076() {
; GCN-LABEL: test_lds_array_size_163840:
; GCN: .amdhsa_group_segment_fixed_size 163840
-; GCN: ; LDSByteSize: 163840 bytes/workgroup
; MESA: granulated_lds_size = 80
define amdgpu_kernel void @test_lds_array_size_163840() {
%gep = getelementptr inbounds [40959 x i32], ptr addrspace(3) @lds.array.size.163840 , i32 0, i32 20
@@ -29,3 +27,8 @@ define amdgpu_kernel void @test_lds_array_size_163840() {
store i32 %val, ptr addrspace(3) @lds.i32
ret void
}
+
+; GCN: ; test_lds_array_size_131076 Kernel info:
+; GCN: ; LDSByteSize: 131076 bytes/workgroup
+; GCN: ; test_lds_array_size_163840 Kernel info:
+; GCN: ; LDSByteSize: 163840 bytes/workgroup
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
index f1733d772928e..a7935fecbdf2e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
@@ -23,6 +23,7 @@ define amdgpu_kernel void @v_fract_f64(ptr addrspace(1) %out, double %src) #1 {
; GCN-LABEL: {{^}}v_fract_undef_f32:
; GCN-NOT: v_fract_f32
; GCN-NOT: store_dword
+; GCN: {{^}}.Lfunc_end
define amdgpu_kernel void @v_fract_undef_f32(ptr addrspace(1) %out) #1 {
%fract = call float @llvm.amdgcn.fract.f32(float poison)
store float %fract, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
index abce1f6cd8f84..0d53b6c11b30d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
@@ -26,13 +26,6 @@ declare i32 @llvm.amdgcn.workgroup.id.z() #0
; MESA3D: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s6{{$}}
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
-
-; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
-; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
-; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
-; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
-; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
%id = call i32 @llvm.amdgcn.workgroup.id.x()
store i32 %id, ptr addrspace(1) %out
@@ -53,13 +46,6 @@ define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
-
-; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
-; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
-; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
-; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
-; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
-; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
%id = call i32 @llvm.amdgcn.workgroup.id.y()
store i32 %id, ptr addrspace(1) %out
@@ -88,18 +74,33 @@ define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
+define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
+ %id = call i32 @llvm.amdgcn.workgroup.id.z()
+ store i32 %id, ptr addrspace(1) %out
+ ret void
+}
+; ALL: ; test_workgroup_id_x Kernel info:
+; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
+; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
+; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
+; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
+; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
+; ALL: ; test_workgroup_id_y Kernel info:
+; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
+; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
+; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
+; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
+; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
+; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
+; ALL: ; test_workgroup_id_z Kernel info:
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
-define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
- %id = call i32 @llvm.amdgcn.workgroup.id.z()
- store i32 %id, ptr addrspace(1) %out
- ret void
-}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
index 618a4c294cae5..9410e3af8496e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
@@ -24,7 +24,6 @@ define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_16(i32 %val) #0 {
ret ptr addrspace(5) %stack.base
}
-; CHECK: ScratchSize: 8
define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_32(i32 %val) #1 {
; CHECK-LABEL: sponentry_cs_dvgpr_32:
@@ -44,7 +43,6 @@ define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_32(i32 %val) #1 {
ret ptr addrspace(5) %stack.base
}
-; CHECK: ScratchSize: 8
; If we're not in dynamic VGPR mode, then sponentry can just return 0.
@@ -61,7 +59,6 @@ define amdgpu_cs ptr addrspace(5) @sponentry_cs_no_dvgpr(i32 %val) #2 {
ret ptr addrspace(5) %stack.base
}
-; CHECK: ScratchSize: 8
define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_control_flow(i32 %val, ptr addrspace(5) %ptr) #0 {
; CHECK-LABEL: sponentry_cs_dvgpr_control_flow:
@@ -100,7 +97,6 @@ if.end:
ret ptr addrspace(5) %ret
}
-; CHECK: ScratchSize: 8
declare amdgpu_gfx i32 @callee()
@@ -149,7 +145,6 @@ define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_calls(i32 %val) #0 {
ret ptr addrspace(5) %stack.base
}
-; CHECK: ScratchSize: 16
define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_realign(i32 %val) #0 {
; CHECK-LABEL: sponentry_cs_dvgpr_realign:
@@ -170,7 +165,6 @@ define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_realign(i32 %val) #0 {
ret ptr addrspace(5) %stack.base
}
-; CHECK: ScratchSize: 128
define amdgpu_gfx ptr addrspace(5) @sponentry_gfx(i32 %val, ptr addrspace(5) %ptr) #0 {
; DAGISEL-LABEL: sponentry_gfx:
@@ -231,7 +225,6 @@ if.end:
}
; FIXME: Optimize away the 4 bytes for the sponentry frame index.
-; CHECK: ScratchSize: 12
define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_dvgpr_realign(i32 %val) #0 {
; CHECK-LABEL: sponentry_gfx_dvgpr_realign:
@@ -266,7 +259,6 @@ define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_dvgpr_realign(i32 %val) #0 {
}
; FIXME: Optimize away the sponentry fixed object.
-; CHECK: ScratchSize: 384
define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_stack_args(<32 x i32> %fill.vgprs, i32 %val, ptr addrspace(5) %ptr) #0 {
; DAGISEL-LABEL: sponentry_gfx_stack_args:
@@ -307,7 +299,6 @@ define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_stack_args(<32 x i32> %fill.vg
ret ptr addrspace(5) %stack.base
}
-; CHECK: ScratchSize: 12
define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_dyn_alloc(i32 %val) #0 {
; DAGISEL-LABEL: sponentry_gfx_dyn_alloc:
@@ -424,7 +415,6 @@ define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_dyn_alloc(i32 %val) #0 {
ret ptr addrspace(5) %stack.base
}
-; CHECK: ScratchSize: 16
define amdgpu_cs_chain void @sponentry_cs_chain(i32 %val, ptr addrspace(5) %ptr) #0 {
; DAGISEL-LABEL: sponentry_cs_chain:
@@ -490,7 +480,6 @@ if.end:
}
; FIXME: Optimize away the 4 bytes for the sponentry frame index.
-; CHECK: ScratchSize: 12
define amdgpu_cs_chain void @sponentry_cs_chain_dvgpr_realign(i32 %val) #0 {
; CHECK-LABEL: sponentry_cs_chain_dvgpr_realign:
@@ -522,7 +511,6 @@ define amdgpu_cs_chain void @sponentry_cs_chain_dvgpr_realign(i32 %val) #0 {
}
; FIXME: Optimize away the sponentry fixed object.
-; CHECK: ScratchSize: 384
define amdgpu_cs_chain void @sponentry_cs_chain_dyn_alloc(i32 %val) #0 {
; DAGISEL-LABEL: sponentry_cs_chain_dyn_alloc:
@@ -611,8 +599,34 @@ define amdgpu_cs_chain void @sponentry_cs_chain_dyn_alloc(i32 %val) #0 {
ret void
}
-; CHECK: ScratchSize: 16
attributes #0 = { nounwind "amdgpu-dynamic-vgpr-block-size"="16" }
attributes #1 = { nounwind "amdgpu-dynamic-vgpr-block-size"="32" }
attributes #2 = { nounwind "amdgpu-dynamic-vgpr-block-size"="0" }
+
+; CHECK: ; sponentry_cs_dvgpr_16 Kernel info:
+; CHECK: ScratchSize: 8
+; CHECK: ; sponentry_cs_dvgpr_32 Kernel info:
+; CHECK: ScratchSize: 8
+; CHECK: ; sponentry_cs_no_dvgpr Kernel info:
+; CHECK: ScratchSize: 8
+; CHECK: ; sponentry_cs_dvgpr_control_flow Kernel info:
+; CHECK: ScratchSize: 8
+; CHECK: ; sponentry_cs_dvgpr_calls Kernel info:
+; CHECK: ScratchSize: 16
+; CHECK: ; sponentry_cs_dvgpr_realign Kernel info:
+; CHECK: ScratchSize: 128
+; CHECK: ; sponentry_gfx Function info:
+; CHECK: ScratchSize: 12
+; CHECK: ; sponentry_gfx_dvgpr_realign Function info:
+; CHECK: ScratchSize: 384
+; CHECK: ; sponentry_gfx_stack_args Function info:
+; CHECK: ScratchSize: 12
+; CHECK: ; sponentry_gfx_dyn_alloc Function info:
+; CHECK: ScratchSize: 16
+; CHECK: ; sponentry_cs_chain Function info:
+; CHECK: ScratchSize: 12
+; CHECK: ; sponentry_cs_chain_dvgpr_realign Function info:
+; CHECK: ScratchSize: 384
+; CHECK: ; sponentry_cs_chain_dyn_alloc Function info:
+; CHECK: ScratchSize: 16
diff --git a/llvm/test/CodeGen/AMDGPU/merge-stores.ll b/llvm/test/CodeGen/AMDGPU/merge-stores.ll
index 7457509ffe193..798bb47a8d243 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-stores.ll
+++ b/llvm/test/CodeGen/AMDGPU/merge-stores.ll
@@ -1145,7 +1145,6 @@ define amdgpu_kernel void @copy_v3i32_align4(ptr addrspace(1) noalias %out, ptr
store <3 x i32> %vec, ptr addrspace(1) %out
ret void
}
-; GCN: ScratchSize: 0{{$}}
define amdgpu_kernel void @copy_v3i64_align4(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
; GCN-LABEL: copy_v3i64_align4:
@@ -1171,7 +1170,6 @@ define amdgpu_kernel void @copy_v3i64_align4(ptr addrspace(1) noalias %out, ptr
store <3 x i64> %vec, ptr addrspace(1) %out
ret void
}
-; GCN: ScratchSize: 0{{$}}
define amdgpu_kernel void @copy_v3f32_align4(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
; SI-LABEL: copy_v3f32_align4:
@@ -1221,7 +1219,6 @@ define amdgpu_kernel void @copy_v3f32_align4(ptr addrspace(1) noalias %out, ptr
store <3 x float> %fadd, ptr addrspace(1) %out
ret void
}
-; GCN: ScratchSize: 0{{$}}
define amdgpu_kernel void @copy_v3f64_align4(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
; GCN-LABEL: copy_v3f64_align4:
@@ -1251,9 +1248,17 @@ define amdgpu_kernel void @copy_v3f64_align4(ptr addrspace(1) noalias %out, ptr
store <3 x double> %fadd, ptr addrspace(1) %out
ret void
}
-; GCN: ScratchSize: 0{{$}}
declare void @llvm.amdgcn.s.barrier() #1
attributes #0 = { nounwind }
attributes #1 = { convergent nounwind }
+
+; GCN: ; merge_global_store_2_constants_i8 Kernel info:
+; GCN: ScratchSize: 0{{$}}
+; GCN: ; merge_global_store_2_constants_i8_natural_align Kernel info:
+; GCN: ScratchSize: 0{{$}}
+; GCN: ; merge_global_store_2_constants_i16 Kernel info:
+; GCN: ScratchSize: 0{{$}}
+; GCN: ; merge_global_store_2_constants_0_i16 Kernel info:
+; GCN: ScratchSize: 0{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
index ea9361acb175f..2e02dae1c16c9 100644
--- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
+++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
@@ -22,7 +22,6 @@ define amdgpu_kernel void @nocall_ideal() {
store i32 0, ptr addrspace(3) @used_by_kernel
ret void
}
-; CHECK: ; LDSByteSize: 4 bytes
define void @nonkernel() {
; GFX9-LABEL: nonkernel:
@@ -214,7 +213,6 @@ define amdgpu_kernel void @withcall() {
call void @nonkernel()
ret void
}
-; CHECK: ; LDSByteSize: 16 bytes
; Previous lowering was less efficient here than necessary as the i32 used
; by the kernel is also used by an unrelated non-kernel function. Codegen
@@ -228,5 +226,10 @@ define amdgpu_kernel void @nocall_false_sharing() {
store i32 0, ptr addrspace(3) @used_by_both
ret void
}
-; CHECK: ; LDSByteSize: 4 bytes
+; CHECK: ; nocall_ideal Kernel info:
+; CHECK: ; LDSByteSize: 4 bytes
+; CHECK: ; withcall Kernel info:
+; CHECK: ; LDSByteSize: 16 bytes
+; CHECK: ; nocall_false_sharing Kernel info:
+; CHECK: ; LDSByteSize: 4 bytes
diff --git a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
index 154a75a674890..4a8fe34a169c8 100644
--- a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
+++ b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
@@ -107,13 +107,10 @@ bb.2:
ret void
}
; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 4112
-; DEFAULTSIZE: ; ScratchSize: 4112
; DEFAULTSIZE-V5: .amdhsa_private_segment_fixed_size 16
; DEFAULTSIZE-V5: .amdhsa_uses_dynamic_stack 1
-; DEFAULTSIZE-V5: ; ScratchSize: 16
; ASSUME1024: .amdhsa_private_segment_fixed_size 1040
-; ASSUME1024: ; ScratchSize: 1040
define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) #2 {
; MUBUF-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
@@ -200,13 +197,10 @@ bb.1:
}
; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 4160
-; DEFAULTSIZE: ; ScratchSize: 4160
; DEFAULTSIZE-V5: .amdhsa_private_segment_fixed_size 64
; DEFAULTSIZE-V5: .amdhsa_uses_dynamic_stack 1
-; DEFAULTSIZE-V5: ; ScratchSize: 64
; ASSUME1024: .amdhsa_private_segment_fixed_size 1088
-; ASSUME1024: ; ScratchSize: 1088
define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) #2 {
@@ -410,3 +404,12 @@ attributes #2 = { nounwind }
; ASSUME1024: {{.*}}
; DEFAULTSIZE: {{.*}}
; DEFAULTSIZE-V5: {{.*}}
+
+; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4 Kernel info:
+; DEFAULTSIZE: ; ScratchSize: 4112
+; DEFAULTSIZE-V5: ; ScratchSize: 16
+; ASSUME1024: ; ScratchSize: 1040
+; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64 Kernel info:
+; DEFAULTSIZE: ; ScratchSize: 4160
+; DEFAULTSIZE-V5: ; ScratchSize: 64
+; ASSUME1024: ; ScratchSize: 1088
diff --git a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
index fcfeb099c698f..dd125a1327662 100644
--- a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
+++ b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
@@ -24,17 +24,265 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 < %s | FileCheck --check-prefixes=GCN,GFX1100,GFX1100W32 %s
; GCN-LABEL: {{^}}max_occupancy:
+define amdgpu_kernel void @max_occupancy() #10 {
+ ret void
+}
+
+; GCN-LABEL: {{^}}limited_occupancy_3:
+define amdgpu_kernel void @limited_occupancy_3() #0 {
+ ret void
+}
+
+; GCN-LABEL: {{^}}limited_occupancy_18:
+define amdgpu_kernel void @limited_occupancy_18() #1 {
+ ret void
+}
+
+; GCN-LABEL: {{^}}limited_occupancy_19:
+define amdgpu_kernel void @limited_occupancy_19() #2 {
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_24_vgprs:
+define amdgpu_kernel void @used_24_vgprs() #10 {
+ call void asm sideeffect "", "~{v23}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_28_vgprs:
+define amdgpu_kernel void @used_28_vgprs() #10 {
+ call void asm sideeffect "", "~{v27}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_32_vgprs:
+define amdgpu_kernel void @used_32_vgprs() #10 {
+ call void asm sideeffect "", "~{v31}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_36_vgprs:
+define amdgpu_kernel void @used_36_vgprs() #10 {
+ call void asm sideeffect "", "~{v35}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_40_vgprs:
+define amdgpu_kernel void @used_40_vgprs() #10 {
+ call void asm sideeffect "", "~{v39}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_44_vgprs:
+define amdgpu_kernel void @used_44_vgprs() #10 {
+ call void asm sideeffect "", "~{v43}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_48_vgprs:
+define amdgpu_kernel void @used_48_vgprs() #10 {
+ call void asm sideeffect "", "~{v47}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_56_vgprs:
+define amdgpu_kernel void @used_56_vgprs() #10 {
+ call void asm sideeffect "", "~{v55}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_64_vgprs:
+define amdgpu_kernel void @used_64_vgprs() #10 {
+ call void asm sideeffect "", "~{v63}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_72_vgprs:
+define amdgpu_kernel void @used_72_vgprs() #10 {
+ call void asm sideeffect "", "~{v71}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_80_vgprs:
+define amdgpu_kernel void @used_80_vgprs() #10 {
+ call void asm sideeffect "", "~{v79}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_84_vgprs:
+define amdgpu_kernel void @used_84_vgprs() #10 {
+ call void asm sideeffect "", "~{v83}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_88_vgprs:
+define amdgpu_kernel void @used_88_vgprs() #10 {
+ call void asm sideeffect "", "~{v87}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_96_vgprs:
+define amdgpu_kernel void @used_96_vgprs() #10 {
+ call void asm sideeffect "", "~{v95}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_100_vgprs:
+define amdgpu_kernel void @used_100_vgprs() #10 {
+ call void asm sideeffect "", "~{v99}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_112_vgprs:
+define amdgpu_kernel void @used_112_vgprs() #10 {
+ call void asm sideeffect "", "~{v111}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_128_vgprs:
+define amdgpu_kernel void @used_128_vgprs() #10 {
+ call void asm sideeffect "", "~{v127}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_144_vgprs:
+define amdgpu_kernel void @used_144_vgprs() #10 {
+ call void asm sideeffect "", "~{v143}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_168_vgprs:
+define amdgpu_kernel void @used_168_vgprs() #10 {
+ call void asm sideeffect "", "~{v167}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_200_vgprs:
+define amdgpu_kernel void @used_200_vgprs() #10 {
+ call void asm sideeffect "", "~{v199}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_256_vgprs:
+define amdgpu_kernel void @used_256_vgprs() #10 {
+ call void asm sideeffect "", "~{v255}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_80_sgprs:
+define amdgpu_kernel void @used_80_sgprs() #10 {
+ call void asm sideeffect "", "~{s79}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_88_sgprs:
+define amdgpu_kernel void @used_88_sgprs() #10 {
+ call void asm sideeffect "", "~{s87}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_100_sgprs:
+define amdgpu_kernel void @used_100_sgprs() #10 {
+ call void asm sideeffect "", "~{s99}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_101_sgprs:
+define amdgpu_kernel void @used_101_sgprs() #10 {
+ call void asm sideeffect "", "~{s100}" ()
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_6552:
+ at lds6552 = internal addrspace(3) global [6552 x i8] poison, align 4
+define amdgpu_kernel void @used_lds_6552() {
+ store volatile i8 1, ptr addrspace(3) @lds6552
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_6556:
+ at lds6556 = internal addrspace(3) global [6556 x i8] poison, align 4
+define amdgpu_kernel void @used_lds_6556() {
+ store volatile i8 1, ptr addrspace(3) @lds6556
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_13112:
+ at lds13112 = internal addrspace(3) global [13112 x i8] poison, align 4
+define amdgpu_kernel void @used_lds_13112() {
+ store volatile i8 1, ptr addrspace(3) @lds13112
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_8252_max_group_size_64:
+ at lds8252 = internal addrspace(3) global [8252 x i8] poison, align 4
+define amdgpu_kernel void @used_lds_8252_max_group_size_64() #3 {
+ store volatile i8 1, ptr addrspace(3) @lds8252
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_8252_max_group_size_96:
+define amdgpu_kernel void @used_lds_8252_max_group_size_96() #4 {
+ store volatile i8 1, ptr addrspace(3) @lds8252
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_8252_max_group_size_128:
+define amdgpu_kernel void @used_lds_8252_max_group_size_128() #5 {
+ store volatile i8 1, ptr addrspace(3) @lds8252
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_8252_max_group_size_192:
+define amdgpu_kernel void @used_lds_8252_max_group_size_192() #6 {
+ store volatile i8 1, ptr addrspace(3) @lds8252
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_8252_max_group_size_256:
+define amdgpu_kernel void @used_lds_8252_max_group_size_256() #7 {
+ store volatile i8 1, ptr addrspace(3) @lds8252
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_8252_max_group_size_512:
+define amdgpu_kernel void @used_lds_8252_max_group_size_512() #8 {
+ store volatile i8 1, ptr addrspace(3) @lds8252
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_8252_max_group_size_1024:
+define amdgpu_kernel void @used_lds_8252_max_group_size_1024() #9 {
+ store volatile i8 1, ptr addrspace(3) @lds8252
+ ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_8252_max_group_size_32:
+define amdgpu_kernel void @used_lds_8252_max_group_size_32() #10 {
+ store volatile i8 1, ptr addrspace(3) @lds8252
+ ret void
+}
+
+attributes #0 = { "amdgpu-waves-per-eu"="2,3" "amdgpu-flat-work-group-size"="1,64" }
+attributes #1 = { "amdgpu-waves-per-eu"="18,18" "amdgpu-flat-work-group-size"="1,32" }
+attributes #2 = { "amdgpu-waves-per-eu"="19,19" "amdgpu-flat-work-group-size"="1,32" }
+attributes #3 = { "amdgpu-flat-work-group-size"="1,64" }
+attributes #4 = { "amdgpu-flat-work-group-size"="1,96" }
+attributes #5 = { "amdgpu-flat-work-group-size"="1,128" }
+attributes #6 = { "amdgpu-flat-work-group-size"="1,192" }
+attributes #7 = { "amdgpu-flat-work-group-size"="1,256" }
+attributes #8 = { "amdgpu-flat-work-group-size"="1,512" }
+attributes #9 = { "amdgpu-flat-work-group-size"="1,1024" }
+attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
+
+; GCN: ; max_occupancy Kernel info:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @max_occupancy() #10 {
- ret void
-}
-
-; GCN-LABEL: {{^}}limited_occupancy_3:
+; GCN: ; limited_occupancy_3 Kernel info:
; GFX9: ; Occupancy: 3
; GFX950: ; Occupancy: 3
; GFX10W64: ; Occupancy: 3
@@ -42,45 +290,28 @@ define amdgpu_kernel void @max_occupancy() #10 {
; GFX1100W64: ; Occupancy: 3
; GFX1100W32: ; Occupancy: 5
; GFX1250: ; Occupancy: 3
-define amdgpu_kernel void @limited_occupancy_3() #0 {
- ret void
-}
-
-; GCN-LABEL: {{^}}limited_occupancy_18:
+; GCN: ; limited_occupancy_18 Kernel info:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 18
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @limited_occupancy_18() #1 {
- ret void
-}
-
-; GCN-LABEL: {{^}}limited_occupancy_19:
+; GCN: ; limited_occupancy_19 Kernel info:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @limited_occupancy_19() #2 {
- ret void
-}
-
-; GCN-LABEL: {{^}}used_24_vgprs:
+; GCN: ; used_24_vgprs Kernel info:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_24_vgprs() #10 {
- call void asm sideeffect "", "~{v23}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_28_vgprs:
+; GCN: ; used_28_vgprs Kernel info:
; GFX9: ; Occupancy: 9
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 18
@@ -88,12 +319,7 @@ define amdgpu_kernel void @used_24_vgprs() #10 {
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_28_vgprs() #10 {
- call void asm sideeffect "", "~{v27}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_32_vgprs:
+; GCN: ; used_32_vgprs Kernel info:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 16
@@ -101,12 +327,7 @@ define amdgpu_kernel void @used_28_vgprs() #10 {
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_32_vgprs() #10 {
- call void asm sideeffect "", "~{v31}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_36_vgprs:
+; GCN: ; used_36_vgprs Kernel info:
; GFX9: ; Occupancy: 7
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 14
@@ -115,12 +336,7 @@ define amdgpu_kernel void @used_32_vgprs() #10 {
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_36_vgprs() #10 {
- call void asm sideeffect "", "~{v35}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_40_vgprs:
+; GCN: ; used_40_vgprs Kernel info:
; GFX9: ; Occupancy: 6
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 12
@@ -128,12 +344,7 @@ define amdgpu_kernel void @used_36_vgprs() #10 {
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_40_vgprs() #10 {
- call void asm sideeffect "", "~{v39}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_44_vgprs:
+; GCN: ; used_44_vgprs Kernel info:
; GFX9: ; Occupancy: 5
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 11
@@ -142,12 +353,7 @@ define amdgpu_kernel void @used_40_vgprs() #10 {
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_44_vgprs() #10 {
- call void asm sideeffect "", "~{v43}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_48_vgprs:
+; GCN: ; used_48_vgprs Kernel info:
; GFX9: ; Occupancy: 5
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 10
@@ -155,12 +361,7 @@ define amdgpu_kernel void @used_44_vgprs() #10 {
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_48_vgprs() #10 {
- call void asm sideeffect "", "~{v47}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_56_vgprs:
+; GCN: ; used_56_vgprs Kernel info:
; GFX9: ; Occupancy: 4
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 9
@@ -169,12 +370,7 @@ define amdgpu_kernel void @used_48_vgprs() #10 {
; GFX1100W64: ; Occupancy: 12
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_56_vgprs() #10 {
- call void asm sideeffect "", "~{v55}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_64_vgprs:
+; GCN: ; used_64_vgprs Kernel info:
; GFX9: ; Occupancy: 4
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 8
@@ -182,12 +378,7 @@ define amdgpu_kernel void @used_56_vgprs() #10 {
; GFX1100W64: ; Occupancy: 10
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_64_vgprs() #10 {
- call void asm sideeffect "", "~{v63}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_72_vgprs:
+; GCN: ; used_72_vgprs Kernel info:
; GFX9: ; Occupancy: 3
; GFX950: ; Occupancy: 7
; GFX10W64: ; Occupancy: 7
@@ -196,12 +387,7 @@ define amdgpu_kernel void @used_64_vgprs() #10 {
; GFX1100W64: ; Occupancy: 10
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 12
-define amdgpu_kernel void @used_72_vgprs() #10 {
- call void asm sideeffect "", "~{v71}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_80_vgprs:
+; GCN: ; used_80_vgprs Kernel info:
; GFX9: ; Occupancy: 3
; GFX950: ; Occupancy: 6
; GFX10W64: ; Occupancy: 6
@@ -209,12 +395,7 @@ define amdgpu_kernel void @used_72_vgprs() #10 {
; GFX1100W64: ; Occupancy: 9
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 12
-define amdgpu_kernel void @used_80_vgprs() #10 {
- call void asm sideeffect "", "~{v79}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_84_vgprs:
+; GCN: ; used_84_vgprs Kernel info:
; GFX9: ; Occupancy: 3
; GFX950: ; Occupancy: 5
; GFX1010W64: ; Occupancy: 6
@@ -224,12 +405,7 @@ define amdgpu_kernel void @used_80_vgprs() #10 {
; GFX1100W64: ; Occupancy: 9
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 10
-define amdgpu_kernel void @used_84_vgprs() #10 {
- call void asm sideeffect "", "~{v83}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_88_vgprs:
+; GCN: ; used_88_vgprs Kernel info:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 5
; GFX10W64: ; Occupancy: 5
@@ -238,12 +414,7 @@ define amdgpu_kernel void @used_84_vgprs() #10 {
; GFX1100W64: ; Occupancy: 8
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 10
-define amdgpu_kernel void @used_88_vgprs() #10 {
- call void asm sideeffect "", "~{v87}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_96_vgprs:
+; GCN: ; used_96_vgprs Kernel info:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 5
; GFX10W64: ; Occupancy: 5
@@ -251,12 +422,7 @@ define amdgpu_kernel void @used_88_vgprs() #10 {
; GFX1100W64: ; Occupancy: 8
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 10
-define amdgpu_kernel void @used_96_vgprs() #10 {
- call void asm sideeffect "", "~{v95}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_100_vgprs:
+; GCN: ; used_100_vgprs Kernel info:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 4
; GFX1010W64: ; Occupancy: 5
@@ -265,12 +431,7 @@ define amdgpu_kernel void @used_96_vgprs() #10 {
; GFX1100W64: ; Occupancy: 7
; GFX1100W32: ; Occupancy: 12
; GFX1250: ; Occupancy: 9
-define amdgpu_kernel void @used_100_vgprs() #10 {
- call void asm sideeffect "", "~{v99}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_112_vgprs:
+; GCN: ; used_112_vgprs Kernel info:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 4
; GFX10W64: ; Occupancy: 4
@@ -278,12 +439,7 @@ define amdgpu_kernel void @used_100_vgprs() #10 {
; GFX1100W64: ; Occupancy: 6
; GFX1100W32: ; Occupancy: 12
; GFX1250: ; Occupancy: 9
-define amdgpu_kernel void @used_112_vgprs() #10 {
- call void asm sideeffect "", "~{v111}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_128_vgprs:
+; GCN: ; used_128_vgprs Kernel info:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 4
; GFX10W64: ; Occupancy: 4
@@ -291,12 +447,7 @@ define amdgpu_kernel void @used_112_vgprs() #10 {
; GFX1100W64: ; Occupancy: 5
; GFX1100W32: ; Occupancy: 10
; GFX1250: ; Occupancy: 8
-define amdgpu_kernel void @used_128_vgprs() #10 {
- call void asm sideeffect "", "~{v127}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_144_vgprs:
+; GCN: ; used_144_vgprs Kernel info:
; GFX9: ; Occupancy: 1
; GFX950: ; Occupancy: 3
; GFX10W64: ; Occupancy: 3
@@ -304,12 +455,7 @@ define amdgpu_kernel void @used_128_vgprs() #10 {
; GFX1100W64: ; Occupancy: 5
; GFX1100W32: ; Occupancy: 10
; GFX1250: ; Occupancy: 7
-define amdgpu_kernel void @used_144_vgprs() #10 {
- call void asm sideeffect "", "~{v143}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_168_vgprs:
+; GCN: ; used_168_vgprs Kernel info:
; GFX9: ; Occupancy: 1
; GFX950: ; Occupancy: 3
; GFX10W64: ; Occupancy: 3
@@ -318,12 +464,7 @@ define amdgpu_kernel void @used_144_vgprs() #10 {
; GFX1100W64: ; Occupancy: 4
; GFX1100W32: ; Occupancy: 9
; GFX1250: ; Occupancy: 5
-define amdgpu_kernel void @used_168_vgprs() #10 {
- call void asm sideeffect "", "~{v167}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_200_vgprs:
+; GCN: ; used_200_vgprs Kernel info:
; GFX9: ; Occupancy: 1
; GFX950: ; Occupancy: 2
; GFX10W64: ; Occupancy: 2
@@ -332,12 +473,7 @@ define amdgpu_kernel void @used_168_vgprs() #10 {
; GFX1100W64: ; Occupancy: 3
; GFX1100W32: ; Occupancy: 7
; GFX1250: ; Occupancy: 4
-define amdgpu_kernel void @used_200_vgprs() #10 {
- call void asm sideeffect "", "~{v199}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_256_vgprs:
+; GCN: ; used_256_vgprs Kernel info:
; GFX9: ; Occupancy: 1
; GFX950: ; Occupancy: 2
; GFX10W64: ; Occupancy: 2
@@ -345,60 +481,35 @@ define amdgpu_kernel void @used_200_vgprs() #10 {
; GFX1100W64: ; Occupancy: 2
; GFX1100W32: ; Occupancy: 5
; GFX1250: ; Occupancy: 4
-define amdgpu_kernel void @used_256_vgprs() #10 {
- call void asm sideeffect "", "~{v255}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_80_sgprs:
+; GCN: ; used_80_sgprs Kernel info:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_80_sgprs() #10 {
- call void asm sideeffect "", "~{s79}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_88_sgprs:
+; GCN: ; used_88_sgprs Kernel info:
; GFX9: ; Occupancy: 9
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_88_sgprs() #10 {
- call void asm sideeffect "", "~{s87}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_100_sgprs:
+; GCN: ; used_100_sgprs Kernel info:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 7
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_100_sgprs() #10 {
- call void asm sideeffect "", "~{s99}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_101_sgprs:
+; GCN: ; used_101_sgprs Kernel info:
; GFX9: ; Occupancy: 7
; GFX950: ; Occupancy: 7
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-define amdgpu_kernel void @used_101_sgprs() #10 {
- call void asm sideeffect "", "~{s100}" ()
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_6552:
+; GCN: ; used_lds_6552 Kernel info:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 20
@@ -406,13 +517,7 @@ define amdgpu_kernel void @used_101_sgprs() #10 {
; GFX10W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
- at lds6552 = internal addrspace(3) global [6552 x i8] poison, align 4
-define amdgpu_kernel void @used_lds_6552() {
- store volatile i8 1, ptr addrspace(3) @lds6552
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_6556:
+; GCN: ; used_lds_6556 Kernel info:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 20
@@ -420,13 +525,7 @@ define amdgpu_kernel void @used_lds_6552() {
; GFX10W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
- at lds6556 = internal addrspace(3) global [6556 x i8] poison, align 4
-define amdgpu_kernel void @used_lds_6556() {
- store volatile i8 1, ptr addrspace(3) @lds6556
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_13112:
+; GCN: ; used_lds_13112 Kernel info:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 20
@@ -434,13 +533,7 @@ define amdgpu_kernel void @used_lds_6556() {
; GFX10W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
- at lds13112 = internal addrspace(3) global [13112 x i8] poison, align 4
-define amdgpu_kernel void @used_lds_13112() {
- store volatile i8 1, ptr addrspace(3) @lds13112
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_8252_max_group_size_64:
+; GCN: ; used_lds_8252_max_group_size_64 Kernel info:
; GFX9: ; Occupancy: 2{{$}}
; GFX950: ; Occupancy: 5{{$}}
; GFX10W64: ; Occupancy: 4{{$}}
@@ -448,13 +541,7 @@ define amdgpu_kernel void @used_lds_13112() {
; GFX1100W64: ; Occupancy: 4{{$}}
; GFX1100W32: ; Occupancy: 8{{$}}
; GFX1250: ; Occupancy: 10{{$}}
- at lds8252 = internal addrspace(3) global [8252 x i8] poison, align 4
-define amdgpu_kernel void @used_lds_8252_max_group_size_64() #3 {
- store volatile i8 1, ptr addrspace(3) @lds8252
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_8252_max_group_size_96:
+; GCN: ; used_lds_8252_max_group_size_96 Kernel info:
; GFX9: ; Occupancy: 4{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX10W64: ; Occupancy: 8{{$}}
@@ -462,12 +549,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_64() #3 {
; GFX1100W64: ; Occupancy: 8{{$}}
; GFX1100W32: ; Occupancy: 12{{$}}
; GFX1250: ; Occupancy: 12{{$}}
-define amdgpu_kernel void @used_lds_8252_max_group_size_96() #4 {
- store volatile i8 1, ptr addrspace(3) @lds8252
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_8252_max_group_size_128:
+; GCN: ; used_lds_8252_max_group_size_128 Kernel info:
; GFX9: ; Occupancy: 4{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX10W64: ; Occupancy: 8{{$}}
@@ -475,12 +557,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_96() #4 {
; GFX1100W64: ; Occupancy: 8{{$}}
; GFX1100W32: ; Occupancy: 15{{$}}
; GFX1250: ; Occupancy: 16{{$}}
-define amdgpu_kernel void @used_lds_8252_max_group_size_128() #5 {
- store volatile i8 1, ptr addrspace(3) @lds8252
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_8252_max_group_size_192:
+; GCN: ; used_lds_8252_max_group_size_192 Kernel info:
; GFX9: ; Occupancy: 6{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX10W64: ; Occupancy: 12{{$}}
@@ -489,12 +566,7 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_128() #5 {
; GFX1100W64: ; Occupancy: 12{{$}}
; GFX1100W32: ; Occupancy: 15{{$}}
; GFX1250: ; Occupancy: 15{{$}}
-define amdgpu_kernel void @used_lds_8252_max_group_size_192() #6 {
- store volatile i8 1, ptr addrspace(3) @lds8252
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_8252_max_group_size_256:
+; GCN: ; used_lds_8252_max_group_size_256 Kernel info:
; GFX9: ; Occupancy: 7{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX10W64: ; Occupancy: 15{{$}}
@@ -503,24 +575,14 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_192() #6 {
; GFX1100W64: ; Occupancy: 15{{$}}
; GFX1100W32: ; Occupancy: 16{{$}}
; GFX1250: ; Occupancy: 16{{$}}
-define amdgpu_kernel void @used_lds_8252_max_group_size_256() #7 {
- store volatile i8 1, ptr addrspace(3) @lds8252
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_8252_max_group_size_512:
+; GCN: ; used_lds_8252_max_group_size_512 Kernel info:
; GFX9: ; Occupancy: 10{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX1010: ; Occupancy: 20{{$}}
; GFX1030: ; Occupancy: 16{{$}}
; GFX1100: ; Occupancy: 16{{$}}
; GFX1250: ; Occupancy: 16{{$}}
-define amdgpu_kernel void @used_lds_8252_max_group_size_512() #8 {
- store volatile i8 1, ptr addrspace(3) @lds8252
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_8252_max_group_size_1024:
+; GCN: ; used_lds_8252_max_group_size_1024 Kernel info:
; GFX9: ; Occupancy: 8{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX1010W32: ; Occupancy: 16{{$}}
@@ -528,30 +590,9 @@ define amdgpu_kernel void @used_lds_8252_max_group_size_512() #8 {
; GFX1030: ; Occupancy: 16{{$}}
; GFX1100: ; Occupancy: 16{{$}}
; GFX1250: ; Occupancy: 16{{$}}
-define amdgpu_kernel void @used_lds_8252_max_group_size_1024() #9 {
- store volatile i8 1, ptr addrspace(3) @lds8252
- ret void
-}
-
-; GCN-LABEL: {{^}}used_lds_8252_max_group_size_32:
+; GCN: ; used_lds_8252_max_group_size_32 Kernel info:
; GFX9: ; Occupancy: 2{{$}}
; GFX950: ; Occupancy: 5{{$}}
; GFX10: ; Occupancy: 4{{$}}
; GFX1100: ; Occupancy: 4{{$}}
; GFX1250: ; Occupancy: 10{{$}}
-define amdgpu_kernel void @used_lds_8252_max_group_size_32() #10 {
- store volatile i8 1, ptr addrspace(3) @lds8252
- ret void
-}
-
-attributes #0 = { "amdgpu-waves-per-eu"="2,3" "amdgpu-flat-work-group-size"="1,64" }
-attributes #1 = { "amdgpu-waves-per-eu"="18,18" "amdgpu-flat-work-group-size"="1,32" }
-attributes #2 = { "amdgpu-waves-per-eu"="19,19" "amdgpu-flat-work-group-size"="1,32" }
-attributes #3 = { "amdgpu-flat-work-group-size"="1,64" }
-attributes #4 = { "amdgpu-flat-work-group-size"="1,96" }
-attributes #5 = { "amdgpu-flat-work-group-size"="1,128" }
-attributes #6 = { "amdgpu-flat-work-group-size"="1,192" }
-attributes #7 = { "amdgpu-flat-work-group-size"="1,256" }
-attributes #8 = { "amdgpu-flat-work-group-size"="1,512" }
-attributes #9 = { "amdgpu-flat-work-group-size"="1,1024" }
-attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
diff --git a/llvm/test/CodeGen/AMDGPU/perfhint.ll b/llvm/test/CodeGen/AMDGPU/perfhint.ll
index 3ff9e6a3b3da4..d1faa5aa76bdf 100644
--- a/llvm/test/CodeGen/AMDGPU/perfhint.ll
+++ b/llvm/test/CodeGen/AMDGPU/perfhint.ll
@@ -4,8 +4,6 @@
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_membound:
-; GCN: MemoryBound: 1
-; GCN: WaveLimiterHint : 1
define amdgpu_kernel void @test_membound(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {
; CHECK-LABEL: define amdgpu_kernel void @test_membound(
; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]]) #[[ATTR0:[0-9]+]] {
@@ -39,7 +37,6 @@ bb:
}
; GCN-LABEL: {{^}}test_membound_1:
-; GCN: MemoryBound: 1
define amdgpu_kernel void @test_membound_1(ptr addrspace(1) nocapture readonly %ptr.0,
; CHECK-LABEL: define amdgpu_kernel void @test_membound_1(
; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[PTR_0:%.*]], ptr addrspace(1) captures(none) [[PTR_1:%.*]], <2 x double> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], <4 x double> [[ARG_2:%.*]]) #[[ATTR1:[0-9]+]] {
@@ -163,8 +160,6 @@ bb.ret:
}
; GCN-LABEL: {{^}}test_large_stride:
-; GCN: MemoryBound: 0
-; GCN: WaveLimiterHint : 1
define amdgpu_kernel void @test_large_stride(ptr addrspace(1) nocapture %arg) {
; CHECK-LABEL: define amdgpu_kernel void @test_large_stride(
; CHECK-SAME: ptr addrspace(1) captures(none) [[ARG:%.*]]) #[[ATTR2:[0-9]+]] {
@@ -206,8 +201,6 @@ bb:
}
; GCN-LABEL: {{^}}test_indirect:
-; GCN: MemoryBound: 1
-; GCN: WaveLimiterHint : 1
define amdgpu_kernel void @test_indirect(ptr addrspace(1) nocapture %arg) {
; CHECK-LABEL: define amdgpu_kernel void @test_indirect(
; CHECK-SAME: ptr addrspace(1) captures(none) [[ARG:%.*]]) #[[ATTR2]] {
@@ -267,8 +260,6 @@ bb:
}
; GCN-LABEL: {{^}}test_indirect_through_phi:
-; GCN: MemoryBound: 0
-; GCN: WaveLimiterHint : 0
define amdgpu_kernel void @test_indirect_through_phi(ptr addrspace(1) %arg) {
; CHECK-LABEL: define amdgpu_kernel void @test_indirect_through_phi(
; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]]) {
@@ -346,8 +337,6 @@ bb:
}
; GCN-LABEL: {{^}}kernel_call_test_membound_func:
-; GCN: MemoryBound: 1
-; GCN: WaveLimiterHint : 1
define amdgpu_kernel void @kernel_call_test_membound_func(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {
; CHECK-LABEL: define amdgpu_kernel void @kernel_call_test_membound_func(
; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]]) #[[ATTR0]] {
@@ -360,8 +349,6 @@ define amdgpu_kernel void @kernel_call_test_membound_func(ptr addrspace(1) nocap
; TODO: Probably should assume yes?
; GCN-LABEL: {{^}}kernel_indirect_call:
-; GCN: MemoryBound: 0
-; GCN: WaveLimiterHint : 0
define amdgpu_kernel void @kernel_indirect_call(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, ptr %fptr) {
; CHECK-LABEL: define amdgpu_kernel void @kernel_indirect_call(
; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]], ptr [[FPTR:%.*]]) {
@@ -409,8 +396,6 @@ bb:
}
; GCN-LABEL: {{^}}kernel_call_maybe_recursive_test_membound_func:
-; GCN: MemoryBound: 1
-; GCN: WaveLimiterHint : 1
define amdgpu_kernel void @kernel_call_maybe_recursive_test_membound_func(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, ptr %fptr) {
; CHECK-LABEL: define amdgpu_kernel void @kernel_call_maybe_recursive_test_membound_func(
; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]], ptr [[FPTR:%.*]]) #[[ATTR0]] {
@@ -468,8 +453,6 @@ define void @mutually_recursive_test_membound_func_1(ptr addrspace(1) nocapture
}
; GCN-LABEL: {{^}}kernel_call_mutually_recursive_test_membound_func_0:
-; GCN: MemoryBound: 1
-; GCN: WaveLimiterHint : 1
define amdgpu_kernel void @kernel_call_mutually_recursive_test_membound_func_0(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, ptr %fptr) {
; CHECK-LABEL: define amdgpu_kernel void @kernel_call_mutually_recursive_test_membound_func_0(
; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]], ptr [[FPTR:%.*]]) #[[ATTR0]] {
@@ -489,3 +472,30 @@ declare i32 @llvm.amdgcn.workitem.id.x()
; CHECK: attributes #[[ATTR2]] = { "amdgpu-wave-limiter"="true" }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
;.
+
+; GCN: ; test_membound Kernel info:
+; GCN: MemoryBound: 1
+; GCN: WaveLimiterHint : 1
+; GCN: ; test_membound_1 Kernel info:
+; GCN: MemoryBound: 1
+; GCN: ; test_large_stride Kernel info:
+; GCN: MemoryBound: 0
+; GCN: WaveLimiterHint : 1
+; GCN: ; test_indirect Kernel info:
+; GCN: MemoryBound: 1
+; GCN: WaveLimiterHint : 1
+; GCN: ; test_indirect_through_phi Kernel info:
+; GCN: MemoryBound: 0
+; GCN: WaveLimiterHint : 0
+; GCN: ; kernel_call_test_membound_func Kernel info:
+; GCN: MemoryBound: 1
+; GCN: WaveLimiterHint : 1
+; GCN: ; kernel_indirect_call Kernel info:
+; GCN: MemoryBound: 0
+; GCN: WaveLimiterHint : 0
+; GCN: ; kernel_call_maybe_recursive_test_membound_func Kernel info:
+; GCN: MemoryBound: 1
+; GCN: WaveLimiterHint : 1
+; GCN: ; kernel_call_mutually_recursive_test_membound_func_0 Kernel info:
+; GCN: MemoryBound: 1
+; GCN: WaveLimiterHint : 1
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
index a88acb69bc4da..cd976568cf1f8 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
@@ -5,7 +5,6 @@
; IR: alloca [5 x i32]
; ASM-LABEL: {{^}}promote_alloca_shaders:
-; ASM: ; ScratchSize: 24
define amdgpu_vs void @promote_alloca_shaders(ptr addrspace(1) inreg %out, ptr addrspace(1) inreg %in) #0 {
entry:
%stack = alloca [5 x i32], align 4, addrspace(5)
@@ -30,8 +29,6 @@ entry:
; OPT: extractelement <2 x i32> %{{[0-9]+}}, i32 %in
; ASM-LABEL: {{^}}promote_to_vector_call_c:
-; ASM-NOT: LDSByteSize
-; ASM: ; ScratchSize: 12
define void @promote_to_vector_call_c(ptr addrspace(1) %out, i32 %in) #0 {
entry:
%tmp = alloca [2 x i32], addrspace(5)
@@ -50,8 +47,6 @@ entry:
; OPT: alloca
; ASM-LABEL: {{^}}no_promote_to_lds_c:
-; ASM-NOT: LDSByteSize
-; ASM: ; ScratchSize: 24
define void @no_promote_to_lds_c(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #0 {
entry:
%stack = alloca [5 x i32], align 4, addrspace(5)
@@ -77,7 +72,6 @@ declare i32 @foo(ptr addrspace(5)) #0
; ASM: buffer_store_dword
; ASM: buffer_store_dword
; ASM: s_swappc_b64
-; ASM: ScratchSize: 16
define amdgpu_kernel void @call_private(ptr addrspace(1) %out, i32 %in) #0 {
entry:
%tmp = alloca [2 x i32], addrspace(5)
@@ -92,6 +86,20 @@ entry:
declare i32 @llvm.amdgcn.workitem.id.x() #1
+; ASM: .section .AMDGPU.csdata
+; promote_alloca_shaders (Kernel info):
+; ASM: ; ScratchSize: 24
+; promote_to_vector_call_c (Function info):
+; ASM: ; promote_to_vector_call_c Function info:
+; ASM-NOT: LDSByteSize
+; ASM: ; ScratchSize: 12
+; no_promote_to_lds_c (Function info):
+; ASM: ; no_promote_to_lds_c Function info:
+; ASM-NOT: LDSByteSize
+; ASM: ; ScratchSize: 24
+; call_private (Kernel info):
+; ASM: ; ScratchSize: 16
+
attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" }
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
index 0a9346326d7d4..c78f28b6e408d 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
@@ -63,6 +63,7 @@ entry:
; GCN-LABEL: {{^}}stored_fi_to_self:
; GCN-NOT: ds_
+; GCN: {{^}}.Lfunc_end
define amdgpu_kernel void @stored_fi_to_self() #0 {
%tmp = alloca ptr addrspace(5), addrspace(5)
store volatile ptr addrspace(5) inttoptr (i32 1234 to ptr addrspace(5)), ptr addrspace(5) %tmp
diff --git a/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll b/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
index 161856cfd7863..73f6b98555d28 100644
--- a/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
@@ -4,7 +4,6 @@
;RUN: llc -global-isel=0 < %s -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 | FileCheck %s --check-prefixes=CHECK
; ;CHECK-LABEL: {{^}}_amdgpu_ps_1_arg:
-; ;CHECK: NumVgprs: 4
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_1_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -14,7 +13,6 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_1_arg(i32 inreg %arg, i32
}
; CHECK-LABEL: {{^}}_amdgpu_ps_3_arg:
-; CHECK: NumVgprs: 6
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_3_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -28,7 +26,6 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_3_arg(i32 inreg %arg, i32
}
; CHECK-LABEL: {{^}}_amdgpu_ps_2_arg_gap:
-; CHECK: NumVgprs: 4
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_gap(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -42,7 +39,6 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_gap(i32 inreg %arg,
; Using InitialPSInputAddr of 0x2 causes the 2nd VGPR arg to be included in the packing - this increases the total number of VGPRs and in turn makes arg3 not be packed to be
; adjacent to arg1 (the only 2 used arguments)
; CHECK-LABEL: {{^}}_amdgpu_ps_2_arg_no_pack:
-; CHECK: NumVgprs: 6
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_no_pack(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #1 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -54,7 +50,6 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_no_pack(i32 inreg %
}
; CHECK-LABEL: {{^}}_amdgpu_ps_all_arg:
-; CHECK: NumVgprs: 24
define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -100,7 +95,6 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
; Extra arguments have to be allocated even if they're unused
; CHECK-LABEL: {{^}}_amdgpu_ps_all_arg_extra_unused:
-; CHECK: NumVgprs: 26
define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg_extra_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -145,8 +139,6 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
}
; CHECK-LABEL: {{^}}_amdgpu_ps_all_arg_extra:
-; CHECK: NumVgprs: 26
-; CHECK: NumVGPRsForWavesPerEU: 26
define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg_extra(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -195,7 +187,6 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
; Check that when no input args are used we get the minimum allocation - note that we always enable the first input
; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused:
-; CHECK: NumVgprs: 4
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
.entry:
ret { <4 x float> } undef
@@ -204,14 +195,12 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused(i32 inreg %arg
; Check that when no input args are used we get the minimum allocation - note that we always enable the first input
; Additionally set the PSInputAddr to 0 via the metadata
; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_ia0:
-; CHECK: NumVgprs: 4
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_ia0(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #3 {
.entry:
ret { <4 x float> } undef
}
; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_extra_used:
-; CHECK: NumVgprs: 4
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
%ret4.1 = insertelement <4 x float> poison, float %extra_arg1, i32 0
@@ -223,7 +212,6 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used(i32
}
; CHECK-LABEL: {{^}}_amdgpu_ps_part_unused_extra_used:
-; CHECK: NumVgprs: 5
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_used(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
%ret4.1 = insertelement <4 x float> poison, float %arg14, i32 0
@@ -236,7 +224,6 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_used(i3
}
; CHECK-LABEL: {{^}}_amdgpu_ps_part_unused_extra_unused:
-; CHECK: NumVgprs: 7
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
%ret4.1 = insertelement <4 x float> poison, float %arg12, i32 0
@@ -250,7 +237,6 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_unused(
; Extra unused inputs are always added to the allocation
; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_extra_unused:
-; CHECK: NumVgprs: 4
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
@@ -258,7 +244,6 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_unused(i
}
; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_extra_used_no_packing:
-; CHECK: NumVgprs: 26
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used_no_packing(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #2 {
.entry:
%ret4.1 = insertelement <4 x float> poison, float %extra_arg1, i32 0
@@ -270,15 +255,12 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used_no_
}
; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_extra_unused_no_packing:
-; CHECK: NumVgprs: 26
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_unused_no_packing(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #2 {
.entry:
ret { <4 x float> } undef
}
; CHECK-LABEL: {{^}}_amdgpu_ps_some_unused_arg_extra:
-; CHECK: NumVgprs: 24
-; CHECK: NumVGPRsForWavesPerEU: 24
define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_some_unused_arg_extra(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -321,8 +303,6 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
}
;CHECK-LABEL: {{^}}_amdgpu_ps_some_unused_no_packing_arg_extra:
-;CHECK: NumVgprs: 26
-;CHECK: NumVGPRsForWavesPerEU: 26
define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_some_unused_no_packing_arg_extra(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #2 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
@@ -363,3 +343,41 @@ attributes #0 = { nounwind "target-features"="+wavefrontsize64,+cumode" }
attributes #1 = { nounwind "InitialPSInputAddr"="2" "target-features"="+wavefrontsize64,+cumode" }
attributes #2 = { nounwind "InitialPSInputAddr"="0xffff" "target-features"="+wavefrontsize64,+cumode" }
attributes #3 = { nounwind "InitialPSInputAddr"="0" "target-features"="+wavefrontsize64,+cumode" }
+
+; CHECK: ; _amdgpu_ps_1_arg Kernel info:
+; CHECK: NumVgprs: 4
+; CHECK: ; _amdgpu_ps_3_arg Kernel info:
+; CHECK: NumVgprs: 6
+; CHECK: ; _amdgpu_ps_2_arg_gap Kernel info:
+; CHECK: NumVgprs: 4
+; CHECK: ; _amdgpu_ps_2_arg_no_pack Kernel info:
+; CHECK: NumVgprs: 6
+; CHECK: ; _amdgpu_ps_all_arg Kernel info:
+; CHECK: NumVgprs: 24
+; CHECK: ; _amdgpu_ps_all_arg_extra_unused Kernel info:
+; CHECK: NumVgprs: 26
+; CHECK: ; _amdgpu_ps_all_arg_extra Kernel info:
+; CHECK: NumVgprs: 26
+; CHECK: NumVGPRsForWavesPerEU: 26
+; CHECK: ; _amdgpu_ps_all_unused Kernel info:
+; CHECK: NumVgprs: 4
+; CHECK: ; _amdgpu_ps_all_unused_ia0 Kernel info:
+; CHECK: NumVgprs: 4
+; CHECK: ; _amdgpu_ps_all_unused_extra_used Kernel info:
+; CHECK: NumVgprs: 4
+; CHECK: ; _amdgpu_ps_part_unused_extra_used Kernel info:
+; CHECK: NumVgprs: 5
+; CHECK: ; _amdgpu_ps_part_unused_extra_unused Kernel info:
+; CHECK: NumVgprs: 7
+; CHECK: ; _amdgpu_ps_all_unused_extra_unused Kernel info:
+; CHECK: NumVgprs: 4
+; CHECK: ; _amdgpu_ps_all_unused_extra_used_no_packing Kernel info:
+; CHECK: NumVgprs: 26
+; CHECK: ; _amdgpu_ps_all_unused_extra_unused_no_packing Kernel info:
+; CHECK: NumVgprs: 26
+; CHECK: ; _amdgpu_ps_some_unused_arg_extra Kernel info:
+; CHECK: NumVgprs: 24
+; CHECK: NumVGPRsForWavesPerEU: 24
+; CHECK: ; _amdgpu_ps_some_unused_no_packing_arg_extra Kernel info:
+;CHECK: NumVgprs: 26
+;CHECK: NumVGPRsForWavesPerEU: 26
diff --git a/llvm/test/CodeGen/AMDGPU/recursion.ll b/llvm/test/CodeGen/AMDGPU/recursion.ll
index f1ccbe57dd50f..591152a7fe256 100644
--- a/llvm/test/CodeGen/AMDGPU/recursion.ll
+++ b/llvm/test/CodeGen/AMDGPU/recursion.ll
@@ -4,7 +4,6 @@
; CHECK-LABEL: {{^}}recursive:
; CHECK: .set .Lrecursive.private_seg_size, 16+max(16384)
-; CHECK: ScratchSize: 16
; V5-LABEL: {{^}}recursive:
; V5: .set .Lrecursive.has_recursion, 1
@@ -16,7 +15,6 @@ define void @recursive() {
; CHECK-LABEL: {{^}}tail_recursive:
; CHECK: .set .Ltail_recursive.private_seg_size, 0
-; CHECK: ScratchSize: 0
define void @tail_recursive() {
tail call void @tail_recursive()
ret void
@@ -86,5 +84,10 @@ define amdgpu_kernel void @kernel_calls_tail_recursive_with_stack() {
ret void
}
+; CHECK: ; recursive Function info:
+; CHECK: ScratchSize: 16
+; CHECK: ; tail_recursive Function info:
+; CHECK: ScratchSize: 0
+
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 CODE_OBJECT_VERSION}
diff --git a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
index 4571f3278fefd..6933779e0f11b 100644
--- a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
+++ b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
@@ -5,10 +5,6 @@ declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
; SI-LABEL: {{^}}foo:
-; SI: .section .AMDGPU.csdata
-; SI: ; Kernel info:
-; SI: ; TotalNumSgprs: {{[0-9]+}}
-; SI: ; NumVgprs: {{[0-9]+}}
define amdgpu_kernel void @foo(ptr addrspace(1) noalias %out, ptr addrspace(1) %abase, ptr addrspace(1) %bbase) nounwind {
%mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0);
%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo)
@@ -23,8 +19,15 @@ define amdgpu_kernel void @foo(ptr addrspace(1) noalias %out, ptr addrspace(1) %
}
; SI-LABEL: {{^}}one_vgpr_used:
-; SI: NumVgprs: 1
define amdgpu_kernel void @one_vgpr_used(ptr addrspace(1) %out, i32 %x) nounwind {
store i32 %x, ptr addrspace(1) %out, align 4
ret void
}
+
+; SI: .section .AMDGPU.csdata
+; SI: ; foo Kernel info:
+; SI: ; TotalNumSgprs: {{[0-9]+}}
+; SI: ; NumVgprs: {{[0-9]+}}
+; SI: ; one_vgpr_used Kernel info:
+; SI: ; TotalNumSgprs: {{[0-9]+}}
+; SI: ; NumVgprs: 1
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll b/llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
index cf7d16edac4b7..630720388795b 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
@@ -9,7 +9,6 @@
; Vectors of i1 are always unpacked
; CHECK-LABEL: vec_of_i1:
-; CHECK: TotalNumSgprs: 8
define amdgpu_ps void @vec_of_i1(<8 x i1> inreg %v8i1) {
ret void
}
@@ -17,20 +16,26 @@ define amdgpu_ps void @vec_of_i1(<8 x i1> inreg %v8i1) {
; Vectors of i8 are always unpacked
; CHECK-LABEL: vec_of_i8:
-; CHECK: TotalNumSgprs: 4
define amdgpu_ps void @vec_of_i8(<4 x i8> inreg %v4i8) {
ret void
}
; Vectors of 16-bit types are packed.
; CHECK-LABEL: vec_of_16_bit_ty:
-; CHECK: TotalNumSgprs: 3
define amdgpu_ps void @vec_of_16_bit_ty(<2 x i16> inreg %v2i16, <4 x half> inreg %v4half) {
ret void
}
; CHECK-LABEL: buffer_fat_ptr:
-; CHECK: TotalNumSgprs: 5
define amdgpu_ps void @buffer_fat_ptr(ptr addrspace(7) inreg %p) {
ret void
}
+
+; CHECK: ; vec_of_i1 Kernel info:
+; CHECK: TotalNumSgprs: 8
+; CHECK: ; vec_of_i8 Kernel info:
+; CHECK: TotalNumSgprs: 4
+; CHECK: ; vec_of_16_bit_ty Kernel info:
+; CHECK: TotalNumSgprs: 3
+; CHECK: ; buffer_fat_ptr Kernel info:
+; CHECK: TotalNumSgprs: 5
diff --git a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
index d564e745f4506..fe58814fd0115 100644
--- a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
@@ -30,7 +30,6 @@
; GCN: s_endpgm
-; TOVGPR: ScratchSize: 0{{$}}
define amdgpu_ps void @main(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) {
main_body:
%lds = inttoptr i32 0 to ptr addrspace(3)
@@ -647,7 +646,6 @@ ENDIF66: ; preds = %LOOP65
; GCN-LABEL: {{^}}main1:
; GCN: s_endpgm
-; TOVGPR: ScratchSize: 0{{$}}
define amdgpu_ps void @main1(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
main_body:
%tmp21 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0
@@ -1691,6 +1689,11 @@ attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }
+; TOVGPR: ; main Kernel info:
+; TOVGPR: ScratchSize: 0{{$}}
+; TOVGPR: ; main1 Kernel info:
+; TOVGPR: ScratchSize: 0{{$}}
+
!0 = !{!1, !1, i64 0, i32 1}
!1 = !{!"const", !2}
!2 = !{!"tbaa root"}
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr.ll b/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
index f2dd473162034..e2b3450a436a0 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
@@ -120,7 +120,6 @@ st:
call void asm sideeffect "", "a,a"(<4 x float> %mai.1, <4 x float> %mai.2)
ret void
}
-; GCN: ScratchSize: 0
define amdgpu_kernel void @max_10_vgprs_used_9a() #1 {
; GFX908-LABEL: max_10_vgprs_used_9a:
@@ -186,7 +185,6 @@ define amdgpu_kernel void @max_10_vgprs_used_9a() #1 {
call void asm sideeffect "", "a"(<2 x i32> %a4)
ret void
}
-; GCN: ScratchSize: 0
define amdgpu_kernel void @max_32regs_mfma32(ptr addrspace(1) %arg) #3 {
; GFX908-LABEL: max_32regs_mfma32:
@@ -357,7 +355,6 @@ use:
store float %elt1, ptr addrspace(1) %arg
ret void
}
-; GCN: ScratchSize: 0
; Should spill agprs to memory for both gfx908 and gfx90a.
define amdgpu_kernel void @max_6regs_used_8a(ptr addrspace(1) %arg) #4 {
@@ -472,7 +469,6 @@ define amdgpu_kernel void @max_6regs_used_8a(ptr addrspace(1) %arg) #4 {
call void asm sideeffect "; use $0", "v"(float %v0);
ret void
}
-; GCN: ScratchSize: 20
declare i32 @llvm.amdgcn.workitem.id.x()
declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float, float, <16 x float>, i32, i32, i32)
@@ -491,3 +487,12 @@ attributes #3 = { nounwind "amdgpu-num-vgpr"="32" "amdgpu-no-dispatch-id" "amdgp
attributes #4 = { nounwind "amdgpu-num-vgpr"="6" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
+
+; GCN: ; max_12regs_13a_used Kernel info:
+; GCN: ScratchSize: 0
+; GCN: ; max_10_vgprs_used_9a Kernel info:
+; GCN: ScratchSize: 0
+; GCN: ; max_32regs_mfma32 Kernel info:
+; GCN: ScratchSize: 0
+; GCN: ; max_6regs_used_8a Kernel info:
+; GCN: ScratchSize: 20
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll b/llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
index f485b3feeb394..862ec13d15f40 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
@@ -10,10 +10,6 @@
; GFX908: v_accvgpr_read_b32 [[V_REG]], [[A_REG]]
; GFX908-NOT: buffer_
-; GFX908: NumVgprs: 10
-; GFX908: ScratchSize: 0
-; GFX908: VGPRBlocks: 2
-; GFX908: NumVGPRsForWavesPerEU: 10
define amdgpu_kernel void @max_11_vgprs_used_9a(ptr addrspace(1) %p) #0 {
%tid = load volatile i32, ptr addrspace(1) poison
call void asm sideeffect "", "a,a,a,a,a,a,a,a,a"(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9)
@@ -79,10 +75,6 @@ define amdgpu_kernel void @max_11_vgprs_used_9a(ptr addrspace(1) %p) #0 {
; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a9
; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a10
-; GFX908: NumVgprs: 10
-; GFX908: ScratchSize: 12
-; GFX908: VGPRBlocks: 2
-; GFX908: NumVGPRsForWavesPerEU: 11
define amdgpu_kernel void @max_11_vgprs_used_1a_partial_spill(ptr addrspace(1) %p) #0 {
%tid = load volatile i32, ptr addrspace(1) poison
call void asm sideeffect "", "a"(i32 1)
@@ -105,4 +97,15 @@ define amdgpu_kernel void @max_11_vgprs_used_1a_partial_spill(ptr addrspace(1) %
ret void
}
+; GFX908: ; max_11_vgprs_used_9a Kernel info:
+; GFX908: NumVgprs: 10
+; GFX908: ScratchSize: 0
+; GFX908: VGPRBlocks: 2
+; GFX908: NumVGPRsForWavesPerEU: 10
+; GFX908: ; max_11_vgprs_used_1a_partial_spill Kernel info:
+; GFX908: NumVgprs: 10
+; GFX908: ScratchSize: 12
+; GFX908: VGPRBlocks: 2
+; GFX908: NumVGPRsForWavesPerEU: 11
+
attributes #0 = { nounwind "amdgpu-num-vgpr"="11" }
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vgpr.ll b/llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
index 2b20f9d545899..3ef4eba0a1981 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
@@ -10,13 +10,6 @@
; GFX908-DAG: v_mov_b32_e32 v{{[0-9]}}, [[V_REG:v[0-9]+]]
; GFX908-DAG: v_accvgpr_read_b32 [[V_REG]], [[A_REG]]
-; GFX900: NumVgprs: 11
-; GFX908: NumVgprs: 10
-; GFX900: ScratchSize: 0
-; GFX908: ScratchSize: 0
-; GCN: VGPRBlocks: 2
-; GFX900: NumVGPRsForWavesPerEU: 11
-; GFX908: NumVGPRsForWavesPerEU: 10
define amdgpu_kernel void @max_11_vgprs(ptr addrspace(1) %p) #2 {
%tid = load volatile i32, ptr addrspace(1) poison
%p1 = getelementptr inbounds i32, ptr addrspace(1) %p, i32 %tid
@@ -61,11 +54,6 @@ define amdgpu_kernel void @max_11_vgprs(ptr addrspace(1) %p) #2 {
; GFX908-DAG: v_accvgpr_write_b32 a9, v{{[0-9]}}
; GCN-NOT: a10
-; GFX908: NumVgprs: 10
-; GFX900: ScratchSize: 100
-; GFX908: ScratchSize: 68
-; GFX908: VGPRBlocks: 2
-; GFX908: NumVGPRsForWavesPerEU: 10
define amdgpu_kernel void @max_10_vgprs_spill_v32(ptr addrspace(1) %p) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds <32 x float>, ptr addrspace(1) %p, i32 %tid
@@ -84,14 +72,6 @@ define amdgpu_kernel void @max_10_vgprs_spill_v32(ptr addrspace(1) %p) #0 {
; GFX908-NOT: buffer_
; GFX908-DAG: v_accvgpr_read_b32
-; GFX900: NumVgprs: 256
-; GFX900: ScratchSize: 132
-; GFX908: NumVgprs: 252
-; GFX908: ScratchSize: 0
-; GFX900: VGPRBlocks: 63
-; GFX908: VGPRBlocks: 62
-; GFX900: NumVGPRsForWavesPerEU: 256
-; GFX908: NumVGPRsForWavesPerEU: 252
define amdgpu_kernel void @max_256_vgprs_spill_9x32(ptr addrspace(1) %p) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%p1 = getelementptr inbounds <32 x float>, ptr addrspace(1) %p, i32 %tid
@@ -135,14 +115,6 @@ define amdgpu_kernel void @max_256_vgprs_spill_9x32(ptr addrspace(1) %p) #1 {
; GFX908-NOT: buffer_
; GFX908-DAG: v_accvgpr_read_b32
-; GFX900: NumVgprs: 256
-; GFX908: NumVgprs: 254
-; GFX900: ScratchSize: 132
-; GFX908: ScratchSize: 0
-; GFX900: VGPRBlocks: 63
-; GFX908: VGPRBlocks: 63
-; GFX900: NumVGPRsForWavesPerEU: 256
-; GFX908: NumVGPRsForWavesPerEU: 254
define amdgpu_kernel void @max_256_vgprs_spill_9x32_2bb(ptr addrspace(1) %p) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%p1 = getelementptr inbounds <32 x float>, ptr addrspace(1) %p, i32 %tid
@@ -219,6 +191,39 @@ st:
declare i32 @llvm.amdgcn.workitem.id.x()
+; GCN: ; max_11_vgprs Kernel info:
+; GFX900: NumVgprs: 11
+; GFX908: NumVgprs: 10
+; GFX900: ScratchSize: 0
+; GFX908: ScratchSize: 0
+; GCN: VGPRBlocks: 2
+; GFX900: NumVGPRsForWavesPerEU: 11
+; GFX908: NumVGPRsForWavesPerEU: 10
+; GCN: ; max_10_vgprs_spill_v32 Kernel info:
+; GFX908: NumVgprs: 10
+; GFX900: ScratchSize: 100
+; GFX908: ScratchSize: 68
+; GFX908: VGPRBlocks: 2
+; GFX908: NumVGPRsForWavesPerEU: 10
+; GCN: ; max_256_vgprs_spill_9x32 Kernel info:
+; GFX900: NumVgprs: 256
+; GFX900: ScratchSize: 132
+; GFX908: NumVgprs: 252
+; GFX908: ScratchSize: 0
+; GFX900: VGPRBlocks: 63
+; GFX908: VGPRBlocks: 62
+; GFX900: NumVGPRsForWavesPerEU: 256
+; GFX908: NumVGPRsForWavesPerEU: 252
+; GCN: ; max_256_vgprs_spill_9x32_2bb Kernel info:
+; GFX900: NumVgprs: 256
+; GFX908: NumVgprs: 254
+; GFX900: ScratchSize: 132
+; GFX908: ScratchSize: 0
+; GFX900: VGPRBlocks: 63
+; GFX908: VGPRBlocks: 63
+; GFX900: NumVGPRsForWavesPerEU: 256
+; GFX908: NumVGPRsForWavesPerEU: 254
+
attributes #0 = { nounwind "amdgpu-num-vgpr"="10" }
attributes #1 = { "amdgpu-flat-work-group-size"="1,256" }
attributes #2 = { nounwind "amdgpu-num-vgpr"="11" }
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
index c975f3a9ba946..bd0421b0cdfb8 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
@@ -692,3 +692,12 @@ attributes #3 = { noinline nounwind "no-realign-stack" }
attributes #4 = { noinline nounwind "frame-pointer"="all"}
attributes #5 = { noinline nounwind "amdgpu-waves-per-eu"="6,6" }
attributes #6 = { nounwind }
+
+; GCN: ; needs_align16_default_stack_align Function info:
+; GCN: ; ScratchSize: 144
+; GCN: ; needs_align16_stack_align4 Function info:
+; GCN: ; ScratchSize: 160
+; GCN: ; needs_align32 Function info:
+; GCN: ; ScratchSize: 192
+; GCN: ; force_realign4 Function info:
+; GCN: ; ScratchSize: 52
diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll
index 3a4d5b207146e..e7062dc27a4f5 100644
--- a/llvm/test/CodeGen/AMDGPU/trap.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap.ll
@@ -40,11 +40,9 @@ declare void @llvm.debugtrap() #1
; GCN-LABEL: {{^}}hsa_trap:
; HSA-TRAP: s_mov_b64 s[0:1], s[6:7]
; HSA-TRAP: s_trap 2
-; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; for llvm.trap in hsa path without ABI, direct generate s_endpgm instruction without any warning information
; NO-HSA-TRAP: s_endpgm
-; NO-HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; TRAP-BIT: enable_trap_handler = 1
; NO-TRAP-BIT: enable_trap_handler = 0
@@ -68,7 +66,6 @@ define amdgpu_kernel void @hsa_trap(ptr addrspace(1) nocapture readonly %arg0) {
; GCN-LABEL: {{^}}hsa_debugtrap:
; HSA-TRAP: s_trap 3
; HSA-TRAP: flat_store_dword v[0:1], v3
-; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction
; NO-HSA-TRAP: s_endpgm
@@ -147,3 +144,9 @@ attributes #1 = { nounwind }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
+
+; GCN: ; hsa_trap Kernel info:
+; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
+; NO-HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
+; GCN: ; hsa_debugtrap Kernel info:
+; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
diff --git a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
index 15065ebdc44d5..ffd7abcdf54df 100644
--- a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
@@ -567,7 +567,6 @@ define amdgpu_kernel void @constant_align4_merge_load_2_i32(ptr addrspace(4) %p,
; SI: ds_read_u8
; SI: ds_read_u8
-; SI: ScratchSize: 0{{$}}
define amdgpu_kernel void @local_load_align1_v16i8(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {
%ld = load <16 x i8>, ptr addrspace(3) %in, align 1
store <16 x i8> %ld, ptr addrspace(1) %out
@@ -592,7 +591,6 @@ define amdgpu_kernel void @local_load_align1_v16i8(ptr addrspace(1) %out, ptr ad
; SI: ds_write_b8
; SI: ds_write_b8
-; SI: ScratchSize: 0{{$}}
define amdgpu_kernel void @local_store_align1_v16i8(ptr addrspace(3) %out) #0 {
store <16 x i8> zeroinitializer, ptr addrspace(3) %out, align 1
ret void
@@ -710,3 +708,8 @@ define i32 @load_2xi16_align2(ptr addrspace(1) %p) #0 {
}
attributes #0 = { nounwind }
+
+; SI: ; local_unaligned_load_store_i16 Kernel info:
+; SI: ScratchSize: 0{{$}}
+; SI: ; global_unaligned_load_store_i16 Kernel info:
+; SI: ScratchSize: 0{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
index a935bf1d1c6ec..3954596041233 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
@@ -18,7 +18,6 @@
; GCN-PROMOTE: s_cselect_b32 [[IND2:s[0-9]+]], [[IND1]], 2
; GCN-PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 3
; GCN-PROMOTE: s_cselect_b32 [[IND3:s[0-9]+]], [[IND2]], 3
-; GCN-PROMOTE: ScratchSize: 0
define amdgpu_kernel void @vector_read_alloca_bitcast(ptr addrspace(1) %out, i32 %index) {
entry:
@@ -48,7 +47,6 @@ entry:
; GCN-PROMOTE-COUNT-7: s_cselect_b32
-; GCN-PROMOTE: ScratchSize: 0
define amdgpu_kernel void @vector_write_alloca_bitcast(ptr addrspace(1) %out, i32 %w_index, i32 %r_index) {
entry:
@@ -87,7 +85,6 @@ entry:
; GCN-ALLOCA: buffer_load_dword
-; GCN-PROMOTE: ScratchSize: 0
define amdgpu_kernel void @vector_write_read_bitcast_to_float(ptr addrspace(1) %arg) {
bb:
@@ -149,7 +146,6 @@ bb15: ; preds = %.preheader
; GCN-ALLOCA-COUNT-2: buffer_load_dword
; GCN-PROMOTE-COUNT-2: v_movrels_b32_e32
-; GCN-PROMOTE: ScratchSize: 0
define amdgpu_kernel void @vector_write_read_bitcast_to_double(ptr addrspace(1) %arg) {
bb:
@@ -209,7 +205,6 @@ bb15: ; preds = %.preheader
; GCN-ALLOCA-COUNT-2: buffer_load_dword
; GCN-PROMOTE-COUNT-2: v_movrels_b32_e32
-; GCN-PROMOTE: ScratchSize: 0
define amdgpu_kernel void @vector_write_read_bitcast_to_i64(ptr addrspace(1) %arg) {
bb:
@@ -295,7 +290,6 @@ entry:
; GCN-PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 3
; GCN-PROMOTE: s_cselect_b32 [[IND3:s[0-9]+]], [[IND2]], 3
-; GCN-PROMOTE: ScratchSize: 0
define amdgpu_kernel void @vector_read_alloca_multiuse(ptr addrspace(1) %out, i32 %index) {
entry:
@@ -327,7 +321,6 @@ entry:
; GCN: v_mov_b32_e32 v2, 3
; GCN: v_mov_b32_e32 v3, 4
-; GCN: ScratchSize: 0
define amdgpu_kernel void @bitcast_vector_to_vector(ptr addrspace(1) %out) {
.entry:
@@ -348,7 +341,6 @@ define amdgpu_kernel void @bitcast_vector_to_vector(ptr addrspace(1) %out) {
; GCN: v_mov_b32_e32 v2, 3
; GCN: v_mov_b32_e32 v3, 4
-; GCN: ScratchSize: 0
define amdgpu_kernel void @vector_bitcast_from_alloca_array(ptr addrspace(1) %out) {
.entry:
@@ -375,7 +367,6 @@ define amdgpu_kernel void @vector_bitcast_from_alloca_array(ptr addrspace(1) %ou
; GCN: v_mov_b32_e32 v2, 3
; GCN: v_mov_b32_e32 v3, 4
-; GCN: ScratchSize: 0
define amdgpu_kernel void @vector_bitcast_to_array_from_alloca_array(ptr addrspace(1) %out) {
%alloca = alloca [4 x float], align 16, addrspace(5)
@@ -401,7 +392,6 @@ define amdgpu_kernel void @vector_bitcast_to_array_from_alloca_array(ptr addrspa
; GCN: v_mov_b32_e32 v2, 3
; GCN: v_mov_b32_e32 v3, 4
-; GCN: ScratchSize: 0
%struct.v4 = type { i32, i32, i32, i32 }
@@ -418,3 +408,24 @@ declare void @llvm.lifetime.start.p5(i64 immarg, ptr addrspace(5) nocapture)
declare void @llvm.lifetime.end.p5(i64 immarg, ptr addrspace(5) nocapture)
declare void @llvm.assume(i1)
+
+; GCN-PROMOTE: ; vector_read_alloca_bitcast Kernel info:
+; GCN-PROMOTE: ScratchSize: 0
+; GCN-PROMOTE: ; vector_write_alloca_bitcast Kernel info:
+; GCN-PROMOTE: ScratchSize: 0
+; GCN-PROMOTE: ; vector_write_read_bitcast_to_float Kernel info:
+; GCN-PROMOTE: ScratchSize: 0
+; GCN-PROMOTE: ; vector_write_read_bitcast_to_double Kernel info:
+; GCN-PROMOTE: ScratchSize: 0
+; GCN-PROMOTE: ; vector_write_read_bitcast_to_i64 Kernel info:
+; GCN-PROMOTE: ScratchSize: 0
+; GCN-PROMOTE: ; vector_read_alloca_bitcast_assume Kernel info:
+; GCN-PROMOTE: ScratchSize: 0
+; GCN: ; bitcast_vector_to_vector Kernel info:
+; GCN: ScratchSize: 0
+; GCN: ; vector_bitcast_from_alloca_array Kernel info:
+; GCN: ScratchSize: 0
+; GCN: ; vector_bitcast_to_array_from_alloca_array Kernel info:
+; GCN: ScratchSize: 0
+; GCN: ; vector_bitcast_to_struct_from_alloca_array Kernel info:
+; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
index c0e03b7f339e2..3444bbc8f9834 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
@@ -1063,9 +1063,6 @@ define void @foo() #0 {
attributes #0 = { noinline }
; GCN-LABEL: {{^}}k256_w8:
-; GFX90A: NumVgprs: 32
-; GFX90A: NumAgprs: 32
-; GFX90A: TotalNumVgprs: 64
define amdgpu_kernel void @k256_w8() #2568 {
call void @foo()
call void @use256vgprs()
@@ -1073,9 +1070,6 @@ define amdgpu_kernel void @k256_w8() #2568 {
}
; GCN-LABEL: {{^}}k256_w8_no_agprs:
-; GFX90A: NumVgprs: 64
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 64
define amdgpu_kernel void @k256_w8_no_agprs() #2569 {
call void @use256vgprs()
ret void
@@ -1085,9 +1079,6 @@ attributes #2568 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-wa
attributes #2569 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-waves-per-eu"="8" "amdgpu-agpr-alloc"="0" }
; GCN-LABEL: {{^}}k256_w4:
-; GFX90A: NumVgprs: 64
-; GFX90A: NumAgprs: 64
-; GFX90A: TotalNumVgprs: 128
define amdgpu_kernel void @k256_w4() #2564 {
call void @foo()
call void @use256vgprs()
@@ -1095,9 +1086,6 @@ define amdgpu_kernel void @k256_w4() #2564 {
}
; GCN-LABEL: {{^}}k256_w4_no_agprs:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 128
define amdgpu_kernel void @k256_w4_no_agprs() #2565 {
call void @use256vgprs()
ret void
@@ -1107,9 +1095,6 @@ attributes #2564 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-wa
attributes #2565 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-waves-per-eu"="4" "amdgpu-agpr-alloc"="0" }
; GCN-LABEL: {{^}}k256_w2:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 128
-; GFX90A: TotalNumVgprs: 256
define amdgpu_kernel void @k256_w2() #2562 {
call void @foo()
call void @use256vgprs()
@@ -1117,9 +1102,6 @@ define amdgpu_kernel void @k256_w2() #2562 {
}
; GCN-LABEL: {{^}}k256_w2_no_agprs:
-; GFX90A: NumVgprs: 256
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 256
define amdgpu_kernel void @k256_w2_no_agprs() #2563 {
call void @use256vgprs()
ret void
@@ -1129,9 +1111,6 @@ attributes #2562 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-wa
attributes #2563 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-waves-per-eu"="2" "amdgpu-agpr-alloc"="0" }
; GCN-LABEL: {{^}}k256_w1:
-; GFX90A: NumVgprs: 256
-; GFX90A: NumAgprs: 256
-; GFX90A: TotalNumVgprs: 512
define amdgpu_kernel void @k256_w1() #2561 {
call void @foo()
call void @use512vgprs()
@@ -1139,9 +1118,6 @@ define amdgpu_kernel void @k256_w1() #2561 {
}
; GCN-LABEL: {{^}}k256_w1_no_agprs:
-; GFX90A: NumVgprs: 256
-; GFX90A: NumAgprs: 256
-; GFX90A: TotalNumVgprs: 512
define amdgpu_kernel void @k256_w1_no_agprs() #2561 {
call void @use512vgprs()
ret void
@@ -1150,18 +1126,12 @@ define amdgpu_kernel void @k256_w1_no_agprs() #2561 {
attributes #2561 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-waves-per-eu"="1" }
; GCN-LABEL: {{^}}k512_no_agprs:
-; GFX90A: NumVgprs: 256
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 256
define amdgpu_kernel void @k512_no_agprs() #513 {
call void @use256vgprs()
ret void
}
; GCN-LABEL: {{^}}k512_call:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 128
-; GFX90A: TotalNumVgprs: 256
define amdgpu_kernel void @k512_call() #512 {
call void @foo()
call void @use256vgprs()
@@ -1169,9 +1139,6 @@ define amdgpu_kernel void @k512_call() #512 {
}
; GCN-LABEL: {{^}}k512_virtual_agpr:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 128
-; GFX90A: TotalNumVgprs: 256
define amdgpu_kernel void @k512_virtual_agpr() #512 {
%a0 = call i32 asm sideeffect "; def $0", "=a"()
call void @use256vgprs()
@@ -1179,9 +1146,6 @@ define amdgpu_kernel void @k512_virtual_agpr() #512 {
}
; GCN-LABEL: {{^}}k512_physical_agpr:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 128
-; GFX90A: TotalNumVgprs: 256
define amdgpu_kernel void @k512_physical_agpr() #512 {
call void asm sideeffect "", "~{a8}" ()
call void @use256vgprs()
@@ -1189,24 +1153,18 @@ define amdgpu_kernel void @k512_physical_agpr() #512 {
}
; GCN-LABEL: {{^}}f512:
-; GFX90A: NumVgprs: 12{{[0-9]}}
-; GFX90A: NumAgprs: {{[1-9]}}
define void @f512() #512 {
call void @use256vgprs()
ret void
}
; GCN-LABEL: {{^}}f512_no_agpr:
-; GFX90A: NumVgprs: 256
-; GFX90A: NumAgprs: 0
define void @f512_no_agpr() #513 {
call void @use256vgprs_no_agpr()
ret void
}
; GCN-LABEL: {{^}}f512_no_agpr_ub:
-; GFX90A: NumVgprs: 256
-; GFX90A: NumAgprs: 0
define void @f512_no_agpr_ub() #513 {
call void @use256vgprs()
ret void
@@ -1216,27 +1174,18 @@ attributes #512 = { nounwind "amdgpu-flat-work-group-size"="512,512" }
attributes #513 = { nounwind "amdgpu-flat-work-group-size"="512,512" "amdgpu-agpr-alloc"="0" }
; GCN-LABEL: {{^}}k1024:
-; GFX90A: NumVgprs: 64
-; GFX90A: NumAgprs: 64
-; GFX90A: TotalNumVgprs: 128
define amdgpu_kernel void @k1024() #1024 {
call void @use256vgprs()
ret void
}
; GCN-LABEL: {{^}}k1024_no_agprs:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 128
define amdgpu_kernel void @k1024_no_agprs() #1025 {
call void @use256vgprs()
ret void
}
; GCN-LABEL: {{^}}k1024_call:
-; GFX90A: NumVgprs: 64
-; GFX90A: NumAgprs: 64
-; GFX90A: TotalNumVgprs: 128
define amdgpu_kernel void @k1024_call() #1024 {
call void @foo()
call void @use256vgprs()
@@ -1244,9 +1193,6 @@ define amdgpu_kernel void @k1024_call() #1024 {
}
; GCN-LABEL: {{^}}k1024_call_no_agprs:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 128
define amdgpu_kernel void @k1024_call_no_agprs() #1025 {
call void @use256vgprs()
ret void
@@ -1254,9 +1200,6 @@ define amdgpu_kernel void @k1024_call_no_agprs() #1025 {
; @foo uses an AGPRs so amdgpu-no-agpr is undefined
; GCN-LABEL: {{^}}k1024_call_no_agprs_ub_callee:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 1
-; GFX90A: TotalNumVgprs: 129
define amdgpu_kernel void @k1024_call_no_agprs_ub_callee() #1025 {
call void @foo()
call void @use256vgprs()
@@ -1264,36 +1207,24 @@ define amdgpu_kernel void @k1024_call_no_agprs_ub_callee() #1025 {
}
; GCN-LABEL: {{^}}f1024_0:
-; GFX90A: NumVgprs: 1
-; GFX90A: NumAgprs: 1
-; GFX90A: TotalNumVgprs: 5
define void @f1024_0() #1024 {
call void @foo()
ret void
}
; GCN-LABEL: {{^}}f1024_1:
-; GFX90A: NumVgprs: 64
-; GFX90A: NumAgprs: 32
-; GFX90A: TotalNumVgprs: 96
define void @f1024_1() #1024 {
call void @use256vgprs()
ret void
}
; GCN-LABEL: {{^}}f1024_call_no_agprs:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 128
define void @f1024_call_no_agprs() #1025 {
call void @use256vgprs_no_agpr()
ret void
}
; GCN-LABEL: {{^}}f1024_call_no_agprs_ub:
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 0
-; GFX90A: TotalNumVgprs: 128
define void @f1024_call_no_agprs_ub() #1025 {
call void @use256vgprs()
ret void
@@ -1301,3 +1232,97 @@ define void @f1024_call_no_agprs_ub() #1025 {
attributes #1024 = { nounwind "amdgpu-flat-work-group-size"="1024,1024" }
attributes #1025 = { nounwind "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-agpr-alloc"="0" }
+
+; GFX90A: ; k256_w8 Kernel info:
+; GFX90A: NumVgprs: 32
+; GFX90A: NumAgprs: 32
+; GFX90A: TotalNumVgprs: 64
+; GFX90A: ; k256_w8_no_agprs Kernel info:
+; GFX90A: NumVgprs: 64
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 64
+; GFX90A: ; k256_w4 Kernel info:
+; GFX90A: NumVgprs: 64
+; GFX90A: NumAgprs: 64
+; GFX90A: TotalNumVgprs: 128
+; GFX90A: ; k256_w4_no_agprs Kernel info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 128
+; GFX90A: ; k256_w2 Kernel info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 128
+; GFX90A: TotalNumVgprs: 256
+; GFX90A: ; k256_w2_no_agprs Kernel info:
+; GFX90A: NumVgprs: 256
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 256
+; GFX90A: ; k256_w1 Kernel info:
+; GFX90A: NumVgprs: 256
+; GFX90A: NumAgprs: 256
+; GFX90A: TotalNumVgprs: 512
+; GFX90A: ; k256_w1_no_agprs Kernel info:
+; GFX90A: NumVgprs: 256
+; GFX90A: NumAgprs: 256
+; GFX90A: TotalNumVgprs: 512
+; GFX90A: ; k512_no_agprs Kernel info:
+; GFX90A: NumVgprs: 256
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 256
+; GFX90A: ; k512_call Kernel info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 128
+; GFX90A: TotalNumVgprs: 256
+; GFX90A: ; k512_virtual_agpr Kernel info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 128
+; GFX90A: TotalNumVgprs: 256
+; GFX90A: ; k512_physical_agpr Kernel info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 128
+; GFX90A: TotalNumVgprs: 256
+; GFX90A: ; f512 Function info:
+; GFX90A: NumVgprs: 12{{[0-9]}}
+; GFX90A: NumAgprs: {{[1-9]}}
+; GFX90A: ; f512_no_agpr Function info:
+; GFX90A: NumVgprs: 256
+; GFX90A: NumAgprs: 0
+; GFX90A: ; f512_no_agpr_ub Function info:
+; GFX90A: NumVgprs: 256
+; GFX90A: NumAgprs: 0
+; GFX90A: ; k1024 Kernel info:
+; GFX90A: NumVgprs: 64
+; GFX90A: NumAgprs: 64
+; GFX90A: TotalNumVgprs: 128
+; GFX90A: ; k1024_no_agprs Kernel info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 128
+; GFX90A: ; k1024_call Kernel info:
+; GFX90A: NumVgprs: 64
+; GFX90A: NumAgprs: 64
+; GFX90A: TotalNumVgprs: 128
+; GFX90A: ; k1024_call_no_agprs Kernel info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 128
+; GFX90A: ; k1024_call_no_agprs_ub_callee Kernel info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 1
+; GFX90A: TotalNumVgprs: 129
+; GFX90A: ; f1024_0 Function info:
+; GFX90A: NumVgprs: 1
+; GFX90A: NumAgprs: 1
+; GFX90A: TotalNumVgprs: 5
+; GFX90A: ; f1024_1 Function info:
+; GFX90A: NumVgprs: 64
+; GFX90A: NumAgprs: 32
+; GFX90A: TotalNumVgprs: 96
+; GFX90A: ; f1024_call_no_agprs Function info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 128
+; GFX90A: ; f1024_call_no_agprs_ub Function info:
+; GFX90A: NumVgprs: 128
+; GFX90A: NumAgprs: 0
+; GFX90A: TotalNumVgprs: 128
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
index 2b1309492b73f..27148f304b5a6 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
@@ -548,18 +548,12 @@ define internal void @use512vgprs_asm() {
; GCN-DAG: def v[64:95]
; GCN-DAG: def v[32:63]
; GCN-DAG: def v[0:31]
-; GFX1250: NumVgprs: 256
-; GFX1250-NOT: NumAgprs:
-; GFX1250-NOT: TotalNumVgprs:
-; GFX1250: VGPRBlocks: 15
define amdgpu_kernel void @k256_w1_asm() #2561 {
call void @use512vgprs_asm()
ret void
}
; GCN-LABEL: {{^}}use512vgprs_codegen:
-; GFX1250: NumVgprs: 482
-; GFX1250: VGPRBlocks: 30
define amdgpu_kernel void @use512vgprs_codegen(ptr %p) #2561 {
%r0 = load volatile <512 x float>, ptr %p, align 1
store volatile <512 x float> %r0, ptr %p
@@ -567,8 +561,6 @@ define amdgpu_kernel void @use512vgprs_codegen(ptr %p) #2561 {
}
; GCN-LABEL: {{^}}use1024vgprs_codegen:
-; GFX1250: NumVgprs: 998
-; GFX1250: VGPRBlocks: 62
define amdgpu_kernel void @use1024vgprs_codegen(ptr %p) #1281 {
%r0 = load volatile <1024 x float>, ptr %p, align 1
store volatile <1024 x float> %r0, ptr %p
@@ -577,3 +569,15 @@ define amdgpu_kernel void @use1024vgprs_codegen(ptr %p) #1281 {
attributes #2561 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-waves-per-eu"="1" }
attributes #1281 = { nounwind "amdgpu-flat-work-group-size"="128,128" "amdgpu-waves-per-eu"="1" }
+
+; GCN: ; k256_w1_asm Kernel info:
+; GFX1250: NumVgprs: 256
+; GFX1250-NOT: NumAgprs:
+; GFX1250-NOT: TotalNumVgprs:
+; GFX1250: VGPRBlocks: 15
+; GCN: ; use512vgprs_codegen Kernel info:
+; GFX1250: NumVgprs: 482
+; GFX1250: VGPRBlocks: 30
+; GCN: ; use1024vgprs_codegen Kernel info:
+; GFX1250: NumVgprs: 998
+; GFX1250: VGPRBlocks: 62
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
index f018ca040a304..ad6b52dabc949 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
@@ -246,7 +246,6 @@ body: |
; GCN-NEXT: v_wmma_f32_16x16x32_bf16 v[14:21] /*v[270:277]*/, v[26:33] /*v[282:289]*/, v[34:41] /*v[290:297]*/, v[14:21] /*v[270:277]*/
early-clobber $vgpr270_vgpr271_vgpr272_vgpr273_vgpr274_vgpr275_vgpr276_vgpr277 = V_WMMA_F32_16X16X32_BF16_w32_twoaddr undef $vgpr282_vgpr283_vgpr284_vgpr285_vgpr286_vgpr287_vgpr288_vgpr289, undef $vgpr290_vgpr291_vgpr292_vgpr293_vgpr294_vgpr295_vgpr296_vgpr297, 8, killed undef $vgpr270_vgpr271_vgpr272_vgpr273_vgpr274_vgpr275_vgpr276_vgpr277, 0, 0, 0, 0, implicit $exec
- ; ASM: NumVgprs: 1024
...
@@ -323,7 +322,6 @@ body: |
; GCN-NEXT: v_dual_fmac_f32 v7 /*v263*/, v1, v1 /*v257*/ :: v_dual_fmamk_f32 v244 /*v500*/, v0, 0xa, v44 /*v300*/
$vgpr263, $vgpr500 = V_DUAL_FMAC_F32_e32_X_FMAMK_F32_gfx1250 undef $vgpr1, undef $vgpr257, $vgpr263, undef $vgpr0, 10, undef $vgpr300, implicit $mode, implicit $exec
- ; ASM: NumVgprs: 777
...
@@ -412,7 +410,6 @@ body: |
; GCN-NEXT: v_fmamk_f16 v5, v2, 0x1, v4
$vgpr5 = V_FMAMK_F16_fake16 undef $vgpr2, 1, undef $vgpr4, implicit $exec, implicit $mode
- ; ASM: NumVgprs: 358
...
@@ -434,7 +431,6 @@ body: |
; GCN-NEXT: v_fmac_f32_e32 v1 /*v257*/, v0, v1
$vgpr257 = V_FMAC_F32_e32 undef $vgpr0, undef $vgpr1, undef $vgpr257, implicit $mode, implicit $exec
- ; ASM: NumVgprs: 258
...
@@ -481,7 +477,6 @@ body: |
; GCN-NEXT: s_set_vgpr_msb 0x100
; ASM-SAME: ; msbs: dst=0 src0=0 src1=0 src2=0
- ; ASM: NumVgprs: 513
...
# ASM-LABEL: {{^}}minimal_mode_change:
@@ -549,7 +544,6 @@ body: |
$vgpr8 = V_MOV_B32_e32 undef $vgpr530, implicit $exec
$vgpr9 = V_ADD_U32_e32 4660, undef $vgpr531, implicit $exec
- ; ASM: NumVgprs: 532
...
@@ -666,7 +660,6 @@ body: |
$vgpr256 = V_MOV_B32_e32 undef $vgpr1, implicit $exec
S_SETPC_B64_return undef $sgpr0_sgpr1, implicit-def $exec
- ; ASM: NumVgprs: 257
...
# ASM-LABEL: {{^}}control_flow:
@@ -737,7 +730,6 @@ body: |
INLINEASM &"; no vgprs, mode preserved", 1, 327690, undef $sgpr0
$vgpr256 = V_MOV_B32_e32 undef $vgpr1, implicit $exec
- ; ASM: NumVgprs: 257
...
# ASM-LABEL: {{^}}bundle:
@@ -763,7 +755,6 @@ body: |
$vgpr1 = V_MOV_B32_e32 $vgpr256, implicit $exec
}
- ; ASM: NumVgprs: 257
...
# ASM-LABEL: {{^}}hard_clauses:
@@ -899,7 +890,6 @@ body: |
$vgpr1 = V_MOV_B32_e32 undef $vgpr1, implicit $exec
}
- ; ASM: NumVgprs: 259
...
# ASM-LABEL: {{^}}pseudo:
@@ -1008,7 +998,6 @@ body: |
; GCN-NEXT: s_set_vgpr_msb 0x4a00
; ASM-SAME: ; msbs: dst=0 src0=0 src1=0 src2=0
- ; ASM: NumVgprs: 514
...
# ASM-LABEL: {{^}}redundant_xcnt:
@@ -1043,3 +1032,34 @@ body: |
; GCN-NEXT: s_set_vgpr_msb 0x400
; ASM-SAME: ; msbs: dst=0 src0=0 src1=0 src2=0
...
+
+# ASM: ; high_vgprs Function info:
+# ASM: NumVgprs: 1024
+# ASM: ; vopd Function info:
+# ASM: NumVgprs: 777
+# ASM: ; fmaak_fmamk Function info:
+# ASM: NumVgprs: 358
+# ASM: ; fmac Function info:
+# ASM: NumVgprs: 258
+# ASM: ; rev_opcodes Function info:
+# ASM: NumVgprs: 513
+# ASM: ; minimal_mode_change Function info:
+# ASM: NumVgprs: 532
+# ASM: ; terminators Function info:
+# ASM: NumVgprs: 257
+# ASM: ; control_flow Function info:
+# ASM: NumVgprs: 259
+# ASM: ; inline_asm Function info:
+# ASM: NumVgprs: 257
+# ASM: ; bundle Function info:
+# ASM: NumVgprs: 257
+# ASM: ; hard_clauses Function info:
+# ASM: NumVgprs: 259
+# ASM: ; pseudo Function info:
+# ASM: NumVgprs: 1
+# ASM: ; ld_scale Function info:
+# ASM: NumVgprs: 516
+# ASM: ; commute_no_piggyback Function info:
+# ASM: NumVgprs: 514
+# ASM: ; redundant_xcnt Function info:
+# ASM: NumVgprs: 258
>From 21508f7689e6b309d7a29009cc670a965b10b9e0 Mon Sep 17 00:00:00 2001
From: Janek van Oirschot <janek.vanoirschot at amd.com>
Date: Mon, 18 May 2026 07:12:18 +0100
Subject: [PATCH 2/4] formatting
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 86 +++++++++------------
1 file changed, 38 insertions(+), 48 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 830bb251411d1..a8ca90bee0b4d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -787,10 +787,11 @@ void AMDGPUAsmPrinter::emitDeferredComments() {
const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F);
MCSymbol *FnSym = TM.getSymbol(&F);
StringRef FuncName = FnSym->getName();
- bool IsMemoryBound = F.getFnAttribute("amdgpu-memory-bound").getValueAsBool();
+ bool IsMemoryBound =
+ F.getFnAttribute("amdgpu-memory-bound").getValueAsBool();
- MCSectionELF *CommentSection = OutContext.getELFSection(
- ".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
+ MCSectionELF *CommentSection =
+ OutContext.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
OutStreamer->switchSection(CommentSection);
if (!AMDGPU::isEntryFunctionCC(F.getCallingConv())) {
@@ -806,9 +807,8 @@ void AMDGPUAsmPrinter::emitDeferredComments() {
->getVariableValue()
: nullptr,
RI.createTotalNumVGPRs(FuncName, OutContext),
- RI.createTotalNumSGPRs(
- FuncName,
- STM.getTargetID().isXnackOnOrAny(), OutContext),
+ RI.createTotalNumSGPRs(FuncName, STM.getTargetID().isXnackOnOrAny(),
+ OutContext),
RI.getSymbol(FuncName, RIK::RIK_PrivateSegSize, OutContext)
->getVariableValue(),
Info.CodeSize, IsMemoryBound);
@@ -818,33 +818,26 @@ void AMDGPUAsmPrinter::emitDeferredComments() {
const SIProgramInfo &PI = Info.ProgInfo;
OutStreamer->emitRawComment(" " + Twine(FuncName) + " Kernel info:", false);
emitCommonFunctionComments(
- PI.NumArchVGPR,
- STM.hasMAIInsts() ? PI.NumAccVGPR : nullptr,
- PI.NumVGPR, PI.NumSGPR, PI.ScratchSize,
- Info.CodeSize, IsMemoryBound);
+ PI.NumArchVGPR, STM.hasMAIInsts() ? PI.NumAccVGPR : nullptr, PI.NumVGPR,
+ PI.NumSGPR, PI.ScratchSize, Info.CodeSize, IsMemoryBound);
- OutStreamer->emitRawComment(
- " FloatMode: " + Twine(PI.FloatMode), false);
- OutStreamer->emitRawComment(
- " IeeeMode: " + Twine(PI.IEEEMode), false);
- OutStreamer->emitRawComment(
- " LDSByteSize: " + Twine(PI.LDSSize) +
- " bytes/workgroup (compile time only)",
- false);
+ OutStreamer->emitRawComment(" FloatMode: " + Twine(PI.FloatMode), false);
+ OutStreamer->emitRawComment(" IeeeMode: " + Twine(PI.IEEEMode), false);
+ OutStreamer->emitRawComment(" LDSByteSize: " + Twine(PI.LDSSize) +
+ " bytes/workgroup (compile time only)",
+ false);
- OutStreamer->emitRawComment(
- " SGPRBlocks: " + getMCExprStr(PI.SGPRBlocks), false);
- OutStreamer->emitRawComment(
- " VGPRBlocks: " + getMCExprStr(PI.VGPRBlocks), false);
+ OutStreamer->emitRawComment(" SGPRBlocks: " + getMCExprStr(PI.SGPRBlocks),
+ false);
+ OutStreamer->emitRawComment(" VGPRBlocks: " + getMCExprStr(PI.VGPRBlocks),
+ false);
- OutStreamer->emitRawComment(
- " NumSGPRsForWavesPerEU: " +
- getMCExprStr(PI.NumSGPRsForWavesPerEU),
- false);
- OutStreamer->emitRawComment(
- " NumVGPRsForWavesPerEU: " +
- getMCExprStr(PI.NumVGPRsForWavesPerEU),
- false);
+ OutStreamer->emitRawComment(" NumSGPRsForWavesPerEU: " +
+ getMCExprStr(PI.NumSGPRsForWavesPerEU),
+ false);
+ OutStreamer->emitRawComment(" NumVGPRsForWavesPerEU: " +
+ getMCExprStr(PI.NumVGPRsForWavesPerEU),
+ false);
if (STM.hasGFX90AInsts()) {
const MCExpr *AdjustedAccum = MCBinaryExpr::createAdd(
@@ -859,33 +852,31 @@ void AMDGPUAsmPrinter::emitDeferredComments() {
OutStreamer->emitRawComment(
" NamedBarCnt: " + getMCExprStr(PI.NamedBarCnt), false);
- OutStreamer->emitRawComment(
- " Occupancy: " + getMCExprStr(PI.Occupancy), false);
+ OutStreamer->emitRawComment(" Occupancy: " + getMCExprStr(PI.Occupancy),
+ false);
bool NeedsWaveLimiter =
F.getFnAttribute("amdgpu-wave-limiter").getValueAsBool();
- OutStreamer->emitRawComment(
- " WaveLimiterHint : " + Twine(NeedsWaveLimiter), false);
+ OutStreamer->emitRawComment(" WaveLimiterHint : " + Twine(NeedsWaveLimiter),
+ false);
- OutStreamer->emitRawComment(
- " COMPUTE_PGM_RSRC2:SCRATCH_EN: " +
- getMCExprStr(PI.ScratchEnable),
- false);
+ OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:SCRATCH_EN: " +
+ getMCExprStr(PI.ScratchEnable),
+ false);
OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:USER_SGPR: " + Twine(PI.UserSGPR), false);
- OutStreamer->emitRawComment(
- " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
- Twine(PI.TrapHandlerEnable),
- false);
+ OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
+ Twine(PI.TrapHandlerEnable),
+ false);
OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:TGID_X_EN: " + Twine(PI.TGIdXEnable), false);
OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:TGID_Y_EN: " + Twine(PI.TGIdYEnable), false);
OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:TGID_Z_EN: " + Twine(PI.TGIdZEnable), false);
- OutStreamer->emitRawComment(
- " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " + Twine(PI.TIdIGCompCount),
- false);
+ OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
+ Twine(PI.TIdIGCompCount),
+ false);
[[maybe_unused]] int64_t PGMRSrc3;
assert(STM.getGeneration() >= AMDGPUSubtarget::GFX10 ||
@@ -1106,9 +1097,8 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
emitDVgprSymbol(MF);
if (isVerbose()) {
- DeferredComments.push_back(
- {&MF.getFunction(), CurrentProgramInfo,
- CurrentProgramInfo.getFunctionCodeSize(MF)});
+ DeferredComments.push_back({&MF.getFunction(), CurrentProgramInfo,
+ CurrentProgramInfo.getFunctionCodeSize(MF)});
if (!MFI->isEntryFunction())
return false;
>From 5644962ef2e9c839fe33b6199452e7e97b2697d8 Mon Sep 17 00:00:00 2001
From: Janek van Oirschot <janek.vanoirschot at amd.com>
Date: Wed, 3 Jun 2026 05:56:14 +0100
Subject: [PATCH 3/4] rebase + partial feedback
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 13 +--
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 6 ++
.../AMDGPU/GlobalISel/flat-scratch-init.ll | 6 +-
.../GlobalISel/llvm.amdgcn.workgroup.id.ll | 6 +-
.../AMDGPU/GlobalISel/non-entry-alloca.ll | 8 +-
llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 +-
.../CodeGen/AMDGPU/agpr-register-count.ll | 20 ++---
.../AMDGPU/amdgpu-no-agprs-violations.ll | 6 +-
.../amdhsa-kernarg-preload-num-sgprs.ll | 8 +-
.../amdpal-metadata-agpr-register-count.ll | 14 ++--
...-amdgpu-flat-work-group-size-vgpr-limit.ll | 6 +-
.../attr-amdgpu-flat-work-group-size.ll | 8 +-
.../AMDGPU/attr-amdgpu-waves-per-eu.ll | 26 +++---
.../AMDGPU/call-graph-register-usage.ll | 50 ++++++------
.../callee-special-input-vgprs-packed.ll | 2 +-
.../AMDGPU/callee-special-input-vgprs.ll | 2 +-
.../AMDGPU/code-size-estimate-gfx1250.ll | 4 +-
.../test/CodeGen/AMDGPU/code-size-estimate.ll | 34 ++++----
.../CodeGen/AMDGPU/code-size-estimate.mir | 14 ++--
llvm/test/CodeGen/AMDGPU/default-fp-mode.ll | 36 ++++-----
llvm/test/CodeGen/AMDGPU/empty-function.ll | 4 +-
llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll | 14 ++--
.../CodeGen/AMDGPU/function-resource-usage.ll | 70 ++++++++--------
.../AMDGPU/gfx11-user-sgpr-init16-bug.ll | 8 +-
.../AMDGPU/greedy-liverange-priority.mir | 4 +-
llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll | 18 ++---
llvm/test/CodeGen/AMDGPU/hsa-func.ll | 2 +-
.../CodeGen/AMDGPU/hsa-metadata-agpr-small.ll | 4 +-
llvm/test/CodeGen/AMDGPU/inline-asm.ll | 36 ++++-----
.../AMDGPU/insert-subvector-unused-scratch.ll | 4 +-
.../test/CodeGen/AMDGPU/inst-prefetch-hint.ll | 6 +-
llvm/test/CodeGen/AMDGPU/ipra.ll | 12 +--
.../CodeGen/AMDGPU/kernarg-stack-alignment.ll | 10 +--
.../CodeGen/AMDGPU/large-alloca-graphics.ll | 4 +-
.../CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll | 12 +--
.../CodeGen/AMDGPU/lds-size-hsa-gfx950.ll | 4 +-
.../AMDGPU/llvm.amdgcn.workgroup.id.ll | 6 +-
llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll | 26 +++---
llvm/test/CodeGen/AMDGPU/merge-stores.ll | 8 +-
.../AMDGPU/module-lds-false-sharing.ll | 6 +-
llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll | 4 +-
llvm/test/CodeGen/AMDGPU/occupancy-levels.ll | 80 +++++++++----------
llvm/test/CodeGen/AMDGPU/perfhint.ll | 18 ++---
.../AMDGPU/promote-alloca-calling-conv.ll | 4 +-
.../CodeGen/AMDGPU/ps-shader-arg-count.ll | 34 ++++----
llvm/test/CodeGen/AMDGPU/recursion.ll | 4 +-
.../CodeGen/AMDGPU/register-count-comments.ll | 4 +-
.../CodeGen/AMDGPU/sgpr-count-graphics.ll | 8 +-
llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll | 4 +-
llvm/test/CodeGen/AMDGPU/spill-agpr.ll | 8 +-
.../test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll | 4 +-
llvm/test/CodeGen/AMDGPU/spill-vgpr.ll | 8 +-
llvm/test/CodeGen/AMDGPU/stack-realign.ll | 8 +-
llvm/test/CodeGen/AMDGPU/trap.ll | 4 +-
.../CodeGen/AMDGPU/unaligned-load-store.ll | 4 +-
.../CodeGen/AMDGPU/vector-alloca-bitcast.ll | 20 ++---
.../CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll | 48 +++++------
.../test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll | 6 +-
.../CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir | 30 +++----
59 files changed, 415 insertions(+), 416 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index a8ca90bee0b4d..9cf3e6f7bbfee 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -796,8 +796,7 @@ void AMDGPUAsmPrinter::emitDeferredComments() {
if (!AMDGPU::isEntryFunctionCC(F.getCallingConv())) {
using RIK = MCResourceInfo::ResourceInfoKind;
- OutStreamer->emitRawComment(" " + Twine(FuncName) + " Function info:",
- false);
+ OutStreamer->emitRawComment(" " + Twine(FuncName) + ":", false);
emitCommonFunctionComments(
RI.getSymbol(FuncName, RIK::RIK_NumVGPR, OutContext)
@@ -816,7 +815,7 @@ void AMDGPUAsmPrinter::emitDeferredComments() {
}
const SIProgramInfo &PI = Info.ProgInfo;
- OutStreamer->emitRawComment(" " + Twine(FuncName) + " Kernel info:", false);
+ OutStreamer->emitRawComment(" " + Twine(FuncName) + ":", false);
emitCommonFunctionComments(
PI.NumArchVGPR, STM.hasMAIInsts() ? PI.NumAccVGPR : nullptr, PI.NumVGPR,
PI.NumSGPR, PI.ScratchSize, Info.CodeSize, IsMemoryBound);
@@ -878,11 +877,6 @@ void AMDGPUAsmPrinter::emitDeferredComments() {
Twine(PI.TIdIGCompCount),
false);
- [[maybe_unused]] int64_t PGMRSrc3;
- assert(STM.getGeneration() >= AMDGPUSubtarget::GFX10 ||
- STM.hasGFX90AInsts() || STM.hasGFX1250Insts() ||
- (PI.ComputePGMRSrc3->evaluateAsAbsolute(PGMRSrc3) &&
- static_cast<uint64_t>(PGMRSrc3) == 0));
if (STM.hasGFX90AInsts()) {
OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: " +
@@ -985,8 +979,7 @@ AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(const MachineFunction &MF,
CurrentProgramInfo.ComputePGMRSrc3->evaluateAsAbsolute(PGM_Rsrc3);
(void)PGM_Rsrc3;
(void)EvaluatableRsrc3;
- assert(STM.getGeneration() >= AMDGPUSubtarget::GFX10 ||
- STM.hasGFX90AInsts() || STM.hasGFX1250Insts() || !EvaluatableRsrc3 ||
+ assert(STM.hasPGMRSrc3() || !EvaluatableRsrc3 ||
static_cast<uint64_t>(PGM_Rsrc3) == 0);
KernelDescriptor.compute_pgm_rsrc3 = CurrentProgramInfo.ComputePGMRSrc3;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index dd89db3419c47..8d6d0bb1edae9 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -313,6 +313,12 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return getGeneration() >= AMDGPUSubtarget::GFX10;
}
+ /// \returns true if the target has the COMPUTE_PGM_RSRC3 register.
+ bool hasPGMRSrc3() const {
+ return getGeneration() >= AMDGPUSubtarget::GFX10 || hasGFX90AInsts() ||
+ hasGFX1250Insts();
+ }
+
/// \returns If target supports ds_read/write_b128 and user enables generation
/// of ds_read/write_b128.
bool useDS128() const { return HasCIInsts && EnableDS128; }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
index 6e50ae0fbeb32..50822e005b853 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
@@ -60,15 +60,15 @@ define amdgpu_kernel void @kernel_no_calls_no_stack() {
ret void
}
-; GCN: ; stack_object_addrspacecast_in_kernel_no_calls Kernel info:
+; GCN: ; stack_object_addrspacecast_in_kernel_no_calls:
; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 6
; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
-; GCN: ; stack_object_in_kernel_no_calls Kernel info:
+; GCN: ; stack_object_in_kernel_no_calls:
; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 4
; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
-; GCN: ; kernel_no_calls_no_stack Kernel info:
+; GCN: ; kernel_no_calls_no_stack:
; GCN: COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 4
; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
index dac3d10116b66..fe907645b73ea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
@@ -86,21 +86,21 @@ define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
-; ALL: ; test_workgroup_id_x Kernel info:
+; ALL: ; test_workgroup_id_x:
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
-; ALL: ; test_workgroup_id_y Kernel info:
+; ALL: ; test_workgroup_id_y:
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
-; ALL: ; test_workgroup_id_z Kernel info:
+; ALL: ; test_workgroup_id_z:
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
index 1359910d01da2..39013770e847d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
@@ -274,11 +274,11 @@ attributes #1 = { nounwind }
; ASSUME1024: {{.*}}
; DEFAULTSIZE: {{.*}}
-; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4 Kernel info:
+; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4:
; DEFAULTSIZE: ; ScratchSize: 16
-; ASSUME1024: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4 Kernel info:
+; ASSUME1024: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4:
; ASSUME1024: ; ScratchSize: 1040
-; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64 Kernel info:
+; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64:
; DEFAULTSIZE: ; ScratchSize: 64
-; ASSUME1024: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64 Kernel info:
+; ASSUME1024: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64:
; ASSUME1024: ; ScratchSize: 1088
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 333cd8abd66a5..3188a992992d7 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -1597,7 +1597,7 @@ attributes #3 = { nounwind "amdgpu-32bit-address-high-bits"="0xffff8000" }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
-; HSA: ; use_group_to_flat_addrspacecast Kernel info:
+; HSA: ; use_group_to_flat_addrspacecast:
; HSA: NumSgprs: {{[0-9]+}}
-; HSA: ; use_private_to_flat_addrspacecast Kernel info:
+; HSA: ; use_private_to_flat_addrspacecast:
; HSA: NumSgprs: {{[0-9]+}}
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
index e364ba97ee3d7..2754738ba5d26 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
@@ -95,7 +95,7 @@ bb:
ret void
}
-; GCN: ; kernel_32_agprs Kernel info:
+; GCN: ; kernel_32_agprs:
; GCN: NumVgprs: 9
; GCN: NumAgprs: 32
; GFX908: TotalNumVgprs: 32
@@ -108,7 +108,7 @@ bb:
; GCN: Occupancy: 8
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2
-; GCN: ; kernel_0_agprs Kernel info:
+; GCN: ; kernel_0_agprs:
; GCN: NumVgprs: 1
; GCN: NumAgprs: 0
; GCN: TotalNumVgprs: 1
@@ -119,7 +119,7 @@ bb:
; GFX90A: Occupancy: 8
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 0
-; GCN: ; kernel_40_vgprs Kernel info:
+; GCN: ; kernel_40_vgprs:
; GCN: NumVgprs: 40
; GCN: NumAgprs: 16
; GFX908: TotalNumVgprs: 40
@@ -133,24 +133,24 @@ bb:
; GFX90A: Occupancy: 8
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 9
-; GCN: ; func_32_agprs Function info:
+; GCN: ; func_32_agprs:
; GCN: NumVgprs: 9
; GCN: NumAgprs: 32
; GFX908: TotalNumVgprs: 32
; GFX90A: TotalNumVgprs: 44
-; GCN: ; func_32_vgprs Function info:
+; GCN: ; func_32_vgprs:
; GCN: NumVgprs: 32
; GCN: NumAgprs: 9
; GFX908: TotalNumVgprs: 32
; GFX90A: TotalNumVgprs: 41
-; GCN: ; func_0_agprs Kernel info:
+; GCN: ; func_0_agprs:
; GCN: NumVgprs: 1
; GCN: NumAgprs: 0
; GCN: TotalNumVgprs: 1
-; GCN: ; kernel_max_gprs Kernel info:
+; GCN: ; kernel_max_gprs:
; GCN: NumVgprs: 256
; GCN: NumAgprs: 256
; GFX908: TotalNumVgprs: 256
@@ -163,7 +163,7 @@ bb:
; GCN: Occupancy: 1
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63
-; GCN: ; kernel_call_func_32_agprs Kernel info:
+; GCN: ; kernel_call_func_32_agprs:
; GCN: NumVgprs: 9
; GCN: NumAgprs: 32
; GFX908: TotalNumVgprs: 32
@@ -176,13 +176,13 @@ bb:
; GCN: Occupancy: 8
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2
-; GCN: ; func_call_func_32_agprs Function info:
+; GCN: ; func_call_func_32_agprs:
; GCN: NumVgprs: 9
; GCN: NumAgprs: 32
; GFX908: TotalNumVgprs: 32
; GFX90A: TotalNumVgprs: 44
-; GCN: ; kernel_call_undef_func Kernel info:
+; GCN: ; kernel_call_undef_func:
; GCN: NumVgprs: 32
; GCN: NumAgprs: 32
; GFX908: TotalNumVgprs: 32
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll
index a02f2b779c5bf..9de43758edfd3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll
@@ -34,13 +34,13 @@ define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32(ptr addrspace(1) %ou
ret void
}
-; CHECK: ; kernel_illegal_agpr_use_asm Kernel info:
+; CHECK: ; kernel_illegal_agpr_use_asm:
; CHECK: NumVgprs: 0
; CHECK: NumAgprs: 1
-; CHECK: ; func_illegal_agpr_use_asm Function info:
+; CHECK: ; func_illegal_agpr_use_asm:
; CHECK: NumVgprs: 0
; CHECK: NumAgprs: 1
-; CHECK: ; kernel_calls_mfma.f32.32x32x1f32 Kernel info:
+; CHECK: ; kernel_calls_mfma.f32.32x32x1f32:
; GFX908: NumVgprs: 5
; GFX908: NumAgprs: 32
; GFX90A: NumVgprs: 35
diff --git a/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll b/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
index bf1befc4bcd7c..27689f807fd57 100644
--- a/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
@@ -85,15 +85,15 @@ define amdgpu_kernel void @many__i32(
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
-; ASM: ; amdhsa_kernarg_preload_4_implicit_6 Kernel info:
+; ASM: ; amdhsa_kernarg_preload_4_implicit_6:
; ASM: ; TotalNumSgprs: 18
; ASM: ; NumSGPRsForWavesPerEU: 18
-; ASM: ; amdhsa_kernarg_preload_8_implicit_2 Kernel info:
+; ASM: ; amdhsa_kernarg_preload_8_implicit_2:
; ASM: ; TotalNumSgprs: 16
; ASM: ; NumSGPRsForWavesPerEU: 16
-; ASM: ; amdhsa_kernarg_preload_1_implicit_2 Kernel info:
+; ASM: ; amdhsa_kernarg_preload_1_implicit_2:
; ASM: ; TotalNumSgprs: 9
; ASM: ; NumSGPRsForWavesPerEU: 9
-; ASM: ; amdhsa_kernarg_preload_0_implicit_2 Kernel info:
+; ASM: ; amdhsa_kernarg_preload_0_implicit_2:
; ASM: ; TotalNumSgprs: 6
; ASM: ; NumSGPRsForWavesPerEU: 6
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll b/llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
index e1c685522d192..0140cd65b38d9 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
@@ -61,19 +61,19 @@ bb:
ret void
}
-; CHECK: ; kernel_32_agprs Kernel info:
+; CHECK: ; kernel_32_agprs:
; CHECK: NumAgprs: 32
-; CHECK: ; kernel_0_agprs Kernel info:
+; CHECK: ; kernel_0_agprs:
; CHECK: NumAgprs: 0
-; CHECK: ; kernel_40_vgprs Kernel info:
+; CHECK: ; kernel_40_vgprs:
; CHECK: NumAgprs: 16
-; CHECK: ; kernel_max_gprs Kernel info:
+; CHECK: ; kernel_max_gprs:
; CHECK: NumAgprs: 256
-; CHECK: ; func_32_agprs Function info:
+; CHECK: ; func_32_agprs:
; CHECK: NumAgprs: 32
-; CHECK: ; kernel_call_func_32_agprs Kernel info:
+; CHECK: ; kernel_call_func_32_agprs:
; CHECK: NumAgprs: 32
-; CHECK: ; kernel_call_undef_func Kernel info:
+; CHECK: ; kernel_call_undef_func:
; CHECK: NumAgprs: 32
; CHECK: .set amdgpu.max_num_agpr, 32
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
index 7dcfdf2cedbb7..2cc7fee81f85c 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
@@ -575,7 +575,7 @@ attributes #1024 = { nounwind "amdgpu-flat-work-group-size"="1024,1024" }
declare void @foo()
-; GCN: ; f256 Kernel info:
+; GCN: ; f256:
; GFX9: NumVgprs: 256
; GFX90A: NumVgprs: 256
; GFX90A: NumAgprs: 0
@@ -588,7 +588,7 @@ declare void @foo()
; GFX11WGP-WAVE64: NumVgprs: 256
; GFX11CU-WAVE32: NumVgprs: 256
; GFX11CU-WAVE64: NumVgprs: 256
-; GCN: ; f512 Kernel info:
+; GCN: ; f512:
; GFX9: NumVgprs: 128
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 128
@@ -601,7 +601,7 @@ declare void @foo()
; GFX11WGP-WAVE64: NumVgprs: 256
; GFX11CU-WAVE32: NumVgprs: 192
; GFX11CU-WAVE64: NumVgprs: 192
-; GCN: ; f1024 Kernel info:
+; GCN: ; f1024:
; GFX9: NumVgprs: 64
; GFX90A: NumVgprs: 64
; GFX90A: NumAgprs: 64
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
index 1c5290422f917..99f98933a79f3 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
@@ -126,22 +126,22 @@ attributes #3 = {"amdgpu-flat-work-group-size"="1024,1024"}
; HSAMD: .max_flat_workgroup_size: 1024
; HSAMD: .name: min_1024_max_1024
-; CHECK: ; min_64_max_64 Kernel info:
+; CHECK: ; min_64_max_64:
; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1
-; CHECK: ; min_64_max_128 Kernel info:
+; CHECK: ; min_64_max_128:
; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1
-; CHECK: ; min_128_max_128 Kernel info:
+; CHECK: ; min_128_max_128:
; CHECK: SGPRBlocks: 8
; CHECK: VGPRBlocks: 7
; CHECK: NumSGPRsForWavesPerEU: 65
; CHECK: NumVGPRsForWavesPerEU: 29
-; CHECK: ; min_1024_max_1024 Kernel info:
+; CHECK: ; min_1024_max_1024:
; CHECK: SGPRBlocks: 8
; CHECK: VGPRBlocks: 10
; CHECK: NumSGPRsForWavesPerEU: 65
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
index cae517a5c4460..e95f8d45d48c5 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
@@ -174,67 +174,67 @@ entry:
}
attributes #12 = {"amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="2,10" "amdgpu-lds-size"="16384"}
-; CHECK: ; empty_exactly_1 Kernel info:
+; CHECK: ; empty_exactly_1:
; CHECK: SGPRBlocks: 12
; CHECK: VGPRBlocks: 32
; CHECK: NumSGPRsForWavesPerEU: 102
; CHECK: NumVGPRsForWavesPerEU: 129
-; CHECK: ; empty_exactly_5 Kernel info:
+; CHECK: ; empty_exactly_5:
; CHECK: SGPRBlocks: 12
; CHECK: VGPRBlocks: 10
; CHECK: NumSGPRsForWavesPerEU: 102
; CHECK: NumVGPRsForWavesPerEU: 41
-; CHECK: ; empty_exactly_10 Kernel info:
+; CHECK: ; empty_exactly_10:
; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1
-; CHECK: ; empty_at_least_1 Kernel info:
+; CHECK: ; empty_at_least_1:
; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1
-; CHECK: ; empty_at_least_5 Kernel info:
+; CHECK: ; empty_at_least_5:
; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1
-; CHECK: ; empty_at_least_10 Kernel info:
+; CHECK: ; empty_at_least_10:
; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1
-; CHECK: ; empty_at_most_5 Kernel info:
+; CHECK: ; empty_at_most_5:
; CHECK: SGPRBlocks: 12
; CHECK: VGPRBlocks: 10
; CHECK: NumSGPRsForWavesPerEU: 102
; CHECK: NumVGPRsForWavesPerEU: 41
-; CHECK: ; empty_at_most_10 Kernel info:
+; CHECK: ; empty_at_most_10:
; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1
-; CHECK: ; empty_between_5_and_10 Kernel info:
+; CHECK: ; empty_between_5_and_10:
; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1
-; CHECK: ; exactly_10 Kernel info:
+; CHECK: ; exactly_10:
; CHECK: SGPRBlocks: 3
; CHECK: VGPRBlocks: 5
; CHECK: NumSGPRsForWavesPerEU: 30
; CHECK: NumVGPRsForWavesPerEU: 24
-; CHECK: ; empty_workitems_exactly_256_waves_exactly_2 Kernel info:
+; CHECK: ; empty_workitems_exactly_256_waves_exactly_2:
; CHECK: SGPRBlocks: 12
; CHECK: VGPRBlocks: 21
; CHECK: NumSGPRsForWavesPerEU: 102
; CHECK: NumVGPRsForWavesPerEU: 85
-; CHECK: ; empty_at_least_2_lds_limited Kernel info:
+; CHECK: ; empty_at_least_2_lds_limited:
; CHECK: SGPRBlocks: 12
; CHECK: VGPRBlocks: 12
; CHECK: NumSGPRsForWavesPerEU: 102
; CHECK: NumVGPRsForWavesPerEU: 49
-; CHECK: ; empty_at_least_2_lds_limited_max_above_achievable Kernel info:
+; CHECK: ; empty_at_least_2_lds_limited_max_above_achievable:
; CHECK: SGPRBlocks: 12
; CHECK: VGPRBlocks: 12
; CHECK: NumSGPRsForWavesPerEU: 102
diff --git a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
index f4d0a1274b9fe..2b1b1b508029c 100644
--- a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
@@ -233,79 +233,79 @@ entry:
ret void
}
-; GCN: ; use_vcc Function info:
+; GCN: ; use_vcc:
; GCN: ; TotalNumSgprs: 34
; GCN: ; NumVgprs: 0
-; GCN: ; indirect_use_vcc Function info:
+; GCN: ; indirect_use_vcc:
; GCN: ; TotalNumSgprs: 36
; GCN: ; NumVgprs: 41
-; GCN: ; indirect_2level_use_vcc_kernel Kernel info:
+; GCN: ; indirect_2level_use_vcc_kernel:
; CI: ; TotalNumSgprs: 38
; VI-NOBUG: ; TotalNumSgprs: 40
; VI-BUG: ; TotalNumSgprs: 96
; GCN: ; NumVgprs: 41
-; GCN: ; use_flat_scratch Function info:
+; GCN: ; use_flat_scratch:
; CI: ; TotalNumSgprs: 36
; VI: ; TotalNumSgprs: 38
; GCN: ; NumVgprs: 0
-; GCN: ; indirect_use_flat_scratch Function info:
+; GCN: ; indirect_use_flat_scratch:
; CI: ; TotalNumSgprs: 38
; VI: ; TotalNumSgprs: 40
; GCN: ; NumVgprs: 41
-; GCN: ; indirect_2level_use_flat_scratch_kernel Kernel info:
+; GCN: ; indirect_2level_use_flat_scratch_kernel:
; CI: ; TotalNumSgprs: 38
; VI-NOBUG: ; TotalNumSgprs: 40
; VI-BUG: ; TotalNumSgprs: 96
; GCN: ; NumVgprs: 41
-; GCN: ; use_10_vgpr Function info:
+; GCN: ; use_10_vgpr:
; GCN: ; NumVgprs: 10
-; GCN: ; indirect_use_10_vgpr Function info:
+; GCN: ; indirect_use_10_vgpr:
; GCN: ; NumVgprs: 41
-; GCN: ; indirect_2_level_use_10_vgpr Kernel info:
+; GCN: ; indirect_2_level_use_10_vgpr:
; GCN: ; NumVgprs: 41
-; GCN: ; use_50_vgpr Function info:
+; GCN: ; use_50_vgpr:
; GCN: ; NumVgprs: 50
-; GCN: ; indirect_use_50_vgpr Function info:
+; GCN: ; indirect_use_50_vgpr:
; GCN: ; NumVgprs: 50
-; GCN: ; use_80_sgpr Function info:
+; GCN: ; use_80_sgpr:
; GCN: ; TotalNumSgprs: 80
-; GCN: ; indirect_use_80_sgpr Function info:
+; GCN: ; indirect_use_80_sgpr:
; GCN: ; TotalNumSgprs: 82
-; GCN: ; indirect_2_level_use_80_sgpr Kernel info:
+; GCN: ; indirect_2_level_use_80_sgpr:
; CI: ; TotalNumSgprs: 84
; VI-NOBUG: ; TotalNumSgprs: 86
; VI-BUG: ; TotalNumSgprs: 96
-; GCN: ; use_stack0 Function info:
+; GCN: ; use_stack0:
; GCN: ScratchSize: 2052
-; GCN: ; use_stack1 Function info:
+; GCN: ; use_stack1:
; GCN: ScratchSize: 404
-; GCN: ; indirect_use_stack Function info:
+; GCN: ; indirect_use_stack:
; GCN: ScratchSize: 2132
-; GCN: ; indirect_2_level_use_stack Kernel info:
+; GCN: ; indirect_2_level_use_stack:
; GCN: ScratchSize: 2132
-; GCN: ; multi_call_use_use_stack Kernel info:
+; GCN: ; multi_call_use_use_stack:
; GCN: ScratchSize: 2052
-; GCN: ; usage_external Kernel info:
+; GCN: ; usage_external:
; GCN: ScratchSize: 16384
;
; GCN-V5: ScratchSize: 0
-; GCN: ; usage_external_recurse Kernel info:
+; GCN: ; usage_external_recurse:
; GCN: ScratchSize: 16384
;
; GCN-V5: ScratchSize: 0
-; GCN: ; direct_recursion_use_stack Function info:
+; GCN: ; direct_recursion_use_stack:
; GCN: ScratchSize: 18448{{$}}
;
; GCN-V5: ScratchSize: 2064{{$}}
-; GCN: ; count_use_sgpr96_external_call Kernel info:
+; GCN: ; count_use_sgpr96_external_call:
; CI: TotalNumSgprs: 84
; VI-BUG: TotalNumSgprs: 96
; GCN: NumVgprs: 50
-; GCN: ; count_use_sgpr160_external_call Kernel info:
+; GCN: ; count_use_sgpr160_external_call:
; CI: TotalNumSgprs: 84
; VI-BUG: TotalNumSgprs: 96
; GCN: NumVgprs: 50
-; GCN: ; count_use_vgpr160_external_call Kernel info:
+; GCN: ; count_use_vgpr160_external_call:
; CI: TotalNumSgprs: 84
; VI-BUG: TotalNumSgprs: 96
; GCN: NumVgprs: 50
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
index ab0cea0ce12ca..2f3fd20152ec7 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
@@ -2106,5 +2106,5 @@ declare i32 @llvm.amdgcn.workitem.id.z() #0
attributes #0 = { nounwind readnone speculatable "amdgpu-flat-work-group-size"="1,512" }
attributes #1 = { nounwind noinline "amdgpu-flat-work-group-size"="1,512" }
-; GCN: ; too_many_args_use_workitem_id_x_stack_yz Function info:
+; GCN: ; too_many_args_use_workitem_id_x_stack_yz:
; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
index b764faa52c2c4..5c1aa0af56b62 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
@@ -1519,5 +1519,5 @@ attributes #2 = { nounwind "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
-; GCN: ; use_workitem_id_x Function info:
+; GCN: ; use_workitem_id_x:
; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
index 5e8e6b70be7ce..1b6b9636e85fc 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
@@ -42,7 +42,7 @@ define i16 @cvt_pk_fp8_f16_v(ptr addrspace(1) %out) {
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1250: {{.*}}
-; GFX1250: ; cvt_pk_bf8_f16_v Function info:
+; GFX1250: ; cvt_pk_bf8_f16_v:
; GFX1250: codeLenInByte = 24
-; GFX1250: ; cvt_pk_fp8_f16_v Function info:
+; GFX1250: ; cvt_pk_fp8_f16_v:
; GFX1250: codeLenInByte = 24
diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll b/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
index ec5222f4b7596..e225d4f8534eb 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
@@ -728,94 +728,94 @@ define i64 @v_add_u64_vop2_literal_64(i64 %x) {
ret i64 %add
}
-; CHECK: ; v_mul_f32_vop2 Function info:
+; CHECK: ; v_mul_f32_vop2:
; NOT-GFX12: codeLenInByte = 12
; GFX1200: codeLenInByte = 28
; GFX1250: codeLenInByte = 16
-; CHECK: ; v_mul_f32_vop2_inline_imm Function info:
+; CHECK: ; v_mul_f32_vop2_inline_imm:
; NOT-GFX12: codeLenInByte = 12
; GFX1200: codeLenInByte = 28
; GFX1250: codeLenInByte = 16
-; CHECK: ; v_mul_f32_vop2_literal Function info:
+; CHECK: ; v_mul_f32_vop2_literal:
; NOT-GFX12: codeLenInByte = 16
; GFX1200: codeLenInByte = 32
; GFX1250: codeLenInByte = 20
-; CHECK: ; v_mul_f32_vop3_src_mods Function info:
+; CHECK: ; v_mul_f32_vop3_src_mods:
; NOT-GFX12: codeLenInByte = 16
; GFX1200: codeLenInByte = 32
; GFX1250: codeLenInByte = 20
-; CHECK: ; v_mul_f32_vop3_src_mods_inline_imm Function info:
+; CHECK: ; v_mul_f32_vop3_src_mods_inline_imm:
; NOT-GFX12: codeLenInByte = 16
; GFX1200: codeLenInByte = 32
; GFX1250: codeLenInByte = 20
-; CHECK: ; v_mul_f32_vop3_src_mods_literal Function info:
+; CHECK: ; v_mul_f32_vop3_src_mods_literal:
; GFX9: codeLenInByte = 24
; GFX10: codeLenInByte = 20
; GFX11: codeLenInByte = 20
; GFX1200: codeLenInByte = 36
; GFX1250: codeLenInByte = 24
-; CHECK: ; v_mul_f32_vop2_frame_index Function info:
+; CHECK: ; v_mul_f32_vop2_frame_index:
; GFX9: codeLenInByte = 20
; GFX10: codeLenInByte = 20
; GFX11: codeLenInByte = 12
; GFX1200: codeLenInByte = 28
; GFX1250: codeLenInByte = 16
-; CHECK: ; v_fma_f32 Function info:
+; CHECK: ; v_fma_f32:
; NOT-GFX12: codeLenInByte = 16
; GFX1200: codeLenInByte = 32
; GFX1250: codeLenInByte = 20
-; CHECK: ; v_fma_f32_src_mods Function info:
+; CHECK: ; v_fma_f32_src_mods:
; NOT-GFX12: codeLenInByte = 16
; GFX1200: codeLenInByte = 32
; GFX1250: codeLenInByte = 20
-; CHECK: ; v_fmac_f32 Function info:
+; CHECK: ; v_fmac_f32:
; GFX9: codeLenInByte = 16
; GFX10: codeLenInByte = 12
; GFX11: codeLenInByte = 12
; GFX1200: codeLenInByte = 28
; GFX1250: codeLenInByte = 16
-; CHECK: ; v_fmaak_f32 Function info:
+; CHECK: ; v_fmaak_f32:
; GFX9: codeLenInByte = 24
; GFX10: codeLenInByte = 16
; GFX11: codeLenInByte = 16
; GFX1200: codeLenInByte = 32
; GFX1250: codeLenInByte = 20
-; CHECK: ; v_fma_k_f32_src_mods Function info:
+; CHECK: ; v_fma_k_f32_src_mods:
; GFX9: codeLenInByte = 24
; GFX10: codeLenInByte = 20
; GFX1100: codeLenInByte = 20
; GFX1150: codeLenInByte = 20
; GFX1200: codeLenInByte = 36
; GFX1250: codeLenInByte = 24
-; CHECK: ; s_fmaak_f32 Kernel info:
+; CHECK: ; s_fmaak_f32:
; GFX9: codeLenInByte = 20
; GFX10: codeLenInByte = 12
; GFX1100: codeLenInByte = 16
; GFX1150: codeLenInByte = 16
; GFX1200: codeLenInByte = 16
; GFX1250: codeLenInByte = 24
-; CHECK: ; v_mul_f64_vop2_literal_32 Function info:
+; CHECK: ; v_mul_f64_vop2_literal_32:
; GFX9: codeLenInByte = 28
; GFX10: codeLenInByte = 20
; GFX1100: codeLenInByte = 20
; GFX1150: codeLenInByte = 20
; GFX1200: codeLenInByte = 32
; GFX1250: codeLenInByte = 20
-; CHECK: ; v_mul_f64_vop2_literal_64 Function info:
+; CHECK: ; v_mul_f64_vop2_literal_64:
; GFX9: codeLenInByte = 32
; GFX10: codeLenInByte = 32
; GFX1100: codeLenInByte = 36
; GFX1150: codeLenInByte = 36
; GFX1200: codeLenInByte = 48
; GFX1250: codeLenInByte = 24
-; CHECK: ; v_add_u64_vop2_literal_32 Function info:
+; CHECK: ; v_add_u64_vop2_literal_32:
; GFX9: codeLenInByte = 20
; GFX10: codeLenInByte = 28
; GFX1100: codeLenInByte = 32
; GFX1150: codeLenInByte = 32
; GFX1200: codeLenInByte = 48
; GFX1250: codeLenInByte = 20
-; CHECK: ; v_add_u64_vop2_literal_64 Function info:
+; CHECK: ; v_add_u64_vop2_literal_64:
; GFX9: codeLenInByte = 20
; GFX10: codeLenInByte = 28
; GFX1100: codeLenInByte = 32
diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir b/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
index adabbd11aa07b..1f90e9c8d497b 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
@@ -129,17 +129,17 @@ body: |
S_ENDPGM 0
...
-# CHECK: ; indirect_mov Function info:
+# CHECK: ; indirect_mov:
# CHECK: ; codeLenInByte = 12
-# CHECK: ; meta Function info:
+# CHECK: ; meta:
# CHECK: ; codeLenInByte = 4
-# CHECK: ; wait_asyncmark_meta Function info:
+# CHECK: ; wait_asyncmark_meta:
# CHECK: ; codeLenInByte = 4
-# CHECK: ; align4 Function info:
+# CHECK: ; align4:
# CHECK: ; codeLenInByte = 16
-# CHECK: ; align8 Function info:
+# CHECK: ; align8:
# CHECK: ; codeLenInByte = 20
-# CHECK: ; align16 Function info:
+# CHECK: ; align16:
# CHECK: ; codeLenInByte = 20
-# CHECK: ; align32 Function info:
+# CHECK: ; align32:
# CHECK: ; codeLenInByte = 36
diff --git a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
index d0696ec1c99a5..1d4dcae8c20d7 100644
--- a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
@@ -152,57 +152,57 @@ attributes #13 = { nounwind denormal_fpenv(ieee, float:preservesign|ieee) }
attributes #14 = { nounwind denormal_fpenv(ieee|preservesign, float:ieee) }
attributes #15 = { nounwind denormal_fpenv(preservesign|ieee, float:ieee) }
-; GCN: ; test_default_si Kernel info:
+; GCN: ; test_default_si:
; GCN: FloatMode: 240
; GCN: IeeeMode: 1
-; GCN: ; test_default_vi Kernel info:
+; GCN: ; test_default_vi:
; GCN: FloatMode: 240
; GCN: IeeeMode: 1
-; GCN: ; test_f64_denormals Kernel info:
+; GCN: ; test_f64_denormals:
; GCN: FloatMode: 240
; GCN: IeeeMode: 1
-; GCNL: ; test_f32_denormals Kernel info:
+; GCNL: ; test_f32_denormals:
; GCNL: FloatMode: 48
; GCN: IeeeMode: 1
-; GCN: ; test_f32_f64_denormals Kernel info:
+; GCN: ; test_f32_f64_denormals:
; GCN: FloatMode: 240
; GCN: IeeeMode: 1
-; GCN: ; test_no_denormals Kernel info:
+; GCN: ; test_no_denormals:
; GCN: FloatMode: 0
; GCN: IeeeMode: 1
-; GCN: ; test_f16_f64_denormals Kernel info:
+; GCN: ; test_f16_f64_denormals:
; GCN: FloatMode: 240
; GCN: IeeeMode: 1
-; GCN: ; test_no_f16_f64_denormals Kernel info:
+; GCN: ; test_no_f16_f64_denormals:
; GCN: FloatMode: 48
; GCN: IeeeMode: 1
-; GCN: ; test_f32_f16_f64_denormals Kernel info:
+; GCN: ; test_f32_f16_f64_denormals:
; GCN: FloatMode: 240
; GCN: IeeeMode: 1
-; GCN: ; test_just_f32_attr_flush Kernel info:
+; GCN: ; test_just_f32_attr_flush:
; GCN: FloatMode: 192
; GCN: IeeeMode: 1
-; GCN: ; test_flush_all_outputs Kernel info:
+; GCN: ; test_flush_all_outputs:
; GCN: FloatMode: 80
; GCN: IeeeMode: 1
-; GCN: ; test_flush_all_inputs Kernel info:
+; GCN: ; test_flush_all_inputs:
; GCN: FloatMode: 160
; GCN: IeeeMode: 1
-; GCN: ; test_flush_f32_inputs Kernel info:
+; GCN: ; test_flush_f32_inputs:
; GCN: FloatMode: 224
; GCN: IeeeMode: 1
-; GCN: ; test_flush_f32_outputs Kernel info:
+; GCN: ; test_flush_f32_outputs:
; GCN: FloatMode: 208
; GCN: IeeeMode: 1
-; GCN: ; test_flush_f64_inputs Kernel info:
+; GCN: ; test_flush_f64_inputs:
; GCN: FloatMode: 176
; GCN: IeeeMode: 1
-; GCN: ; test_flush_f64_outputs Kernel info:
+; GCN: ; test_flush_f64_outputs:
; GCN: FloatMode: 112
; GCN: IeeeMode: 1
-; GCN: ; kill_gs_const Kernel info:
+; GCN: ; kill_gs_const:
; GCN: FloatMode: 240
; GCN: IeeeMode: 0
-; GCN: ; kill_vcc_implicit_def Kernel info:
+; GCN: ; kill_vcc_implicit_def:
; GCN: FloatMode: 240
; GCN: IeeeMode: 0
diff --git a/llvm/test/CodeGen/AMDGPU/empty-function.ll b/llvm/test/CodeGen/AMDGPU/empty-function.ll
index 62099ffecd0b8..d4788bbb53153 100644
--- a/llvm/test/CodeGen/AMDGPU/empty-function.ll
+++ b/llvm/test/CodeGen/AMDGPU/empty-function.ll
@@ -18,7 +18,7 @@ define amdgpu_kernel void @empty_function_unreachable() #0 {
attributes #0 = { nounwind }
-; SI: ; empty_function_ret Kernel info:
+; SI: ; empty_function_ret:
; SI: codeLenInByte = 4
-; SI: ; empty_function_unreachable Kernel info:
+; SI: ; empty_function_unreachable:
; SI: codeLenInByte = 0
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
index 60ef3eb9532ef..d48074bc78527 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
@@ -123,7 +123,7 @@ attributes #0 = { nounwind }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
-; GCN: ; no_vcc_no_flat Kernel info:
+; GCN: ; no_vcc_no_flat:
; CI: ; TotalNumSgprs: 8
; VI-NOXNACK: ; TotalNumSgprs: 8
; HSA-VI-NOXNACK: ; TotalNumSgprs: 8
@@ -134,7 +134,7 @@ attributes #0 = { nounwind }
; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 8
; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 8
-; GCN: ; vcc_no_flat Kernel info:
+; GCN: ; vcc_no_flat:
; CI: ; TotalNumSgprs: 10
; VI-NOXNACK: ; TotalNumSgprs: 10
; HSA-VI-NOXNACK: ; TotalNumSgprs: 10
@@ -145,7 +145,7 @@ attributes #0 = { nounwind }
; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 10
; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 10
-; GCN: ; no_vcc_flat Kernel info:
+; GCN: ; no_vcc_flat:
; CI: ; TotalNumSgprs: 12
; VI-NOXNACK: ; TotalNumSgprs: 14
; HSA-VI-NOXNACK: ; TotalNumSgprs: 24
@@ -156,7 +156,7 @@ attributes #0 = { nounwind }
; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 8
; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 8
-; GCN: ; vcc_flat Kernel info:
+; GCN: ; vcc_flat:
; CI: ; TotalNumSgprs: 12
; VI-NOXNACK: ; TotalNumSgprs: 14
; HSA-VI-NOXNACK: ; TotalNumSgprs: 24
@@ -167,7 +167,7 @@ attributes #0 = { nounwind }
; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 10
; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 10
-; GCN: ; use_flat_scr Kernel info:
+; GCN: ; use_flat_scr:
; CI: NumSgprs: 4
; VI-NOXNACK: NumSgprs: 6
; HSA-VI-NOXNACK: NumSgprs: 24
@@ -178,7 +178,7 @@ attributes #0 = { nounwind }
; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 0
; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 0
-; GCN: ; use_flat_scr_lo Kernel info:
+; GCN: ; use_flat_scr_lo:
; CI: NumSgprs: 4
; VI-NOXNACK: NumSgprs: 6
; HSA-VI-NOXNACK: NumSgprs: 24
@@ -189,7 +189,7 @@ attributes #0 = { nounwind }
; GFX10-ARCH-FLAT-NOXNACK: ; TotalNumSgprs: 0
; GFX10-ARCH-FLAT-XNACK: ; TotalNumSgprs: 0
-; GCN: ; use_flat_scr_hi Kernel info:
+; GCN: ; use_flat_scr_hi:
; CI: NumSgprs: 4
; VI-NOXNACK: NumSgprs: 6
; HSA-VI-NOXNACK: NumSgprs: 24
diff --git a/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll b/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
index a7ac8f5899b23..79704eb99c33e 100644
--- a/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
@@ -580,143 +580,143 @@ define internal void @ctor_func() {
ret void
}
-; GCN: ; use_vcc Function info:
+; GCN: ; use_vcc:
; GCN: TotalNumSgprs: 36
; GCN: NumVgprs: 0
; GCN: ScratchSize: 0
-; GCN: ; indirect_use_vcc Function info:
+; GCN: ; indirect_use_vcc:
; GCN: TotalNumSgprs: 38
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; indirect_2level_use_vcc_kernel Kernel info:
+; GCN: ; indirect_2level_use_vcc_kernel:
; GCN: TotalNumSgprs: 40
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; use_flat_scratch Function info:
+; GCN: ; use_flat_scratch:
; GCN: TotalNumSgprs: 38
; GCN: NumVgprs: 0
; GCN: ScratchSize: 0
-; GCN: ; indirect_use_flat_scratch Function info:
+; GCN: ; indirect_use_flat_scratch:
; GCN: TotalNumSgprs: 40
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; indirect_2level_use_flat_scratch_kernel Kernel info:
+; GCN: ; indirect_2level_use_flat_scratch_kernel:
; GCN: TotalNumSgprs: 40
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; use_10_vgpr Function info:
+; GCN: ; use_10_vgpr:
; GCN: TotalNumSgprs: 36
; GCN: NumVgprs: 10
; GCN: ScratchSize: 0
-; GCN: ; indirect_use_10_vgpr Function info:
+; GCN: ; indirect_use_10_vgpr:
; GCN: TotalNumSgprs: 38
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; indirect_2_level_use_10_vgpr Kernel info:
+; GCN: ; indirect_2_level_use_10_vgpr:
; GCN: TotalNumSgprs: 40
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; use_50_vgpr Function info:
+; GCN: ; use_50_vgpr:
; GCN: TotalNumSgprs: 36
; GCN: NumVgprs: 50
; GCN: ScratchSize: 0
-; GCN: ; indirect_use_50_vgpr Function info:
+; GCN: ; indirect_use_50_vgpr:
; GCN: TotalNumSgprs: 38
; GCN: NumVgprs: 50
; GCN: ScratchSize: 16
-; GCN: ; use_80_sgpr Function info:
+; GCN: ; use_80_sgpr:
; GCN: TotalNumSgprs: 84
; GCN: NumVgprs: 0
; GCN: ScratchSize: 0
-; GCN: ; indirect_use_80_sgpr Function info:
+; GCN: ; indirect_use_80_sgpr:
; GCN: TotalNumSgprs: 84
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; indirect_2_level_use_80_sgpr Kernel info:
+; GCN: ; indirect_2_level_use_80_sgpr:
; GCN: TotalNumSgprs: 86
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; use_stack0 Function info:
+; GCN: ; use_stack0:
; GCN: TotalNumSgprs: 37
; GCN: NumVgprs: 1
; GCN: ScratchSize: 2052
-; GCN: ; use_stack1 Function info:
+; GCN: ; use_stack1:
; GCN: TotalNumSgprs: 37
; GCN: NumVgprs: 1
; GCN: ScratchSize: 404
-; GCN: ; indirect_use_stack Function info:
+; GCN: ; indirect_use_stack:
; GCN: TotalNumSgprs: 38
; GCN: NumVgprs: 41
; GCN: ScratchSize: 2132
-; GCN: ; indirect_2_level_use_stack Kernel info:
+; GCN: ; indirect_2_level_use_stack:
; GCN: TotalNumSgprs: 40
; GCN: NumVgprs: 41
; GCN: ScratchSize: 2132
-; GCN: ; multi_call_use_use_stack Kernel info:
+; GCN: ; multi_call_use_use_stack:
; GCN: TotalNumSgprs: 58
; GCN: NumVgprs: 41
; GCN: ScratchSize: 2052
-; GCN: ; multi_call_with_external Kernel info:
+; GCN: ; multi_call_with_external:
; GCN: TotalNumSgprs: 86
; GCN: NumVgprs: 50
; GCN: ScratchSize: 2052
-; GCN: ; multi_call_with_external_and_duplicates Kernel info:
+; GCN: ; multi_call_with_external_and_duplicates:
; GCN: TotalNumSgprs: 86
; GCN: NumVgprs: 50
; GCN: ScratchSize: 2052
-; GCN: ; usage_external Kernel info:
+; GCN: ; usage_external:
; GCN: TotalNumSgprs: 86
; GCN: NumVgprs: 50
; GCN: ScratchSize: 0
-; GCN: ; usage_external_recurse Kernel info:
+; GCN: ; usage_external_recurse:
; GCN: TotalNumSgprs: 86
; GCN: NumVgprs: 50
; GCN: ScratchSize: 0
-; GCN: ; direct_recursion_use_stack Function info:
+; GCN: ; direct_recursion_use_stack:
; GCN: TotalNumSgprs: 40
; GCN: NumVgprs: 41
; GCN: ScratchSize: 2064
-; GCN: ; usage_direct_recursion Kernel info:
+; GCN: ; usage_direct_recursion:
; GCN: TotalNumSgprs: 42
; GCN: NumVgprs: 41
; GCN: ScratchSize: 2064
-; GCN: ; multi_stage_recurse2 Function info:
+; GCN: ; multi_stage_recurse2:
; GCN: TotalNumSgprs: 38
; GCN: NumVgprs: 48
; GCN: ScratchSize: 32
-; GCN: ; multi_stage_recurse1 Function info:
+; GCN: ; multi_stage_recurse1:
; GCN: TotalNumSgprs: 38
; GCN: NumVgprs: 48
; GCN: ScratchSize: 16
-; GCN: ; usage_multi_stage_recurse Kernel info:
+; GCN: ; usage_multi_stage_recurse:
; GCN: TotalNumSgprs: 40
; GCN: NumVgprs: 48
; GCN: ScratchSize: 16
-; GCN: ; multi_stage_recurse_noattr2 Function info:
+; GCN: ; multi_stage_recurse_noattr2:
; GCN: TotalNumSgprs: 61
; GCN: NumVgprs: 41
; GCN: ScratchSize: 32
-; GCN: ; multi_stage_recurse_noattr1 Function info:
+; GCN: ; multi_stage_recurse_noattr1:
; GCN: TotalNumSgprs: 61
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; usage_multi_stage_recurse_noattrs Kernel info:
+; GCN: ; usage_multi_stage_recurse_noattrs:
; GCN: TotalNumSgprs: 63
; GCN: NumVgprs: 41
; GCN: ScratchSize: 16
-; GCN: ; multi_call_with_multi_stage_recurse Kernel info:
+; GCN: ; multi_call_with_multi_stage_recurse:
; GCN: TotalNumSgprs: 59
; GCN: NumVgprs: 48
; GCN: ScratchSize: 2052
-; GCN: ; count_use_sgpr96_external_call Kernel info:
+; GCN: ; count_use_sgpr96_external_call:
; GCN: TotalNumSgprs: 86
; GCN: NumVgprs: 50
; GCN: ScratchSize: 0
-; GCN: ; count_use_sgpr160_external_call Kernel info:
+; GCN: ; count_use_sgpr160_external_call:
; GCN: TotalNumSgprs: 86
; GCN: NumVgprs: 50
; GCN: ScratchSize: 0
-; GCN: ; count_use_vgpr160_external_call Kernel info:
+; GCN: ; count_use_vgpr160_external_call:
; GCN: TotalNumSgprs: 86
; GCN: NumVgprs: 50
; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll b/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
index 748b473a7b4a5..26abf6d4827f5 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
@@ -197,15 +197,15 @@ attributes #1 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-ld
attributes #2 = { "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
-; GCN: ; minimal_kernel_inputs Kernel info:
+; GCN: ; minimal_kernel_inputs:
; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
-; GCN: ; minimal_kernel_inputs_with_stack Kernel info:
+; GCN: ; minimal_kernel_inputs_with_stack:
; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
-; GCN: ; queue_ptr Kernel info:
+; GCN: ; queue_ptr:
; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 4
-; GCN: ; all_inputs Kernel info:
+; GCN: ; all_inputs:
; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 8
diff --git a/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir b/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
index de53143eee7cf..702b26307b02b 100644
--- a/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
+++ b/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
@@ -99,9 +99,9 @@ body: |
S_ENDPGM 0
...
-# GCN: ; test1 Function info:
+# GCN: ; test1:
# OLD: NumVgprs: 11{{$}}
# NEW: NumVgprs: 7{{$}}
-# GCN: ; test2 Function info:
+# GCN: ; test2:
# OLD: NumVgprs: 7{{$}}
# NEW: NumVgprs: 11{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
index a64c95cd442e8..aa47821cca6fe 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
@@ -94,21 +94,21 @@ attributes #8 = { nounwind "amdgpu-dx10-clamp"="false" "amdgpu-ieee"="false" "ta
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
-; GCN: ; test_default_ci Kernel info:
+; GCN: ; test_default_ci:
; GCN: FloatMode: 240
-; GCN: ; test_default_vi Kernel info:
+; GCN: ; test_default_vi:
; GCN: FloatMode: 240
-; GCN: ; test_f64_denormals Kernel info:
+; GCN: ; test_f64_denormals:
; GCN: FloatMode: 192
-; GCN: ; test_f32_denormals Kernel info:
+; GCN: ; test_f32_denormals:
; GCN: FloatMode: 48
-; GCN: ; test_f32_f64_denormals Kernel info:
+; GCN: ; test_f32_f64_denormals:
; GCN: FloatMode: 240
-; GCN: ; test_no_denormals Kernel info:
+; GCN: ; test_no_denormals:
; GCN: FloatMode: 0
-; GCN: ; test_no_dx10_clamp_vi Kernel info:
+; GCN: ; test_no_dx10_clamp_vi:
; GCN: FloatMode: 240
-; GCN: ; test_no_ieee_mode_vi Kernel info:
+; GCN: ; test_no_ieee_mode_vi:
; GCN: FloatMode: 240
-; GCN: ; test_no_ieee_mode_no_dx10_clamp_vi Kernel info:
+; GCN: ; test_no_ieee_mode_no_dx10_clamp_vi:
; GCN: FloatMode: 240
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-func.ll b/llvm/test/CodeGen/AMDGPU/hsa-func.ll
index ce5a6299225d2..22173d57a0305 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-func.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-func.ll
@@ -66,7 +66,7 @@ entry:
ret void
}
-; HSA: ; {{.*}} Function info:
+; HSA: ; {{.*}}:
; HSA-NOT: COMPUTE_PGM_RSRC2
!llvm.module.flags = !{!0}
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
index 5e5894992107f..aaada1b86034a 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
@@ -17,7 +17,7 @@ bb:
}
; CHECK: .section .AMDGPU.csdata
-; CHECK: ; kernel_32_agprs Kernel info:
+; CHECK: ; kernel_32_agprs:
; GFX908: ; NumVgprs: 9
; GFX908: ; NumAgprs: 32
; GFX908: ; TotalNumVgprs: 32
@@ -28,7 +28,7 @@ bb:
; GFX801: ; NumVgprs: 9
-; CHECK: ; kernel_40_vgprs Kernel info:
+; CHECK: ; kernel_40_vgprs:
; GFX908: ; NumVgprs: 40
; GFX908: ; NumAgprs: 16
; GFX908: ; TotalNumVgprs: 40
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
index 85c97fab37308..da5d1030c3602 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
@@ -351,39 +351,39 @@ define void @mixed_def_sgpr_vgpr_def_asm() {
ret void
}
-; CHECK: ; inline_asm Kernel info:
+; CHECK: ; inline_asm:
; CHECK: codeLenInByte = {{[0-9]+}}
-; CHECK: ; inline_asm_shader Kernel info:
+; CHECK: ; inline_asm_shader:
; CHECK: codeLenInByte = {{[0-9]+}}
-; CHECK: ; branch_on_asm_vgpr Kernel info:
+; CHECK: ; branch_on_asm_vgpr:
; CHECK: codeLenInByte = {{[0-9]+}}
-; CHECK: ; branch_on_asm_sgpr Kernel info:
+; CHECK: ; branch_on_asm_sgpr:
; CHECK: codeLenInByte = {{[0-9]+}}
-; CHECK: ; v_cmp_asm Kernel info:
+; CHECK: ; v_cmp_asm:
; CHECK: codeLenInByte = {{[0-9]+}}
-; CHECK: ; code_size_inline_asm Kernel info:
+; CHECK: ; code_size_inline_asm:
; CHECK: codeLenInByte = 12
-; CHECK: ; code_size_inline_asm_small_inst Kernel info:
+; CHECK: ; code_size_inline_asm_small_inst:
; CHECK: codeLenInByte = 12
-; CHECK: ; code_size_inline_asm_2_inst Kernel info:
+; CHECK: ; code_size_inline_asm_2_inst:
; CHECK: codeLenInByte = 20
-; CHECK: ; code_size_inline_asm_2_inst_extra_newline Kernel info:
+; CHECK: ; code_size_inline_asm_2_inst_extra_newline:
; CHECK: codeLenInByte = 20
-; CHECK: ; code_size_inline_asm_0_inst Kernel info:
+; CHECK: ; code_size_inline_asm_0_inst:
; CHECK: codeLenInByte = 4
-; CHECK: ; code_size_inline_asm_1_comment Kernel info:
+; CHECK: ; code_size_inline_asm_1_comment:
; CHECK: codeLenInByte = 4
-; CHECK: ; code_size_inline_asm_newline_1_comment Kernel info:
+; CHECK: ; code_size_inline_asm_newline_1_comment:
; CHECK: codeLenInByte = 4
-; CHECK: ; code_size_inline_asm_1_comment_newline Kernel info:
+; CHECK: ; code_size_inline_asm_1_comment_newline:
; CHECK: codeLenInByte = 4
-; CHECK: ; code_size_inline_asm_2_comments_line Kernel info:
+; CHECK: ; code_size_inline_asm_2_comments_line:
; CHECK: codeLenInByte = 4
-; CHECK: ; code_size_inline_asm_2_comments_line_nospace Kernel info:
+; CHECK: ; code_size_inline_asm_2_comments_line_nospace:
; CHECK: codeLenInByte = 4
-; CHECK: ; code_size_inline_asm_mixed_comments0 Kernel info:
+; CHECK: ; code_size_inline_asm_mixed_comments0:
; CHECK: codeLenInByte = 20
-; CHECK: ; code_size_inline_asm_mixed_comments1 Kernel info:
+; CHECK: ; code_size_inline_asm_mixed_comments1:
; CHECK: codeLenInByte = 20
-; CHECK: ; code_size_inline_asm_mixed_comments_operands Kernel info:
+; CHECK: ; code_size_inline_asm_mixed_comments_operands:
; CHECK: codeLenInByte = 20
diff --git a/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll b/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
index b85f48363f759..3c7e22a44523b 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
@@ -25,7 +25,7 @@ define amdgpu_kernel void @store_v5i32(ptr addrspace(3) %out, <5 x i32> %a) noun
ret void
}
-; GCN: ; store_v3i32 Kernel info:
+; GCN: ; store_v3i32:
; GCN: ScratchSize: 0
-; GCN: ; store_v5i32 Kernel info:
+; GCN: ; store_v5i32:
; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll b/llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
index 114382bd7b5ad..7a05628ca916a 100644
--- a/llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
+++ b/llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
@@ -64,10 +64,10 @@ bb:
ret void
}
-; GCN: ; large Kernel info:
+; GCN: ; large:
; GFX11: codeLenInByte = 3{{[0-9][0-9]$}}
; GFX12: codeLenInByte = 4{{[0-9][0-9]$}}
-; GCN: ; small Kernel info:
+; GCN: ; small:
; GCN: codeLenInByte = {{[0-9]$}}
-; GCN: ; inline_asm Kernel info:
+; GCN: ; inline_asm:
; GCN: codeLenInByte = 24
diff --git a/llvm/test/CodeGen/AMDGPU/ipra.ll b/llvm/test/CodeGen/AMDGPU/ipra.ll
index 1ac1c281f899f..09982073acdd9 100644
--- a/llvm/test/CodeGen/AMDGPU/ipra.ll
+++ b/llvm/test/CodeGen/AMDGPU/ipra.ll
@@ -126,19 +126,19 @@ attributes #0 = { nounwind }
attributes #1 = { nounwind noinline "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
attributes #2 = { norecurse }
-; GCN: ; kernel Kernel info:
+; GCN: ; kernel:
; GCN: ; NumVgprs: 3
-; GCN: ; func Function info:
+; GCN: ; func:
; GCN: ; NumVgprs: 8
-; GCN: ; kernel_call Kernel info:
+; GCN: ; kernel_call:
; GCN: ; TotalNumSgprs: 37
; GCN: ; NumVgprs: 9
-; GCN: ; func_regular_call Function info:
+; GCN: ; func_regular_call:
; GCN: ; TotalNumSgprs: 34
; GCN: ; NumVgprs: 10
-; GCN: ; func_tail_call Function info:
+; GCN: ; func_tail_call:
; GCN: ; TotalNumSgprs: 32
; GCN: ; NumVgprs: 8
-; GCN: ; func_call_tail_call Function info:
+; GCN: ; func_call_tail_call:
; GCN: ; TotalNumSgprs: 34
; GCN: ; NumVgprs: 10
diff --git a/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll b/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
index 89ad5c9414124..bc78e17314027 100644
--- a/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
@@ -38,13 +38,13 @@ define amdgpu_kernel void @force_align256(<64 x i32>) {
ret void
}
-; CHECK: ; no_args Kernel info:
+; CHECK: ; no_args:
; CHECK: ScratchSize: 8{{$}}
-; CHECK: ; force_align32 Kernel info:
+; CHECK: ; force_align32:
; CHECK: ScratchSize: 8{{$}}
-; CHECK: ; force_align64 Kernel info:
+; CHECK: ; force_align64:
; CHECK: ScratchSize: 8{{$}}
-; CHECK: ; force_align128 Kernel info:
+; CHECK: ; force_align128:
; CHECK: ScratchSize: 8{{$}}
-; CHECK: ; force_align256 Kernel info:
+; CHECK: ; force_align256:
; CHECK: ScratchSize: 8{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll b/llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
index 1ef0d8248ecf4..c648e3260ae03 100644
--- a/llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
+++ b/llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
@@ -54,7 +54,7 @@ define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %
attributes #0 = { nounwind }
-; ALL: ; large_alloca_pixel_shader Kernel info:
+; ALL: ; large_alloca_pixel_shader:
; ALL: ; ScratchSize: 32772
-; ALL: ; large_alloca_pixel_shader_inreg Kernel info:
+; ALL: ; large_alloca_pixel_shader_inreg:
; ALL: ; ScratchSize: 32772
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
index e86cfb84dfb53..b1f63adaf6509 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
@@ -65,15 +65,15 @@ define amdgpu_kernel void @test_lds_array_i32() {
ret void
}
-; GCN: ; test_lds_i8 Kernel info:
+; GCN: ; test_lds_i8:
; GCN: ; LDSByteSize: 1 bytes/workgroup
-; GCN: ; test_lds_i16 Kernel info:
+; GCN: ; test_lds_i16:
; GCN: ; LDSByteSize: 2 bytes/workgroup
-; GCN: ; test_lds_i32 Kernel info:
+; GCN: ; test_lds_i32:
; GCN: ; LDSByteSize: 4 bytes/workgroup
-; GCN: ; test_lds_array_i8 Kernel info:
+; GCN: ; test_lds_array_i8:
; GCN: ; LDSByteSize: 327680 bytes/workgroup
-; GCN: ; test_lds_array_i16 Kernel info:
+; GCN: ; test_lds_array_i16:
; GCN: ; LDSByteSize: 327680 bytes/workgroup
-; GCN: ; test_lds_array_i32 Kernel info:
+; GCN: ; test_lds_array_i32:
; GCN: ; LDSByteSize: 327680 bytes/workgroup
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
index f73e95650eeb7..da7c045cccdf0 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
@@ -28,7 +28,7 @@ define amdgpu_kernel void @test_lds_array_size_163840() {
ret void
}
-; GCN: ; test_lds_array_size_131076 Kernel info:
+; GCN: ; test_lds_array_size_131076:
; GCN: ; LDSByteSize: 131076 bytes/workgroup
-; GCN: ; test_lds_array_size_163840 Kernel info:
+; GCN: ; test_lds_array_size_163840:
; GCN: ; LDSByteSize: 163840 bytes/workgroup
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
index 0d53b6c11b30d..b0f95d4e9a4d6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
@@ -80,21 +80,21 @@ define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
ret void
}
-; ALL: ; test_workgroup_id_x Kernel info:
+; ALL: ; test_workgroup_id_x:
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
-; ALL: ; test_workgroup_id_y Kernel info:
+; ALL: ; test_workgroup_id_y:
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
-; ALL: ; test_workgroup_id_z Kernel info:
+; ALL: ; test_workgroup_id_z:
; MESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 6
; ALL-NOMESA3D: COMPUTE_PGM_RSRC2:USER_SGPR: 2
; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
index 9410e3af8496e..174dbdb75a705 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
@@ -604,29 +604,29 @@ attributes #0 = { nounwind "amdgpu-dynamic-vgpr-block-size"="16" }
attributes #1 = { nounwind "amdgpu-dynamic-vgpr-block-size"="32" }
attributes #2 = { nounwind "amdgpu-dynamic-vgpr-block-size"="0" }
-; CHECK: ; sponentry_cs_dvgpr_16 Kernel info:
+; CHECK: ; sponentry_cs_dvgpr_16:
; CHECK: ScratchSize: 8
-; CHECK: ; sponentry_cs_dvgpr_32 Kernel info:
+; CHECK: ; sponentry_cs_dvgpr_32:
; CHECK: ScratchSize: 8
-; CHECK: ; sponentry_cs_no_dvgpr Kernel info:
+; CHECK: ; sponentry_cs_no_dvgpr:
; CHECK: ScratchSize: 8
-; CHECK: ; sponentry_cs_dvgpr_control_flow Kernel info:
+; CHECK: ; sponentry_cs_dvgpr_control_flow:
; CHECK: ScratchSize: 8
-; CHECK: ; sponentry_cs_dvgpr_calls Kernel info:
+; CHECK: ; sponentry_cs_dvgpr_calls:
; CHECK: ScratchSize: 16
-; CHECK: ; sponentry_cs_dvgpr_realign Kernel info:
+; CHECK: ; sponentry_cs_dvgpr_realign:
; CHECK: ScratchSize: 128
-; CHECK: ; sponentry_gfx Function info:
+; CHECK: ; sponentry_gfx:
; CHECK: ScratchSize: 12
-; CHECK: ; sponentry_gfx_dvgpr_realign Function info:
+; CHECK: ; sponentry_gfx_dvgpr_realign:
; CHECK: ScratchSize: 384
-; CHECK: ; sponentry_gfx_stack_args Function info:
+; CHECK: ; sponentry_gfx_stack_args:
; CHECK: ScratchSize: 12
-; CHECK: ; sponentry_gfx_dyn_alloc Function info:
+; CHECK: ; sponentry_gfx_dyn_alloc:
; CHECK: ScratchSize: 16
-; CHECK: ; sponentry_cs_chain Function info:
+; CHECK: ; sponentry_cs_chain:
; CHECK: ScratchSize: 12
-; CHECK: ; sponentry_cs_chain_dvgpr_realign Function info:
+; CHECK: ; sponentry_cs_chain_dvgpr_realign:
; CHECK: ScratchSize: 384
-; CHECK: ; sponentry_cs_chain_dyn_alloc Function info:
+; CHECK: ; sponentry_cs_chain_dyn_alloc:
; CHECK: ScratchSize: 16
diff --git a/llvm/test/CodeGen/AMDGPU/merge-stores.ll b/llvm/test/CodeGen/AMDGPU/merge-stores.ll
index 798bb47a8d243..47f2c121865af 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-stores.ll
+++ b/llvm/test/CodeGen/AMDGPU/merge-stores.ll
@@ -1254,11 +1254,11 @@ declare void @llvm.amdgcn.s.barrier() #1
attributes #0 = { nounwind }
attributes #1 = { convergent nounwind }
-; GCN: ; merge_global_store_2_constants_i8 Kernel info:
+; GCN: ; merge_global_store_2_constants_i8:
; GCN: ScratchSize: 0{{$}}
-; GCN: ; merge_global_store_2_constants_i8_natural_align Kernel info:
+; GCN: ; merge_global_store_2_constants_i8_natural_align:
; GCN: ScratchSize: 0{{$}}
-; GCN: ; merge_global_store_2_constants_i16 Kernel info:
+; GCN: ; merge_global_store_2_constants_i16:
; GCN: ScratchSize: 0{{$}}
-; GCN: ; merge_global_store_2_constants_0_i16 Kernel info:
+; GCN: ; merge_global_store_2_constants_0_i16:
; GCN: ScratchSize: 0{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
index 2e02dae1c16c9..ba7365ab7c530 100644
--- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
+++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
@@ -227,9 +227,9 @@ define amdgpu_kernel void @nocall_false_sharing() {
ret void
}
-; CHECK: ; nocall_ideal Kernel info:
+; CHECK: ; nocall_ideal:
; CHECK: ; LDSByteSize: 4 bytes
-; CHECK: ; withcall Kernel info:
+; CHECK: ; withcall:
; CHECK: ; LDSByteSize: 16 bytes
-; CHECK: ; nocall_false_sharing Kernel info:
+; CHECK: ; nocall_false_sharing:
; CHECK: ; LDSByteSize: 4 bytes
diff --git a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
index 4a8fe34a169c8..f6b27fc927635 100644
--- a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
+++ b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
@@ -405,11 +405,11 @@ attributes #2 = { nounwind }
; DEFAULTSIZE: {{.*}}
; DEFAULTSIZE-V5: {{.*}}
-; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4 Kernel info:
+; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align4:
; DEFAULTSIZE: ; ScratchSize: 4112
; DEFAULTSIZE-V5: ; ScratchSize: 16
; ASSUME1024: ; ScratchSize: 1040
-; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64 Kernel info:
+; DEFAULTSIZE: ; kernel_non_entry_block_static_alloca_uniformly_reached_align64:
; DEFAULTSIZE: ; ScratchSize: 4160
; DEFAULTSIZE-V5: ; ScratchSize: 64
; ASSUME1024: ; ScratchSize: 1088
diff --git a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
index dd125a1327662..ddec1ebceb001 100644
--- a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
+++ b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
@@ -275,14 +275,14 @@ attributes #8 = { "amdgpu-flat-work-group-size"="1,512" }
attributes #9 = { "amdgpu-flat-work-group-size"="1,1024" }
attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
-; GCN: ; max_occupancy Kernel info:
+; GCN: ; max_occupancy:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; limited_occupancy_3 Kernel info:
+; GCN: ; limited_occupancy_3:
; GFX9: ; Occupancy: 3
; GFX950: ; Occupancy: 3
; GFX10W64: ; Occupancy: 3
@@ -290,28 +290,28 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 3
; GFX1100W32: ; Occupancy: 5
; GFX1250: ; Occupancy: 3
-; GCN: ; limited_occupancy_18 Kernel info:
+; GCN: ; limited_occupancy_18:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 18
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; limited_occupancy_19 Kernel info:
+; GCN: ; limited_occupancy_19:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_24_vgprs Kernel info:
+; GCN: ; used_24_vgprs:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_28_vgprs Kernel info:
+; GCN: ; used_28_vgprs:
; GFX9: ; Occupancy: 9
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 18
@@ -319,7 +319,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_32_vgprs Kernel info:
+; GCN: ; used_32_vgprs:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 16
@@ -327,7 +327,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_36_vgprs Kernel info:
+; GCN: ; used_36_vgprs:
; GFX9: ; Occupancy: 7
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 14
@@ -336,7 +336,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_40_vgprs Kernel info:
+; GCN: ; used_40_vgprs:
; GFX9: ; Occupancy: 6
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 12
@@ -344,7 +344,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_44_vgprs Kernel info:
+; GCN: ; used_44_vgprs:
; GFX9: ; Occupancy: 5
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 11
@@ -353,7 +353,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_48_vgprs Kernel info:
+; GCN: ; used_48_vgprs:
; GFX9: ; Occupancy: 5
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 10
@@ -361,7 +361,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1030W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_56_vgprs Kernel info:
+; GCN: ; used_56_vgprs:
; GFX9: ; Occupancy: 4
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 9
@@ -370,7 +370,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 12
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_64_vgprs Kernel info:
+; GCN: ; used_64_vgprs:
; GFX9: ; Occupancy: 4
; GFX950: ; Occupancy: 8
; GFX10W64: ; Occupancy: 8
@@ -378,7 +378,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 10
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_72_vgprs Kernel info:
+; GCN: ; used_72_vgprs:
; GFX9: ; Occupancy: 3
; GFX950: ; Occupancy: 7
; GFX10W64: ; Occupancy: 7
@@ -387,7 +387,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 10
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 12
-; GCN: ; used_80_vgprs Kernel info:
+; GCN: ; used_80_vgprs:
; GFX9: ; Occupancy: 3
; GFX950: ; Occupancy: 6
; GFX10W64: ; Occupancy: 6
@@ -395,7 +395,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 9
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 12
-; GCN: ; used_84_vgprs Kernel info:
+; GCN: ; used_84_vgprs:
; GFX9: ; Occupancy: 3
; GFX950: ; Occupancy: 5
; GFX1010W64: ; Occupancy: 6
@@ -405,7 +405,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 9
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 10
-; GCN: ; used_88_vgprs Kernel info:
+; GCN: ; used_88_vgprs:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 5
; GFX10W64: ; Occupancy: 5
@@ -414,7 +414,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 8
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 10
-; GCN: ; used_96_vgprs Kernel info:
+; GCN: ; used_96_vgprs:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 5
; GFX10W64: ; Occupancy: 5
@@ -422,7 +422,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 8
; GFX1100W32: ; Occupancy: 16
; GFX1250: ; Occupancy: 10
-; GCN: ; used_100_vgprs Kernel info:
+; GCN: ; used_100_vgprs:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 4
; GFX1010W64: ; Occupancy: 5
@@ -431,7 +431,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 7
; GFX1100W32: ; Occupancy: 12
; GFX1250: ; Occupancy: 9
-; GCN: ; used_112_vgprs Kernel info:
+; GCN: ; used_112_vgprs:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 4
; GFX10W64: ; Occupancy: 4
@@ -439,7 +439,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 6
; GFX1100W32: ; Occupancy: 12
; GFX1250: ; Occupancy: 9
-; GCN: ; used_128_vgprs Kernel info:
+; GCN: ; used_128_vgprs:
; GFX9: ; Occupancy: 2
; GFX950: ; Occupancy: 4
; GFX10W64: ; Occupancy: 4
@@ -447,7 +447,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 5
; GFX1100W32: ; Occupancy: 10
; GFX1250: ; Occupancy: 8
-; GCN: ; used_144_vgprs Kernel info:
+; GCN: ; used_144_vgprs:
; GFX9: ; Occupancy: 1
; GFX950: ; Occupancy: 3
; GFX10W64: ; Occupancy: 3
@@ -455,7 +455,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 5
; GFX1100W32: ; Occupancy: 10
; GFX1250: ; Occupancy: 7
-; GCN: ; used_168_vgprs Kernel info:
+; GCN: ; used_168_vgprs:
; GFX9: ; Occupancy: 1
; GFX950: ; Occupancy: 3
; GFX10W64: ; Occupancy: 3
@@ -464,7 +464,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 4
; GFX1100W32: ; Occupancy: 9
; GFX1250: ; Occupancy: 5
-; GCN: ; used_200_vgprs Kernel info:
+; GCN: ; used_200_vgprs:
; GFX9: ; Occupancy: 1
; GFX950: ; Occupancy: 2
; GFX10W64: ; Occupancy: 2
@@ -473,7 +473,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 3
; GFX1100W32: ; Occupancy: 7
; GFX1250: ; Occupancy: 4
-; GCN: ; used_256_vgprs Kernel info:
+; GCN: ; used_256_vgprs:
; GFX9: ; Occupancy: 1
; GFX950: ; Occupancy: 2
; GFX10W64: ; Occupancy: 2
@@ -481,35 +481,35 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 2
; GFX1100W32: ; Occupancy: 5
; GFX1250: ; Occupancy: 4
-; GCN: ; used_80_sgprs Kernel info:
+; GCN: ; used_80_sgprs:
; GFX9: ; Occupancy: 10
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_88_sgprs Kernel info:
+; GCN: ; used_88_sgprs:
; GFX9: ; Occupancy: 9
; GFX950: ; Occupancy: 8
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_100_sgprs Kernel info:
+; GCN: ; used_100_sgprs:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 7
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_101_sgprs Kernel info:
+; GCN: ; used_101_sgprs:
; GFX9: ; Occupancy: 7
; GFX950: ; Occupancy: 7
; GFX1010: ; Occupancy: 20
; GFX1030: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_lds_6552 Kernel info:
+; GCN: ; used_lds_6552:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 20
@@ -517,7 +517,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX10W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_lds_6556 Kernel info:
+; GCN: ; used_lds_6556:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 20
@@ -525,7 +525,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX10W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_lds_13112 Kernel info:
+; GCN: ; used_lds_13112:
; GFX9: ; Occupancy: 8
; GFX950: ; Occupancy: 8
; GFX1010W64: ; Occupancy: 20
@@ -533,7 +533,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX10W32: ; Occupancy: 16
; GFX1100: ; Occupancy: 16
; GFX1250: ; Occupancy: 16
-; GCN: ; used_lds_8252_max_group_size_64 Kernel info:
+; GCN: ; used_lds_8252_max_group_size_64:
; GFX9: ; Occupancy: 2{{$}}
; GFX950: ; Occupancy: 5{{$}}
; GFX10W64: ; Occupancy: 4{{$}}
@@ -541,7 +541,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 4{{$}}
; GFX1100W32: ; Occupancy: 8{{$}}
; GFX1250: ; Occupancy: 10{{$}}
-; GCN: ; used_lds_8252_max_group_size_96 Kernel info:
+; GCN: ; used_lds_8252_max_group_size_96:
; GFX9: ; Occupancy: 4{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX10W64: ; Occupancy: 8{{$}}
@@ -549,7 +549,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 8{{$}}
; GFX1100W32: ; Occupancy: 12{{$}}
; GFX1250: ; Occupancy: 12{{$}}
-; GCN: ; used_lds_8252_max_group_size_128 Kernel info:
+; GCN: ; used_lds_8252_max_group_size_128:
; GFX9: ; Occupancy: 4{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX10W64: ; Occupancy: 8{{$}}
@@ -557,7 +557,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 8{{$}}
; GFX1100W32: ; Occupancy: 15{{$}}
; GFX1250: ; Occupancy: 16{{$}}
-; GCN: ; used_lds_8252_max_group_size_192 Kernel info:
+; GCN: ; used_lds_8252_max_group_size_192:
; GFX9: ; Occupancy: 6{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX10W64: ; Occupancy: 12{{$}}
@@ -566,7 +566,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 12{{$}}
; GFX1100W32: ; Occupancy: 15{{$}}
; GFX1250: ; Occupancy: 15{{$}}
-; GCN: ; used_lds_8252_max_group_size_256 Kernel info:
+; GCN: ; used_lds_8252_max_group_size_256:
; GFX9: ; Occupancy: 7{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX10W64: ; Occupancy: 15{{$}}
@@ -575,14 +575,14 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1100W64: ; Occupancy: 15{{$}}
; GFX1100W32: ; Occupancy: 16{{$}}
; GFX1250: ; Occupancy: 16{{$}}
-; GCN: ; used_lds_8252_max_group_size_512 Kernel info:
+; GCN: ; used_lds_8252_max_group_size_512:
; GFX9: ; Occupancy: 10{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX1010: ; Occupancy: 20{{$}}
; GFX1030: ; Occupancy: 16{{$}}
; GFX1100: ; Occupancy: 16{{$}}
; GFX1250: ; Occupancy: 16{{$}}
-; GCN: ; used_lds_8252_max_group_size_1024 Kernel info:
+; GCN: ; used_lds_8252_max_group_size_1024:
; GFX9: ; Occupancy: 8{{$}}
; GFX950: ; Occupancy: 8{{$}}
; GFX1010W32: ; Occupancy: 16{{$}}
@@ -590,7 +590,7 @@ attributes #10 = { "amdgpu-flat-work-group-size"="1,32" }
; GFX1030: ; Occupancy: 16{{$}}
; GFX1100: ; Occupancy: 16{{$}}
; GFX1250: ; Occupancy: 16{{$}}
-; GCN: ; used_lds_8252_max_group_size_32 Kernel info:
+; GCN: ; used_lds_8252_max_group_size_32:
; GFX9: ; Occupancy: 2{{$}}
; GFX950: ; Occupancy: 5{{$}}
; GFX10: ; Occupancy: 4{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/perfhint.ll b/llvm/test/CodeGen/AMDGPU/perfhint.ll
index d1faa5aa76bdf..bb40ec66b8264 100644
--- a/llvm/test/CodeGen/AMDGPU/perfhint.ll
+++ b/llvm/test/CodeGen/AMDGPU/perfhint.ll
@@ -473,29 +473,29 @@ declare i32 @llvm.amdgcn.workitem.id.x()
; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
;.
-; GCN: ; test_membound Kernel info:
+; GCN: ; test_membound:
; GCN: MemoryBound: 1
; GCN: WaveLimiterHint : 1
-; GCN: ; test_membound_1 Kernel info:
+; GCN: ; test_membound_1:
; GCN: MemoryBound: 1
-; GCN: ; test_large_stride Kernel info:
+; GCN: ; test_large_stride:
; GCN: MemoryBound: 0
; GCN: WaveLimiterHint : 1
-; GCN: ; test_indirect Kernel info:
+; GCN: ; test_indirect:
; GCN: MemoryBound: 1
; GCN: WaveLimiterHint : 1
-; GCN: ; test_indirect_through_phi Kernel info:
+; GCN: ; test_indirect_through_phi:
; GCN: MemoryBound: 0
; GCN: WaveLimiterHint : 0
-; GCN: ; kernel_call_test_membound_func Kernel info:
+; GCN: ; kernel_call_test_membound_func:
; GCN: MemoryBound: 1
; GCN: WaveLimiterHint : 1
-; GCN: ; kernel_indirect_call Kernel info:
+; GCN: ; kernel_indirect_call:
; GCN: MemoryBound: 0
; GCN: WaveLimiterHint : 0
-; GCN: ; kernel_call_maybe_recursive_test_membound_func Kernel info:
+; GCN: ; kernel_call_maybe_recursive_test_membound_func:
; GCN: MemoryBound: 1
; GCN: WaveLimiterHint : 1
-; GCN: ; kernel_call_mutually_recursive_test_membound_func_0 Kernel info:
+; GCN: ; kernel_call_mutually_recursive_test_membound_func_0:
; GCN: MemoryBound: 1
; GCN: WaveLimiterHint : 1
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
index cd976568cf1f8..030e47f0f82c3 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
@@ -90,11 +90,11 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
; promote_alloca_shaders (Kernel info):
; ASM: ; ScratchSize: 24
; promote_to_vector_call_c (Function info):
-; ASM: ; promote_to_vector_call_c Function info:
+; ASM: ; promote_to_vector_call_c:
; ASM-NOT: LDSByteSize
; ASM: ; ScratchSize: 12
; no_promote_to_lds_c (Function info):
-; ASM: ; no_promote_to_lds_c Function info:
+; ASM: ; no_promote_to_lds_c:
; ASM-NOT: LDSByteSize
; ASM: ; ScratchSize: 24
; call_private (Kernel info):
diff --git a/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll b/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
index 73f6b98555d28..def7e3a147b69 100644
--- a/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
@@ -344,40 +344,40 @@ attributes #1 = { nounwind "InitialPSInputAddr"="2" "target-features"="+wavefron
attributes #2 = { nounwind "InitialPSInputAddr"="0xffff" "target-features"="+wavefrontsize64,+cumode" }
attributes #3 = { nounwind "InitialPSInputAddr"="0" "target-features"="+wavefrontsize64,+cumode" }
-; CHECK: ; _amdgpu_ps_1_arg Kernel info:
+; CHECK: ; _amdgpu_ps_1_arg:
; CHECK: NumVgprs: 4
-; CHECK: ; _amdgpu_ps_3_arg Kernel info:
+; CHECK: ; _amdgpu_ps_3_arg:
; CHECK: NumVgprs: 6
-; CHECK: ; _amdgpu_ps_2_arg_gap Kernel info:
+; CHECK: ; _amdgpu_ps_2_arg_gap:
; CHECK: NumVgprs: 4
-; CHECK: ; _amdgpu_ps_2_arg_no_pack Kernel info:
+; CHECK: ; _amdgpu_ps_2_arg_no_pack:
; CHECK: NumVgprs: 6
-; CHECK: ; _amdgpu_ps_all_arg Kernel info:
+; CHECK: ; _amdgpu_ps_all_arg:
; CHECK: NumVgprs: 24
-; CHECK: ; _amdgpu_ps_all_arg_extra_unused Kernel info:
+; CHECK: ; _amdgpu_ps_all_arg_extra_unused:
; CHECK: NumVgprs: 26
-; CHECK: ; _amdgpu_ps_all_arg_extra Kernel info:
+; CHECK: ; _amdgpu_ps_all_arg_extra:
; CHECK: NumVgprs: 26
; CHECK: NumVGPRsForWavesPerEU: 26
-; CHECK: ; _amdgpu_ps_all_unused Kernel info:
+; CHECK: ; _amdgpu_ps_all_unused:
; CHECK: NumVgprs: 4
-; CHECK: ; _amdgpu_ps_all_unused_ia0 Kernel info:
+; CHECK: ; _amdgpu_ps_all_unused_ia0:
; CHECK: NumVgprs: 4
-; CHECK: ; _amdgpu_ps_all_unused_extra_used Kernel info:
+; CHECK: ; _amdgpu_ps_all_unused_extra_used:
; CHECK: NumVgprs: 4
-; CHECK: ; _amdgpu_ps_part_unused_extra_used Kernel info:
+; CHECK: ; _amdgpu_ps_part_unused_extra_used:
; CHECK: NumVgprs: 5
-; CHECK: ; _amdgpu_ps_part_unused_extra_unused Kernel info:
+; CHECK: ; _amdgpu_ps_part_unused_extra_unused:
; CHECK: NumVgprs: 7
-; CHECK: ; _amdgpu_ps_all_unused_extra_unused Kernel info:
+; CHECK: ; _amdgpu_ps_all_unused_extra_unused:
; CHECK: NumVgprs: 4
-; CHECK: ; _amdgpu_ps_all_unused_extra_used_no_packing Kernel info:
+; CHECK: ; _amdgpu_ps_all_unused_extra_used_no_packing:
; CHECK: NumVgprs: 26
-; CHECK: ; _amdgpu_ps_all_unused_extra_unused_no_packing Kernel info:
+; CHECK: ; _amdgpu_ps_all_unused_extra_unused_no_packing:
; CHECK: NumVgprs: 26
-; CHECK: ; _amdgpu_ps_some_unused_arg_extra Kernel info:
+; CHECK: ; _amdgpu_ps_some_unused_arg_extra:
; CHECK: NumVgprs: 24
; CHECK: NumVGPRsForWavesPerEU: 24
-; CHECK: ; _amdgpu_ps_some_unused_no_packing_arg_extra Kernel info:
+; CHECK: ; _amdgpu_ps_some_unused_no_packing_arg_extra:
;CHECK: NumVgprs: 26
;CHECK: NumVGPRsForWavesPerEU: 26
diff --git a/llvm/test/CodeGen/AMDGPU/recursion.ll b/llvm/test/CodeGen/AMDGPU/recursion.ll
index 591152a7fe256..535991e1de040 100644
--- a/llvm/test/CodeGen/AMDGPU/recursion.ll
+++ b/llvm/test/CodeGen/AMDGPU/recursion.ll
@@ -84,9 +84,9 @@ define amdgpu_kernel void @kernel_calls_tail_recursive_with_stack() {
ret void
}
-; CHECK: ; recursive Function info:
+; CHECK: ; recursive:
; CHECK: ScratchSize: 16
-; CHECK: ; tail_recursive Function info:
+; CHECK: ; tail_recursive:
; CHECK: ScratchSize: 0
!llvm.module.flags = !{!0}
diff --git a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
index 6933779e0f11b..45339f66c3c02 100644
--- a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
+++ b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
@@ -25,9 +25,9 @@ define amdgpu_kernel void @one_vgpr_used(ptr addrspace(1) %out, i32 %x) nounwind
}
; SI: .section .AMDGPU.csdata
-; SI: ; foo Kernel info:
+; SI: ; foo:
; SI: ; TotalNumSgprs: {{[0-9]+}}
; SI: ; NumVgprs: {{[0-9]+}}
-; SI: ; one_vgpr_used Kernel info:
+; SI: ; one_vgpr_used:
; SI: ; TotalNumSgprs: {{[0-9]+}}
; SI: ; NumVgprs: 1
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll b/llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
index 630720388795b..8f74968614822 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
@@ -31,11 +31,11 @@ define amdgpu_ps void @buffer_fat_ptr(ptr addrspace(7) inreg %p) {
ret void
}
-; CHECK: ; vec_of_i1 Kernel info:
+; CHECK: ; vec_of_i1:
; CHECK: TotalNumSgprs: 8
-; CHECK: ; vec_of_i8 Kernel info:
+; CHECK: ; vec_of_i8:
; CHECK: TotalNumSgprs: 4
-; CHECK: ; vec_of_16_bit_ty Kernel info:
+; CHECK: ; vec_of_16_bit_ty:
; CHECK: TotalNumSgprs: 3
-; CHECK: ; buffer_fat_ptr Kernel info:
+; CHECK: ; buffer_fat_ptr:
; CHECK: TotalNumSgprs: 5
diff --git a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
index fe58814fd0115..38ca494f02e55 100644
--- a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
@@ -1689,9 +1689,9 @@ attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }
-; TOVGPR: ; main Kernel info:
+; TOVGPR: ; main:
; TOVGPR: ScratchSize: 0{{$}}
-; TOVGPR: ; main1 Kernel info:
+; TOVGPR: ; main1:
; TOVGPR: ScratchSize: 0{{$}}
!0 = !{!1, !1, i64 0, i32 1}
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr.ll b/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
index e2b3450a436a0..a928611a0a497 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
@@ -488,11 +488,11 @@ attributes #4 = { nounwind "amdgpu-num-vgpr"="6" "amdgpu-no-dispatch-id" "amdgpu
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
-; GCN: ; max_12regs_13a_used Kernel info:
+; GCN: ; max_12regs_13a_used:
; GCN: ScratchSize: 0
-; GCN: ; max_10_vgprs_used_9a Kernel info:
+; GCN: ; max_10_vgprs_used_9a:
; GCN: ScratchSize: 0
-; GCN: ; max_32regs_mfma32 Kernel info:
+; GCN: ; max_32regs_mfma32:
; GCN: ScratchSize: 0
-; GCN: ; max_6regs_used_8a Kernel info:
+; GCN: ; max_6regs_used_8a:
; GCN: ScratchSize: 20
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll b/llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
index 862ec13d15f40..b2de57db98a9e 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
@@ -97,12 +97,12 @@ define amdgpu_kernel void @max_11_vgprs_used_1a_partial_spill(ptr addrspace(1) %
ret void
}
-; GFX908: ; max_11_vgprs_used_9a Kernel info:
+; GFX908: ; max_11_vgprs_used_9a:
; GFX908: NumVgprs: 10
; GFX908: ScratchSize: 0
; GFX908: VGPRBlocks: 2
; GFX908: NumVGPRsForWavesPerEU: 10
-; GFX908: ; max_11_vgprs_used_1a_partial_spill Kernel info:
+; GFX908: ; max_11_vgprs_used_1a_partial_spill:
; GFX908: NumVgprs: 10
; GFX908: ScratchSize: 12
; GFX908: VGPRBlocks: 2
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vgpr.ll b/llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
index 3ef4eba0a1981..43e2b2a64f321 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
@@ -191,7 +191,7 @@ st:
declare i32 @llvm.amdgcn.workitem.id.x()
-; GCN: ; max_11_vgprs Kernel info:
+; GCN: ; max_11_vgprs:
; GFX900: NumVgprs: 11
; GFX908: NumVgprs: 10
; GFX900: ScratchSize: 0
@@ -199,13 +199,13 @@ declare i32 @llvm.amdgcn.workitem.id.x()
; GCN: VGPRBlocks: 2
; GFX900: NumVGPRsForWavesPerEU: 11
; GFX908: NumVGPRsForWavesPerEU: 10
-; GCN: ; max_10_vgprs_spill_v32 Kernel info:
+; GCN: ; max_10_vgprs_spill_v32:
; GFX908: NumVgprs: 10
; GFX900: ScratchSize: 100
; GFX908: ScratchSize: 68
; GFX908: VGPRBlocks: 2
; GFX908: NumVGPRsForWavesPerEU: 10
-; GCN: ; max_256_vgprs_spill_9x32 Kernel info:
+; GCN: ; max_256_vgprs_spill_9x32:
; GFX900: NumVgprs: 256
; GFX900: ScratchSize: 132
; GFX908: NumVgprs: 252
@@ -214,7 +214,7 @@ declare i32 @llvm.amdgcn.workitem.id.x()
; GFX908: VGPRBlocks: 62
; GFX900: NumVGPRsForWavesPerEU: 256
; GFX908: NumVGPRsForWavesPerEU: 252
-; GCN: ; max_256_vgprs_spill_9x32_2bb Kernel info:
+; GCN: ; max_256_vgprs_spill_9x32_2bb:
; GFX900: NumVgprs: 256
; GFX908: NumVgprs: 254
; GFX900: ScratchSize: 132
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
index bd0421b0cdfb8..dce5dd9ab5096 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
@@ -693,11 +693,11 @@ attributes #4 = { noinline nounwind "frame-pointer"="all"}
attributes #5 = { noinline nounwind "amdgpu-waves-per-eu"="6,6" }
attributes #6 = { nounwind }
-; GCN: ; needs_align16_default_stack_align Function info:
+; GCN: ; needs_align16_default_stack_align:
; GCN: ; ScratchSize: 144
-; GCN: ; needs_align16_stack_align4 Function info:
+; GCN: ; needs_align16_stack_align4:
; GCN: ; ScratchSize: 160
-; GCN: ; needs_align32 Function info:
+; GCN: ; needs_align32:
; GCN: ; ScratchSize: 192
-; GCN: ; force_realign4 Function info:
+; GCN: ; force_realign4:
; GCN: ; ScratchSize: 52
diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll
index e7062dc27a4f5..e5a7887735cb7 100644
--- a/llvm/test/CodeGen/AMDGPU/trap.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap.ll
@@ -145,8 +145,8 @@ attributes #1 = { nounwind }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
-; GCN: ; hsa_trap Kernel info:
+; GCN: ; hsa_trap:
; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; NO-HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
-; GCN: ; hsa_debugtrap Kernel info:
+; GCN: ; hsa_debugtrap:
; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
diff --git a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
index ffd7abcdf54df..e0195249f9688 100644
--- a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
@@ -709,7 +709,7 @@ define i32 @load_2xi16_align2(ptr addrspace(1) %p) #0 {
attributes #0 = { nounwind }
-; SI: ; local_unaligned_load_store_i16 Kernel info:
+; SI: ; local_unaligned_load_store_i16:
; SI: ScratchSize: 0{{$}}
-; SI: ; global_unaligned_load_store_i16 Kernel info:
+; SI: ; global_unaligned_load_store_i16:
; SI: ScratchSize: 0{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
index 3954596041233..5b9c4e4555323 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
@@ -409,23 +409,23 @@ declare void @llvm.lifetime.end.p5(i64 immarg, ptr addrspace(5) nocapture)
declare void @llvm.assume(i1)
-; GCN-PROMOTE: ; vector_read_alloca_bitcast Kernel info:
+; GCN-PROMOTE: ; vector_read_alloca_bitcast:
; GCN-PROMOTE: ScratchSize: 0
-; GCN-PROMOTE: ; vector_write_alloca_bitcast Kernel info:
+; GCN-PROMOTE: ; vector_write_alloca_bitcast:
; GCN-PROMOTE: ScratchSize: 0
-; GCN-PROMOTE: ; vector_write_read_bitcast_to_float Kernel info:
+; GCN-PROMOTE: ; vector_write_read_bitcast_to_float:
; GCN-PROMOTE: ScratchSize: 0
-; GCN-PROMOTE: ; vector_write_read_bitcast_to_double Kernel info:
+; GCN-PROMOTE: ; vector_write_read_bitcast_to_double:
; GCN-PROMOTE: ScratchSize: 0
-; GCN-PROMOTE: ; vector_write_read_bitcast_to_i64 Kernel info:
+; GCN-PROMOTE: ; vector_write_read_bitcast_to_i64:
; GCN-PROMOTE: ScratchSize: 0
-; GCN-PROMOTE: ; vector_read_alloca_bitcast_assume Kernel info:
+; GCN-PROMOTE: ; vector_read_alloca_bitcast_assume:
; GCN-PROMOTE: ScratchSize: 0
-; GCN: ; bitcast_vector_to_vector Kernel info:
+; GCN: ; bitcast_vector_to_vector:
; GCN: ScratchSize: 0
-; GCN: ; vector_bitcast_from_alloca_array Kernel info:
+; GCN: ; vector_bitcast_from_alloca_array:
; GCN: ScratchSize: 0
-; GCN: ; vector_bitcast_to_array_from_alloca_array Kernel info:
+; GCN: ; vector_bitcast_to_array_from_alloca_array:
; GCN: ScratchSize: 0
-; GCN: ; vector_bitcast_to_struct_from_alloca_array Kernel info:
+; GCN: ; vector_bitcast_to_struct_from_alloca_array:
; GCN: ScratchSize: 0
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
index 3444bbc8f9834..f5c2daa7addd1 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
@@ -1233,96 +1233,96 @@ define void @f1024_call_no_agprs_ub() #1025 {
attributes #1024 = { nounwind "amdgpu-flat-work-group-size"="1024,1024" }
attributes #1025 = { nounwind "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-agpr-alloc"="0" }
-; GFX90A: ; k256_w8 Kernel info:
+; GFX90A: ; k256_w8:
; GFX90A: NumVgprs: 32
; GFX90A: NumAgprs: 32
; GFX90A: TotalNumVgprs: 64
-; GFX90A: ; k256_w8_no_agprs Kernel info:
+; GFX90A: ; k256_w8_no_agprs:
; GFX90A: NumVgprs: 64
; GFX90A: NumAgprs: 0
; GFX90A: TotalNumVgprs: 64
-; GFX90A: ; k256_w4 Kernel info:
+; GFX90A: ; k256_w4:
; GFX90A: NumVgprs: 64
; GFX90A: NumAgprs: 64
; GFX90A: TotalNumVgprs: 128
-; GFX90A: ; k256_w4_no_agprs Kernel info:
+; GFX90A: ; k256_w4_no_agprs:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 0
; GFX90A: TotalNumVgprs: 128
-; GFX90A: ; k256_w2 Kernel info:
+; GFX90A: ; k256_w2:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 128
; GFX90A: TotalNumVgprs: 256
-; GFX90A: ; k256_w2_no_agprs Kernel info:
+; GFX90A: ; k256_w2_no_agprs:
; GFX90A: NumVgprs: 256
; GFX90A: NumAgprs: 0
; GFX90A: TotalNumVgprs: 256
-; GFX90A: ; k256_w1 Kernel info:
+; GFX90A: ; k256_w1:
; GFX90A: NumVgprs: 256
; GFX90A: NumAgprs: 256
; GFX90A: TotalNumVgprs: 512
-; GFX90A: ; k256_w1_no_agprs Kernel info:
+; GFX90A: ; k256_w1_no_agprs:
; GFX90A: NumVgprs: 256
; GFX90A: NumAgprs: 256
; GFX90A: TotalNumVgprs: 512
-; GFX90A: ; k512_no_agprs Kernel info:
+; GFX90A: ; k512_no_agprs:
; GFX90A: NumVgprs: 256
; GFX90A: NumAgprs: 0
; GFX90A: TotalNumVgprs: 256
-; GFX90A: ; k512_call Kernel info:
+; GFX90A: ; k512_call:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 128
; GFX90A: TotalNumVgprs: 256
-; GFX90A: ; k512_virtual_agpr Kernel info:
+; GFX90A: ; k512_virtual_agpr:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 128
; GFX90A: TotalNumVgprs: 256
-; GFX90A: ; k512_physical_agpr Kernel info:
+; GFX90A: ; k512_physical_agpr:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 128
; GFX90A: TotalNumVgprs: 256
-; GFX90A: ; f512 Function info:
+; GFX90A: ; f512:
; GFX90A: NumVgprs: 12{{[0-9]}}
; GFX90A: NumAgprs: {{[1-9]}}
-; GFX90A: ; f512_no_agpr Function info:
+; GFX90A: ; f512_no_agpr:
; GFX90A: NumVgprs: 256
; GFX90A: NumAgprs: 0
-; GFX90A: ; f512_no_agpr_ub Function info:
+; GFX90A: ; f512_no_agpr_ub:
; GFX90A: NumVgprs: 256
; GFX90A: NumAgprs: 0
-; GFX90A: ; k1024 Kernel info:
+; GFX90A: ; k1024:
; GFX90A: NumVgprs: 64
; GFX90A: NumAgprs: 64
; GFX90A: TotalNumVgprs: 128
-; GFX90A: ; k1024_no_agprs Kernel info:
+; GFX90A: ; k1024_no_agprs:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 0
; GFX90A: TotalNumVgprs: 128
-; GFX90A: ; k1024_call Kernel info:
+; GFX90A: ; k1024_call:
; GFX90A: NumVgprs: 64
; GFX90A: NumAgprs: 64
; GFX90A: TotalNumVgprs: 128
-; GFX90A: ; k1024_call_no_agprs Kernel info:
+; GFX90A: ; k1024_call_no_agprs:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 0
; GFX90A: TotalNumVgprs: 128
-; GFX90A: ; k1024_call_no_agprs_ub_callee Kernel info:
+; GFX90A: ; k1024_call_no_agprs_ub_callee:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 1
; GFX90A: TotalNumVgprs: 129
-; GFX90A: ; f1024_0 Function info:
+; GFX90A: ; f1024_0:
; GFX90A: NumVgprs: 1
; GFX90A: NumAgprs: 1
; GFX90A: TotalNumVgprs: 5
-; GFX90A: ; f1024_1 Function info:
+; GFX90A: ; f1024_1:
; GFX90A: NumVgprs: 64
; GFX90A: NumAgprs: 32
; GFX90A: TotalNumVgprs: 96
-; GFX90A: ; f1024_call_no_agprs Function info:
+; GFX90A: ; f1024_call_no_agprs:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 0
; GFX90A: TotalNumVgprs: 128
-; GFX90A: ; f1024_call_no_agprs_ub Function info:
+; GFX90A: ; f1024_call_no_agprs_ub:
; GFX90A: NumVgprs: 128
; GFX90A: NumAgprs: 0
; GFX90A: TotalNumVgprs: 128
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
index 27148f304b5a6..bbd35af6d00e9 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
@@ -570,14 +570,14 @@ define amdgpu_kernel void @use1024vgprs_codegen(ptr %p) #1281 {
attributes #2561 = { nounwind "amdgpu-flat-work-group-size"="256,256" "amdgpu-waves-per-eu"="1" }
attributes #1281 = { nounwind "amdgpu-flat-work-group-size"="128,128" "amdgpu-waves-per-eu"="1" }
-; GCN: ; k256_w1_asm Kernel info:
+; GCN: ; k256_w1_asm:
; GFX1250: NumVgprs: 256
; GFX1250-NOT: NumAgprs:
; GFX1250-NOT: TotalNumVgprs:
; GFX1250: VGPRBlocks: 15
-; GCN: ; use512vgprs_codegen Kernel info:
+; GCN: ; use512vgprs_codegen:
; GFX1250: NumVgprs: 482
; GFX1250: VGPRBlocks: 30
-; GCN: ; use1024vgprs_codegen Kernel info:
+; GCN: ; use1024vgprs_codegen:
; GFX1250: NumVgprs: 998
; GFX1250: VGPRBlocks: 62
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
index ad6b52dabc949..bd37633cdaba2 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
@@ -1033,33 +1033,33 @@ body: |
; ASM-SAME: ; msbs: dst=0 src0=0 src1=0 src2=0
...
-# ASM: ; high_vgprs Function info:
+# ASM: ; high_vgprs:
# ASM: NumVgprs: 1024
-# ASM: ; vopd Function info:
+# ASM: ; vopd:
# ASM: NumVgprs: 777
-# ASM: ; fmaak_fmamk Function info:
+# ASM: ; fmaak_fmamk:
# ASM: NumVgprs: 358
-# ASM: ; fmac Function info:
+# ASM: ; fmac:
# ASM: NumVgprs: 258
-# ASM: ; rev_opcodes Function info:
+# ASM: ; rev_opcodes:
# ASM: NumVgprs: 513
-# ASM: ; minimal_mode_change Function info:
+# ASM: ; minimal_mode_change:
# ASM: NumVgprs: 532
-# ASM: ; terminators Function info:
+# ASM: ; terminators:
# ASM: NumVgprs: 257
-# ASM: ; control_flow Function info:
+# ASM: ; control_flow:
# ASM: NumVgprs: 259
-# ASM: ; inline_asm Function info:
+# ASM: ; inline_asm:
# ASM: NumVgprs: 257
-# ASM: ; bundle Function info:
+# ASM: ; bundle:
# ASM: NumVgprs: 257
-# ASM: ; hard_clauses Function info:
+# ASM: ; hard_clauses:
# ASM: NumVgprs: 259
-# ASM: ; pseudo Function info:
+# ASM: ; pseudo:
# ASM: NumVgprs: 1
-# ASM: ; ld_scale Function info:
+# ASM: ; ld_scale:
# ASM: NumVgprs: 516
-# ASM: ; commute_no_piggyback Function info:
+# ASM: ; commute_no_piggyback:
# ASM: NumVgprs: 514
-# ASM: ; redundant_xcnt Function info:
+# ASM: ; redundant_xcnt:
# ASM: NumVgprs: 258
>From abbdaac629bdf8e44345988f1dd1632b8ddfbdfa Mon Sep 17 00:00:00 2001
From: Janek van Oirschot <janek.vanoirschot at amd.com>
Date: Wed, 3 Jun 2026 13:17:25 +0100
Subject: [PATCH 4/4] Remove switching csdata section switch
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 4 ----
llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll | 1 -
llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll | 1 -
llvm/test/CodeGen/AMDGPU/register-count-comments.ll | 1 -
4 files changed, 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 9cf3e6f7bbfee..132cfaf2d5cfe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -790,10 +790,6 @@ void AMDGPUAsmPrinter::emitDeferredComments() {
bool IsMemoryBound =
F.getFnAttribute("amdgpu-memory-bound").getValueAsBool();
- MCSectionELF *CommentSection =
- OutContext.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
- OutStreamer->switchSection(CommentSection);
-
if (!AMDGPU::isEntryFunctionCC(F.getCallingConv())) {
using RIK = MCResourceInfo::ResourceInfoKind;
OutStreamer->emitRawComment(" " + Twine(FuncName) + ":", false);
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
index aaada1b86034a..9ad2515e54112 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
@@ -16,7 +16,6 @@ bb:
ret void
}
-; CHECK: .section .AMDGPU.csdata
; CHECK: ; kernel_32_agprs:
; GFX908: ; NumVgprs: 9
; GFX908: ; NumAgprs: 32
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
index 030e47f0f82c3..30cce7433e817 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
@@ -86,7 +86,6 @@ entry:
declare i32 @llvm.amdgcn.workitem.id.x() #1
-; ASM: .section .AMDGPU.csdata
; promote_alloca_shaders (Kernel info):
; ASM: ; ScratchSize: 24
; promote_to_vector_call_c (Function info):
diff --git a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
index 45339f66c3c02..eb17b24ae1e17 100644
--- a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
+++ b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
@@ -24,7 +24,6 @@ define amdgpu_kernel void @one_vgpr_used(ptr addrspace(1) %out, i32 %x) nounwind
ret void
}
-; SI: .section .AMDGPU.csdata
; SI: ; foo:
; SI: ; TotalNumSgprs: {{[0-9]+}}
; SI: ; NumVgprs: {{[0-9]+}}
More information about the llvm-commits
mailing list