[llvm] [RISCV] Allow 64-bit fixed frame-offsets on RV64 (PR #201338)
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Wed Jun 3 05:17:45 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Philipp Rados (prados-oc)
<details>
<summary>Changes</summary>
Some HPC code requires a _very_ large stack. GCC also allows 64-bit frame-offsets on 64-bit systems.
Since RISCVInstrInfo::movImm() supports materializing 64-bit immediates the existing framework already handles the lowering correctly.
This patch only enables support for 64-bit _fixed_ frame offsets. Scalable offsets call TargetLibraryInfo::mulImm() which doesn't seem to support 64-bit calculations yet. This should be fine since there'd have to be more than 2^31 RVV spills for this case to happen.
---
Full diff: https://github.com/llvm/llvm-project/pull/201338.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+3-3)
- (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp (+10-5)
- (added) llvm/test/CodeGen/RISCV/stack-offset-large.ll (+192)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 1be81ea93129a..212abf301f353 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1598,9 +1598,9 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
} else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
// Ensure the base of the RVV stack is correctly aligned: add on the
// alignment padding.
- int ScalarLocalVarSize = MFI.getStackSize() -
- RVFI->getCalleeSavedStackSize() -
- RVFI->getVarArgsSaveSize() + RVFI->getRVVPadding();
+ int64_t ScalarLocalVarSize =
+ MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
+ RVFI->getVarArgsSaveSize() + RVFI->getRVVPadding();
Offset += StackOffset::get(ScalarLocalVarSize, RVFI->getRVVStackSize());
}
return Offset;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 6baa30cf9e6f6..7802c6144f79f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -270,8 +270,12 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
const int64_t NumOfVReg = Offset.getScalable() / 8;
const int64_t FixedOffset = NumOfVReg * VLENB;
if (!isInt<32>(FixedOffset)) {
- reportFatalUsageError(
- "Frame size outside of the signed 32-bit range not supported");
+ // This check might also need to be updated to 64bit.
+ // However mulImm() still assumes 32bit. For now only support fixed
+ // 64bit frame offsets, since scalable offsets would require the number
+ // of spilled registers to exceed 2^31, which is unlikely.
+ reportFatalUsageError("Scalable frame size outside of the signed "
+ "32-bit range not supported");
}
Offset = StackOffset::getFixed(FixedOffset + Offset.getFixed());
}
@@ -561,6 +565,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
+ bool Is64Bit = MF.getSubtarget<RISCVSubtarget>().is64Bit();
DebugLoc DL = MI.getDebugLoc();
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
@@ -571,9 +576,9 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (!IsRVVSpill)
Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
- if (!isInt<32>(Offset.getFixed())) {
- reportFatalUsageError(
- "Frame offsets outside of the signed 32-bit range not supported");
+ if (!Is64Bit && !isInt<32>(Offset.getFixed())) {
+ reportFatalUsageError("Frame offsets outside of the signed 32-bit range "
+ "not supported on RV32");
}
if (!IsRVVSpill) {
diff --git a/llvm/test/CodeGen/RISCV/stack-offset-large.ll b/llvm/test/CodeGen/RISCV/stack-offset-large.ll
new file mode 100644
index 0000000000000..ed422d1fa76d9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/stack-offset-large.ll
@@ -0,0 +1,192 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: not llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s 2>&1 \
+; RUN: | FileCheck %s -check-prefixes=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=RV64
+
+declare void @inspect(...)
+
+; Tests stack addressing when stack-size doesn't fit in 32bit.
+
+; Should fail on 32-bit systems.
+; RV32: LLVM ERROR: Frame offsets outside of the signed 32-bit range not supported on RV32
+
+define void @stack_bigger_than_32bit() {
+; RV64-LABEL: stack_bigger_than_32bit:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -2032
+; RV64-NEXT: .cfi_def_cfa_offset 2032
+; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: lui a0, 524288
+; RV64-NEXT: addiw a0, a0, -2000
+; RV64-NEXT: sub sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa_offset 2147483680
+; RV64-NEXT: li a0, 1
+; RV64-NEXT: slli a0, a0, 31
+; RV64-NEXT: addi a0, a0, 8
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a1, sp, 8
+; RV64-NEXT: call inspect
+; RV64-NEXT: lui a0, 524288
+; RV64-NEXT: addiw a0, a0, -2000
+; RV64-NEXT: add sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa_offset 2032
+; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
+; RV64-NEXT: .cfi_restore ra
+; RV64-NEXT: addi sp, sp, 2032
+; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: ret
+ %p1 = alloca [2 x i64], align 1
+ %p2 = alloca [2147483648 x i8], align 1
+ call void (...) @inspect(ptr %p1, ptr %p2)
+ ret void
+}
+
+
+; Same as previous test, just uses frame-pointer to access fixed objects.
+define void @vla(i64 %n) {
+; RV64-LABEL: vla:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -2032
+; RV64-NEXT: .cfi_def_cfa_offset 2032
+; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: .cfi_offset s0, -16
+; RV64-NEXT: addi s0, sp, 2032
+; RV64-NEXT: .cfi_def_cfa s0, 0
+; RV64-NEXT: lui a1, 524288
+; RV64-NEXT: addiw a1, a1, -1984
+; RV64-NEXT: sub sp, sp, a1
+; RV64-NEXT: slli a0, a0, 2
+; RV64-NEXT: addi a0, a0, 15
+; RV64-NEXT: andi a0, a0, -16
+; RV64-NEXT: sub a2, sp, a0
+; RV64-NEXT: mv sp, a2
+; RV64-NEXT: addi a0, s0, -40
+; RV64-NEXT: li a1, 1
+; RV64-NEXT: slli a1, a1, 31
+; RV64-NEXT: addi a1, a1, 40
+; RV64-NEXT: sub a1, s0, a1
+; RV64-NEXT: call inspect
+; RV64-NEXT: addi sp, s0, -2032
+; RV64-NEXT: .cfi_def_cfa sp, 2032
+; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
+; RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
+; RV64-NEXT: .cfi_restore ra
+; RV64-NEXT: .cfi_restore s0
+; RV64-NEXT: addi sp, sp, 2032
+; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: ret
+ %p1 = alloca [2 x i64], align 1
+ %p2 = alloca [2147483648 x i8], align 1
+ %vla = alloca i32, i64 %n, align 4
+ call void (...) @inspect(ptr %p1, ptr %p2, ptr %vla)
+ ret void
+}
+
+define void @rvv_frame_obj() {
+; RV64-LABEL: rvv_frame_obj:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -2032
+; RV64-NEXT: .cfi_def_cfa_offset 2032
+; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: lui a0, 524288
+; RV64-NEXT: addiw a0, a0, -1984
+; RV64-NEXT: sub sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa_offset 2147483696
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 1
+; RV64-NEXT: sub sp, sp, a0
+; RV64-NEXT: .cfi_escape 0x0f, 0x11, 0x72, 0x00, 0x11, 0xb0, 0x80, 0x80, 0x80, 0x08, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 2147483696 + 2 * vlenb
+; RV64-NEXT: li a0, 1
+; RV64-NEXT: slli a0, a0, 31
+; RV64-NEXT: addi a0, a0, 8
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a1, sp, 8
+; RV64-NEXT: csrr a2, vlenb
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: li a3, 1
+; RV64-NEXT: slli a3, a3, 31
+; RV64-NEXT: addi a3, a3, 32
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: li a3, 1
+; RV64-NEXT: slli a3, a3, 31
+; RV64-NEXT: addi a3, a3, 32
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: call inspect
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 1
+; RV64-NEXT: add sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa sp, 2032
+; RV64-NEXT: lui a0, 524288
+; RV64-NEXT: addiw a0, a0, -1984
+; RV64-NEXT: add sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa_offset 2032
+; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
+; RV64-NEXT: .cfi_restore ra
+; RV64-NEXT: addi sp, sp, 2032
+; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: ret
+ %p1 = alloca [2 x i64], align 1
+ %p2 = alloca [2147483648 x i8], align 1
+ %vector1 = alloca <vscale x 1 x i64>, align 1
+ %vector2 = alloca <vscale x 1 x i64>, align 1
+ call void (...) @inspect(ptr %p1, ptr %p2, ptr %vector1, ptr %vector2)
+ ret void
+}
+
+define <vscale x 1 x i64> @rvv_spill(<vscale x 1 x i64> %vector) {
+; RV64-LABEL: rvv_spill:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -2032
+; RV64-NEXT: .cfi_def_cfa_offset 2032
+; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: lui a0, 524288
+; RV64-NEXT: addiw a0, a0, -1968
+; RV64-NEXT: sub sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa_offset 2147483712
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: sub sp, sp, a0
+; RV64-NEXT: .cfi_escape 0x0f, 0x11, 0x72, 0x00, 0x11, 0xc0, 0x80, 0x80, 0x80, 0x08, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 2147483712 + 1 * vlenb
+; RV64-NEXT: li a0, 1
+; RV64-NEXT: slli a0, a0, 31
+; RV64-NEXT: addi a0, a0, 48
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: #APP
+; RV64-NEXT: #NO_APP
+; RV64-NEXT: li a0, 1
+; RV64-NEXT: slli a0, a0, 31
+; RV64-NEXT: addi a0, a0, 24
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a1, sp, 24
+; RV64-NEXT: call inspect
+; RV64-NEXT: li a0, 1
+; RV64-NEXT: slli a0, a0, 31
+; RV64-NEXT: addi a0, a0, 48
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: add sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa sp, 2032
+; RV64-NEXT: lui a0, 524288
+; RV64-NEXT: addiw a0, a0, -1968
+; RV64-NEXT: add sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa_offset 2032
+; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
+; RV64-NEXT: .cfi_restore ra
+; RV64-NEXT: addi sp, sp, 2032
+; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: ret
+ call void asm sideeffect "",
+ "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
+
+ %p1 = alloca [2 x i64], align 1
+ %p2 = alloca [2147483648 x i8], align 1
+ call void (...) @inspect(ptr %p1, ptr %p2)
+ ret <vscale x 1 x i64> %vector
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/201338
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