[llvm] [CodeGen][AMDGPU] Remove premature empty subrange elimination (PR #201263)
Steffen Larsen via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 3 05:12:23 PDT 2026
https://github.com/steffenlarsen updated https://github.com/llvm/llvm-project/pull/201263
>From 900d5e5ad3e2ab38338b4dcd9d31147408c4d83c Mon Sep 17 00:00:00 2001
From: Steffen Holst Larsen <sholstla at amd.com>
Date: Tue, 2 Jun 2026 09:52:02 -0500
Subject: [PATCH 1/2] [CodeGen][AMDGPU] Remove premature empty subrange
elimination
This commit removes a call to `removeEmptySubRanges` inside
`SplitEditor::rewriteAssigned` which removes empty subranges that may be
expected at a later stage. The empty subranges are eliminated by a later
call to `removeEmptySubRanges`.
Fixes https://github.com/llvm/llvm-project/issues/199337.
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
---
llvm/lib/CodeGen/SplitKit.cpp | 1 -
.../splitkit-getsubrangeformask-phi-extend.ll | 1524 +++++++++++++++++
2 files changed, 1524 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index d8da81c307f31..7dbd9b5f31d56 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -1477,7 +1477,6 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
if (!LI.hasSubRanges())
continue;
LI.clear();
- LI.removeEmptySubRanges();
LIS.constructMainRangeFromSubranges(LI);
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
new file mode 100644
index 0000000000000..388633fe5bb56
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
@@ -0,0 +1,1524 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stop-after=greedy,2 < %s | FileCheck %s
+
+declare <16 x i63> @llvm.masked.load.v16i63.p0(ptr, <16 x i1>, <16 x i63>)
+
+define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
+ ; CHECK-LABEL: name: f
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr63, $sgpr30_sgpr31
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr34, 0, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr34, $vgpr63, 0, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr35, 1, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr35, $vgpr63, 1, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr36, 2, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr36, $vgpr63, 2, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr37, 3, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr37, $vgpr63, 3, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr38, 4, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr38, $vgpr63, 4, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr39, 5, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr39, $vgpr63, 5, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr48, 6, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr48, $vgpr63, 6, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr49, 7, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr49, $vgpr63, 7, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr50, 8, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr50, $vgpr63, 8, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr51, 9, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr51, $vgpr63, 9, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr52, 10, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr52, $vgpr63, 10, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr53, 11, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr53, $vgpr63, 11, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr54, 12, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr54, $vgpr63, 12, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr55, 13, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr55, $vgpr63, 13, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr30, 14, $vgpr63, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 15, $vgpr63, implicit killed $sgpr30_sgpr31
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr63, 14, 32, $vgpr63, 15, 32
+ ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr30
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY]], %stack.16, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.16, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr29
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY1]], %stack.18, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.18, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr28
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY2]], %stack.31, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.31, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr27
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY3]], %stack.19, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.19, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY4:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr26
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY4]], %stack.20, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.20, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY5:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr25
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY5]], %stack.22, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.22, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY6:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr24
+ ; CHECK-NEXT: undef [[COPY7:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr23
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY7]], %stack.21, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.21, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY8:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr22
+ ; CHECK-NEXT: undef [[COPY9:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr21
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY9]], %stack.23, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.23, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY10:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr20
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY10]], %stack.24, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.24, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY11:%[0-9]+]].sub2:av_128_align2 = COPY $vgpr19
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]].sub0:av_128_align2 = COPY $vgpr18
+ ; CHECK-NEXT: undef [[COPY12:%[0-9]+]].sub0:av_128_align2 = COPY [[COPY11]].sub0 {
+ ; CHECK-NEXT: internal [[COPY12]].sub2:av_128_align2 = COPY [[COPY11]].sub2
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: SI_SPILL_AV128_SAVE [[COPY12]], %stack.26, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.26, align 4, addrspace 5)
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY $vgpr17
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY $vgpr16
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY $vgpr15
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY $vgpr14
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY $vgpr13
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY $vgpr12
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY $vgpr11
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY $vgpr10
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY $vgpr9
+ ; CHECK-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; CHECK-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY $vgpr7
+ ; CHECK-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY $vgpr6
+ ; CHECK-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; CHECK-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; CHECK-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; CHECK-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; CHECK-NEXT: undef [[COPY29:%[0-9]+]].sub1:av_64_align2 = COPY $vgpr1
+ ; CHECK-NEXT: [[COPY29:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr0
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY29]], %stack.25, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.25, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.164, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.164, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.165, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.165, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.166, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.166, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.167, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.167, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN4:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.168, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.168, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN5:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.169, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.169, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN6:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.170, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.170, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN7:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.171, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.171, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN8:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.172, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.172, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN9:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.173, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.173, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN10:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.174, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.174, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN11:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.175, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.175, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN12:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.176, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.176, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN13:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.177, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.177, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN14:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.178, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.178, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN15:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.179, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.179, align 4, addrspace 5)
+ ; CHECK-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY13]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY14]], implicit $exec
+ ; CHECK-NEXT: renamable $vcc = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_2:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_3:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN1]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_4:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN2]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_5:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN3]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_6:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN4]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_7:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN5]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_8:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN6]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_9:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN7]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_10:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN8]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_11:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN9]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_12:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN10]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_13:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN11]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_14:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN12]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_15:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN13]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_16:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN14]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_17:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN15]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr40_sgpr41 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_2]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr44_sgpr45 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_3]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr26_sgpr27 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_4]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr42_sgpr43 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_5]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr22_sgpr23 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_6]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr28_sgpr29 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_7]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr18_sgpr19 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_8]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr24_sgpr25 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_9]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr14_sgpr15 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_10]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr20_sgpr21 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_11]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr10_sgpr11 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_12]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr16_sgpr17 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_13]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr6_sgpr7 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_14]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr12_sgpr13 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_15]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr8_sgpr9 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_16]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_17]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr56_sgpr57 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_1]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_18:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY15]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr58_sgpr59 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_18]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_19:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY16]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr60_sgpr61 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_19]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_20:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY17]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr62_sgpr63 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_20]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_21:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY18]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr72_sgpr73 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_21]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_22:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY19]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr74_sgpr75 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_22]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_23:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY20]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr76_sgpr77 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_23]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_24:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY21]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr78_sgpr79 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_24]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_25:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY22]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr88_sgpr89 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_25]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_26:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY23]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr90_sgpr91 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_26]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_27:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY24]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr92_sgpr93 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_27]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_28:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY25]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr94_sgpr95 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_28]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_29:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY26]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr30_sgpr31 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_29]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_30:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY27]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr34_sgpr35 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_30]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_31:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY28]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_31]], implicit $exec
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub31:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.100, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.100, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.101, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.101, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub29:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.102, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.102, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.103, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.103, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub27:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.104, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.104, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.105, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.105, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN %fixed-stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8) from %fixed-stack.0, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.1, addrspace 5)
+ ; CHECK-NEXT: [[V_AND_B32_e32_32:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_UBYTE_OFFEN]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr46_sgpr47 = V_CMP_NE_U32_e64 1, [[V_AND_B32_e32_32]], implicit $exec
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub25:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.106, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.106, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub24:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.107, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.107, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub23:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.108, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.108, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub22:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.109, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.109, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub21:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.110, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.110, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub20:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.111, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.111, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub19:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.112, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.112, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub18:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.113, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.113, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub17:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.114, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.114, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub16:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.115, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.115, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub15:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.116, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.116, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub14:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.117, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.117, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub13:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.118, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.118, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub12:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.119, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.119, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub11:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.120, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.120, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub10:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.121, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.121, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub9:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.122, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.122, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub8:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.123, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.123, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub7:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.124, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.124, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub6:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.125, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.125, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub5:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.126, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.126, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub4:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.127, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.127, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub3:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.128, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.128, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub2:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.129, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.129, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub1:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.130, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.130, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub0:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.131, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.131, addrspace 5)
+ ; CHECK-NEXT: SI_SPILL_AV1024_SAVE [[BUFFER_LOAD_DWORD_OFFEN]], %stack.15, $sgpr32, 0, implicit $exec :: (store (s1024) into %stack.15, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub31:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.132, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.132, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.133, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.133, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub29:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.134, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.134, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.135, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.135, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub27:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.136, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.136, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.137, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.137, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub25:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.138, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.138, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub24:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.139, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.139, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub23:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.140, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.140, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub22:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.141, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.141, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub21:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.142, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.142, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub20:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.143, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.143, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub19:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.144, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.144, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub18:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.145, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.145, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub17:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.146, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.146, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub16:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.147, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.147, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub15:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.148, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.148, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub14:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.149, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.149, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub13:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.150, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.150, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub12:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.151, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.151, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub11:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.152, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.152, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub10:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.153, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.153, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub9:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.154, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.154, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub8:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.155, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.155, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub7:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.156, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.156, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub6:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.157, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.157, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub5:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.158, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.158, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub4:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.159, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.159, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub3:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.160, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.160, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub2:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.161, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.161, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub1:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.162, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.162, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub0:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.163, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.163, addrspace 5)
+ ; CHECK-NEXT: SI_SPILL_AV1024_SAVE [[BUFFER_LOAD_DWORD_OFFEN2]], %stack.17, $sgpr32, 0, implicit $exec :: (store (s1024) into %stack.17, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.20, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.20, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.21, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.21, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.22, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.22, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub24:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.23, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.23, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub22:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.24, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.24, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub20:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.25, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.25, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub18:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.26, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.26, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub16:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.27, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.27, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub14:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.28, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.28, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub12:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.29, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.29, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub10:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.30, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.30, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub8:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.31, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.31, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub6:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.32, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.32, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub4:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.33, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.33, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub1:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub3:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub5:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub7:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub9:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub11:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub13:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub15:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub17:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub19:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub21:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub23:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub25:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub27:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub29:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub31:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub2:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.34, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub0:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.35, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.35, addrspace 5)
+ ; CHECK-NEXT: SI_SPILL_AV1024_SAVE [[BUFFER_LOAD_DWORD_OFFEN3]], %stack.33, $sgpr32, 0, implicit $exec :: (store (s1024) into %stack.33, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN4:%[0-9]+]].sub0:vreg_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.95, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.95, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN4:%[0-9]+]].sub1:vreg_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY30:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY30:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.96, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.96, align 8, addrspace 5)
+ ; CHECK-NEXT: [[COPY31:%[0-9]+]]:av_64_align2 = COPY [[COPY30]]
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN5:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.94, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.94, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN5:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY32:%[0-9]+]]:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN5]]
+ ; CHECK-NEXT: undef [[COPY33:%[0-9]+]].sub1:vreg_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY33:%[0-9]+]].sub0:vreg_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.97, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.97, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN6:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.93, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.93, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN6:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY34:%[0-9]+]]:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN6]]
+ ; CHECK-NEXT: undef [[COPY35:%[0-9]+]].sub3:vreg_128_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub2:vreg_128_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.98, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.98, align 16, addrspace 5)
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub0:vreg_128_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.99, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.99, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY36:%[0-9]+]].sub1:vreg_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY36:%[0-9]+]].sub0:vreg_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.92, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.92, align 8, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN7:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.88, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.88, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN7:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY37:%[0-9]+]]:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN7]]
+ ; CHECK-NEXT: undef [[COPY38:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY38:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.89, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.89, addrspace 5)
+ ; CHECK-NEXT: [[COPY39:%[0-9]+]]:av_64_align2 = COPY [[COPY38]]
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN8:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.87, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.87, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN8:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[BUFFER_LOAD_DWORD_OFFEN8]], %stack.27, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.27, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY40:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY40:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.90, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.90, align 16, addrspace 5)
+ ; CHECK-NEXT: [[COPY41:%[0-9]+]]:av_64_align2 = COPY [[COPY40]]
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN9:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.86, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.86, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN9:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[BUFFER_LOAD_DWORD_OFFEN9]], %stack.28, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.28, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY42:%[0-9]+]].sub1:vreg_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY42:%[0-9]+]].sub0:vreg_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.91, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.91, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY43:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: [[COPY43:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.85, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.85, addrspace 5)
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY43]], %stack.29, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.29, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN10:%[0-9]+]].sub1:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.2, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.2, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN10:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.3, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.3, addrspace 5)
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[BUFFER_LOAD_DWORD_OFFEN10]], %stack.34, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.34, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN11:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.196, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.196, align 8, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY44:%[0-9]+]].sub0:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN11]].sub0
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN12:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.197, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.197, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY45:%[0-9]+]].sub0:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN12]].sub0
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN13:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.198, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.198, align 16, addrspace 5)
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[BUFFER_LOAD_DWORD_OFFEN13]], %stack.30, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.30, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN14:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.84, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.84, align 8, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY46:%[0-9]+]].sub30:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN14]].sub30
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN15:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.52, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.52, align 8, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY47:%[0-9]+]].sub30:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN15]].sub30
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN16:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.53, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.53, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY48:%[0-9]+]].sub28:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN16]].sub28
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN17:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.54, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.54, align 16, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY49:%[0-9]+]].sub26:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN17]].sub26
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN18:%[0-9]+]].sub24:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.55, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.55, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY50:%[0-9]+]].sub24:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN18]].sub24
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN19:%[0-9]+]].sub22:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.56, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.56, align 8, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY51:%[0-9]+]].sub22:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN19]].sub22
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN20:%[0-9]+]].sub20:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.57, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.57, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN21:%[0-9]+]].sub18:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.58, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.58, align 16, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY52:%[0-9]+]].sub18:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN21]].sub18
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN22:%[0-9]+]].sub16:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.59, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.59, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN23:%[0-9]+]].sub14:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.60, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.60, align 8, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN24:%[0-9]+]].sub12:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.61, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.61, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN25:%[0-9]+]].sub10:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.62, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.62, align 16, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN26:%[0-9]+]].sub8:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.63, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.63, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN27:%[0-9]+]].sub6:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.64, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.64, align 8, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN28:%[0-9]+]].sub4:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.65, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.65, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN29:%[0-9]+]].sub2:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.66, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.66, align 16, addrspace 5)
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN30:%[0-9]+]].sub0:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.67, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.67, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY53:%[0-9]+]].sub1:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY54:%[0-9]+]].sub3:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY55:%[0-9]+]].sub5:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY56:%[0-9]+]].sub7:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY57:%[0-9]+]].sub9:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY58:%[0-9]+]].sub11:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY59:%[0-9]+]].sub13:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY60:%[0-9]+]].sub15:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY61:%[0-9]+]].sub17:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY62:%[0-9]+]].sub19:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY63:%[0-9]+]].sub21:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY64:%[0-9]+]].sub23:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY65:%[0-9]+]].sub25:vreg_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY66:%[0-9]+]].sub27:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY67:%[0-9]+]].sub29:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY68:%[0-9]+]].sub31:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: undef [[COPY69:%[0-9]+]].sub1:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: SI_SPILL_AV1024_SAVE [[COPY69]], %stack.32, $sgpr32, 0, implicit $exec :: (store (s1024) into %stack.32, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY70:%[0-9]+]].sub31:av_1024_align2 = COPY undef renamable $sgpr4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.NodeBlock:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.47(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr38_sgpr39 = V_CMP_LT_I32_e64 2, [[BUFFER_LOAD_DWORD_OFFEN1]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
+ ; CHECK-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 0
+ ; CHECK-NEXT: renamable $sgpr50_sgpr51 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr38_sgpr39 = S_AND_B64 renamable $sgpr50_sgpr51, killed renamable $sgpr38_sgpr39, implicit-def dead $scc
+ ; CHECK-NEXT: renamable $sgpr50_sgpr51 = S_XOR_B64 renamable $sgpr38_sgpr39, killed renamable $sgpr50_sgpr51, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr38_sgpr39
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.47, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.LeafBlock46:
+ ; CHECK-NEXT: successors: %bb.48(0x40000000), %bb.3(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr38_sgpr39 = V_CMP_EQ_U32_e64 3, [[BUFFER_LOAD_DWORD_OFFEN1]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 -1
+ ; CHECK-NEXT: renamable $sgpr52_sgpr53 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr38_sgpr39 = S_AND_B64 renamable $sgpr52_sgpr53, killed renamable $sgpr38_sgpr39, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr38_sgpr39
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.48
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.Flow52:
+ ; CHECK-NEXT: successors: %bb.47(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr52_sgpr53, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: S_BRANCH %bb.47
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.LeafBlock:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr38_sgpr39 = V_CMP_NE_U32_e64 2, [[BUFFER_LOAD_DWORD_OFFEN1]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr48_sgpr49 = S_ANDN2_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
+ ; CHECK-NEXT: renamable $sgpr38_sgpr39 = S_AND_B64 killed renamable $sgpr38_sgpr39, $exec, implicit-def dead $scc
+ ; CHECK-NEXT: renamable $sgpr52_sgpr53 = S_OR_B64 killed renamable $sgpr48_sgpr49, killed renamable $sgpr38_sgpr39, implicit-def dead $scc
+ ; CHECK-NEXT: renamable $sgpr48_sgpr49 = COPY $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.Flow53:
+ ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.42(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr50_sgpr51, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr38_sgpr39 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr50_sgpr51 = S_AND_B64 renamable $sgpr38_sgpr39, killed renamable $sgpr52_sgpr53, implicit-def dead $scc
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.25, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.25, align 4, addrspace 5)
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr50_sgpr51
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.42, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb0:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.10(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr50_sgpr51 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr52_sgpr53 = S_AND_B64 renamable $sgpr50_sgpr51, renamable $sgpr46_sgpr47, implicit-def dead $scc
+ ; CHECK-NEXT: renamable $sgpr50_sgpr51 = S_XOR_B64 renamable $sgpr52_sgpr53, killed renamable $sgpr50_sgpr51, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr52_sgpr53
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.10, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb0a:
+ ; CHECK-NEXT: successors: %bb.49(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE1:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 124, [[SI_SPILL_AV64_RESTORE1]].sub0, implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e32_]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE1]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: [[COPY71:%[0-9]+]]:av_64_align2 = COPY [[COPY39]]
+ ; CHECK-NEXT: [[COPY72:%[0-9]+]]:av_64_align2 = COPY [[COPY37]]
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]]:vreg_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.33, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.33, align 4, addrspace 5)
+ ; CHECK-NEXT: [[V_LSHRREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 15, [[SI_SPILL_AV1024_RESTORE]].sub31, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_SHORT [[V_ADD_CO_U32_e32_]], [[V_LSHRREV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %ir.sink + 124, align 4, basealign 128)
+ ; CHECK-NEXT: [[V_ALIGNBIT_B32_opsel_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[SI_SPILL_AV1024_RESTORE]].sub31, 0, [[SI_SPILL_AV1024_RESTORE]].sub30, 0, 15, 0, 0, implicit $exec
+ ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 120, [[SI_SPILL_AV64_RESTORE1]].sub0, implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e32_1]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE1]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORD [[V_ADD_CO_U32_e32_1]], [[V_ALIGNBIT_B32_opsel_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.sink + 120, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 31, [[SI_SPILL_AV1024_RESTORE]].sub2, implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_33:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub1, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub1:vreg_1024_align2 = V_OR_B32_e32 [[V_AND_B32_e32_33]], [[V_LSHLREV_B32_e32_]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 17, [[SI_SPILL_AV1024_RESTORE]].sub30, implicit $exec
+ ; CHECK-NEXT: [[COPY37:%[0-9]+]]:av_64_align2 = COPY [[COPY72]]
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub29:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub29, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 14, [[SI_SPILL_AV1024_RESTORE]].sub28_sub29, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_]].sub3, [[V_LSHLREV_B32_e32_1]], implicit $exec
+ ; CHECK-NEXT: undef %2534.sub0:vreg_64_align2, renamable $vcc = V_ADD_CO_U32_e64 24, [[SI_SPILL_AV64_RESTORE1]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: %2534.sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE1]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 18, [[SI_SPILL_AV1024_RESTORE]].sub28, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub27:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub27, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 13, [[SI_SPILL_AV1024_RESTORE]].sub26_sub27, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_]].sub1, [[V_LSHLREV_B32_e32_2]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2534, [[V_LSHRREV_B64_e64_]], 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 104, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 19, [[SI_SPILL_AV1024_RESTORE]].sub26, implicit $exec
+ ; CHECK-NEXT: [[COPY39:%[0-9]+]]:av_64_align2 = COPY [[COPY71]]
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub25:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub25, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_1:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 12, [[SI_SPILL_AV1024_RESTORE]].sub24_sub25, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_1:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_1]].sub3, [[V_LSHLREV_B32_e32_3]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 20, [[SI_SPILL_AV1024_RESTORE]].sub24, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub23:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub23, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_1:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 11, [[SI_SPILL_AV1024_RESTORE]].sub22_sub23, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_1:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_1]].sub1, [[V_LSHLREV_B32_e32_4]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2534, [[V_LSHRREV_B64_e64_1]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 88, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_5:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 21, [[SI_SPILL_AV1024_RESTORE]].sub22, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub21:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub21, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_2:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 10, [[SI_SPILL_AV1024_RESTORE]].sub20_sub21, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_2:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_2]].sub3, [[V_LSHLREV_B32_e32_5]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_6:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 22, [[SI_SPILL_AV1024_RESTORE]].sub20, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub19:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub19, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_2:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 9, [[SI_SPILL_AV1024_RESTORE]].sub18_sub19, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_2:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_2]].sub1, [[V_LSHLREV_B32_e32_6]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2534, [[V_LSHRREV_B64_e64_2]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 72, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_7:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 23, [[SI_SPILL_AV1024_RESTORE]].sub18, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub17:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub17, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_3:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 8, [[SI_SPILL_AV1024_RESTORE]].sub16_sub17, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_3:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_3]].sub1, [[V_LSHLREV_B32_e32_7]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE1]], [[V_LSHRREV_B64_e64_3]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 64, align 64, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_8:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[SI_SPILL_AV1024_RESTORE]].sub16, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub15:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub15, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_4:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 7, [[SI_SPILL_AV1024_RESTORE]].sub14_sub15, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_4:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_4]].sub1, [[V_LSHLREV_B32_e32_8]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2534, [[V_LSHRREV_B64_e64_4]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 56, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_9:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 25, [[SI_SPILL_AV1024_RESTORE]].sub14, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub13:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub13, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_5:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 6, [[SI_SPILL_AV1024_RESTORE]].sub12_sub13, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_5:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_5]].sub3, [[V_LSHLREV_B32_e32_9]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_10:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 26, [[SI_SPILL_AV1024_RESTORE]].sub12, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub11:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub11, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_5:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 5, [[SI_SPILL_AV1024_RESTORE]].sub10_sub11, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_5:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_5]].sub1, [[V_LSHLREV_B32_e32_10]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2534, [[V_LSHRREV_B64_e64_5]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 40, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_11:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 27, [[SI_SPILL_AV1024_RESTORE]].sub10, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub9:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub9, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_6:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 4, [[SI_SPILL_AV1024_RESTORE]].sub8_sub9, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_6:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_6]].sub1, [[V_LSHLREV_B32_e32_11]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE1]], [[V_LSHRREV_B64_e64_6]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 32, align 32, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_12:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 28, [[SI_SPILL_AV1024_RESTORE]].sub8, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub7:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub7, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_7:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 3, [[SI_SPILL_AV1024_RESTORE]].sub6_sub7, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_7:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_7]].sub1, [[V_LSHLREV_B32_e32_12]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2534, [[V_LSHRREV_B64_e64_7]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 24, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_13:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 29, [[SI_SPILL_AV1024_RESTORE]].sub6, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub5:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub5, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_8:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 2, [[SI_SPILL_AV1024_RESTORE]].sub4_sub5, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_8:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_8]].sub1, [[V_LSHLREV_B32_e32_13]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE1]], [[V_LSHRREV_B64_e64_8]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 16, align 16, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_14:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 30, [[SI_SPILL_AV1024_RESTORE]].sub4, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub3:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub3, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub2_sub3:vreg_1024_align2 = V_LSHRREV_B64_e64 1, [[SI_SPILL_AV1024_RESTORE]].sub2_sub3, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub3:vreg_1024_align2 = V_OR_B32_e32 [[SI_SPILL_AV1024_RESTORE]].sub3, [[V_LSHLREV_B32_e32_14]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE1]], [[SI_SPILL_AV1024_RESTORE]].sub0_sub1_sub2_sub3, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
+ ; CHECK-NEXT: S_BRANCH %bb.49
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.bb0b:
+ ; CHECK-NEXT: successors: %bb.9(0x40000000), %bb.11(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr52_sgpr53 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37 = S_AND_B64 renamable $sgpr52_sgpr53, killed renamable $sgpr36_sgpr37, implicit-def dead $scc
+ ; CHECK-NEXT: [[SI_SPILL_AV128_RESTORE:%[0-9]+]]:av_128_align2 = SI_SPILL_AV128_RESTORE %stack.26, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.26, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY73:%[0-9]+]].sub0:vreg_128_align2 = COPY [[SI_SPILL_AV128_RESTORE]].sub0 {
+ ; CHECK-NEXT: internal [[COPY73]].sub2:vreg_128_align2 = COPY [[SI_SPILL_AV128_RESTORE]].sub2
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr36_sgpr37
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.11, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9.cond.load:
+ ; CHECK-NEXT: successors: %bb.11(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub0_sub1:vreg_128_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.p, align 1)
+ ; CHECK-NEXT: S_BRANCH %bb.11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.10.Flow:
+ ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.49(0x40000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr56_sgpr57 = S_OR_SAVEEXEC_B64 killed renamable $sgpr50_sgpr51, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, renamable $sgpr56_sgpr57, implicit-def $scc
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.49, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.11.else:
+ ; CHECK-NEXT: successors: %bb.12(0x40000000), %bb.13(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr52_sgpr53, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr34_sgpr35 = S_AND_B64 renamable $sgpr36_sgpr37, killed renamable $sgpr34_sgpr35, implicit-def dead $scc
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE2:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.24, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.24, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE3:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.23, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.23, align 4, addrspace 5)
+ ; CHECK-NEXT: [[COPY74:%[0-9]+]]:vreg_64_align2 = COPY [[COPY8]]
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE4:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.21, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.21, align 4, addrspace 5)
+ ; CHECK-NEXT: [[COPY75:%[0-9]+]]:vreg_64_align2 = COPY [[COPY6]]
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE5:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.22, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.22, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE6:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.20, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.20, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE7:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.19, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.19, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE8:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.31, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.31, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE9:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.18, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.18, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE10:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.16, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.16, align 4, addrspace 5)
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr34_sgpr35
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.13, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.12.cond.load1:
+ ; CHECK-NEXT: successors: %bb.13(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub2_sub3:vreg_128_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 8, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.28, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.13.else2:
+ ; CHECK-NEXT: successors: %bb.14(0x40000000), %bb.15(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr36_sgpr37, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr34_sgpr35 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr30_sgpr31 = S_AND_B64 renamable $sgpr34_sgpr35, killed renamable $sgpr30_sgpr31, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr30_sgpr31
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.15, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.14
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.14.cond.load4:
+ ; CHECK-NEXT: successors: %bb.15(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE2:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.35, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.15.else5:
+ ; CHECK-NEXT: successors: %bb.16(0x40000000), %bb.17(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr34_sgpr35, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr30_sgpr31 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr94_sgpr95 = S_AND_B64 renamable $sgpr30_sgpr31, killed renamable $sgpr94_sgpr95, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr94_sgpr95
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.17, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.16.cond.load7:
+ ; CHECK-NEXT: successors: %bb.17(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE3:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 24, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.42, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.17.else8:
+ ; CHECK-NEXT: successors: %bb.18(0x40000000), %bb.19(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr30_sgpr31, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr94_sgpr95 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr92_sgpr93 = S_AND_B64 renamable $sgpr94_sgpr95, killed renamable $sgpr92_sgpr93, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr92_sgpr93
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.19, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.18
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.18.cond.load10:
+ ; CHECK-NEXT: successors: %bb.19(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY74:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 32, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.49, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.19.else11:
+ ; CHECK-NEXT: successors: %bb.20(0x40000000), %bb.21(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr94_sgpr95, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr92_sgpr93 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr90_sgpr91 = S_AND_B64 renamable $sgpr92_sgpr93, killed renamable $sgpr90_sgpr91, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr90_sgpr91
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.21, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.20
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.20.cond.load13:
+ ; CHECK-NEXT: successors: %bb.21(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr92_sgpr93
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE4:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 40, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.56, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.21.else14:
+ ; CHECK-NEXT: successors: %bb.22(0x40000000), %bb.23(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr92_sgpr93
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr92_sgpr93, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr90_sgpr91 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr88_sgpr89 = S_AND_B64 renamable $sgpr90_sgpr91, killed renamable $sgpr88_sgpr89, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr88_sgpr89
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.23, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.22
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.22.cond.load16:
+ ; CHECK-NEXT: successors: %bb.23(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr90_sgpr91
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY75:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 48, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.63, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.23.else17:
+ ; CHECK-NEXT: successors: %bb.24(0x40000000), %bb.25(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr90_sgpr91
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr90_sgpr91, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr88_sgpr89 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr78_sgpr79 = S_AND_B64 renamable $sgpr88_sgpr89, killed renamable $sgpr78_sgpr79, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr78_sgpr79
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.25, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.24
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.24.cond.load19:
+ ; CHECK-NEXT: successors: %bb.25(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr88_sgpr89
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE5:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 56, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.70, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.25.else20:
+ ; CHECK-NEXT: successors: %bb.26(0x40000000), %bb.27(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr88_sgpr89
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr88_sgpr89, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr78_sgpr79 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr76_sgpr77 = S_AND_B64 renamable $sgpr78_sgpr79, killed renamable $sgpr76_sgpr77, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr76_sgpr77
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.27, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.26
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.26.cond.load22:
+ ; CHECK-NEXT: successors: %bb.27(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr78_sgpr79
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE6:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 64, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.77, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.27.else23:
+ ; CHECK-NEXT: successors: %bb.28(0x40000000), %bb.29(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr78_sgpr79
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr78_sgpr79, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr76_sgpr77 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr74_sgpr75 = S_AND_B64 renamable $sgpr76_sgpr77, killed renamable $sgpr74_sgpr75, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr74_sgpr75
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.29, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.28
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.28.cond.load25:
+ ; CHECK-NEXT: successors: %bb.29(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr76_sgpr77
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE7:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 72, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.84, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.29.else26:
+ ; CHECK-NEXT: successors: %bb.30(0x40000000), %bb.31(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr76_sgpr77
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr76_sgpr77, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr74_sgpr75 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr72_sgpr73 = S_AND_B64 renamable $sgpr74_sgpr75, killed renamable $sgpr72_sgpr73, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr72_sgpr73
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.31, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.30
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.30.cond.load28:
+ ; CHECK-NEXT: successors: %bb.31(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr74_sgpr75
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE8:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 80, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.91, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.31.else29:
+ ; CHECK-NEXT: successors: %bb.32(0x40000000), %bb.33(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr74_sgpr75
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr74_sgpr75, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr72_sgpr73 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr62_sgpr63 = S_AND_B64 renamable $sgpr72_sgpr73, killed renamable $sgpr62_sgpr63, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr62_sgpr63
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.33, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.32
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.32.cond.load31:
+ ; CHECK-NEXT: successors: %bb.33(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr72_sgpr73
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE9:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 88, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.98, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.33.else32:
+ ; CHECK-NEXT: successors: %bb.34(0x40000000), %bb.35(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr72_sgpr73
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr72_sgpr73, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr62_sgpr63 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr60_sgpr61 = S_AND_B64 renamable $sgpr62_sgpr63, killed renamable $sgpr60_sgpr61, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr60_sgpr61
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.35, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.34
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.34.cond.load34:
+ ; CHECK-NEXT: successors: %bb.35(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr62_sgpr63
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE10:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 96, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.105, align 1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.35.else35:
+ ; CHECK-NEXT: successors: %bb.36(0x40000000), %bb.37(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr62_sgpr63
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr62_sgpr63, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr60_sgpr61 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr58_sgpr59 = S_AND_B64 renamable $sgpr60_sgpr61, killed renamable $sgpr58_sgpr59, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr58_sgpr59
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.37, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.36
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.36.cond.load37:
+ ; CHECK-NEXT: successors: %bb.37(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr60_sgpr61
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:av_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 104, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.112, align 1)
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[FLAT_LOAD_DWORDX2_]], %stack.30, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.30, align 4, addrspace 5)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.37.else38:
+ ; CHECK-NEXT: successors: %bb.38(0x40000000), %bb.39(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr60_sgpr61
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr60_sgpr61, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr58_sgpr59 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr56_sgpr57 = S_AND_B64 renamable $sgpr58_sgpr59, killed renamable $sgpr56_sgpr57, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr56_sgpr57
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.39, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.38
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.38.cond.load40:
+ ; CHECK-NEXT: successors: %bb.39(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[FLAT_LOAD_DWORDX2_1:%[0-9]+]]:av_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 112, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.119, align 1)
+ ; CHECK-NEXT: [[COPY45:%[0-9]+]]:av_64_align2 = COPY [[FLAT_LOAD_DWORDX2_1]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.39.else41:
+ ; CHECK-NEXT: successors: %bb.40(0x40000000), %bb.41(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr58_sgpr59, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr56_sgpr57 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr58_sgpr59 = S_AND_B64 renamable $sgpr56_sgpr57, killed renamable $vcc, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr58_sgpr59
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.41, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.40
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.40.cond.load43:
+ ; CHECK-NEXT: successors: %bb.41(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[FLAT_LOAD_DWORDX2_2:%[0-9]+]]:av_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 120, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.126, align 1)
+ ; CHECK-NEXT: [[COPY44:%[0-9]+]]:av_64_align2 = COPY [[FLAT_LOAD_DWORDX2_2]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.41.else44:
+ ; CHECK-NEXT: successors: %bb.10(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr56_sgpr57, implicit-def $scc
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE11:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 124, [[SI_SPILL_AV64_RESTORE11]].sub0, implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e32_2]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE11]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: [[COPY76:%[0-9]+]]:vreg_64_align2 = COPY [[COPY44]]
+ ; CHECK-NEXT: [[V_LSHRREV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 15, [[COPY76]].sub1, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_SHORT [[V_ADD_CO_U32_e32_2]], [[V_LSHRREV_B32_e32_1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %ir.sink + 124, align 4, basealign 128)
+ ; CHECK-NEXT: [[V_ALIGNBIT_B32_opsel_e64_1:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY76]].sub1, 0, [[COPY76]].sub0, 0, 15, 0, 0, implicit $exec
+ ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_3:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 120, [[SI_SPILL_AV64_RESTORE11]].sub0, implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e32_3]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE11]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORD [[V_ADD_CO_U32_e32_3]], [[V_ALIGNBIT_B32_opsel_e64_1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.sink + 120, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_15:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 31, [[COPY73]].sub2, implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_34:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 2147483647, [[COPY73]].sub1, implicit $exec
+ ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_AND_B32_e32_34]], [[V_LSHLREV_B32_e32_15]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_16:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 17, [[COPY76]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY77:%[0-9]+]]:vreg_64_align2 = COPY [[COPY45]]
+ ; CHECK-NEXT: [[COPY77:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY77]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_9:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 14, [[COPY77]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_9:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_9]].sub3, [[V_LSHLREV_B32_e32_16]], implicit $exec
+ ; CHECK-NEXT: undef %2544.sub0:vreg_64_align2, renamable $vcc = V_ADD_CO_U32_e64 24, [[SI_SPILL_AV64_RESTORE11]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: %2544.sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE11]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_17:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 18, [[COPY77]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE12:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.30, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.30, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE12:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE12]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_9:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 13, [[SI_SPILL_AV64_RESTORE12]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_9:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_9]].sub1, [[V_LSHLREV_B32_e32_17]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2544, [[V_LSHRREV_B64_e64_9]], 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 104, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_18:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 19, [[SI_SPILL_AV64_RESTORE12]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE10:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE10]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_10:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 12, [[SI_SPILL_AV64_RESTORE10]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_10:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_10]].sub3, [[V_LSHLREV_B32_e32_18]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_19:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 20, [[SI_SPILL_AV64_RESTORE10]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE9:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE9]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_10:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 11, [[SI_SPILL_AV64_RESTORE9]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_10:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_10]].sub1, [[V_LSHLREV_B32_e32_19]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2544, [[V_LSHRREV_B64_e64_10]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 88, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_20:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 21, [[SI_SPILL_AV64_RESTORE9]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE8:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE8]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_11:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 10, [[SI_SPILL_AV64_RESTORE8]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_11:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_11]].sub3, [[V_LSHLREV_B32_e32_20]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_21:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 22, [[SI_SPILL_AV64_RESTORE8]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE7:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE7]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_11:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 9, [[SI_SPILL_AV64_RESTORE7]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_11:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_11]].sub1, [[V_LSHLREV_B32_e32_21]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2544, [[V_LSHRREV_B64_e64_11]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 72, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_22:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 23, [[SI_SPILL_AV64_RESTORE7]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE6:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE6]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_12:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 8, [[SI_SPILL_AV64_RESTORE6]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_12:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_12]].sub1, [[V_LSHLREV_B32_e32_22]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE11]], [[V_LSHRREV_B64_e64_12]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 64, align 64, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_23:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[SI_SPILL_AV64_RESTORE6]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE5:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE5]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_13:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 7, [[SI_SPILL_AV64_RESTORE5]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_13:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_13]].sub1, [[V_LSHLREV_B32_e32_23]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2544, [[V_LSHRREV_B64_e64_13]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 56, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_24:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 25, [[SI_SPILL_AV64_RESTORE5]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY75:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY75]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_14:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 6, [[COPY75]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_14:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_14]].sub3, [[V_LSHLREV_B32_e32_24]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_25:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 26, [[COPY75]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE4:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE4]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_14:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 5, [[SI_SPILL_AV64_RESTORE4]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_14:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_14]].sub1, [[V_LSHLREV_B32_e32_25]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2544, [[V_LSHRREV_B64_e64_14]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 40, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_26:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 27, [[SI_SPILL_AV64_RESTORE4]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY74:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY74]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_15:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 4, [[COPY74]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_15:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_15]].sub1, [[V_LSHLREV_B32_e32_26]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE11]], [[V_LSHRREV_B64_e64_15]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 32, align 32, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_27:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 28, [[COPY74]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE3:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE3]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_16:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 3, [[SI_SPILL_AV64_RESTORE3]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_16:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_16]].sub1, [[V_LSHLREV_B32_e32_27]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2544, [[V_LSHRREV_B64_e64_16]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 24, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_28:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 29, [[SI_SPILL_AV64_RESTORE3]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE2:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE2]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_17:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 2, [[SI_SPILL_AV64_RESTORE2]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_17:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_17]].sub1, [[V_LSHLREV_B32_e32_28]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE11]], [[V_LSHRREV_B64_e64_17]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 16, align 16, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_29:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 30, [[SI_SPILL_AV64_RESTORE2]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub3:vreg_128_align2 = V_AND_B32_e32 2147483647, [[COPY73]].sub3, implicit $exec
+ ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 1, [[COPY73]].sub2_sub3, implicit $exec
+ ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[COPY73]].sub3, [[V_LSHLREV_B32_e32_29]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE11]], [[COPY73]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
+ ; CHECK-NEXT: KILL [[DEF]]
+ ; CHECK-NEXT: S_BRANCH %bb.10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.42.Flow54:
+ ; CHECK-NEXT: successors: %bb.43(0x40000000), %bb.51(0x40000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr38_sgpr39, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr56_sgpr57 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr58_sgpr59 = S_AND_B64 renamable $sgpr56_sgpr57, killed renamable $sgpr48_sgpr49, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr58_sgpr59
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.51, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.43
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.43.bb1:
+ ; CHECK-NEXT: successors: %bb.46(0x40000000), %bb.44(0x40000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr58_sgpr59 = COPY $exec, implicit-def $exec
+ ; CHECK-NEXT: renamable $sgpr60_sgpr61 = S_AND_B64 renamable $sgpr58_sgpr59, killed renamable $sgpr46_sgpr47, implicit-def dead $scc
+ ; CHECK-NEXT: renamable $sgpr46_sgpr47 = S_XOR_B64 renamable $sgpr60_sgpr61, killed renamable $sgpr58_sgpr59, implicit-def dead $scc
+ ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr60_sgpr61
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.44, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.46
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.44.Flow49:
+ ; CHECK-NEXT: successors: %bb.45(0x40000000), %bb.51(0x40000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr46_sgpr47 = S_OR_SAVEEXEC_B64 killed renamable $sgpr46_sgpr47, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, killed renamable $sgpr46_sgpr47, implicit-def $scc
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.51, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.45
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.45.bb1a:
+ ; CHECK-NEXT: successors: %bb.51(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE1:%[0-9]+]]:av_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.15, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.15, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE2:%[0-9]+]]:av_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.17, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.17, align 4, addrspace 5)
+ ; CHECK-NEXT: [[COPY78:%[0-9]+]]:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]]
+ ; CHECK-NEXT: [[COPY79:%[0-9]+]]:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]]
+ ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY79]].sub29, 0, [[COPY78]].sub29, $sgpr44_sgpr45, implicit $exec
+ ; CHECK-NEXT: undef [[COPY80:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY80]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
+ ; CHECK-NEXT: internal [[COPY80]].sub30_sub31:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub30_sub31
+ ; CHECK-NEXT: internal [[COPY80]].sub28:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub28
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY81:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY81]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
+ ; CHECK-NEXT: internal [[COPY81]].sub30_sub31:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub30_sub31
+ ; CHECK-NEXT: internal [[COPY81]].sub28:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub28
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY81]].sub28, 0, [[COPY80]].sub28, killed $sgpr44_sgpr45, implicit $exec
+ ; CHECK-NEXT: undef [[COPY82:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY82]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
+ ; CHECK-NEXT: internal [[COPY82]].sub30_sub31:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub30_sub31
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY83:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY83]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
+ ; CHECK-NEXT: internal [[COPY83]].sub30_sub31:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub30_sub31
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY83]].sub31, 0, [[COPY82]].sub31, $sgpr40_sgpr41, implicit $exec
+ ; CHECK-NEXT: undef [[COPY84:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY84]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
+ ; CHECK-NEXT: internal [[COPY84]].sub30:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub30
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY85:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY85]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
+ ; CHECK-NEXT: internal [[COPY85]].sub30:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub30
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY85]].sub30, 0, [[COPY84]].sub30, killed $sgpr40_sgpr41, implicit $exec
+ ; CHECK-NEXT: undef [[COPY86:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY86]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY87:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY87]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_1:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY87]].sub25, 0, [[COPY86]].sub25, $sgpr42_sgpr43, implicit $exec
+ ; CHECK-NEXT: undef [[COPY88:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY88]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16
+ ; CHECK-NEXT: internal [[COPY88]].sub26_sub27:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub26_sub27
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY89:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY89]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16
+ ; CHECK-NEXT: internal [[COPY89]].sub26_sub27:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub26_sub27
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY89]].sub24, 0, [[COPY88]].sub24, killed $sgpr42_sgpr43, implicit $exec
+ ; CHECK-NEXT: undef [[COPY90:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY90]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
+ ; CHECK-NEXT: internal [[COPY90]].sub26_sub27:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub26_sub27
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY91:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY91]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
+ ; CHECK-NEXT: internal [[COPY91]].sub26_sub27:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub26_sub27
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY91]].sub27, 0, [[COPY90]].sub27, $sgpr26_sgpr27, implicit $exec
+ ; CHECK-NEXT: undef [[COPY92:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY92]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
+ ; CHECK-NEXT: internal [[COPY92]].sub26:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub26
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY93:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY93]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
+ ; CHECK-NEXT: internal [[COPY93]].sub26:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub26
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY93]].sub26, 0, [[COPY92]].sub26, killed $sgpr26_sgpr27, implicit $exec
+ ; CHECK-NEXT: undef [[COPY94:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY94]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY95:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY95]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_2:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY95]].sub21, 0, [[COPY94]].sub21, $sgpr28_sgpr29, implicit $exec
+ ; CHECK-NEXT: undef [[COPY96:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY96]].sub16_sub17_sub18_sub19_sub20:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19_sub20
+ ; CHECK-NEXT: internal [[COPY96]].sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub22_sub23
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY97:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY97]].sub16_sub17_sub18_sub19_sub20:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19_sub20
+ ; CHECK-NEXT: internal [[COPY97]].sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub22_sub23
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_2:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY97]].sub20, 0, [[COPY96]].sub20, killed $sgpr28_sgpr29, implicit $exec
+ ; CHECK-NEXT: undef [[COPY98:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY98]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19
+ ; CHECK-NEXT: internal [[COPY98]].sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub22_sub23
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY99:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY99]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19
+ ; CHECK-NEXT: internal [[COPY99]].sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub22_sub23
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_2:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY99]].sub23, 0, [[COPY98]].sub23, $sgpr22_sgpr23, implicit $exec
+ ; CHECK-NEXT: undef [[COPY100:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY100]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19
+ ; CHECK-NEXT: internal [[COPY100]].sub22:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub22
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY101:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY101]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19
+ ; CHECK-NEXT: internal [[COPY101]].sub22:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub22
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_2:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY101]].sub22, 0, [[COPY100]].sub22, killed $sgpr22_sgpr23, implicit $exec
+ ; CHECK-NEXT: undef [[COPY102:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY102]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY103:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY103]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_3:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY103]].sub17, 0, [[COPY102]].sub17, $sgpr24_sgpr25, implicit $exec
+ ; CHECK-NEXT: undef [[COPY104:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY104]].sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub18_sub19
+ ; CHECK-NEXT: internal [[COPY104]].sub16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY105:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY105]].sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub18_sub19
+ ; CHECK-NEXT: internal [[COPY105]].sub16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_3:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY105]].sub16, 0, [[COPY104]].sub16, killed $sgpr24_sgpr25, implicit $exec
+ ; CHECK-NEXT: undef [[COPY106:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY106]].sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub18_sub19
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY107:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY107]].sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub18_sub19
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_3:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY107]].sub19, 0, [[COPY106]].sub19, $sgpr18_sgpr19, implicit $exec
+ ; CHECK-NEXT: undef [[COPY108:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY108]].sub18:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub18
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY109:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
+ ; CHECK-NEXT: internal [[COPY109]].sub18:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub18
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_3:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY109]].sub18, 0, [[COPY108]].sub18, killed $sgpr18_sgpr19, implicit $exec
+ ; CHECK-NEXT: undef [[COPY110:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
+ ; CHECK-NEXT: undef [[COPY111:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
+ ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_4:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY111]].sub13, 0, [[COPY110]].sub13, $sgpr20_sgpr21, implicit $exec
+ ; CHECK-NEXT: undef [[COPY112:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
+ ; CHECK-NEXT: internal [[COPY112]].sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub14_sub15
+ ; CHECK-NEXT: internal [[COPY112]].sub12:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub12
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY113:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
+ ; CHECK-NEXT: internal [[COPY113]].sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub14_sub15
+ ; CHECK-NEXT: internal [[COPY113]].sub12:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub12
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_4:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY113]].sub12, 0, [[COPY112]].sub12, killed $sgpr20_sgpr21, implicit $exec
+ ; CHECK-NEXT: undef [[COPY114:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
+ ; CHECK-NEXT: internal [[COPY114]].sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub14_sub15
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY115:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
+ ; CHECK-NEXT: internal [[COPY115]].sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub14_sub15
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_4:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY115]].sub15, 0, [[COPY114]].sub15, $sgpr14_sgpr15, implicit $exec
+ ; CHECK-NEXT: undef [[COPY116:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
+ ; CHECK-NEXT: internal [[COPY116]].sub14:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub14
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY117:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
+ ; CHECK-NEXT: internal [[COPY117]].sub14:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub14
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_4:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY117]].sub14, 0, [[COPY116]].sub14, killed $sgpr14_sgpr15, implicit $exec
+ ; CHECK-NEXT: undef [[COPY118:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16
+ ; CHECK-NEXT: undef [[COPY119:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16
+ ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_5:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY119]].sub9, 0, [[COPY118]].sub9, $sgpr16_sgpr17, implicit $exec
+ ; CHECK-NEXT: undef [[COPY120:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16 {
+ ; CHECK-NEXT: internal [[COPY120]].sub10_sub11:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub10_sub11
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY121:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16 {
+ ; CHECK-NEXT: internal [[COPY121]].sub10_sub11:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub10_sub11
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_5:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY121]].sub8, 0, [[COPY120]].sub8, killed $sgpr16_sgpr17, implicit $exec
+ ; CHECK-NEXT: undef [[COPY122:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 {
+ ; CHECK-NEXT: internal [[COPY122]].sub10_sub11:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub10_sub11
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY123:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 {
+ ; CHECK-NEXT: internal [[COPY123]].sub10_sub11:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub10_sub11
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_5:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY123]].sub11, 0, [[COPY122]].sub11, $sgpr10_sgpr11, implicit $exec
+ ; CHECK-NEXT: undef [[COPY124:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 {
+ ; CHECK-NEXT: internal [[COPY124]].sub10:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub10
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY125:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 {
+ ; CHECK-NEXT: internal [[COPY125]].sub10:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub10
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_5:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY125]].sub10, 0, [[COPY124]].sub10, killed $sgpr10_sgpr11, implicit $exec
+ ; CHECK-NEXT: undef [[COPY126:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
+ ; CHECK-NEXT: undef [[COPY127:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
+ ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_6:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY127]].sub5, 0, [[COPY126]].sub5, $sgpr12_sgpr13, implicit $exec
+ ; CHECK-NEXT: undef [[COPY128:%[0-9]+]].sub0_sub1_sub2_sub3_sub4:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4 {
+ ; CHECK-NEXT: internal [[COPY128]].sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub6_sub7
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY129:%[0-9]+]].sub0_sub1_sub2_sub3_sub4:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4 {
+ ; CHECK-NEXT: internal [[COPY129]].sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub6_sub7
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_6:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY129]].sub4, 0, [[COPY128]].sub4, killed $sgpr12_sgpr13, implicit $exec
+ ; CHECK-NEXT: undef [[COPY130:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3 {
+ ; CHECK-NEXT: internal [[COPY130]].sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub6_sub7
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY131:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3 {
+ ; CHECK-NEXT: internal [[COPY131]].sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub6_sub7
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_6:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY131]].sub7, 0, [[COPY130]].sub7, $sgpr6_sgpr7, implicit $exec
+ ; CHECK-NEXT: undef [[COPY132:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3 {
+ ; CHECK-NEXT: internal [[COPY132]].sub6:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub6
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY133:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3 {
+ ; CHECK-NEXT: internal [[COPY133]].sub6:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub6
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_6:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY133]].sub6, 0, [[COPY132]].sub6, killed $sgpr6_sgpr7, implicit $exec
+ ; CHECK-NEXT: undef [[COPY134:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3
+ ; CHECK-NEXT: undef [[COPY135:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3
+ ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_7:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY134]].sub3, 0, [[COPY135]].sub3, $sgpr8_sgpr9, implicit $exec
+ ; CHECK-NEXT: undef [[COPY136:%[0-9]+]].sub0_sub1_sub2:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_7:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY134]].sub2, 0, [[COPY136]].sub2, killed $sgpr8_sgpr9, implicit $exec
+ ; CHECK-NEXT: undef [[COPY137:%[0-9]+]].sub0_sub1:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_7:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY134]].sub1, 0, [[COPY137]].sub1, $sgpr4_sgpr5, implicit $exec
+ ; CHECK-NEXT: undef [[COPY138:%[0-9]+]].sub0:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_7:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY134]].sub0, 0, [[COPY138]].sub0, killed $sgpr4_sgpr5, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE13:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE13]], [[V_CNDMASK_B32_e64_7]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE13]], [[V_CNDMASK_B32_e64_6]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 16)
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE13]], [[V_CNDMASK_B32_e64_5]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 32, align 32)
+ ; CHECK-NEXT: undef %2024.sub0:vreg_64_align2, renamable $vcc = V_ADD_CO_U32_e64 48, [[SI_SPILL_AV64_RESTORE13]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: %2024.sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE13]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2024, [[V_CNDMASK_B32_e64_4]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 48)
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE13]], [[V_CNDMASK_B32_e64_3]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 64, align 64)
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2024, [[V_CNDMASK_B32_e64_2]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 80)
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2024, [[V_CNDMASK_B32_e64_1]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 96, align 32)
+ ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_4:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 112, [[SI_SPILL_AV64_RESTORE13]].sub0, implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e32_4]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE13]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[V_ADD_CO_U32_e32_4]], [[V_CNDMASK_B32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 112)
+ ; CHECK-NEXT: S_BRANCH %bb.51
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.46.bb1b:
+ ; CHECK-NEXT: successors: %bb.44(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: undef [[COPY139:%[0-9]+]].sub31:vreg_1024_align2 = COPY [[COPY70]].sub31
+ ; CHECK-NEXT: [[V_LSHRREV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 15, [[COPY139]].sub31, implicit $exec
+ ; CHECK-NEXT: undef [[COPY140:%[0-9]+]].sub30:vreg_1024_align2 = COPY [[COPY46]].sub30
+ ; CHECK-NEXT: [[V_ALIGNBIT_B32_opsel_e64_2:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY139]].sub31, 0, [[COPY140]].sub30, 0, 15, 0, 0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE3:%[0-9]+]]:vreg_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.32, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.32, align 4, addrspace 5)
+ ; CHECK-NEXT: [[V_AND_B32_e32_35:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE3]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_30:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 17, [[COPY140]].sub30, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE14:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_5:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 124, [[SI_SPILL_AV64_RESTORE14]].sub0, implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e32_5]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE14]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_SHORT [[V_ADD_CO_U32_e32_5]], [[V_LSHRREV_B32_e32_2]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %ir.sink + 124, align 4, basealign 128)
+ ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_6:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 120, [[SI_SPILL_AV64_RESTORE14]].sub0, implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e32_6]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE14]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORD [[V_ADD_CO_U32_e32_6]], [[V_ALIGNBIT_B32_opsel_e64_2]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.sink + 120, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_31:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 31, [[COPY35]].sub2, implicit $exec
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_AND_B32_e32_35]], [[V_LSHLREV_B32_e32_31]], implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE15:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.29, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.29, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE15:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE15]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_18:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 14, [[SI_SPILL_AV64_RESTORE15]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_18:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_18]].sub3, [[V_LSHLREV_B32_e32_30]], implicit $exec
+ ; CHECK-NEXT: undef %2554.sub0:vreg_64_align2, renamable $vcc = V_ADD_CO_U32_e64 24, [[SI_SPILL_AV64_RESTORE14]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: %2554.sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE14]].sub1, killed $vcc, 0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_32:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 18, [[SI_SPILL_AV64_RESTORE15]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE16:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.28, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.28, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE16:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE16]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_18:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 13, [[SI_SPILL_AV64_RESTORE16]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_18:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_18]].sub1, [[V_LSHLREV_B32_e32_32]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2554, [[V_LSHRREV_B64_e64_18]], 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 104, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_33:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 19, [[SI_SPILL_AV64_RESTORE16]].sub0, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE17:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.27, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.27, align 4, addrspace 5)
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE17:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE17]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_19:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 12, [[SI_SPILL_AV64_RESTORE17]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_19:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_19]].sub3, [[V_LSHLREV_B32_e32_33]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_34:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 20, [[SI_SPILL_AV64_RESTORE17]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY141:%[0-9]+]]:vreg_64_align2 = COPY [[COPY37]]
+ ; CHECK-NEXT: [[COPY141:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY141]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_19:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 11, [[COPY141]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_19:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_19]].sub1, [[V_LSHLREV_B32_e32_34]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2554, [[V_LSHRREV_B64_e64_19]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 88, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_35:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 21, [[COPY141]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY142:%[0-9]+]]:vreg_64_align2 = COPY [[COPY39]]
+ ; CHECK-NEXT: [[COPY142:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY142]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_20:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 10, [[COPY142]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_20:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_20]].sub3, [[V_LSHLREV_B32_e32_35]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_36:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 22, [[COPY142]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY143:%[0-9]+]]:vreg_64_align2 = COPY [[COPY41]]
+ ; CHECK-NEXT: [[COPY143:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY143]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_20:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 9, [[COPY143]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_20:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_20]].sub1, [[V_LSHLREV_B32_e32_36]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2554, [[V_LSHRREV_B64_e64_20]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 72, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_37:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 23, [[COPY143]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY42:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY42]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_21:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 8, [[COPY42]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_21:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_21]].sub1, [[V_LSHLREV_B32_e32_37]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE14]], [[V_LSHRREV_B64_e64_21]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 64, align 64, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_38:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[COPY42]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY36:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY36]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_22:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 7, [[COPY36]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_22:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_22]].sub1, [[V_LSHLREV_B32_e32_38]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2554, [[V_LSHRREV_B64_e64_22]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 56, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_39:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 25, [[COPY36]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY144:%[0-9]+]]:vreg_64_align2 = COPY [[COPY34]]
+ ; CHECK-NEXT: [[COPY144:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY144]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_23:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 6, [[COPY144]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_23:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_23]].sub3, [[V_LSHLREV_B32_e32_39]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_40:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 26, [[COPY144]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY145:%[0-9]+]]:vreg_64_align2 = COPY [[COPY32]]
+ ; CHECK-NEXT: [[COPY145:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY145]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_23:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 5, [[COPY145]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_23:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_23]].sub1, [[V_LSHLREV_B32_e32_40]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2554, [[V_LSHRREV_B64_e64_23]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 40, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_41:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 27, [[COPY145]].sub0, implicit $exec
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN4:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[BUFFER_LOAD_DWORD_OFFEN4]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_24:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 4, [[BUFFER_LOAD_DWORD_OFFEN4]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_24:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_24]].sub1, [[V_LSHLREV_B32_e32_41]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE14]], [[V_LSHRREV_B64_e64_24]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 32, align 32, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_42:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 28, [[BUFFER_LOAD_DWORD_OFFEN4]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY146:%[0-9]+]]:vreg_64_align2 = COPY [[COPY31]]
+ ; CHECK-NEXT: [[COPY146:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY146]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_25:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 3, [[COPY146]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_25:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_25]].sub1, [[V_LSHLREV_B32_e32_42]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2554, [[V_LSHRREV_B64_e64_25]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 24, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_43:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 29, [[COPY146]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY33:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY33]].sub1, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_26:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 2, [[COPY33]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_26:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_26]].sub1, [[V_LSHLREV_B32_e32_43]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE14]], [[V_LSHRREV_B64_e64_26]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 16, align 16, basealign 128)
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_44:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 30, [[COPY33]].sub0, implicit $exec
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub3:vreg_128_align2 = V_AND_B32_e32 2147483647, [[COPY35]].sub3, implicit $exec
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 1, [[COPY35]].sub2_sub3, implicit $exec
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[COPY35]].sub3, [[V_LSHLREV_B32_e32_44]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE14]], [[COPY35]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
+ ; CHECK-NEXT: KILL [[DEF1]]
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:av_64_align2 = IMPLICIT_DEF
+ ; CHECK-NEXT: KILL [[DEF2]]
+ ; CHECK-NEXT: [[DEF3:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
+ ; CHECK-NEXT: KILL [[DEF3]]
+ ; CHECK-NEXT: S_BRANCH %bb.44
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.47.Flow51:
+ ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr50_sgpr51 = S_OR_SAVEEXEC_B64 killed renamable $sgpr50_sgpr51, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, renamable $sgpr50_sgpr51, implicit-def $scc
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.48.bb2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: undef [[COPY147:%[0-9]+]].sub2_sub3:av_128_align2 = COPY [[COPY35]].sub2_sub3 {
+ ; CHECK-NEXT: internal [[COPY147]].sub0:av_128_align2 = COPY [[COPY35]].sub0
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: [[COPY148:%[0-9]+]]:av_64_align2 = COPY [[COPY33]]
+ ; CHECK-NEXT: [[COPY149:%[0-9]+]]:av_64_align2 = COPY [[COPY31]]
+ ; CHECK-NEXT: [[COPY150:%[0-9]+]]:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN4]]
+ ; CHECK-NEXT: [[COPY151:%[0-9]+]]:av_64_align2 = COPY [[COPY32]]
+ ; CHECK-NEXT: [[COPY152:%[0-9]+]]:av_64_align2 = COPY [[COPY34]]
+ ; CHECK-NEXT: [[COPY153:%[0-9]+]]:av_64_align2 = COPY [[COPY36]]
+ ; CHECK-NEXT: [[COPY154:%[0-9]+]]:av_64_align2 = COPY [[COPY42]]
+ ; CHECK-NEXT: [[COPY155:%[0-9]+]]:av_64_align2 = COPY [[COPY41]]
+ ; CHECK-NEXT: [[COPY156:%[0-9]+]]:av_64_align2 = COPY [[COPY39]]
+ ; CHECK-NEXT: [[COPY157:%[0-9]+]]:av_64_align2 = COPY [[COPY37]]
+ ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE4:%[0-9]+]]:vreg_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.33, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.33, align 4, addrspace 5)
+ ; CHECK-NEXT: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub3, [[COPY54]].sub3, implicit $exec
+ ; CHECK-NEXT: [[COPY158:%[0-9]+]]:av_32 = COPY [[V_XOR_B32_e32_]]
+ ; CHECK-NEXT: undef [[COPY159:%[0-9]+]].sub5:vreg_1024_align2 = COPY [[COPY55]].sub5
+ ; CHECK-NEXT: [[V_XOR_B32_e32_1:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub5, [[COPY159]].sub5, implicit $exec
+ ; CHECK-NEXT: [[COPY160:%[0-9]+]]:av_32 = COPY [[V_XOR_B32_e32_1]]
+ ; CHECK-NEXT: [[V_XOR_B32_e32_2:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub7, [[COPY56]].sub7, implicit $exec
+ ; CHECK-NEXT: [[COPY161:%[0-9]+]]:av_32 = COPY [[V_XOR_B32_e32_2]]
+ ; CHECK-NEXT: [[V_XOR_B32_e32_3:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub9, [[COPY57]].sub9, implicit $exec
+ ; CHECK-NEXT: [[COPY162:%[0-9]+]]:av_32 = COPY [[V_XOR_B32_e32_3]]
+ ; CHECK-NEXT: [[V_XOR_B32_e32_4:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub11, [[COPY58]].sub11, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_5:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub13, [[COPY59]].sub13, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_6:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub15, [[COPY60]].sub15, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_7:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub17, [[COPY61]].sub17, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_8:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub19, [[COPY62]].sub19, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_9:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub21, [[COPY63]].sub21, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_10:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub23, [[COPY64]].sub23, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_11:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub25, [[COPY65]].sub25, implicit $exec
+ ; CHECK-NEXT: undef [[COPY163:%[0-9]+]].sub27:vreg_1024_align2 = COPY [[COPY66]].sub27
+ ; CHECK-NEXT: [[V_XOR_B32_e32_12:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub27, [[COPY163]].sub27, implicit $exec
+ ; CHECK-NEXT: undef [[COPY164:%[0-9]+]].sub29:vreg_1024_align2 = COPY [[COPY67]].sub29
+ ; CHECK-NEXT: [[V_XOR_B32_e32_13:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub29, [[COPY164]].sub29, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_14:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub1, [[COPY53]].sub1, implicit $exec
+ ; CHECK-NEXT: undef [[COPY165:%[0-9]+]].sub31:vreg_1024_align2 = COPY [[COPY68]].sub31
+ ; CHECK-NEXT: [[V_XOR_B32_e32_15:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub31, [[COPY165]].sub31, implicit $exec
+ ; CHECK-NEXT: undef [[COPY166:%[0-9]+]].sub30:vreg_1024_align2 = COPY [[COPY47]].sub30
+ ; CHECK-NEXT: [[V_XOR_B32_e32_16:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub30, [[COPY166]].sub30, implicit $exec
+ ; CHECK-NEXT: [[COPY41:%[0-9]+]]:av_64_align2 = COPY [[COPY155]]
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_17:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub2, [[BUFFER_LOAD_DWORD_OFFEN29]].sub2, implicit $exec
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_18:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub4, [[BUFFER_LOAD_DWORD_OFFEN28]].sub4, implicit $exec
+ ; CHECK-NEXT: undef [[COPY167:%[0-9]+]].sub0:av_64_align2 = COPY [[V_XOR_B32_e32_18]].sub0
+ ; CHECK-NEXT: [[COPY39:%[0-9]+]]:av_64_align2 = COPY [[COPY156]]
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_19:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub6, [[BUFFER_LOAD_DWORD_OFFEN27]].sub6, implicit $exec
+ ; CHECK-NEXT: undef [[COPY168:%[0-9]+]].sub0:av_64_align2 = COPY [[V_XOR_B32_e32_19]].sub0
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_20:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub8, [[BUFFER_LOAD_DWORD_OFFEN26]].sub8, implicit $exec
+ ; CHECK-NEXT: [[COPY37:%[0-9]+]]:av_64_align2 = COPY [[COPY157]]
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_21:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub10, [[BUFFER_LOAD_DWORD_OFFEN25]].sub10, implicit $exec
+ ; CHECK-NEXT: [[COPY31:%[0-9]+]]:av_64_align2 = COPY [[COPY149]]
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_22:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub12, [[BUFFER_LOAD_DWORD_OFFEN24]].sub12, implicit $exec
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN4:%[0-9]+]]:vreg_64_align2 = COPY [[COPY150]]
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_23:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub14, [[BUFFER_LOAD_DWORD_OFFEN23]].sub14, implicit $exec
+ ; CHECK-NEXT: [[COPY32:%[0-9]+]]:av_64_align2 = COPY [[COPY151]]
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_24:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub16, [[BUFFER_LOAD_DWORD_OFFEN22]].sub16, implicit $exec
+ ; CHECK-NEXT: [[COPY34:%[0-9]+]]:av_64_align2 = COPY [[COPY152]]
+ ; CHECK-NEXT: undef [[COPY169:%[0-9]+]].sub18:vreg_1024_align2 = COPY [[COPY52]].sub18
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_25:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub18, [[COPY169]].sub18, implicit $exec
+ ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE18:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_26:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub20, [[BUFFER_LOAD_DWORD_OFFEN20]].sub20, implicit $exec
+ ; CHECK-NEXT: undef [[COPY170:%[0-9]+]].sub22:vreg_1024_align2 = COPY [[COPY51]].sub22
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_27:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub22, [[COPY170]].sub22, implicit $exec
+ ; CHECK-NEXT: undef [[COPY35:%[0-9]+]].sub2_sub3:vreg_128_align2 = COPY [[COPY147]].sub2_sub3 {
+ ; CHECK-NEXT: internal [[COPY35]].sub0:vreg_128_align2 = COPY [[COPY147]].sub0
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: undef [[COPY171:%[0-9]+]].sub24:vreg_1024_align2 = COPY [[COPY50]].sub24
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_28:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub24, [[COPY171]].sub24, implicit $exec
+ ; CHECK-NEXT: [[COPY33:%[0-9]+]]:vreg_64_align2 = COPY [[COPY148]]
+ ; CHECK-NEXT: undef [[COPY172:%[0-9]+]].sub26:vreg_1024_align2 = COPY [[COPY49]].sub26
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_29:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub26, [[COPY172]].sub26, implicit $exec
+ ; CHECK-NEXT: [[COPY36:%[0-9]+]]:vreg_64_align2 = COPY [[COPY153]]
+ ; CHECK-NEXT: undef [[COPY173:%[0-9]+]].sub28:vreg_1024_align2 = COPY [[COPY48]].sub28
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_30:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub28, [[COPY173]].sub28, implicit $exec
+ ; CHECK-NEXT: [[COPY42:%[0-9]+]]:vreg_64_align2 = COPY [[COPY154]]
+ ; CHECK-NEXT: undef [[V_XOR_B32_e32_31:%[0-9]+]].sub0:vreg_128_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub0, [[BUFFER_LOAD_DWORD_OFFEN30]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_30:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_13]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_45:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 17, [[V_XOR_B32_e32_16]], implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_27:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 14, [[V_XOR_B32_e32_30]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_27:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_27]].sub3, [[V_LSHLREV_B32_e32_45]], implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_29:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_12]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_46:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 18, [[V_XOR_B32_e32_30]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_27:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 13, [[V_XOR_B32_e32_29]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_27:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_27]].sub1, [[V_LSHLREV_B32_e32_46]], implicit $exec
+ ; CHECK-NEXT: undef %2564.sub0:vreg_64_align2, renamable $sgpr38_sgpr39 = V_ADD_CO_U32_e64 24, [[SI_SPILL_AV64_RESTORE18]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: %2564.sub1:vreg_64_align2, dead renamable $sgpr38_sgpr39 = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE18]].sub1, killed $sgpr38_sgpr39, 0, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2564, [[V_LSHRREV_B64_e64_27]], 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 104, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_XOR_B32_e32_28:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_11]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_47:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 19, [[V_XOR_B32_e32_29]].sub0, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_28:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 12, [[V_XOR_B32_e32_28]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_28:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_28]].sub3, [[V_LSHLREV_B32_e32_47]], implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_27:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_10]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_48:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 20, [[V_XOR_B32_e32_28]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_28:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 11, [[V_XOR_B32_e32_27]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_28:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_28]].sub1, [[V_LSHLREV_B32_e32_48]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2564, [[V_LSHRREV_B64_e64_28]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 88, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_XOR_B32_e32_26:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_9]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_49:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 21, [[V_XOR_B32_e32_27]].sub0, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_29:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 10, [[V_XOR_B32_e32_26]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_29:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_29]].sub3, [[V_LSHLREV_B32_e32_49]], implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_25:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_8]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_50:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 22, [[V_XOR_B32_e32_26]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_29:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 9, [[V_XOR_B32_e32_25]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_29:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_29]].sub1, [[V_LSHLREV_B32_e32_50]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2564, [[V_LSHRREV_B64_e64_29]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 72, align 8, basealign 128)
+ ; CHECK-NEXT: renamable $sgpr38 = S_MOV_B32 124
+ ; CHECK-NEXT: undef %731.sub0:vreg_64_align2, renamable $sgpr38_sgpr39 = V_ADD_CO_U32_e64 killed $sgpr38, [[SI_SPILL_AV64_RESTORE18]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: %731.sub1:vreg_64_align2, dead renamable $sgpr38_sgpr39 = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE18]].sub1, killed $sgpr38_sgpr39, 0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 15, [[V_XOR_B32_e32_15]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_SHORT %731, [[V_LSHRREV_B32_e32_3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %ir.sink + 124, align 4, basealign 128)
+ ; CHECK-NEXT: [[V_ALIGNBIT_B32_opsel_e64_3:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[V_XOR_B32_e32_15]], 0, [[V_XOR_B32_e32_16]], 0, 15, 0, 0, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr38 = S_MOV_B32 120
+ ; CHECK-NEXT: undef %735.sub0:vreg_64_align2, renamable $sgpr38_sgpr39 = V_ADD_CO_U32_e64 killed $sgpr38, [[SI_SPILL_AV64_RESTORE18]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: %735.sub1:vreg_64_align2, dead renamable $sgpr38_sgpr39 = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE18]].sub1, killed $sgpr38_sgpr39, 0, implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORD %735, [[V_ALIGNBIT_B32_opsel_e64_3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.sink + 120, align 8, basealign 128)
+ ; CHECK-NEXT: [[V_AND_B32_e32_36:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_14]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_51:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 31, [[V_XOR_B32_e32_17]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_31:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_AND_B32_e32_36]], [[V_LSHLREV_B32_e32_51]], implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_24:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_7]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_52:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 23, [[V_XOR_B32_e32_25]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_30:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 8, [[V_XOR_B32_e32_24]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_30:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_30]].sub1, [[V_LSHLREV_B32_e32_52]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE18]], [[V_LSHRREV_B64_e64_30]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 64, align 64, basealign 128)
+ ; CHECK-NEXT: [[V_XOR_B32_e32_23:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_6]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_53:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_XOR_B32_e32_24]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_31:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 7, [[V_XOR_B32_e32_23]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_31:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_31]].sub1, [[V_LSHLREV_B32_e32_53]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2564, [[V_LSHRREV_B64_e64_31]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 56, basealign 128)
+ ; CHECK-NEXT: [[V_XOR_B32_e32_22:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_5]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_54:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 25, [[V_XOR_B32_e32_23]].sub0, implicit $exec
+ ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_32:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 6, [[V_XOR_B32_e32_22]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_32:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_32]].sub3, [[V_LSHLREV_B32_e32_54]], implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_21:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_4]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_32:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 5, [[V_XOR_B32_e32_21]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_55:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 26, [[V_XOR_B32_e32_22]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_32:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_32]].sub1, [[V_LSHLREV_B32_e32_55]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2564, [[V_LSHRREV_B64_e64_32]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 40, align 8, basealign 128)
+ ; CHECK-NEXT: [[COPY174:%[0-9]+]]:vgpr_32 = COPY [[COPY162]]
+ ; CHECK-NEXT: undef [[COPY175:%[0-9]+]].sub0:vreg_64_align2 = COPY [[V_XOR_B32_e32_20]].sub0
+ ; CHECK-NEXT: [[COPY175:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY174]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_33:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 4, [[COPY175]], implicit $exec
+ ; CHECK-NEXT: undef [[COPY176:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY175]].sub0
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_56:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 27, [[V_XOR_B32_e32_21]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_33:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_33]].sub1, [[V_LSHLREV_B32_e32_56]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE18]], [[V_LSHRREV_B64_e64_33]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 32, align 32, basealign 128)
+ ; CHECK-NEXT: [[COPY177:%[0-9]+]]:vgpr_32 = COPY [[COPY161]]
+ ; CHECK-NEXT: undef [[COPY178:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY168]].sub0
+ ; CHECK-NEXT: [[COPY178:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY177]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_34:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 3, [[COPY178]], implicit $exec
+ ; CHECK-NEXT: undef [[COPY179:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY178]].sub0
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_57:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 28, [[COPY176]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_34:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_34]].sub1, [[V_LSHLREV_B32_e32_57]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2564, [[V_LSHRREV_B64_e64_34]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 24, basealign 128)
+ ; CHECK-NEXT: [[COPY180:%[0-9]+]]:vgpr_32 = COPY [[COPY160]]
+ ; CHECK-NEXT: undef [[COPY181:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY167]].sub0
+ ; CHECK-NEXT: [[COPY181:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY180]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_35:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 2, [[COPY181]], implicit $exec
+ ; CHECK-NEXT: undef [[COPY182:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY181]].sub0
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_58:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 29, [[COPY179]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_35:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_35]].sub1, [[V_LSHLREV_B32_e32_58]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE18]], [[V_LSHRREV_B64_e64_35]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 16, align 16, basealign 128)
+ ; CHECK-NEXT: undef [[COPY183:%[0-9]+]].sub0:vreg_64_align2 = COPY [[V_XOR_B32_e32_17]].sub0
+ ; CHECK-NEXT: [[COPY184:%[0-9]+]]:vgpr_32 = COPY [[COPY158]]
+ ; CHECK-NEXT: [[COPY183:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY184]], implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_31:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 1, [[COPY183]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e32_59:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 30, [[COPY182]].sub0, implicit $exec
+ ; CHECK-NEXT: [[V_XOR_B32_e32_31:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_XOR_B32_e32_31]].sub3, [[V_LSHLREV_B32_e32_59]], implicit $exec
+ ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE18]], [[V_XOR_B32_e32_31]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
+ ; CHECK-NEXT: renamable $sgpr54_sgpr55 = S_XOR_B64 $exec, -1, implicit-def dead $scc
+ ; CHECK-NEXT: S_BRANCH %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.49.Flow48:
+ ; CHECK-NEXT: successors: %bb.42(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr56_sgpr57, implicit-def $scc
+ ; CHECK-NEXT: renamable $sgpr48_sgpr49 = S_ANDN2_B64 killed renamable $sgpr48_sgpr49, $exec, implicit-def dead $scc
+ ; CHECK-NEXT: S_BRANCH %bb.42
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.51.UnifiedReturnBlock:
+ ; CHECK-NEXT: liveins: $vgpr63, $sgpr56_sgpr57
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr56_sgpr57, implicit-def $scc
+ ; CHECK-NEXT: $sgpr30 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 14, implicit-def $sgpr30_sgpr31
+ ; CHECK-NEXT: $sgpr31 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 15
+ ; CHECK-NEXT: $sgpr55 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 13
+ ; CHECK-NEXT: $sgpr54 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 12
+ ; CHECK-NEXT: $sgpr53 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 11
+ ; CHECK-NEXT: $sgpr52 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 10
+ ; CHECK-NEXT: $sgpr51 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 9
+ ; CHECK-NEXT: $sgpr50 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 8
+ ; CHECK-NEXT: $sgpr49 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 7
+ ; CHECK-NEXT: $sgpr48 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 6
+ ; CHECK-NEXT: $sgpr39 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 5
+ ; CHECK-NEXT: $sgpr38 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 4
+ ; CHECK-NEXT: $sgpr37 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 3
+ ; CHECK-NEXT: $sgpr36 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 2
+ ; CHECK-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 1
+ ; CHECK-NEXT: $sgpr34 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 0
+ ; CHECK-NEXT: SI_RETURN
+ <16 x double> %da, <16 x double> %db,
+ <16 x i63> %v, <16 x i63> %w, <16 x i63> %a,
+ ptr %sink, i32 %disc, i1 %c) #0 {
+entry:
+ switch i32 %disc, label %bb0 [
+ i32 2, label %bb1
+ i32 3, label %bb2
+ ]
+bb0:
+ br i1 %c, label %bb0a, label %bb0b
+bb0a:
+ store <16 x i63> %a, ptr %sink
+ ret void
+bb0b:
+ %ld = call <16 x i63> @llvm.masked.load.v16i63.p0(ptr %p, <16 x i1> %m, <16 x i63> %pt)
+ store <16 x i63> %ld, ptr %sink
+ ret void
+bb1:
+ br i1 %c, label %bb1a, label %bb1b
+bb1a:
+ %sel = select <16 x i1> %sc, <16 x double> %da, <16 x double> %db
+ store <16 x double> %sel, ptr %sink
+ ret void
+bb1b:
+ store <16 x i63> %v, ptr %sink
+ ret void
+bb2:
+ %x = xor <16 x i63> %a, %w
+ store <16 x i63> %x, ptr %sink
+ ret void
+}
>From e280f813fca4c95e1d05528405c2f0e05a69c3af Mon Sep 17 00:00:00 2001
From: Steffen Holst Larsen <sholstla at amd.com>
Date: Wed, 3 Jun 2026 07:12:10 -0500
Subject: [PATCH 2/2] Add nounwind and let llc run full
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
---
.../splitkit-getsubrangeformask-phi-extend.ll | 1493 +----------------
1 file changed, 5 insertions(+), 1488 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
index 388633fe5bb56..b9ea2e26c9f55 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
@@ -1,1496 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stop-after=greedy,2 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o /dev/null
+
+; Regression test ensuring that empty subranges are not prematurely eliminated.
declare <16 x i63> @llvm.masked.load.v16i63.p0(ptr, <16 x i1>, <16 x i63>)
define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
- ; CHECK-LABEL: name: f
- ; CHECK: bb.0.entry:
- ; CHECK-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-NEXT: liveins: $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr63, $sgpr30_sgpr31
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr34, 0, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr34, $vgpr63, 0, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr35, 1, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr35, $vgpr63, 1, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr36, 2, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr36, $vgpr63, 2, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr37, 3, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr37, $vgpr63, 3, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr38, 4, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr38, $vgpr63, 4, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr39, 5, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr39, $vgpr63, 5, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr48, 6, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr48, $vgpr63, 6, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr49, 7, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr49, $vgpr63, 7, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr50, 8, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr50, $vgpr63, 8, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr51, 9, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr51, $vgpr63, 9, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr52, 10, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr52, $vgpr63, 10, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr53, 11, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr53, $vgpr63, 11, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr54, 12, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr54, $vgpr63, 12, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr55, 13, $vgpr63
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr55, $vgpr63, 13, 32
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr30, 14, $vgpr63, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
- ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 15, $vgpr63, implicit killed $sgpr30_sgpr31
- ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr63, 14, 32, $vgpr63, 15, 32
- ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr30
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY]], %stack.16, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.16, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr29
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY1]], %stack.18, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.18, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr28
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY2]], %stack.31, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.31, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr27
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY3]], %stack.19, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.19, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY4:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr26
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY4]], %stack.20, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.20, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY5:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr25
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY5]], %stack.22, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.22, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY6:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr24
- ; CHECK-NEXT: undef [[COPY7:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr23
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY7]], %stack.21, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.21, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY8:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr22
- ; CHECK-NEXT: undef [[COPY9:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr21
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY9]], %stack.23, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.23, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY10:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr20
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY10]], %stack.24, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.24, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY11:%[0-9]+]].sub2:av_128_align2 = COPY $vgpr19
- ; CHECK-NEXT: [[COPY11:%[0-9]+]].sub0:av_128_align2 = COPY $vgpr18
- ; CHECK-NEXT: undef [[COPY12:%[0-9]+]].sub0:av_128_align2 = COPY [[COPY11]].sub0 {
- ; CHECK-NEXT: internal [[COPY12]].sub2:av_128_align2 = COPY [[COPY11]].sub2
- ; CHECK-NEXT: }
- ; CHECK-NEXT: SI_SPILL_AV128_SAVE [[COPY12]], %stack.26, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.26, align 4, addrspace 5)
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY $vgpr17
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY $vgpr16
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY $vgpr15
- ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY $vgpr14
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY $vgpr13
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY $vgpr12
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY $vgpr11
- ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY $vgpr10
- ; CHECK-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY $vgpr9
- ; CHECK-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY $vgpr8
- ; CHECK-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY $vgpr7
- ; CHECK-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY $vgpr6
- ; CHECK-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY $vgpr5
- ; CHECK-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY $vgpr4
- ; CHECK-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY $vgpr3
- ; CHECK-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY $vgpr2
- ; CHECK-NEXT: undef [[COPY29:%[0-9]+]].sub1:av_64_align2 = COPY $vgpr1
- ; CHECK-NEXT: [[COPY29:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr0
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY29]], %stack.25, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.25, align 4, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.164, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.164, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.165, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.165, align 4, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.166, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.166, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.167, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.167, align 4, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN4:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.168, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.168, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN5:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.169, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.169, align 4, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN6:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.170, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.170, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN7:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.171, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.171, align 4, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN8:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.172, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.172, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN9:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.173, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.173, align 4, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN10:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.174, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.174, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN11:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.175, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.175, align 4, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN12:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.176, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.176, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN13:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.177, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.177, align 4, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN14:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.178, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.178, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN15:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.179, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.179, align 4, addrspace 5)
- ; CHECK-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY13]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY14]], implicit $exec
- ; CHECK-NEXT: renamable $vcc = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_2:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_3:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN1]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_4:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN2]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_5:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN3]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_6:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN4]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_7:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN5]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_8:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN6]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_9:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN7]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_10:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN8]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_11:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN9]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_12:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN10]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_13:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN11]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_14:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN12]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_15:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN13]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_16:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN14]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_17:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN15]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr40_sgpr41 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_2]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr44_sgpr45 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_3]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr26_sgpr27 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_4]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr42_sgpr43 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_5]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr22_sgpr23 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_6]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr28_sgpr29 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_7]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr18_sgpr19 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_8]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr24_sgpr25 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_9]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr14_sgpr15 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_10]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr20_sgpr21 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_11]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr10_sgpr11 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_12]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr16_sgpr17 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_13]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr6_sgpr7 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_14]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr12_sgpr13 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_15]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr8_sgpr9 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_16]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_17]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr56_sgpr57 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_1]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_18:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY15]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr58_sgpr59 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_18]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_19:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY16]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr60_sgpr61 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_19]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_20:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY17]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr62_sgpr63 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_20]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_21:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY18]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr72_sgpr73 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_21]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_22:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY19]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr74_sgpr75 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_22]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_23:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY20]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr76_sgpr77 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_23]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_24:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY21]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr78_sgpr79 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_24]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_25:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY22]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr88_sgpr89 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_25]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_26:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY23]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr90_sgpr91 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_26]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_27:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY24]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr92_sgpr93 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_27]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_28:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY25]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr94_sgpr95 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_28]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_29:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY26]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr30_sgpr31 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_29]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_30:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY27]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr34_sgpr35 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_30]], implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_31:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY28]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr36_sgpr37 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_31]], implicit $exec
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub31:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.100, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.100, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.101, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.101, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub29:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.102, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.102, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.103, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.103, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub27:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.104, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.104, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.105, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.105, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN %fixed-stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8) from %fixed-stack.0, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.1, addrspace 5)
- ; CHECK-NEXT: [[V_AND_B32_e32_32:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_UBYTE_OFFEN]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr46_sgpr47 = V_CMP_NE_U32_e64 1, [[V_AND_B32_e32_32]], implicit $exec
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub25:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.106, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.106, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub24:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.107, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.107, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub23:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.108, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.108, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub22:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.109, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.109, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub21:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.110, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.110, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub20:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.111, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.111, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub19:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.112, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.112, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub18:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.113, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.113, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub17:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.114, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.114, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub16:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.115, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.115, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub15:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.116, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.116, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub14:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.117, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.117, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub13:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.118, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.118, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub12:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.119, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.119, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub11:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.120, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.120, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub10:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.121, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.121, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub9:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.122, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.122, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub8:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.123, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.123, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub7:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.124, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.124, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub6:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.125, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.125, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub5:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.126, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.126, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub4:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.127, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.127, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub3:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.128, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.128, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub2:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.129, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.129, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub1:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.130, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.130, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub0:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.131, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.131, addrspace 5)
- ; CHECK-NEXT: SI_SPILL_AV1024_SAVE [[BUFFER_LOAD_DWORD_OFFEN]], %stack.15, $sgpr32, 0, implicit $exec :: (store (s1024) into %stack.15, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub31:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.132, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.132, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.133, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.133, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub29:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.134, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.134, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.135, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.135, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub27:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.136, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.136, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.137, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.137, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub25:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.138, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.138, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub24:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.139, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.139, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub23:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.140, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.140, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub22:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.141, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.141, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub21:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.142, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.142, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub20:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.143, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.143, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub19:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.144, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.144, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub18:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.145, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.145, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub17:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.146, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.146, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub16:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.147, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.147, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub15:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.148, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.148, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub14:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.149, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.149, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub13:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.150, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.150, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub12:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.151, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.151, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub11:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.152, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.152, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub10:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.153, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.153, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub9:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.154, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.154, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub8:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.155, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.155, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub7:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.156, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.156, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub6:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.157, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.157, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub5:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.158, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.158, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub4:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.159, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.159, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub3:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.160, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.160, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub2:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.161, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.161, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub1:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.162, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.162, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN2:%[0-9]+]].sub0:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.163, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.163, addrspace 5)
- ; CHECK-NEXT: SI_SPILL_AV1024_SAVE [[BUFFER_LOAD_DWORD_OFFEN2]], %stack.17, $sgpr32, 0, implicit $exec :: (store (s1024) into %stack.17, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.20, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.20, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.21, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.21, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.22, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.22, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub24:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.23, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.23, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub22:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.24, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.24, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub20:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.25, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.25, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub18:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.26, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.26, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub16:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.27, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.27, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub14:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.28, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.28, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub12:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.29, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.29, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub10:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.30, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.30, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub8:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.31, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.31, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub6:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.32, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.32, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub4:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.33, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.33, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub1:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub3:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub5:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub7:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub9:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub11:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub13:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub15:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub17:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub19:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub21:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub23:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub25:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub27:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub29:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub31:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub2:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.34, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN3:%[0-9]+]].sub0:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.35, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.35, addrspace 5)
- ; CHECK-NEXT: SI_SPILL_AV1024_SAVE [[BUFFER_LOAD_DWORD_OFFEN3]], %stack.33, $sgpr32, 0, implicit $exec :: (store (s1024) into %stack.33, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN4:%[0-9]+]].sub0:vreg_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.95, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.95, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN4:%[0-9]+]].sub1:vreg_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY30:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY30:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.96, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.96, align 8, addrspace 5)
- ; CHECK-NEXT: [[COPY31:%[0-9]+]]:av_64_align2 = COPY [[COPY30]]
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN5:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.94, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.94, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN5:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY32:%[0-9]+]]:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN5]]
- ; CHECK-NEXT: undef [[COPY33:%[0-9]+]].sub1:vreg_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY33:%[0-9]+]].sub0:vreg_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.97, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.97, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN6:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.93, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.93, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN6:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY34:%[0-9]+]]:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN6]]
- ; CHECK-NEXT: undef [[COPY35:%[0-9]+]].sub3:vreg_128_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub2:vreg_128_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.98, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.98, align 16, addrspace 5)
- ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub0:vreg_128_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.99, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.99, addrspace 5)
- ; CHECK-NEXT: undef [[COPY36:%[0-9]+]].sub1:vreg_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY36:%[0-9]+]].sub0:vreg_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.92, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.92, align 8, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN7:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.88, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.88, align 8, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN7:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY37:%[0-9]+]]:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN7]]
- ; CHECK-NEXT: undef [[COPY38:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY38:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.89, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.89, addrspace 5)
- ; CHECK-NEXT: [[COPY39:%[0-9]+]]:av_64_align2 = COPY [[COPY38]]
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN8:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.87, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.87, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN8:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[BUFFER_LOAD_DWORD_OFFEN8]], %stack.27, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.27, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY40:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY40:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.90, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.90, align 16, addrspace 5)
- ; CHECK-NEXT: [[COPY41:%[0-9]+]]:av_64_align2 = COPY [[COPY40]]
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN9:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.86, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.86, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN9:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[BUFFER_LOAD_DWORD_OFFEN9]], %stack.28, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.28, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY42:%[0-9]+]].sub1:vreg_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY42:%[0-9]+]].sub0:vreg_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.91, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.91, addrspace 5)
- ; CHECK-NEXT: undef [[COPY43:%[0-9]+]].sub1:av_64_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: [[COPY43:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.85, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.85, addrspace 5)
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY43]], %stack.29, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.29, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN10:%[0-9]+]].sub1:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.2, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.2, align 16, addrspace 5)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN10:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.3, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.3, addrspace 5)
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[BUFFER_LOAD_DWORD_OFFEN10]], %stack.34, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.34, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN11:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.196, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.196, align 8, addrspace 5)
- ; CHECK-NEXT: undef [[COPY44:%[0-9]+]].sub0:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN11]].sub0
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN12:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.197, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.197, addrspace 5)
- ; CHECK-NEXT: undef [[COPY45:%[0-9]+]].sub0:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN12]].sub0
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN13:%[0-9]+]].sub0:av_64_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.198, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.198, align 16, addrspace 5)
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[BUFFER_LOAD_DWORD_OFFEN13]], %stack.30, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.30, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN14:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.84, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.84, align 8, addrspace 5)
- ; CHECK-NEXT: undef [[COPY46:%[0-9]+]].sub30:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN14]].sub30
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN15:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.52, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.52, align 8, addrspace 5)
- ; CHECK-NEXT: undef [[COPY47:%[0-9]+]].sub30:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN15]].sub30
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN16:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.53, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.53, addrspace 5)
- ; CHECK-NEXT: undef [[COPY48:%[0-9]+]].sub28:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN16]].sub28
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN17:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.54, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.54, align 16, addrspace 5)
- ; CHECK-NEXT: undef [[COPY49:%[0-9]+]].sub26:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN17]].sub26
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN18:%[0-9]+]].sub24:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.55, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.55, addrspace 5)
- ; CHECK-NEXT: undef [[COPY50:%[0-9]+]].sub24:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN18]].sub24
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN19:%[0-9]+]].sub22:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.56, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.56, align 8, addrspace 5)
- ; CHECK-NEXT: undef [[COPY51:%[0-9]+]].sub22:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN19]].sub22
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN20:%[0-9]+]].sub20:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.57, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.57, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN21:%[0-9]+]].sub18:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.58, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.58, align 16, addrspace 5)
- ; CHECK-NEXT: undef [[COPY52:%[0-9]+]].sub18:av_1024_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN21]].sub18
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN22:%[0-9]+]].sub16:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.59, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.59, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN23:%[0-9]+]].sub14:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.60, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.60, align 8, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN24:%[0-9]+]].sub12:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.61, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.61, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN25:%[0-9]+]].sub10:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.62, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.62, align 16, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN26:%[0-9]+]].sub8:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.63, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.63, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN27:%[0-9]+]].sub6:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.64, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.64, align 8, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN28:%[0-9]+]].sub4:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.65, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.65, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN29:%[0-9]+]].sub2:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.66, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.66, align 16, addrspace 5)
- ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN30:%[0-9]+]].sub0:vreg_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.67, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.67, addrspace 5)
- ; CHECK-NEXT: undef [[COPY53:%[0-9]+]].sub1:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY54:%[0-9]+]].sub3:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY55:%[0-9]+]].sub5:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY56:%[0-9]+]].sub7:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY57:%[0-9]+]].sub9:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY58:%[0-9]+]].sub11:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY59:%[0-9]+]].sub13:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY60:%[0-9]+]].sub15:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY61:%[0-9]+]].sub17:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY62:%[0-9]+]].sub19:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY63:%[0-9]+]].sub21:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY64:%[0-9]+]].sub23:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY65:%[0-9]+]].sub25:vreg_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY66:%[0-9]+]].sub27:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY67:%[0-9]+]].sub29:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY68:%[0-9]+]].sub31:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: undef [[COPY69:%[0-9]+]].sub1:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: SI_SPILL_AV1024_SAVE [[COPY69]], %stack.32, $sgpr32, 0, implicit $exec :: (store (s1024) into %stack.32, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY70:%[0-9]+]].sub31:av_1024_align2 = COPY undef renamable $sgpr4
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1.NodeBlock:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.47(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr38_sgpr39 = V_CMP_LT_I32_e64 2, [[BUFFER_LOAD_DWORD_OFFEN1]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
- ; CHECK-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 0
- ; CHECK-NEXT: renamable $sgpr50_sgpr51 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr38_sgpr39 = S_AND_B64 renamable $sgpr50_sgpr51, killed renamable $sgpr38_sgpr39, implicit-def dead $scc
- ; CHECK-NEXT: renamable $sgpr50_sgpr51 = S_XOR_B64 renamable $sgpr38_sgpr39, killed renamable $sgpr50_sgpr51, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr38_sgpr39
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.47, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2.LeafBlock46:
- ; CHECK-NEXT: successors: %bb.48(0x40000000), %bb.3(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr38_sgpr39 = V_CMP_EQ_U32_e64 3, [[BUFFER_LOAD_DWORD_OFFEN1]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 -1
- ; CHECK-NEXT: renamable $sgpr52_sgpr53 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr38_sgpr39 = S_AND_B64 renamable $sgpr52_sgpr53, killed renamable $sgpr38_sgpr39, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr38_sgpr39
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.48
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.Flow52:
- ; CHECK-NEXT: successors: %bb.47(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr52_sgpr53, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; CHECK-NEXT: S_BRANCH %bb.47
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.LeafBlock:
- ; CHECK-NEXT: successors: %bb.5(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr38_sgpr39 = V_CMP_NE_U32_e64 2, [[BUFFER_LOAD_DWORD_OFFEN1]], implicit $exec
- ; CHECK-NEXT: renamable $sgpr48_sgpr49 = S_ANDN2_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
- ; CHECK-NEXT: renamable $sgpr38_sgpr39 = S_AND_B64 killed renamable $sgpr38_sgpr39, $exec, implicit-def dead $scc
- ; CHECK-NEXT: renamable $sgpr52_sgpr53 = S_OR_B64 killed renamable $sgpr48_sgpr49, killed renamable $sgpr38_sgpr39, implicit-def dead $scc
- ; CHECK-NEXT: renamable $sgpr48_sgpr49 = COPY $exec
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.5.Flow53:
- ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.42(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr50_sgpr51, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr38_sgpr39 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr50_sgpr51 = S_AND_B64 renamable $sgpr38_sgpr39, killed renamable $sgpr52_sgpr53, implicit-def dead $scc
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.25, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.25, align 4, addrspace 5)
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr50_sgpr51
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.42, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.6
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.6.bb0:
- ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.10(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr50_sgpr51 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr52_sgpr53 = S_AND_B64 renamable $sgpr50_sgpr51, renamable $sgpr46_sgpr47, implicit-def dead $scc
- ; CHECK-NEXT: renamable $sgpr50_sgpr51 = S_XOR_B64 renamable $sgpr52_sgpr53, killed renamable $sgpr50_sgpr51, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr52_sgpr53
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.10, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.7.bb0a:
- ; CHECK-NEXT: successors: %bb.49(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE1:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 124, [[SI_SPILL_AV64_RESTORE1]].sub0, implicit-def $vcc, implicit $exec
- ; CHECK-NEXT: [[V_ADD_CO_U32_e32_]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE1]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: [[COPY71:%[0-9]+]]:av_64_align2 = COPY [[COPY39]]
- ; CHECK-NEXT: [[COPY72:%[0-9]+]]:av_64_align2 = COPY [[COPY37]]
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]]:vreg_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.33, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.33, align 4, addrspace 5)
- ; CHECK-NEXT: [[V_LSHRREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 15, [[SI_SPILL_AV1024_RESTORE]].sub31, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_SHORT [[V_ADD_CO_U32_e32_]], [[V_LSHRREV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %ir.sink + 124, align 4, basealign 128)
- ; CHECK-NEXT: [[V_ALIGNBIT_B32_opsel_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[SI_SPILL_AV1024_RESTORE]].sub31, 0, [[SI_SPILL_AV1024_RESTORE]].sub30, 0, 15, 0, 0, implicit $exec
- ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 120, [[SI_SPILL_AV64_RESTORE1]].sub0, implicit-def $vcc, implicit $exec
- ; CHECK-NEXT: [[V_ADD_CO_U32_e32_1]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE1]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORD [[V_ADD_CO_U32_e32_1]], [[V_ALIGNBIT_B32_opsel_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.sink + 120, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 31, [[SI_SPILL_AV1024_RESTORE]].sub2, implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_33:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub1, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub1:vreg_1024_align2 = V_OR_B32_e32 [[V_AND_B32_e32_33]], [[V_LSHLREV_B32_e32_]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 17, [[SI_SPILL_AV1024_RESTORE]].sub30, implicit $exec
- ; CHECK-NEXT: [[COPY37:%[0-9]+]]:av_64_align2 = COPY [[COPY72]]
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub29:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub29, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 14, [[SI_SPILL_AV1024_RESTORE]].sub28_sub29, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_]].sub3, [[V_LSHLREV_B32_e32_1]], implicit $exec
- ; CHECK-NEXT: undef %2534.sub0:vreg_64_align2, renamable $vcc = V_ADD_CO_U32_e64 24, [[SI_SPILL_AV64_RESTORE1]].sub0, 0, implicit $exec
- ; CHECK-NEXT: %2534.sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE1]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 18, [[SI_SPILL_AV1024_RESTORE]].sub28, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub27:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub27, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 13, [[SI_SPILL_AV1024_RESTORE]].sub26_sub27, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_]].sub1, [[V_LSHLREV_B32_e32_2]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2534, [[V_LSHRREV_B64_e64_]], 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 104, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 19, [[SI_SPILL_AV1024_RESTORE]].sub26, implicit $exec
- ; CHECK-NEXT: [[COPY39:%[0-9]+]]:av_64_align2 = COPY [[COPY71]]
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub25:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub25, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_1:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 12, [[SI_SPILL_AV1024_RESTORE]].sub24_sub25, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_1:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_1]].sub3, [[V_LSHLREV_B32_e32_3]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 20, [[SI_SPILL_AV1024_RESTORE]].sub24, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub23:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub23, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_1:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 11, [[SI_SPILL_AV1024_RESTORE]].sub22_sub23, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_1:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_1]].sub1, [[V_LSHLREV_B32_e32_4]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2534, [[V_LSHRREV_B64_e64_1]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 88, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_5:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 21, [[SI_SPILL_AV1024_RESTORE]].sub22, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub21:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub21, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_2:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 10, [[SI_SPILL_AV1024_RESTORE]].sub20_sub21, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_2:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_2]].sub3, [[V_LSHLREV_B32_e32_5]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_6:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 22, [[SI_SPILL_AV1024_RESTORE]].sub20, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub19:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub19, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_2:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 9, [[SI_SPILL_AV1024_RESTORE]].sub18_sub19, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_2:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_2]].sub1, [[V_LSHLREV_B32_e32_6]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2534, [[V_LSHRREV_B64_e64_2]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 72, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_7:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 23, [[SI_SPILL_AV1024_RESTORE]].sub18, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub17:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub17, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_3:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 8, [[SI_SPILL_AV1024_RESTORE]].sub16_sub17, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_3:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_3]].sub1, [[V_LSHLREV_B32_e32_7]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE1]], [[V_LSHRREV_B64_e64_3]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 64, align 64, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_8:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[SI_SPILL_AV1024_RESTORE]].sub16, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub15:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub15, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_4:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 7, [[SI_SPILL_AV1024_RESTORE]].sub14_sub15, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_4:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_4]].sub1, [[V_LSHLREV_B32_e32_8]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2534, [[V_LSHRREV_B64_e64_4]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 56, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_9:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 25, [[SI_SPILL_AV1024_RESTORE]].sub14, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub13:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub13, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_5:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 6, [[SI_SPILL_AV1024_RESTORE]].sub12_sub13, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_5:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_5]].sub3, [[V_LSHLREV_B32_e32_9]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_10:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 26, [[SI_SPILL_AV1024_RESTORE]].sub12, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub11:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub11, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_5:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 5, [[SI_SPILL_AV1024_RESTORE]].sub10_sub11, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_5:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_5]].sub1, [[V_LSHLREV_B32_e32_10]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2534, [[V_LSHRREV_B64_e64_5]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 40, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_11:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 27, [[SI_SPILL_AV1024_RESTORE]].sub10, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub9:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub9, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_6:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 4, [[SI_SPILL_AV1024_RESTORE]].sub8_sub9, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_6:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_6]].sub1, [[V_LSHLREV_B32_e32_11]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE1]], [[V_LSHRREV_B64_e64_6]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 32, align 32, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_12:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 28, [[SI_SPILL_AV1024_RESTORE]].sub8, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub7:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub7, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_7:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 3, [[SI_SPILL_AV1024_RESTORE]].sub6_sub7, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_7:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_7]].sub1, [[V_LSHLREV_B32_e32_12]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2534, [[V_LSHRREV_B64_e64_7]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 24, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_13:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 29, [[SI_SPILL_AV1024_RESTORE]].sub6, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub5:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub5, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_8:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 2, [[SI_SPILL_AV1024_RESTORE]].sub4_sub5, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_8:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_8]].sub1, [[V_LSHLREV_B32_e32_13]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE1]], [[V_LSHRREV_B64_e64_8]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 16, align 16, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_14:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 30, [[SI_SPILL_AV1024_RESTORE]].sub4, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub3:vreg_1024_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE]].sub3, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub2_sub3:vreg_1024_align2 = V_LSHRREV_B64_e64 1, [[SI_SPILL_AV1024_RESTORE]].sub2_sub3, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE:%[0-9]+]].sub3:vreg_1024_align2 = V_OR_B32_e32 [[SI_SPILL_AV1024_RESTORE]].sub3, [[V_LSHLREV_B32_e32_14]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE1]], [[SI_SPILL_AV1024_RESTORE]].sub0_sub1_sub2_sub3, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
- ; CHECK-NEXT: S_BRANCH %bb.49
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.8.bb0b:
- ; CHECK-NEXT: successors: %bb.9(0x40000000), %bb.11(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr52_sgpr53 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr36_sgpr37 = S_AND_B64 renamable $sgpr52_sgpr53, killed renamable $sgpr36_sgpr37, implicit-def dead $scc
- ; CHECK-NEXT: [[SI_SPILL_AV128_RESTORE:%[0-9]+]]:av_128_align2 = SI_SPILL_AV128_RESTORE %stack.26, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.26, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[COPY73:%[0-9]+]].sub0:vreg_128_align2 = COPY [[SI_SPILL_AV128_RESTORE]].sub0 {
- ; CHECK-NEXT: internal [[COPY73]].sub2:vreg_128_align2 = COPY [[SI_SPILL_AV128_RESTORE]].sub2
- ; CHECK-NEXT: }
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr36_sgpr37
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.11, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.9
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.9.cond.load:
- ; CHECK-NEXT: successors: %bb.11(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub0_sub1:vreg_128_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.p, align 1)
- ; CHECK-NEXT: S_BRANCH %bb.11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.10.Flow:
- ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.49(0x40000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr56_sgpr57 = S_OR_SAVEEXEC_B64 killed renamable $sgpr50_sgpr51, implicit-def $exec, implicit-def $scc, implicit $exec
- ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, renamable $sgpr56_sgpr57, implicit-def $scc
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.49, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.7
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.11.else:
- ; CHECK-NEXT: successors: %bb.12(0x40000000), %bb.13(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr52_sgpr53, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr36_sgpr37 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr34_sgpr35 = S_AND_B64 renamable $sgpr36_sgpr37, killed renamable $sgpr34_sgpr35, implicit-def dead $scc
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE2:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.24, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.24, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE3:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.23, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.23, align 4, addrspace 5)
- ; CHECK-NEXT: [[COPY74:%[0-9]+]]:vreg_64_align2 = COPY [[COPY8]]
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE4:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.21, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.21, align 4, addrspace 5)
- ; CHECK-NEXT: [[COPY75:%[0-9]+]]:vreg_64_align2 = COPY [[COPY6]]
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE5:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.22, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.22, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE6:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.20, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.20, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE7:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.19, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.19, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE8:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.31, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.31, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE9:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.18, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.18, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE10:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.16, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.16, align 4, addrspace 5)
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr34_sgpr35
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.13, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.12
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.12.cond.load1:
- ; CHECK-NEXT: successors: %bb.13(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub2_sub3:vreg_128_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 8, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.28, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.13.else2:
- ; CHECK-NEXT: successors: %bb.14(0x40000000), %bb.15(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr36_sgpr37, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr34_sgpr35 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr30_sgpr31 = S_AND_B64 renamable $sgpr34_sgpr35, killed renamable $sgpr30_sgpr31, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr30_sgpr31
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.15, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.14
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.14.cond.load4:
- ; CHECK-NEXT: successors: %bb.15(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE2:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.35, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.15.else5:
- ; CHECK-NEXT: successors: %bb.16(0x40000000), %bb.17(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr34_sgpr35, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr30_sgpr31 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr94_sgpr95 = S_AND_B64 renamable $sgpr30_sgpr31, killed renamable $sgpr94_sgpr95, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr94_sgpr95
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.17, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.16
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.16.cond.load7:
- ; CHECK-NEXT: successors: %bb.17(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE3:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 24, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.42, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.17.else8:
- ; CHECK-NEXT: successors: %bb.18(0x40000000), %bb.19(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr30_sgpr31, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr94_sgpr95 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr92_sgpr93 = S_AND_B64 renamable $sgpr94_sgpr95, killed renamable $sgpr92_sgpr93, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr92_sgpr93
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.19, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.18
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.18.cond.load10:
- ; CHECK-NEXT: successors: %bb.19(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY74:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 32, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.49, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.19.else11:
- ; CHECK-NEXT: successors: %bb.20(0x40000000), %bb.21(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr94_sgpr95, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr92_sgpr93 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr90_sgpr91 = S_AND_B64 renamable $sgpr92_sgpr93, killed renamable $sgpr90_sgpr91, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr90_sgpr91
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.21, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.20
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.20.cond.load13:
- ; CHECK-NEXT: successors: %bb.21(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr92_sgpr93
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE4:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 40, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.56, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.21.else14:
- ; CHECK-NEXT: successors: %bb.22(0x40000000), %bb.23(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr92_sgpr93
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr92_sgpr93, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr90_sgpr91 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr88_sgpr89 = S_AND_B64 renamable $sgpr90_sgpr91, killed renamable $sgpr88_sgpr89, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr88_sgpr89
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.23, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.22
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.22.cond.load16:
- ; CHECK-NEXT: successors: %bb.23(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr90_sgpr91
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY75:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 48, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.63, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.23.else17:
- ; CHECK-NEXT: successors: %bb.24(0x40000000), %bb.25(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr90_sgpr91
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr90_sgpr91, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr88_sgpr89 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr78_sgpr79 = S_AND_B64 renamable $sgpr88_sgpr89, killed renamable $sgpr78_sgpr79, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr78_sgpr79
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.25, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.24
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.24.cond.load19:
- ; CHECK-NEXT: successors: %bb.25(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr88_sgpr89
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE5:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 56, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.70, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.25.else20:
- ; CHECK-NEXT: successors: %bb.26(0x40000000), %bb.27(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr88_sgpr89
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr88_sgpr89, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr78_sgpr79 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr76_sgpr77 = S_AND_B64 renamable $sgpr78_sgpr79, killed renamable $sgpr76_sgpr77, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr76_sgpr77
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.27, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.26
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.26.cond.load22:
- ; CHECK-NEXT: successors: %bb.27(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr78_sgpr79
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE6:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 64, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.77, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.27.else23:
- ; CHECK-NEXT: successors: %bb.28(0x40000000), %bb.29(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr78_sgpr79
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr78_sgpr79, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr76_sgpr77 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr74_sgpr75 = S_AND_B64 renamable $sgpr76_sgpr77, killed renamable $sgpr74_sgpr75, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr74_sgpr75
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.29, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.28
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.28.cond.load25:
- ; CHECK-NEXT: successors: %bb.29(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr76_sgpr77
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE7:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 72, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.84, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.29.else26:
- ; CHECK-NEXT: successors: %bb.30(0x40000000), %bb.31(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr76_sgpr77
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr76_sgpr77, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr74_sgpr75 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr72_sgpr73 = S_AND_B64 renamable $sgpr74_sgpr75, killed renamable $sgpr72_sgpr73, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr72_sgpr73
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.31, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.30
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.30.cond.load28:
- ; CHECK-NEXT: successors: %bb.31(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr74_sgpr75
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE8:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 80, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.91, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.31.else29:
- ; CHECK-NEXT: successors: %bb.32(0x40000000), %bb.33(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr74_sgpr75
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr74_sgpr75, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr72_sgpr73 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr62_sgpr63 = S_AND_B64 renamable $sgpr72_sgpr73, killed renamable $sgpr62_sgpr63, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr62_sgpr63
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.33, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.32
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.32.cond.load31:
- ; CHECK-NEXT: successors: %bb.33(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr72_sgpr73
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE9:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 88, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.98, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.33.else32:
- ; CHECK-NEXT: successors: %bb.34(0x40000000), %bb.35(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr72_sgpr73
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr72_sgpr73, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr62_sgpr63 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr60_sgpr61 = S_AND_B64 renamable $sgpr62_sgpr63, killed renamable $sgpr60_sgpr61, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr60_sgpr61
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.35, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.34
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.34.cond.load34:
- ; CHECK-NEXT: successors: %bb.35(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr62_sgpr63
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE10:%[0-9]+]]:vreg_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 96, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.105, align 1)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.35.else35:
- ; CHECK-NEXT: successors: %bb.36(0x40000000), %bb.37(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr62_sgpr63
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr62_sgpr63, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr60_sgpr61 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr58_sgpr59 = S_AND_B64 renamable $sgpr60_sgpr61, killed renamable $sgpr58_sgpr59, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr58_sgpr59
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.37, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.36
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.36.cond.load37:
- ; CHECK-NEXT: successors: %bb.37(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr60_sgpr61
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:av_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 104, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.112, align 1)
- ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[FLAT_LOAD_DWORDX2_]], %stack.30, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.30, align 4, addrspace 5)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.37.else38:
- ; CHECK-NEXT: successors: %bb.38(0x40000000), %bb.39(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr60_sgpr61
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr60_sgpr61, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr58_sgpr59 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr56_sgpr57 = S_AND_B64 renamable $sgpr58_sgpr59, killed renamable $sgpr56_sgpr57, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr56_sgpr57
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.39, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.38
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.38.cond.load40:
- ; CHECK-NEXT: successors: %bb.39(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[FLAT_LOAD_DWORDX2_1:%[0-9]+]]:av_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 112, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.119, align 1)
- ; CHECK-NEXT: [[COPY45:%[0-9]+]]:av_64_align2 = COPY [[FLAT_LOAD_DWORDX2_1]]
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.39.else41:
- ; CHECK-NEXT: successors: %bb.40(0x40000000), %bb.41(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr58_sgpr59, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr56_sgpr57 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr58_sgpr59 = S_AND_B64 renamable $sgpr56_sgpr57, killed renamable $vcc, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr58_sgpr59
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.41, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.40
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.40.cond.load43:
- ; CHECK-NEXT: successors: %bb.41(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[FLAT_LOAD_DWORDX2_2:%[0-9]+]]:av_64_align2 = FLAT_LOAD_DWORDX2 [[SI_SPILL_AV64_RESTORE]], 120, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %ir.126, align 1)
- ; CHECK-NEXT: [[COPY44:%[0-9]+]]:av_64_align2 = COPY [[FLAT_LOAD_DWORDX2_2]]
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.41.else44:
- ; CHECK-NEXT: successors: %bb.10(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr56_sgpr57, implicit-def $scc
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE11:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 124, [[SI_SPILL_AV64_RESTORE11]].sub0, implicit-def $vcc, implicit $exec
- ; CHECK-NEXT: [[V_ADD_CO_U32_e32_2]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE11]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: [[COPY76:%[0-9]+]]:vreg_64_align2 = COPY [[COPY44]]
- ; CHECK-NEXT: [[V_LSHRREV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 15, [[COPY76]].sub1, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_SHORT [[V_ADD_CO_U32_e32_2]], [[V_LSHRREV_B32_e32_1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %ir.sink + 124, align 4, basealign 128)
- ; CHECK-NEXT: [[V_ALIGNBIT_B32_opsel_e64_1:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY76]].sub1, 0, [[COPY76]].sub0, 0, 15, 0, 0, implicit $exec
- ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_3:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 120, [[SI_SPILL_AV64_RESTORE11]].sub0, implicit-def $vcc, implicit $exec
- ; CHECK-NEXT: [[V_ADD_CO_U32_e32_3]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE11]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORD [[V_ADD_CO_U32_e32_3]], [[V_ALIGNBIT_B32_opsel_e64_1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.sink + 120, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_15:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 31, [[COPY73]].sub2, implicit $exec
- ; CHECK-NEXT: [[V_AND_B32_e32_34:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 2147483647, [[COPY73]].sub1, implicit $exec
- ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_AND_B32_e32_34]], [[V_LSHLREV_B32_e32_15]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_16:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 17, [[COPY76]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY77:%[0-9]+]]:vreg_64_align2 = COPY [[COPY45]]
- ; CHECK-NEXT: [[COPY77:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY77]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_9:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 14, [[COPY77]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_9:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_9]].sub3, [[V_LSHLREV_B32_e32_16]], implicit $exec
- ; CHECK-NEXT: undef %2544.sub0:vreg_64_align2, renamable $vcc = V_ADD_CO_U32_e64 24, [[SI_SPILL_AV64_RESTORE11]].sub0, 0, implicit $exec
- ; CHECK-NEXT: %2544.sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE11]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_17:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 18, [[COPY77]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE12:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.30, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.30, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE12:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE12]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_9:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 13, [[SI_SPILL_AV64_RESTORE12]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_9:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_9]].sub1, [[V_LSHLREV_B32_e32_17]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2544, [[V_LSHRREV_B64_e64_9]], 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 104, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_18:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 19, [[SI_SPILL_AV64_RESTORE12]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE10:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE10]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_10:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 12, [[SI_SPILL_AV64_RESTORE10]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_10:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_10]].sub3, [[V_LSHLREV_B32_e32_18]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_19:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 20, [[SI_SPILL_AV64_RESTORE10]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE9:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE9]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_10:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 11, [[SI_SPILL_AV64_RESTORE9]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_10:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_10]].sub1, [[V_LSHLREV_B32_e32_19]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2544, [[V_LSHRREV_B64_e64_10]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 88, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_20:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 21, [[SI_SPILL_AV64_RESTORE9]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE8:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE8]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_11:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 10, [[SI_SPILL_AV64_RESTORE8]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_11:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_11]].sub3, [[V_LSHLREV_B32_e32_20]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_21:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 22, [[SI_SPILL_AV64_RESTORE8]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE7:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE7]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_11:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 9, [[SI_SPILL_AV64_RESTORE7]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_11:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_11]].sub1, [[V_LSHLREV_B32_e32_21]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2544, [[V_LSHRREV_B64_e64_11]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 72, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_22:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 23, [[SI_SPILL_AV64_RESTORE7]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE6:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE6]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_12:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 8, [[SI_SPILL_AV64_RESTORE6]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_12:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_12]].sub1, [[V_LSHLREV_B32_e32_22]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE11]], [[V_LSHRREV_B64_e64_12]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 64, align 64, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_23:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[SI_SPILL_AV64_RESTORE6]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE5:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE5]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_13:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 7, [[SI_SPILL_AV64_RESTORE5]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_13:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_13]].sub1, [[V_LSHLREV_B32_e32_23]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2544, [[V_LSHRREV_B64_e64_13]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 56, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_24:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 25, [[SI_SPILL_AV64_RESTORE5]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY75:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY75]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_14:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 6, [[COPY75]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_14:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_14]].sub3, [[V_LSHLREV_B32_e32_24]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_25:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 26, [[COPY75]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE4:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE4]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_14:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 5, [[SI_SPILL_AV64_RESTORE4]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_14:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_14]].sub1, [[V_LSHLREV_B32_e32_25]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2544, [[V_LSHRREV_B64_e64_14]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 40, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_26:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 27, [[SI_SPILL_AV64_RESTORE4]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY74:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY74]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_15:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 4, [[COPY74]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_15:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_15]].sub1, [[V_LSHLREV_B32_e32_26]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE11]], [[V_LSHRREV_B64_e64_15]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 32, align 32, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_27:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 28, [[COPY74]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE3:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE3]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_16:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 3, [[SI_SPILL_AV64_RESTORE3]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_16:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_16]].sub1, [[V_LSHLREV_B32_e32_27]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2544, [[V_LSHRREV_B64_e64_16]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 24, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_28:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 29, [[SI_SPILL_AV64_RESTORE3]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE2:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE2]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_17:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 2, [[SI_SPILL_AV64_RESTORE2]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_17:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_17]].sub1, [[V_LSHLREV_B32_e32_28]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE11]], [[V_LSHRREV_B64_e64_17]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 16, align 16, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_29:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 30, [[SI_SPILL_AV64_RESTORE2]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub3:vreg_128_align2 = V_AND_B32_e32 2147483647, [[COPY73]].sub3, implicit $exec
- ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 1, [[COPY73]].sub2_sub3, implicit $exec
- ; CHECK-NEXT: [[COPY73:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[COPY73]].sub3, [[V_LSHLREV_B32_e32_29]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE11]], [[COPY73]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
- ; CHECK-NEXT: KILL [[DEF]]
- ; CHECK-NEXT: S_BRANCH %bb.10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.42.Flow54:
- ; CHECK-NEXT: successors: %bb.43(0x40000000), %bb.51(0x40000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr38_sgpr39, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr56_sgpr57 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr58_sgpr59 = S_AND_B64 renamable $sgpr56_sgpr57, killed renamable $sgpr48_sgpr49, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr58_sgpr59
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.51, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.43
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.43.bb1:
- ; CHECK-NEXT: successors: %bb.46(0x40000000), %bb.44(0x40000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr58_sgpr59 = COPY $exec, implicit-def $exec
- ; CHECK-NEXT: renamable $sgpr60_sgpr61 = S_AND_B64 renamable $sgpr58_sgpr59, killed renamable $sgpr46_sgpr47, implicit-def dead $scc
- ; CHECK-NEXT: renamable $sgpr46_sgpr47 = S_XOR_B64 renamable $sgpr60_sgpr61, killed renamable $sgpr58_sgpr59, implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr60_sgpr61
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.44, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.46
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.44.Flow49:
- ; CHECK-NEXT: successors: %bb.45(0x40000000), %bb.51(0x40000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr46_sgpr47 = S_OR_SAVEEXEC_B64 killed renamable $sgpr46_sgpr47, implicit-def $exec, implicit-def $scc, implicit $exec
- ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, killed renamable $sgpr46_sgpr47, implicit-def $scc
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.51, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.45
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.45.bb1a:
- ; CHECK-NEXT: successors: %bb.51(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE1:%[0-9]+]]:av_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.15, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.15, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE2:%[0-9]+]]:av_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.17, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.17, align 4, addrspace 5)
- ; CHECK-NEXT: [[COPY78:%[0-9]+]]:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]]
- ; CHECK-NEXT: [[COPY79:%[0-9]+]]:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]]
- ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY79]].sub29, 0, [[COPY78]].sub29, $sgpr44_sgpr45, implicit $exec
- ; CHECK-NEXT: undef [[COPY80:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY80]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
- ; CHECK-NEXT: internal [[COPY80]].sub30_sub31:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub30_sub31
- ; CHECK-NEXT: internal [[COPY80]].sub28:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub28
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY81:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY81]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
- ; CHECK-NEXT: internal [[COPY81]].sub30_sub31:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub30_sub31
- ; CHECK-NEXT: internal [[COPY81]].sub28:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub28
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY81]].sub28, 0, [[COPY80]].sub28, killed $sgpr44_sgpr45, implicit $exec
- ; CHECK-NEXT: undef [[COPY82:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY82]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
- ; CHECK-NEXT: internal [[COPY82]].sub30_sub31:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub30_sub31
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY83:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY83]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
- ; CHECK-NEXT: internal [[COPY83]].sub30_sub31:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub30_sub31
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY83]].sub31, 0, [[COPY82]].sub31, $sgpr40_sgpr41, implicit $exec
- ; CHECK-NEXT: undef [[COPY84:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY84]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
- ; CHECK-NEXT: internal [[COPY84]].sub30:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub30
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY85:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY85]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
- ; CHECK-NEXT: internal [[COPY85]].sub30:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub30
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY85]].sub30, 0, [[COPY84]].sub30, killed $sgpr40_sgpr41, implicit $exec
- ; CHECK-NEXT: undef [[COPY86:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY86]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY87:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY87]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_1:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY87]].sub25, 0, [[COPY86]].sub25, $sgpr42_sgpr43, implicit $exec
- ; CHECK-NEXT: undef [[COPY88:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY88]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16
- ; CHECK-NEXT: internal [[COPY88]].sub26_sub27:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub26_sub27
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY89:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY89]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16
- ; CHECK-NEXT: internal [[COPY89]].sub26_sub27:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub26_sub27
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY89]].sub24, 0, [[COPY88]].sub24, killed $sgpr42_sgpr43, implicit $exec
- ; CHECK-NEXT: undef [[COPY90:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY90]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
- ; CHECK-NEXT: internal [[COPY90]].sub26_sub27:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub26_sub27
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY91:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY91]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
- ; CHECK-NEXT: internal [[COPY91]].sub26_sub27:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub26_sub27
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY91]].sub27, 0, [[COPY90]].sub27, $sgpr26_sgpr27, implicit $exec
- ; CHECK-NEXT: undef [[COPY92:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY92]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
- ; CHECK-NEXT: internal [[COPY92]].sub26:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub26
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY93:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY93]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
- ; CHECK-NEXT: internal [[COPY93]].sub26:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub26
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY93]].sub26, 0, [[COPY92]].sub26, killed $sgpr26_sgpr27, implicit $exec
- ; CHECK-NEXT: undef [[COPY94:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY94]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY95:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY95]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_2:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY95]].sub21, 0, [[COPY94]].sub21, $sgpr28_sgpr29, implicit $exec
- ; CHECK-NEXT: undef [[COPY96:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY96]].sub16_sub17_sub18_sub19_sub20:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19_sub20
- ; CHECK-NEXT: internal [[COPY96]].sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub22_sub23
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY97:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY97]].sub16_sub17_sub18_sub19_sub20:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19_sub20
- ; CHECK-NEXT: internal [[COPY97]].sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub22_sub23
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_2:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY97]].sub20, 0, [[COPY96]].sub20, killed $sgpr28_sgpr29, implicit $exec
- ; CHECK-NEXT: undef [[COPY98:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY98]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19
- ; CHECK-NEXT: internal [[COPY98]].sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub22_sub23
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY99:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY99]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19
- ; CHECK-NEXT: internal [[COPY99]].sub22_sub23:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub22_sub23
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_2:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY99]].sub23, 0, [[COPY98]].sub23, $sgpr22_sgpr23, implicit $exec
- ; CHECK-NEXT: undef [[COPY100:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY100]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19
- ; CHECK-NEXT: internal [[COPY100]].sub22:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub22
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY101:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY101]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19
- ; CHECK-NEXT: internal [[COPY101]].sub22:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub22
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_2:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY101]].sub22, 0, [[COPY100]].sub22, killed $sgpr22_sgpr23, implicit $exec
- ; CHECK-NEXT: undef [[COPY102:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY102]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16_sub17_sub18_sub19
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY103:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY103]].sub16_sub17_sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16_sub17_sub18_sub19
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_3:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY103]].sub17, 0, [[COPY102]].sub17, $sgpr24_sgpr25, implicit $exec
- ; CHECK-NEXT: undef [[COPY104:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY104]].sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub18_sub19
- ; CHECK-NEXT: internal [[COPY104]].sub16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub16
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY105:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY105]].sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub18_sub19
- ; CHECK-NEXT: internal [[COPY105]].sub16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub16
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_3:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY105]].sub16, 0, [[COPY104]].sub16, killed $sgpr24_sgpr25, implicit $exec
- ; CHECK-NEXT: undef [[COPY106:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY106]].sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub18_sub19
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY107:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY107]].sub18_sub19:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub18_sub19
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_3:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY107]].sub19, 0, [[COPY106]].sub19, $sgpr18_sgpr19, implicit $exec
- ; CHECK-NEXT: undef [[COPY108:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY108]].sub18:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub18
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY109:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15 {
- ; CHECK-NEXT: internal [[COPY109]].sub18:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub18
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_3:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY109]].sub18, 0, [[COPY108]].sub18, killed $sgpr18_sgpr19, implicit $exec
- ; CHECK-NEXT: undef [[COPY110:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
- ; CHECK-NEXT: undef [[COPY111:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
- ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_4:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY111]].sub13, 0, [[COPY110]].sub13, $sgpr20_sgpr21, implicit $exec
- ; CHECK-NEXT: undef [[COPY112:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
- ; CHECK-NEXT: internal [[COPY112]].sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub14_sub15
- ; CHECK-NEXT: internal [[COPY112]].sub12:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub12
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY113:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
- ; CHECK-NEXT: internal [[COPY113]].sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub14_sub15
- ; CHECK-NEXT: internal [[COPY113]].sub12:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub12
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_4:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY113]].sub12, 0, [[COPY112]].sub12, killed $sgpr20_sgpr21, implicit $exec
- ; CHECK-NEXT: undef [[COPY114:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
- ; CHECK-NEXT: internal [[COPY114]].sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub14_sub15
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY115:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
- ; CHECK-NEXT: internal [[COPY115]].sub14_sub15:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub14_sub15
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_4:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY115]].sub15, 0, [[COPY114]].sub15, $sgpr14_sgpr15, implicit $exec
- ; CHECK-NEXT: undef [[COPY116:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
- ; CHECK-NEXT: internal [[COPY116]].sub14:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub14
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY117:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16 {
- ; CHECK-NEXT: internal [[COPY117]].sub14:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub14
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_4:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY117]].sub14, 0, [[COPY116]].sub14, killed $sgpr14_sgpr15, implicit $exec
- ; CHECK-NEXT: undef [[COPY118:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16
- ; CHECK-NEXT: undef [[COPY119:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16
- ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_5:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY119]].sub9, 0, [[COPY118]].sub9, $sgpr16_sgpr17, implicit $exec
- ; CHECK-NEXT: undef [[COPY120:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16 {
- ; CHECK-NEXT: internal [[COPY120]].sub10_sub11:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub10_sub11
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY121:%[0-9]+]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16 {
- ; CHECK-NEXT: internal [[COPY121]].sub10_sub11:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub10_sub11
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_5:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY121]].sub8, 0, [[COPY120]].sub8, killed $sgpr16_sgpr17, implicit $exec
- ; CHECK-NEXT: undef [[COPY122:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 {
- ; CHECK-NEXT: internal [[COPY122]].sub10_sub11:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub10_sub11
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY123:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 {
- ; CHECK-NEXT: internal [[COPY123]].sub10_sub11:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub10_sub11
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_5:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY123]].sub11, 0, [[COPY122]].sub11, $sgpr10_sgpr11, implicit $exec
- ; CHECK-NEXT: undef [[COPY124:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 {
- ; CHECK-NEXT: internal [[COPY124]].sub10:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub10
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY125:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7 {
- ; CHECK-NEXT: internal [[COPY125]].sub10:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub10
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_5:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY125]].sub10, 0, [[COPY124]].sub10, killed $sgpr10_sgpr11, implicit $exec
- ; CHECK-NEXT: undef [[COPY126:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
- ; CHECK-NEXT: undef [[COPY127:%[0-9]+]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
- ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_6:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY127]].sub5, 0, [[COPY126]].sub5, $sgpr12_sgpr13, implicit $exec
- ; CHECK-NEXT: undef [[COPY128:%[0-9]+]].sub0_sub1_sub2_sub3_sub4:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3_sub4 {
- ; CHECK-NEXT: internal [[COPY128]].sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub6_sub7
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY129:%[0-9]+]].sub0_sub1_sub2_sub3_sub4:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3_sub4 {
- ; CHECK-NEXT: internal [[COPY129]].sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub6_sub7
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_6:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY129]].sub4, 0, [[COPY128]].sub4, killed $sgpr12_sgpr13, implicit $exec
- ; CHECK-NEXT: undef [[COPY130:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3 {
- ; CHECK-NEXT: internal [[COPY130]].sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub6_sub7
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY131:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3 {
- ; CHECK-NEXT: internal [[COPY131]].sub6_sub7:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub6_sub7
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_6:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY131]].sub7, 0, [[COPY130]].sub7, $sgpr6_sgpr7, implicit $exec
- ; CHECK-NEXT: undef [[COPY132:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3 {
- ; CHECK-NEXT: internal [[COPY132]].sub6:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub6
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY133:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3 {
- ; CHECK-NEXT: internal [[COPY133]].sub6:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub6
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_6:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY133]].sub6, 0, [[COPY132]].sub6, killed $sgpr6_sgpr7, implicit $exec
- ; CHECK-NEXT: undef [[COPY134:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE1]].sub0_sub1_sub2_sub3
- ; CHECK-NEXT: undef [[COPY135:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2_sub3
- ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_7:%[0-9]+]].sub3:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY134]].sub3, 0, [[COPY135]].sub3, $sgpr8_sgpr9, implicit $exec
- ; CHECK-NEXT: undef [[COPY136:%[0-9]+]].sub0_sub1_sub2:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1_sub2
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_7:%[0-9]+]].sub2:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY134]].sub2, 0, [[COPY136]].sub2, killed $sgpr8_sgpr9, implicit $exec
- ; CHECK-NEXT: undef [[COPY137:%[0-9]+]].sub0_sub1:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0_sub1
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_7:%[0-9]+]].sub1:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY134]].sub1, 0, [[COPY137]].sub1, $sgpr4_sgpr5, implicit $exec
- ; CHECK-NEXT: undef [[COPY138:%[0-9]+]].sub0:vreg_1024_align2 = COPY [[SI_SPILL_AV1024_RESTORE2]].sub0
- ; CHECK-NEXT: [[V_CNDMASK_B32_e64_7:%[0-9]+]].sub0:vreg_128_align2 = V_CNDMASK_B32_e64 0, [[COPY134]].sub0, 0, [[COPY138]].sub0, killed $sgpr4_sgpr5, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE13:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE13]], [[V_CNDMASK_B32_e64_7]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE13]], [[V_CNDMASK_B32_e64_6]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 16)
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE13]], [[V_CNDMASK_B32_e64_5]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 32, align 32)
- ; CHECK-NEXT: undef %2024.sub0:vreg_64_align2, renamable $vcc = V_ADD_CO_U32_e64 48, [[SI_SPILL_AV64_RESTORE13]].sub0, 0, implicit $exec
- ; CHECK-NEXT: %2024.sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE13]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2024, [[V_CNDMASK_B32_e64_4]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 48)
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE13]], [[V_CNDMASK_B32_e64_3]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 64, align 64)
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2024, [[V_CNDMASK_B32_e64_2]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 80)
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2024, [[V_CNDMASK_B32_e64_1]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 96, align 32)
- ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_4:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 112, [[SI_SPILL_AV64_RESTORE13]].sub0, implicit-def $vcc, implicit $exec
- ; CHECK-NEXT: [[V_ADD_CO_U32_e32_4]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE13]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[V_ADD_CO_U32_e32_4]], [[V_CNDMASK_B32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 112)
- ; CHECK-NEXT: S_BRANCH %bb.51
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.46.bb1b:
- ; CHECK-NEXT: successors: %bb.44(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: undef [[COPY139:%[0-9]+]].sub31:vreg_1024_align2 = COPY [[COPY70]].sub31
- ; CHECK-NEXT: [[V_LSHRREV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 15, [[COPY139]].sub31, implicit $exec
- ; CHECK-NEXT: undef [[COPY140:%[0-9]+]].sub30:vreg_1024_align2 = COPY [[COPY46]].sub30
- ; CHECK-NEXT: [[V_ALIGNBIT_B32_opsel_e64_2:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY139]].sub31, 0, [[COPY140]].sub30, 0, 15, 0, 0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE3:%[0-9]+]]:vreg_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.32, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.32, align 4, addrspace 5)
- ; CHECK-NEXT: [[V_AND_B32_e32_35:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV1024_RESTORE3]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_30:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 17, [[COPY140]].sub30, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE14:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_5:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 124, [[SI_SPILL_AV64_RESTORE14]].sub0, implicit-def $vcc, implicit $exec
- ; CHECK-NEXT: [[V_ADD_CO_U32_e32_5]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE14]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_SHORT [[V_ADD_CO_U32_e32_5]], [[V_LSHRREV_B32_e32_2]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %ir.sink + 124, align 4, basealign 128)
- ; CHECK-NEXT: undef [[V_ADD_CO_U32_e32_6:%[0-9]+]].sub0:vreg_64_align2 = V_ADD_CO_U32_e32 120, [[SI_SPILL_AV64_RESTORE14]].sub0, implicit-def $vcc, implicit $exec
- ; CHECK-NEXT: [[V_ADD_CO_U32_e32_6]].sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE14]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORD [[V_ADD_CO_U32_e32_6]], [[V_ALIGNBIT_B32_opsel_e64_2]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.sink + 120, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_31:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 31, [[COPY35]].sub2, implicit $exec
- ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_AND_B32_e32_35]], [[V_LSHLREV_B32_e32_31]], implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE15:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.29, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.29, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE15:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE15]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_18:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 14, [[SI_SPILL_AV64_RESTORE15]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_18:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_18]].sub3, [[V_LSHLREV_B32_e32_30]], implicit $exec
- ; CHECK-NEXT: undef %2554.sub0:vreg_64_align2, renamable $vcc = V_ADD_CO_U32_e64 24, [[SI_SPILL_AV64_RESTORE14]].sub0, 0, implicit $exec
- ; CHECK-NEXT: %2554.sub1:vreg_64_align2, dead renamable $vcc = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE14]].sub1, killed $vcc, 0, implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_32:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 18, [[SI_SPILL_AV64_RESTORE15]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE16:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.28, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.28, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE16:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE16]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_18:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 13, [[SI_SPILL_AV64_RESTORE16]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_18:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_18]].sub1, [[V_LSHLREV_B32_e32_32]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2554, [[V_LSHRREV_B64_e64_18]], 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 104, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_33:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 19, [[SI_SPILL_AV64_RESTORE16]].sub0, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE17:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.27, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.27, align 4, addrspace 5)
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE17:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[SI_SPILL_AV64_RESTORE17]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_19:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 12, [[SI_SPILL_AV64_RESTORE17]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_19:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_19]].sub3, [[V_LSHLREV_B32_e32_33]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_34:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 20, [[SI_SPILL_AV64_RESTORE17]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY141:%[0-9]+]]:vreg_64_align2 = COPY [[COPY37]]
- ; CHECK-NEXT: [[COPY141:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY141]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_19:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 11, [[COPY141]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_19:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_19]].sub1, [[V_LSHLREV_B32_e32_34]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2554, [[V_LSHRREV_B64_e64_19]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 88, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_35:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 21, [[COPY141]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY142:%[0-9]+]]:vreg_64_align2 = COPY [[COPY39]]
- ; CHECK-NEXT: [[COPY142:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY142]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_20:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 10, [[COPY142]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_20:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_20]].sub3, [[V_LSHLREV_B32_e32_35]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_36:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 22, [[COPY142]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY143:%[0-9]+]]:vreg_64_align2 = COPY [[COPY41]]
- ; CHECK-NEXT: [[COPY143:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY143]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_20:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 9, [[COPY143]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_20:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_20]].sub1, [[V_LSHLREV_B32_e32_36]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2554, [[V_LSHRREV_B64_e64_20]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 72, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_37:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 23, [[COPY143]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY42:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY42]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_21:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 8, [[COPY42]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_21:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_21]].sub1, [[V_LSHLREV_B32_e32_37]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE14]], [[V_LSHRREV_B64_e64_21]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 64, align 64, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_38:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[COPY42]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY36:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY36]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_22:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 7, [[COPY36]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_22:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_22]].sub1, [[V_LSHLREV_B32_e32_38]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2554, [[V_LSHRREV_B64_e64_22]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 56, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_39:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 25, [[COPY36]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY144:%[0-9]+]]:vreg_64_align2 = COPY [[COPY34]]
- ; CHECK-NEXT: [[COPY144:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY144]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_23:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 6, [[COPY144]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_23:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_23]].sub3, [[V_LSHLREV_B32_e32_39]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_40:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 26, [[COPY144]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY145:%[0-9]+]]:vreg_64_align2 = COPY [[COPY32]]
- ; CHECK-NEXT: [[COPY145:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY145]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_23:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 5, [[COPY145]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_23:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_23]].sub1, [[V_LSHLREV_B32_e32_40]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2554, [[V_LSHRREV_B64_e64_23]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 40, align 8, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_41:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 27, [[COPY145]].sub0, implicit $exec
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN4:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[BUFFER_LOAD_DWORD_OFFEN4]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_24:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 4, [[BUFFER_LOAD_DWORD_OFFEN4]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_24:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_24]].sub1, [[V_LSHLREV_B32_e32_41]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE14]], [[V_LSHRREV_B64_e64_24]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 32, align 32, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_42:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 28, [[BUFFER_LOAD_DWORD_OFFEN4]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY146:%[0-9]+]]:vreg_64_align2 = COPY [[COPY31]]
- ; CHECK-NEXT: [[COPY146:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY146]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_25:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 3, [[COPY146]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_25:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_25]].sub1, [[V_LSHLREV_B32_e32_42]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2554, [[V_LSHRREV_B64_e64_25]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 24, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_43:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 29, [[COPY146]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY33:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY33]].sub1, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_26:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 2, [[COPY33]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_26:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_26]].sub1, [[V_LSHLREV_B32_e32_43]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE14]], [[V_LSHRREV_B64_e64_26]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 16, align 16, basealign 128)
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_44:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 30, [[COPY33]].sub0, implicit $exec
- ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub3:vreg_128_align2 = V_AND_B32_e32 2147483647, [[COPY35]].sub3, implicit $exec
- ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 1, [[COPY35]].sub2_sub3, implicit $exec
- ; CHECK-NEXT: [[COPY35:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[COPY35]].sub3, [[V_LSHLREV_B32_e32_44]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE14]], [[COPY35]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
- ; CHECK-NEXT: KILL [[DEF1]]
- ; CHECK-NEXT: [[DEF2:%[0-9]+]]:av_64_align2 = IMPLICIT_DEF
- ; CHECK-NEXT: KILL [[DEF2]]
- ; CHECK-NEXT: [[DEF3:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
- ; CHECK-NEXT: KILL [[DEF3]]
- ; CHECK-NEXT: S_BRANCH %bb.44
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.47.Flow51:
- ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr50_sgpr51 = S_OR_SAVEEXEC_B64 killed renamable $sgpr50_sgpr51, implicit-def $exec, implicit-def $scc, implicit $exec
- ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, renamable $sgpr50_sgpr51, implicit-def $scc
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.4
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.48.bb2:
- ; CHECK-NEXT: successors: %bb.3(0x80000000)
- ; CHECK-NEXT: liveins: $vcc, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr72_sgpr73, $sgpr74_sgpr75, $sgpr76_sgpr77, $sgpr78_sgpr79, $sgpr88_sgpr89, $sgpr90_sgpr91, $sgpr92_sgpr93, $sgpr94_sgpr95
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: undef [[COPY147:%[0-9]+]].sub2_sub3:av_128_align2 = COPY [[COPY35]].sub2_sub3 {
- ; CHECK-NEXT: internal [[COPY147]].sub0:av_128_align2 = COPY [[COPY35]].sub0
- ; CHECK-NEXT: }
- ; CHECK-NEXT: [[COPY148:%[0-9]+]]:av_64_align2 = COPY [[COPY33]]
- ; CHECK-NEXT: [[COPY149:%[0-9]+]]:av_64_align2 = COPY [[COPY31]]
- ; CHECK-NEXT: [[COPY150:%[0-9]+]]:av_64_align2 = COPY [[BUFFER_LOAD_DWORD_OFFEN4]]
- ; CHECK-NEXT: [[COPY151:%[0-9]+]]:av_64_align2 = COPY [[COPY32]]
- ; CHECK-NEXT: [[COPY152:%[0-9]+]]:av_64_align2 = COPY [[COPY34]]
- ; CHECK-NEXT: [[COPY153:%[0-9]+]]:av_64_align2 = COPY [[COPY36]]
- ; CHECK-NEXT: [[COPY154:%[0-9]+]]:av_64_align2 = COPY [[COPY42]]
- ; CHECK-NEXT: [[COPY155:%[0-9]+]]:av_64_align2 = COPY [[COPY41]]
- ; CHECK-NEXT: [[COPY156:%[0-9]+]]:av_64_align2 = COPY [[COPY39]]
- ; CHECK-NEXT: [[COPY157:%[0-9]+]]:av_64_align2 = COPY [[COPY37]]
- ; CHECK-NEXT: [[SI_SPILL_AV1024_RESTORE4:%[0-9]+]]:vreg_1024_align2 = SI_SPILL_AV1024_RESTORE %stack.33, $sgpr32, 0, implicit $exec :: (load (s1024) from %stack.33, align 4, addrspace 5)
- ; CHECK-NEXT: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub3, [[COPY54]].sub3, implicit $exec
- ; CHECK-NEXT: [[COPY158:%[0-9]+]]:av_32 = COPY [[V_XOR_B32_e32_]]
- ; CHECK-NEXT: undef [[COPY159:%[0-9]+]].sub5:vreg_1024_align2 = COPY [[COPY55]].sub5
- ; CHECK-NEXT: [[V_XOR_B32_e32_1:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub5, [[COPY159]].sub5, implicit $exec
- ; CHECK-NEXT: [[COPY160:%[0-9]+]]:av_32 = COPY [[V_XOR_B32_e32_1]]
- ; CHECK-NEXT: [[V_XOR_B32_e32_2:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub7, [[COPY56]].sub7, implicit $exec
- ; CHECK-NEXT: [[COPY161:%[0-9]+]]:av_32 = COPY [[V_XOR_B32_e32_2]]
- ; CHECK-NEXT: [[V_XOR_B32_e32_3:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub9, [[COPY57]].sub9, implicit $exec
- ; CHECK-NEXT: [[COPY162:%[0-9]+]]:av_32 = COPY [[V_XOR_B32_e32_3]]
- ; CHECK-NEXT: [[V_XOR_B32_e32_4:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub11, [[COPY58]].sub11, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_5:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub13, [[COPY59]].sub13, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_6:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub15, [[COPY60]].sub15, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_7:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub17, [[COPY61]].sub17, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_8:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub19, [[COPY62]].sub19, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_9:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub21, [[COPY63]].sub21, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_10:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub23, [[COPY64]].sub23, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_11:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub25, [[COPY65]].sub25, implicit $exec
- ; CHECK-NEXT: undef [[COPY163:%[0-9]+]].sub27:vreg_1024_align2 = COPY [[COPY66]].sub27
- ; CHECK-NEXT: [[V_XOR_B32_e32_12:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub27, [[COPY163]].sub27, implicit $exec
- ; CHECK-NEXT: undef [[COPY164:%[0-9]+]].sub29:vreg_1024_align2 = COPY [[COPY67]].sub29
- ; CHECK-NEXT: [[V_XOR_B32_e32_13:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub29, [[COPY164]].sub29, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_14:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub1, [[COPY53]].sub1, implicit $exec
- ; CHECK-NEXT: undef [[COPY165:%[0-9]+]].sub31:vreg_1024_align2 = COPY [[COPY68]].sub31
- ; CHECK-NEXT: [[V_XOR_B32_e32_15:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub31, [[COPY165]].sub31, implicit $exec
- ; CHECK-NEXT: undef [[COPY166:%[0-9]+]].sub30:vreg_1024_align2 = COPY [[COPY47]].sub30
- ; CHECK-NEXT: [[V_XOR_B32_e32_16:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub30, [[COPY166]].sub30, implicit $exec
- ; CHECK-NEXT: [[COPY41:%[0-9]+]]:av_64_align2 = COPY [[COPY155]]
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_17:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub2, [[BUFFER_LOAD_DWORD_OFFEN29]].sub2, implicit $exec
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_18:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub4, [[BUFFER_LOAD_DWORD_OFFEN28]].sub4, implicit $exec
- ; CHECK-NEXT: undef [[COPY167:%[0-9]+]].sub0:av_64_align2 = COPY [[V_XOR_B32_e32_18]].sub0
- ; CHECK-NEXT: [[COPY39:%[0-9]+]]:av_64_align2 = COPY [[COPY156]]
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_19:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub6, [[BUFFER_LOAD_DWORD_OFFEN27]].sub6, implicit $exec
- ; CHECK-NEXT: undef [[COPY168:%[0-9]+]].sub0:av_64_align2 = COPY [[V_XOR_B32_e32_19]].sub0
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_20:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub8, [[BUFFER_LOAD_DWORD_OFFEN26]].sub8, implicit $exec
- ; CHECK-NEXT: [[COPY37:%[0-9]+]]:av_64_align2 = COPY [[COPY157]]
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_21:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub10, [[BUFFER_LOAD_DWORD_OFFEN25]].sub10, implicit $exec
- ; CHECK-NEXT: [[COPY31:%[0-9]+]]:av_64_align2 = COPY [[COPY149]]
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_22:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub12, [[BUFFER_LOAD_DWORD_OFFEN24]].sub12, implicit $exec
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN4:%[0-9]+]]:vreg_64_align2 = COPY [[COPY150]]
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_23:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub14, [[BUFFER_LOAD_DWORD_OFFEN23]].sub14, implicit $exec
- ; CHECK-NEXT: [[COPY32:%[0-9]+]]:av_64_align2 = COPY [[COPY151]]
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_24:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub16, [[BUFFER_LOAD_DWORD_OFFEN22]].sub16, implicit $exec
- ; CHECK-NEXT: [[COPY34:%[0-9]+]]:av_64_align2 = COPY [[COPY152]]
- ; CHECK-NEXT: undef [[COPY169:%[0-9]+]].sub18:vreg_1024_align2 = COPY [[COPY52]].sub18
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_25:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub18, [[COPY169]].sub18, implicit $exec
- ; CHECK-NEXT: [[SI_SPILL_AV64_RESTORE18:%[0-9]+]]:vreg_64_align2 = SI_SPILL_AV64_RESTORE %stack.34, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.34, align 4, addrspace 5)
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_26:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub20, [[BUFFER_LOAD_DWORD_OFFEN20]].sub20, implicit $exec
- ; CHECK-NEXT: undef [[COPY170:%[0-9]+]].sub22:vreg_1024_align2 = COPY [[COPY51]].sub22
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_27:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub22, [[COPY170]].sub22, implicit $exec
- ; CHECK-NEXT: undef [[COPY35:%[0-9]+]].sub2_sub3:vreg_128_align2 = COPY [[COPY147]].sub2_sub3 {
- ; CHECK-NEXT: internal [[COPY35]].sub0:vreg_128_align2 = COPY [[COPY147]].sub0
- ; CHECK-NEXT: }
- ; CHECK-NEXT: undef [[COPY171:%[0-9]+]].sub24:vreg_1024_align2 = COPY [[COPY50]].sub24
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_28:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub24, [[COPY171]].sub24, implicit $exec
- ; CHECK-NEXT: [[COPY33:%[0-9]+]]:vreg_64_align2 = COPY [[COPY148]]
- ; CHECK-NEXT: undef [[COPY172:%[0-9]+]].sub26:vreg_1024_align2 = COPY [[COPY49]].sub26
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_29:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub26, [[COPY172]].sub26, implicit $exec
- ; CHECK-NEXT: [[COPY36:%[0-9]+]]:vreg_64_align2 = COPY [[COPY153]]
- ; CHECK-NEXT: undef [[COPY173:%[0-9]+]].sub28:vreg_1024_align2 = COPY [[COPY48]].sub28
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_30:%[0-9]+]].sub0:vreg_64_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub28, [[COPY173]].sub28, implicit $exec
- ; CHECK-NEXT: [[COPY42:%[0-9]+]]:vreg_64_align2 = COPY [[COPY154]]
- ; CHECK-NEXT: undef [[V_XOR_B32_e32_31:%[0-9]+]].sub0:vreg_128_align2 = V_XOR_B32_e32 [[SI_SPILL_AV1024_RESTORE4]].sub0, [[BUFFER_LOAD_DWORD_OFFEN30]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_30:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_13]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_45:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 17, [[V_XOR_B32_e32_16]], implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_27:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 14, [[V_XOR_B32_e32_30]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_27:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_27]].sub3, [[V_LSHLREV_B32_e32_45]], implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_29:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_12]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_46:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 18, [[V_XOR_B32_e32_30]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_27:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 13, [[V_XOR_B32_e32_29]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_27:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_27]].sub1, [[V_LSHLREV_B32_e32_46]], implicit $exec
- ; CHECK-NEXT: undef %2564.sub0:vreg_64_align2, renamable $sgpr38_sgpr39 = V_ADD_CO_U32_e64 24, [[SI_SPILL_AV64_RESTORE18]].sub0, 0, implicit $exec
- ; CHECK-NEXT: %2564.sub1:vreg_64_align2, dead renamable $sgpr38_sgpr39 = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE18]].sub1, killed $sgpr38_sgpr39, 0, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2564, [[V_LSHRREV_B64_e64_27]], 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 104, align 8, basealign 128)
- ; CHECK-NEXT: [[V_XOR_B32_e32_28:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_11]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_47:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 19, [[V_XOR_B32_e32_29]].sub0, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_28:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 12, [[V_XOR_B32_e32_28]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_28:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_28]].sub3, [[V_LSHLREV_B32_e32_47]], implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_27:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_10]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_48:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 20, [[V_XOR_B32_e32_28]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_28:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 11, [[V_XOR_B32_e32_27]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_28:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_28]].sub1, [[V_LSHLREV_B32_e32_48]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2564, [[V_LSHRREV_B64_e64_28]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 88, align 8, basealign 128)
- ; CHECK-NEXT: [[V_XOR_B32_e32_26:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_9]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_49:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 21, [[V_XOR_B32_e32_27]].sub0, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_29:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 10, [[V_XOR_B32_e32_26]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_29:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_29]].sub3, [[V_LSHLREV_B32_e32_49]], implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_25:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_8]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_50:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 22, [[V_XOR_B32_e32_26]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_29:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 9, [[V_XOR_B32_e32_25]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_29:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_29]].sub1, [[V_LSHLREV_B32_e32_50]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2564, [[V_LSHRREV_B64_e64_29]], 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 72, align 8, basealign 128)
- ; CHECK-NEXT: renamable $sgpr38 = S_MOV_B32 124
- ; CHECK-NEXT: undef %731.sub0:vreg_64_align2, renamable $sgpr38_sgpr39 = V_ADD_CO_U32_e64 killed $sgpr38, [[SI_SPILL_AV64_RESTORE18]].sub0, 0, implicit $exec
- ; CHECK-NEXT: %731.sub1:vreg_64_align2, dead renamable $sgpr38_sgpr39 = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE18]].sub1, killed $sgpr38_sgpr39, 0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 15, [[V_XOR_B32_e32_15]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_SHORT %731, [[V_LSHRREV_B32_e32_3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %ir.sink + 124, align 4, basealign 128)
- ; CHECK-NEXT: [[V_ALIGNBIT_B32_opsel_e64_3:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[V_XOR_B32_e32_15]], 0, [[V_XOR_B32_e32_16]], 0, 15, 0, 0, implicit $exec
- ; CHECK-NEXT: renamable $sgpr38 = S_MOV_B32 120
- ; CHECK-NEXT: undef %735.sub0:vreg_64_align2, renamable $sgpr38_sgpr39 = V_ADD_CO_U32_e64 killed $sgpr38, [[SI_SPILL_AV64_RESTORE18]].sub0, 0, implicit $exec
- ; CHECK-NEXT: %735.sub1:vreg_64_align2, dead renamable $sgpr38_sgpr39 = V_ADDC_U32_e64 0, [[SI_SPILL_AV64_RESTORE18]].sub1, killed $sgpr38_sgpr39, 0, implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORD %735, [[V_ALIGNBIT_B32_opsel_e64_3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.sink + 120, align 8, basealign 128)
- ; CHECK-NEXT: [[V_AND_B32_e32_36:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_14]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_51:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 31, [[V_XOR_B32_e32_17]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_31:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_AND_B32_e32_36]], [[V_LSHLREV_B32_e32_51]], implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_24:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_7]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_52:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 23, [[V_XOR_B32_e32_25]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_30:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 8, [[V_XOR_B32_e32_24]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_30:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_30]].sub1, [[V_LSHLREV_B32_e32_52]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE18]], [[V_LSHRREV_B64_e64_30]], 64, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 64, align 64, basealign 128)
- ; CHECK-NEXT: [[V_XOR_B32_e32_23:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_6]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_53:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_XOR_B32_e32_24]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_31:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 7, [[V_XOR_B32_e32_23]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_31:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_31]].sub1, [[V_LSHLREV_B32_e32_53]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2564, [[V_LSHRREV_B64_e64_31]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 56, basealign 128)
- ; CHECK-NEXT: [[V_XOR_B32_e32_22:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_5]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_54:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 25, [[V_XOR_B32_e32_23]].sub0, implicit $exec
- ; CHECK-NEXT: undef [[V_LSHRREV_B64_e64_32:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 6, [[V_XOR_B32_e32_22]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_32:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_32]].sub3, [[V_LSHLREV_B32_e32_54]], implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_21:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[V_XOR_B32_e32_4]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_32:%[0-9]+]].sub0_sub1:vreg_128_align2 = V_LSHRREV_B64_e64 5, [[V_XOR_B32_e32_21]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_55:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 26, [[V_XOR_B32_e32_22]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_32:%[0-9]+]].sub1:vreg_128_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_32]].sub1, [[V_LSHLREV_B32_e32_55]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 %2564, [[V_LSHRREV_B64_e64_32]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink + 40, align 8, basealign 128)
- ; CHECK-NEXT: [[COPY174:%[0-9]+]]:vgpr_32 = COPY [[COPY162]]
- ; CHECK-NEXT: undef [[COPY175:%[0-9]+]].sub0:vreg_64_align2 = COPY [[V_XOR_B32_e32_20]].sub0
- ; CHECK-NEXT: [[COPY175:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY174]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_33:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 4, [[COPY175]], implicit $exec
- ; CHECK-NEXT: undef [[COPY176:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY175]].sub0
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_56:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 27, [[V_XOR_B32_e32_21]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_33:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_33]].sub1, [[V_LSHLREV_B32_e32_56]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE18]], [[V_LSHRREV_B64_e64_33]], 32, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 32, align 32, basealign 128)
- ; CHECK-NEXT: [[COPY177:%[0-9]+]]:vgpr_32 = COPY [[COPY161]]
- ; CHECK-NEXT: undef [[COPY178:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY168]].sub0
- ; CHECK-NEXT: [[COPY178:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY177]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_34:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 3, [[COPY178]], implicit $exec
- ; CHECK-NEXT: undef [[COPY179:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY178]].sub0
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_57:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 28, [[COPY176]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_34:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_34]].sub1, [[V_LSHLREV_B32_e32_57]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 %2564, [[V_LSHRREV_B64_e64_34]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 24, basealign 128)
- ; CHECK-NEXT: [[COPY180:%[0-9]+]]:vgpr_32 = COPY [[COPY160]]
- ; CHECK-NEXT: undef [[COPY181:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY167]].sub0
- ; CHECK-NEXT: [[COPY181:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY180]], implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_35:%[0-9]+]]:vreg_64_align2 = V_LSHRREV_B64_e64 2, [[COPY181]], implicit $exec
- ; CHECK-NEXT: undef [[COPY182:%[0-9]+]].sub0:vreg_64_align2 = COPY [[COPY181]].sub0
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_58:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 29, [[COPY179]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_LSHRREV_B64_e64_35:%[0-9]+]].sub1:vreg_64_align2 = V_OR_B32_e32 [[V_LSHRREV_B64_e64_35]].sub1, [[V_LSHLREV_B32_e32_58]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX2 [[SI_SPILL_AV64_RESTORE18]], [[V_LSHRREV_B64_e64_35]], 16, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %ir.sink + 16, align 16, basealign 128)
- ; CHECK-NEXT: undef [[COPY183:%[0-9]+]].sub0:vreg_64_align2 = COPY [[V_XOR_B32_e32_17]].sub0
- ; CHECK-NEXT: [[COPY184:%[0-9]+]]:vgpr_32 = COPY [[COPY158]]
- ; CHECK-NEXT: [[COPY183:%[0-9]+]].sub1:vreg_64_align2 = V_AND_B32_e32 2147483647, [[COPY184]], implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_31:%[0-9]+]].sub2_sub3:vreg_128_align2 = V_LSHRREV_B64_e64 1, [[COPY183]], implicit $exec
- ; CHECK-NEXT: [[V_LSHLREV_B32_e32_59:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 30, [[COPY182]].sub0, implicit $exec
- ; CHECK-NEXT: [[V_XOR_B32_e32_31:%[0-9]+]].sub3:vreg_128_align2 = V_OR_B32_e32 [[V_XOR_B32_e32_31]].sub3, [[V_LSHLREV_B32_e32_59]], implicit $exec
- ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[SI_SPILL_AV64_RESTORE18]], [[V_XOR_B32_e32_31]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %ir.sink, align 128)
- ; CHECK-NEXT: renamable $sgpr54_sgpr55 = S_XOR_B64 $exec, -1, implicit-def dead $scc
- ; CHECK-NEXT: S_BRANCH %bb.3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.49.Flow48:
- ; CHECK-NEXT: successors: %bb.42(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18_sgpr19, $sgpr20_sgpr21, $sgpr22_sgpr23, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr56_sgpr57, implicit-def $scc
- ; CHECK-NEXT: renamable $sgpr48_sgpr49 = S_ANDN2_B64 killed renamable $sgpr48_sgpr49, $exec, implicit-def dead $scc
- ; CHECK-NEXT: S_BRANCH %bb.42
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.51.UnifiedReturnBlock:
- ; CHECK-NEXT: liveins: $vgpr63, $sgpr56_sgpr57
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr56_sgpr57, implicit-def $scc
- ; CHECK-NEXT: $sgpr30 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 14, implicit-def $sgpr30_sgpr31
- ; CHECK-NEXT: $sgpr31 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 15
- ; CHECK-NEXT: $sgpr55 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 13
- ; CHECK-NEXT: $sgpr54 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 12
- ; CHECK-NEXT: $sgpr53 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 11
- ; CHECK-NEXT: $sgpr52 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 10
- ; CHECK-NEXT: $sgpr51 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 9
- ; CHECK-NEXT: $sgpr50 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 8
- ; CHECK-NEXT: $sgpr49 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 7
- ; CHECK-NEXT: $sgpr48 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 6
- ; CHECK-NEXT: $sgpr39 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 5
- ; CHECK-NEXT: $sgpr38 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 4
- ; CHECK-NEXT: $sgpr37 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 3
- ; CHECK-NEXT: $sgpr36 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 2
- ; CHECK-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 1
- ; CHECK-NEXT: $sgpr34 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 0
- ; CHECK-NEXT: SI_RETURN
<16 x double> %da, <16 x double> %db,
<16 x i63> %v, <16 x i63> %w, <16 x i63> %a,
ptr %sink, i32 %disc, i1 %c) #0 {
@@ -1522,3 +37,5 @@ bb2:
store <16 x i63> %x, ptr %sink
ret void
}
+
+attributes #0 = { nounwind }
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