[llvm] [SystemZ] Fold i16/i32/i64 logical RMW operations into memory operands in TableGen (PR #192802)

[Ulrich Weigand via llvm-commits]

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@@ -444,6 +444,28 @@ defm imm64hh16c : Immediate<i64, [{
          SystemZ::isImmHH(uint64_t(~Imm.getZExtValue()));
 }], HH16, "U16Imm">;
 
+// Immediates for the 8-bit LSB chunk of an i32, with the other bits being one
+// or zero-extended from a 16-bit.
+defm imm32ll8c : Immediate<i32, [{
+  if (!Imm.isIntN(32)) return false;
+  uint64_t Val = Imm.getZExtValue();
+  // Case 1: Upper 24 bits are all ones.
+  if ((Val & 0xffffff00ULL) == 0xffffff00ULL)
+    return true;
+  // Case 2: Zero-extended i16 where the upper 16 bits are zero and the 
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uweigand wrote:

This looks like potential wrong-code bug as well: a 32-bit AND with 0x0000ff00 *cannot* be done with a single NI.   Now, for a *16-bit* AND it's another story - but your code as-is would accept this pattern also for an actual 32-bit AND.   I think to distiniguish the cases you actually need two separate predicates here, e.g. `imm16ll8c` and `imm32ll8c`.

https://github.com/llvm/llvm-project/pull/192802