[llvm] [AMDGPU] Do not scale private alloca size when using flat-scratch (PR #201142)
Juan Manuel Martinez Caamaño via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 3 04:17:13 PDT 2026
https://github.com/jmmartinez updated https://github.com/llvm/llvm-project/pull/201142
>From b7a0fb0fe9a8d382012cc6c4f0ac5dfc6cd6e484 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Tue, 2 Jun 2026 15:39:19 +0200
Subject: [PATCH 1/5] [AMDGPU] Do not scale private alloca size when using
flat-scratch
---
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 20 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 31 ++-
.../GlobalISel/dynamic-alloca-uniform.ll | 21 +-
.../AMDGPU/amdgpu-cs-chain-fp-nosave.ll | 56 ++---
.../test/CodeGen/AMDGPU/dynamic_stackalloc.ll | 233 ++++++++----------
llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll | 12 +-
llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll | 16 +-
7 files changed, 178 insertions(+), 211 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index a24df782cf28a4..540447890dfd25 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1174,6 +1174,11 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
Register AllocSize = MI.getOperand(1).getReg();
Align Alignment = assumeAligned(MI.getOperand(2).getImm());
+ // When using flat-scratch, the stack offset is already scaled by the
+ // wave-size by the hardware instructions.
+ const bool HasFlatScratch = ST.hasFlatScratchEnabled();
+ const unsigned WavefrontSizeLog2 = ST.getWavefrontSizeLog2();
+
const RegisterBank *SizeBank = getRegBank(AllocSize, MRI, *TRI);
if (SizeBank != &AMDGPU::SGPRRegBank) {
@@ -1191,16 +1196,23 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
Register SPReg = Info->getStackPtrOffsetReg();
ApplyRegBankMapping ApplyBank(B, *this, MRI, &AMDGPU::SGPRRegBank);
- auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2());
- auto ScaledSize = B.buildShl(IntPtrTy, AllocSize, WaveSize);
+ Register ScaledSize = AllocSize;
+ if (!HasFlatScratch) {
+ auto WaveSize = B.buildConstant(LLT::scalar(32), WavefrontSizeLog2);
+ ScaledSize = B.buildShl(IntPtrTy, AllocSize, WaveSize).getReg(0);
+ }
auto OldSP = B.buildCopy(PtrTy, SPReg);
if (Alignment > TFI.getStackAlign()) {
- auto StackAlignMask = (Alignment.value() << ST.getWavefrontSizeLog2()) - 1;
+ const uint64_t ScaledAlignment =
+ Alignment.value() << (HasFlatScratch ? 0u : WavefrontSizeLog2);
+ auto StackAlignMask = ScaledAlignment - 1;
auto Tmp1 = B.buildPtrAdd(PtrTy, OldSP,
B.buildConstant(LLT::scalar(32), StackAlignMask));
B.buildMaskLowPtrBits(Dst, Tmp1,
- Log2(Alignment) + ST.getWavefrontSizeLog2());
+ (HasFlatScratch
+ ? Log2(Alignment)
+ : Log2(Alignment) + WavefrontSizeLog2));
} else {
B.buildCopy(Dst, OldSP);
}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 86f2479490c296..4603e6cac6bde8 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4680,10 +4680,15 @@ SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
"Stack grows upwards for AMDGPU");
Chain = BaseAddr.getValue(1);
+ // When using flat-scratch, the stack offset is already is scaled by the
+ // wave-size by the hardware instructions.
+ const bool HasFlatScratch = Subtarget->hasFlatScratchEnabled();
+ const unsigned WavefrontSizeLog2 = Subtarget->getWavefrontSizeLog2();
+
Align StackAlign = TFL->getStackAlign();
if (Alignment > StackAlign) {
uint64_t ScaledAlignment = Alignment.value()
- << Subtarget->getWavefrontSizeLog2();
+ << (HasFlatScratch ? 0 : WavefrontSizeLog2);
uint64_t StackAlignMask = ScaledAlignment - 1;
SDValue TmpAddr = DAG.getNode(ISD::ADD, dl, VT, BaseAddr,
DAG.getConstant(StackAlignMask, dl, VT));
@@ -4694,21 +4699,29 @@ SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
assert(Size.getValueType() == MVT::i32 && "Size must be 32-bit");
SDValue NewSP;
if (isa<ConstantSDNode>(Size)) {
- // For constant sized alloca, scale alloca size by wave-size
- SDValue ScaledSize = DAG.getNode(
- ISD::SHL, dl, VT, Size,
- DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
+ // Increase the stack pointer by the size of the alloca.
+ // If not using flat-scratch, we have to scale the size by the wave-size.
+ SDValue ScaledSize = Size;
+ if (!HasFlatScratch) {
+ ScaledSize =
+ DAG.getNode(ISD::SHL, dl, VT, Size,
+ DAG.getConstant(WavefrontSizeLog2, dl, MVT::i32));
+ }
NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value
} else {
// For dynamic sized alloca, perform wave-wide reduction to get max of
- // alloca size(divergent) and then scale it by wave-size
+ // alloca size(divergent), and then scale it (when not using flat-scratch)
+ // by wave-size.
SDValue WaveReduction =
DAG.getTargetConstant(Intrinsic::amdgcn_wave_reduce_umax, dl, MVT::i32);
Size = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, WaveReduction,
Size, DAG.getTargetConstant(0, dl, MVT::i32));
- SDValue ScaledSize = DAG.getNode(
- ISD::SHL, dl, VT, Size,
- DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
+ SDValue ScaledSize = Size;
+ if (!HasFlatScratch) {
+ ScaledSize =
+ DAG.getNode(ISD::SHL, dl, VT, Size,
+ DAG.getConstant(WavefrontSizeLog2, dl, MVT::i32));
+ }
NewSP =
DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value in vgpr.
SDValue ReadFirstLaneID =
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
index 2e8f8f67bc5eaf..aaff0fc4848ca9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
@@ -54,8 +54,6 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align4(i32 %n) #0 {
; GFX11-NEXT: s_lshl2_add_u32 s1, s1, 15
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s1, s1, -16
-; GFX11-NEXT: s_lshl_b32 s1, s1, 5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_u32 s32, s0, s1
; GFX11-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, align 4, addrspace(5)
@@ -134,8 +132,6 @@ define void @func_dynamic_stackalloc_sgpr_align4() #0 {
; GFX11-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, -16
-; GFX11-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_u32 s32, s2, s0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_mov_b32 s33, s3
@@ -195,8 +191,6 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align16(i32 %n) #0 {
; GFX11-NEXT: s_lshl2_add_u32 s1, s1, 15
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s1, s1, -16
-; GFX11-NEXT: s_lshl_b32 s1, s1, 5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_u32 s32, s0, s1
; GFX11-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, align 16, addrspace(5)
@@ -275,8 +269,6 @@ define void @func_dynamic_stackalloc_sgpr_align16() #0 {
; GFX11-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, -16
-; GFX11-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_u32 s32, s2, s0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_mov_b32 s33, s3
@@ -331,16 +323,14 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align32(i32 %n) #0 {
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0
; GFX11-NEXT: s_mov_b32 s32, 32
; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_add_u32 s1, s32, 0x3ff
+; GFX11-NEXT: s_add_u32 s1, s32, 31
; GFX11-NEXT: s_mov_b32 s33, 0
-; GFX11-NEXT: s_and_b32 s1, s1, 0xfffffc00
+; GFX11-NEXT: s_and_not1_b32 s1, s1, 31
; GFX11-NEXT: scratch_store_b32 off, v0, s1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, -16
-; GFX11-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_u32 s32, s1, s0
; GFX11-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, align 32, addrspace(5)
@@ -427,15 +417,14 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) #0 {
; GFX11-NEXT: s_mov_b32 s33, s2
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
-; GFX11-NEXT: s_add_u32 s1, s32, 0x3ff
+; GFX11-NEXT: s_add_u32 s1, s32, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s1, s1, 0xfffffc00
+; GFX11-NEXT: s_and_not1_b32 s1, s1, 31
; GFX11-NEXT: scratch_store_b32 off, v0, s1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-NEXT: s_and_b32 s0, s0, -16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b32 s0, s0, 5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_u32 s32, s1, s0
; GFX11-NEXT: s_mov_b32 s32, s34
; GFX11-NEXT: s_mov_b32 s34, s3
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
index 0835837a98f989..851bd6d2f75b40 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
@@ -22,7 +22,7 @@ define amdgpu_cs_chain void @test_alloca() #0 {
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s0, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s32, s0, 0x200
+; GFX12-NEXT: s_add_co_i32 s32, s0, 16
; GFX12-NEXT: scratch_store_b32 off, v0, s0
; GFX12-NEXT: s_endpgm
;
@@ -33,7 +33,7 @@ define amdgpu_cs_chain void @test_alloca() #0 {
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: s_mov_b32 s0, s32
; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_add_i32 s32, s0, 0x400
+; GFX942-NEXT: s_add_i32 s32, s0, 16
; GFX942-NEXT: scratch_store_dword off, v0, s0
; GFX942-NEXT: s_endpgm
.entry:
@@ -53,15 +53,13 @@ define amdgpu_cs_chain void @test_alloca_var_uniform(i32 inreg %count) #0 {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
+; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_and_b32 s0, s0, -16
; GFX12-NEXT: s_mov_b32 s1, s32
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_lshl_b32 s0, s0, 5
+; GFX12-NEXT: s_and_b32 s0, s0, -16
; GFX12-NEXT: scratch_store_b32 off, v0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s1, s0
@@ -70,11 +68,10 @@ define amdgpu_cs_chain void @test_alloca_var_uniform(i32 inreg %count) #0 {
; GFX942-LABEL: test_alloca_var_uniform:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
+; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX942-NEXT: s_and_b32 s0, s0, -16
-; GFX942-NEXT: s_lshl_b32 s0, s0, 6
; GFX942-NEXT: s_mov_b32 s1, s32
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_add_i32 s32, s1, s0
@@ -116,7 +113,7 @@ define amdgpu_cs_chain void @test_alloca_var(i32 %count) #0 {
; GFX12-NEXT: s_mov_b32 s0, s32
; GFX12-NEXT: v_mov_b32_e32 v3, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_lshl_add_u32 v2, s1, 5, s0
+; GFX12-NEXT: v_add_nc_u32_e64 v2, s0, s1
; GFX12-NEXT: scratch_store_b32 off, v3, s0
; GFX12-NEXT: v_readfirstlane_b32 s32, v2
; GFX12-NEXT: s_endpgm
@@ -146,8 +143,8 @@ define amdgpu_cs_chain void @test_alloca_var(i32 %count) #0 {
; GFX942-NEXT: v_readlane_b32 s2, v0, 63
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: s_mov_b32 s0, s32
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: v_lshl_add_u32 v1, s2, 6, v1
+; GFX942-NEXT: v_mov_b32_e32 v1, s2
+; GFX942-NEXT: v_add_u32_e32 v1, s0, v1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s32, v1
; GFX942-NEXT: v_mov_b32_e32 v1, 0
@@ -178,7 +175,7 @@ define amdgpu_cs_chain void @test_alloca_and_call() #0 {
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX12-NEXT: s_mov_b32 s2, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s32, s2, 0x200
+; GFX12-NEXT: s_add_co_i32 s32, s2, 16
; GFX12-NEXT: scratch_store_b32 off, v0, s2
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -196,7 +193,7 @@ define amdgpu_cs_chain void @test_alloca_and_call() #0 {
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s2, s32
; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_add_i32 s32, s2, 0x400
+; GFX942-NEXT: s_add_i32 s32, s2, 16
; GFX942-NEXT: scratch_store_dword off, v0, s2
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -227,16 +224,15 @@ define amdgpu_cs_chain void @test_alloca_and_call_var_uniform(i32 inreg %count)
; GFX12-NEXT: s_add_co_u32 s2, s2, foo at gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo at gotpcrel32@hi+24
-; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
-; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-NEXT: s_and_b32 s0, s0, -16
+; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
+; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: s_mov_b32 s1, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_lshl_b32 s0, s0, 5
+; GFX12-NEXT: s_and_b32 s0, s0, -16
+; GFX12-NEXT: scratch_store_b32 off, v0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s1, s0
-; GFX12-NEXT: scratch_store_b32 off, v0, s1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]
@@ -246,10 +242,9 @@ define amdgpu_cs_chain void @test_alloca_and_call_var_uniform(i32 inreg %count)
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15
-; GFX942-NEXT: s_and_b32 s0, s0, -16
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
-; GFX942-NEXT: s_lshl_b32 s2, s0, 6
+; GFX942-NEXT: s_and_b32 s2, s0, -16
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, foo at gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
@@ -308,7 +303,7 @@ define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) #0 {
; GFX12-NEXT: s_mov_b32 s2, s32
; GFX12-NEXT: v_mov_b32_e32 v3, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_lshl_add_u32 v2, s3, 5, s2
+; GFX12-NEXT: v_add_nc_u32_e64 v2, s2, s3
; GFX12-NEXT: scratch_store_b32 off, v3, s2
; GFX12-NEXT: v_readfirstlane_b32 s32, v2
; GFX12-NEXT: s_wait_kmcnt 0x0
@@ -345,8 +340,8 @@ define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) #0 {
; GFX942-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s3, s32
-; GFX942-NEXT: v_mov_b32_e32 v1, s3
-; GFX942-NEXT: v_lshl_add_u32 v1, s2, 6, v1
+; GFX942-NEXT: v_mov_b32_e32 v1, s2
+; GFX942-NEXT: v_add_u32_e32 v1, s3, v1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s32, v1
; GFX942-NEXT: v_mov_b32_e32 v1, 0
@@ -378,7 +373,7 @@ define amdgpu_cs_chain void @test_call_and_alloca() #0 {
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, foo at gotpcrel32@hi+24
; GFX12-NEXT: s_mov_b32 s4, s32
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX12-NEXT: s_add_co_i32 s32, s4, 0x200
+; GFX12-NEXT: s_add_co_i32 s32, s4, 16
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -396,7 +391,7 @@ define amdgpu_cs_chain void @test_call_and_alloca() #0 {
; GFX942-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s4, s32
-; GFX942-NEXT: s_add_i32 s32, s4, 0x400
+; GFX942-NEXT: s_add_i32 s32, s4, 16
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX942-NEXT: v_mov_b32_e32 v0, 0
@@ -433,8 +428,6 @@ define amdgpu_cs_chain void @test_call_and_alloca_var_uniform(i32 inreg %count)
; GFX12-NEXT: s_and_b32 s0, s0, -16
; GFX12-NEXT: s_mov_b32 s4, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_lshl_b32 s0, s0, 5
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s4, s0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -447,10 +440,9 @@ define amdgpu_cs_chain void @test_call_and_alloca_var_uniform(i32 inreg %count)
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15
-; GFX942-NEXT: s_and_b32 s0, s0, -16
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
-; GFX942-NEXT: s_lshl_b32 s2, s0, 6
+; GFX942-NEXT: s_and_b32 s2, s0, -16
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, foo at gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
@@ -508,7 +500,7 @@ define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) #0 {
; GFX12-NEXT: s_mov_b32 exec_lo, s2
; GFX12-NEXT: s_mov_b32 s4, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_lshl_add_u32 v2, s3, 5, s4
+; GFX12-NEXT: v_add_nc_u32_e64 v2, s4, s3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s32, v2
; GFX12-NEXT: s_wait_kmcnt 0x0
@@ -547,8 +539,8 @@ define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) #0 {
; GFX942-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s4, s32
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: v_lshl_add_u32 v1, s2, 6, v1
+; GFX942-NEXT: v_mov_b32_e32 v1, s2
+; GFX942-NEXT: v_add_u32_e32 v1, s4, v1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s32, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
index 927da53d1664c1..560ac268a6b10c 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
@@ -55,8 +55,6 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) #0 {
; GFX11-SDAG-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16
-; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s0
; GFX11-SDAG-NEXT: s_endpgm
;
@@ -73,8 +71,6 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) #0 {
; GFX11-GISEL-NEXT: s_lshl2_add_u32 s1, s1, 15
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_and_b32 s1, s1, -16
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
; GFX11-GISEL-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, addrspace(5)
@@ -128,17 +124,15 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_over_aligned(i
; GFX11-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x0
; GFX11-SDAG-NEXT: s_movk_i32 s32, 0x80
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 10
-; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 0xfff
+; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 0x7f
; GFX11-SDAG-NEXT: s_mov_b32 s33, 0
-; GFX11-SDAG-NEXT: s_and_b32 s1, s1, 0xfffff000
+; GFX11-SDAG-NEXT: s_and_b32 s1, s1, 0xffffff80
; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16
-; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s0
; GFX11-SDAG-NEXT: s_endpgm
;
@@ -147,17 +141,15 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_over_aligned(i
; GFX11-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x0
; GFX11-GISEL-NEXT: s_movk_i32 s32, 0x80
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 10
-; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0xfff
+; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0x7f
; GFX11-GISEL-NEXT: s_mov_b32 s33, 0
-; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000
+; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xffffff80
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_and_b32 s0, s0, -16
-; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0
; GFX11-GISEL-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, align 128, addrspace(5)
@@ -216,8 +208,6 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_under_aligned(
; GFX11-SDAG-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16
-; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s0
; GFX11-SDAG-NEXT: s_endpgm
;
@@ -234,8 +224,6 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_under_aligned(
; GFX11-GISEL-NEXT: s_lshl2_add_u32 s1, s1, 15
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_and_b32 s1, s1, -16
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5
-; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
; GFX11-GISEL-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, align 2, addrspace(5)
@@ -335,7 +323,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent() #0 {
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x7b
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -362,12 +350,11 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent() #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
@@ -469,10 +456,10 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_over_aligned
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_readlane_b32 s1, v1, 31
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0xfff
+; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0x7f
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x1bc
-; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff000
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xffffff80
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -498,13 +485,12 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_over_aligned
; GFX11-GISEL-NEXT: ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s1, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x1bc
-; GFX11-GISEL-NEXT: s_add_u32 s0, s32, 0xfff
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5
-; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 0xfffff000
+; GFX11-GISEL-NEXT: s_add_u32 s0, s32, 0x7f
+; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 0xffffff80
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc
@@ -606,7 +592,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_under_aligne
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x29a
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -633,12 +619,11 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_under_aligne
; GFX11-GISEL-NEXT: ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
@@ -786,9 +771,8 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %
; GFX11-SDAG-NEXT: s_or_saveexec_b32 s2, -1
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v0, s2
+; GFX11-SDAG-NEXT: s_add_i32 s3, s32, 63
; GFX11-SDAG-NEXT: s_lshl2_add_u32 s1, s1, 15
-; GFX11-SDAG-NEXT: s_add_i32 s3, s32, 0x7ff
-; GFX11-SDAG-NEXT: s_and_b32 s1, s1, -16
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX11-SDAG-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
@@ -801,8 +785,8 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_readlane_b32 s4, v1, 31
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s2
-; GFX11-SDAG-NEXT: s_and_b32 s2, s3, 0xfffff800
-; GFX11-SDAG-NEXT: s_lshl_b32 s1, s1, 5
+; GFX11-SDAG-NEXT: s_and_b32 s2, s3, 0xffffffc0
+; GFX11-SDAG-NEXT: s_and_b32 s1, s1, -16
; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 3 :: v_dual_mov_b32 v4, 4
; GFX11-SDAG-NEXT: s_add_i32 s32, s2, s1
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -811,16 +795,15 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b32 off, v4, s1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s4, 5, s1
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s1, s4
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
; GFX11-SDAG-NEXT: .LBB6_2: ; %bb.1
-; GFX11-SDAG-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v3, 2
-; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16
+; GFX11-SDAG-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-NEXT: s_mov_b32 s1, s32
-; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5
+; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16
; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s33 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s1 dlc
@@ -845,6 +828,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v0, s2
; GFX11-GISEL-NEXT: s_lshl2_add_u32 s1, s1, 15
+; GFX11-GISEL-NEXT: s_add_u32 s3, s32, 63
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX11-GISEL-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
@@ -855,28 +839,24 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_readlane_b32 s3, v1, 31
+; GFX11-GISEL-NEXT: v_readlane_b32 s4, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s2
-; GFX11-GISEL-NEXT: s_add_u32 s2, s32, 0x7ff
; GFX11-GISEL-NEXT: s_and_b32 s1, s1, -16
+; GFX11-GISEL-NEXT: s_and_not1_b32 s3, s3, 63
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v3, 4
-; GFX11-GISEL-NEXT: s_and_b32 s2, s2, 0xfffff800
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX11-GISEL-NEXT: s_add_u32 s32, s3, s1
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT: s_add_u32 s32, s2, s1
-; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s2 dlc
-; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_mov_b32 s1, s32
-; GFX11-GISEL-NEXT: s_lshl_b32 s2, s3, 5
+; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s3 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s4
; GFX11-GISEL-NEXT: scratch_store_b32 off, v3, s1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s2
; GFX11-GISEL-NEXT: .LBB6_2: ; %bb.1
-; GFX11-GISEL-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v3, 2
-; GFX11-GISEL-NEXT: s_and_b32 s0, s0, -16
+; GFX11-GISEL-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX11-GISEL-NEXT: s_mov_b32 s1, s32
-; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX11-GISEL-NEXT: s_and_b32 s0, s0, -16
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s33 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b32 off, v3, s1 dlc
@@ -1041,18 +1021,17 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_control_flow(i32 %n, i
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s3, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 1
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s2, 5, s3
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s3, s2
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s3 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
; GFX11-SDAG-NEXT: s_cbranch_execnz .LBB7_3
; GFX11-SDAG-NEXT: .LBB7_2: ; %bb.0
-; GFX11-SDAG-NEXT: s_lshl2_add_u32 s1, s1, 15
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 2
-; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0x7ff
+; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 63
+; GFX11-SDAG-NEXT: s_lshl2_add_u32 s1, s1, 15
+; GFX11-SDAG-NEXT: s_and_not1_b32 s0, s0, 63
; GFX11-SDAG-NEXT: s_and_b32 s1, s1, -16
-; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff800
-; GFX11-SDAG-NEXT: s_lshl_b32 s1, s1, 5
; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_add_i32 s32, s0, s1
@@ -1092,7 +1071,6 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_control_flow(i32 %n, i
; GFX11-GISEL-NEXT: v_readlane_b32 s3, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 1
-; GFX11-GISEL-NEXT: s_lshl_b32 s3, s3, 5
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_add_u32 s32, s2, s3
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s2 dlc
@@ -1103,15 +1081,15 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_control_flow(i32 %n, i
; GFX11-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB7_4
; GFX11-GISEL-NEXT: ; %bb.3: ; %bb.0
-; GFX11-GISEL-NEXT: s_lshl2_add_u32 s0, s1, 15
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 2
-; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0x7ff
+; GFX11-GISEL-NEXT: s_lshl2_add_u32 s0, s1, 15
+; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 63
; GFX11-GISEL-NEXT: s_and_b32 s0, s0, -16
-; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff800
-; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX11-GISEL-NEXT: s_and_not1_b32 s1, s1, 63
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0
; GFX11-GISEL-NEXT: .LBB7_4: ; %bb.2
; GFX11-GISEL-NEXT: s_endpgm
entry:
@@ -1246,7 +1224,7 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) #0 {
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x7b
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -1287,12 +1265,11 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
; GFX11-GISEL-NEXT: s_mov_b32 s32, s33
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
@@ -1437,10 +1414,10 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) #0 {
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_readlane_b32 s1, v1, 31
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0xfff
+; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0x7f
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 10
-; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff000
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xffffff80
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -1485,13 +1462,12 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s1, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-GISEL-NEXT: s_add_u32 s0, s32, 0xfff
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 10
-; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 0xfffff000
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX11-GISEL-NEXT: s_add_u32 s0, s32, 0x7f
+; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 0xffffff80
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc
@@ -1627,7 +1603,7 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) #0 {
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 22
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -1668,12 +1644,11 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 22
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
; GFX11-GISEL-NEXT: s_mov_b32 s32, s33
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
@@ -1809,7 +1784,7 @@ define void @test_dynamic_stackalloc_device_divergent() #0 {
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x7b
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v2, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v2, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v2
@@ -1852,12 +1827,11 @@ define void @test_dynamic_stackalloc_device_divergent() #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v1, v0 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v0, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7b
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
; GFX11-GISEL-NEXT: s_mov_b32 s32, s33
; GFX11-GISEL-NEXT: scratch_store_b32 off, v2, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
@@ -2006,10 +1980,10 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() #0 {
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_readlane_b32 s1, v0, 31
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0xfff
+; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0x7f
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x1bc
-; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff000
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v2, s1, 5, s0
+; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xffffff80
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v2, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v2
@@ -2055,13 +2029,12 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v1, v0 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s1, v0, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-GISEL-NEXT: s_add_u32 s0, s32, 0xfff
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x1bc
-; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 0xfffff000
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX11-GISEL-NEXT: s_add_u32 s0, s32, 0x7f
+; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 0xffffff80
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
; GFX11-GISEL-NEXT: scratch_store_b32 off, v2, s0 dlc
@@ -2201,7 +2174,7 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() #0 {
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x29a
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v2, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v2, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v2
@@ -2244,12 +2217,11 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v1, v0 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v0, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x29a
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
; GFX11-GISEL-NEXT: s_mov_b32 s32, s33
; GFX11-GISEL-NEXT: scratch_store_b32 off, v2, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
@@ -2518,8 +2490,8 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-SDAG-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v1, s1
-; GFX11-SDAG-NEXT: s_add_i32 s3, s32, 0x7ff
-; GFX11-SDAG-NEXT: s_and_b32 s3, s3, 0xfffff800
+; GFX11-SDAG-NEXT: s_add_i32 s3, s32, 63
+; GFX11-SDAG-NEXT: s_and_not1_b32 s3, s3, 63
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX11-SDAG-NEXT: v_max_u32_dpp v3, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf
@@ -2540,7 +2512,7 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-SDAG-NEXT: v_max_u32_e32 v2, v3, v5
; GFX11-SDAG-NEXT: v_readlane_b32 s4, v2, 31
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, s2, 5, s3
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v1, s3, s2
; GFX11-SDAG-NEXT: v_dual_mov_b32 v6, 3 :: v_dual_mov_b32 v7, 4
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v1
@@ -2549,7 +2521,7 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b32 off, v7, s1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, s4, 5, s1
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v1, s1, s4
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v1
; GFX11-SDAG-NEXT: .LBB14_2: ; %bb.1
@@ -2574,7 +2546,7 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v6, 2
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s33 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b32 off, v6, s0 dlc
@@ -2596,7 +2568,7 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_multiple_allocas:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: s_mov_b32 s4, s33
+; GFX11-GISEL-NEXT: s_mov_b32 s5, s33
; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 63
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63
@@ -2607,7 +2579,7 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-GISEL-NEXT: scratch_store_b32 off, v4, s33 offset:72
; GFX11-GISEL-NEXT: scratch_store_b32 off, v5, s33 offset:76
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-GISEL-NEXT: s_mov_b32 s5, s34
+; GFX11-GISEL-NEXT: s_mov_b32 s6, s34
; GFX11-GISEL-NEXT: s_mov_b32 s0, exec_lo
; GFX11-GISEL-NEXT: s_mov_b32 s34, s32
; GFX11-GISEL-NEXT: s_addk_i32 s32, 0xc0
@@ -2624,8 +2596,9 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-GISEL-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v1, s1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v6, s1
+; GFX11-GISEL-NEXT: s_add_u32 s3, s32, 63
; GFX11-GISEL-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_max_u32_dpp v3, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf
@@ -2646,21 +2619,18 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-GISEL-NEXT: v_max_u32_e32 v3, v3, v5
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v2, 31
-; GFX11-GISEL-NEXT: v_readlane_b32 s3, v3, 31
+; GFX11-GISEL-NEXT: v_readlane_b32 s4, v3, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0x7ff
+; GFX11-GISEL-NEXT: s_and_not1_b32 s3, s3, 63
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 3 :: v_dual_mov_b32 v6, 4
-; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff800
-; GFX11-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GFX11-GISEL-NEXT: s_add_u32 s32, s3, s2
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s2
-; GFX11-GISEL-NEXT: scratch_store_b32 off, v1, s1 dlc
-; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_mov_b32 s1, s32
-; GFX11-GISEL-NEXT: s_lshl_b32 s2, s3, 5
+; GFX11-GISEL-NEXT: scratch_store_b32 off, v1, s3 dlc
+; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s4
; GFX11-GISEL-NEXT: scratch_store_b32 off, v6, s1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s2
; GFX11-GISEL-NEXT: .LBB14_2: ; %bb.1
; GFX11-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15
@@ -2679,18 +2649,17 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-GISEL-NEXT: ds_swizzle_b32 v3, v2 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v2, v2, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v2, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
+; GFX11-GISEL-NEXT: s_mov_b32 s32, s34
+; GFX11-GISEL-NEXT: s_mov_b32 s34, s6
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s33 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b32 off, v1, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: s_mov_b32 s32, s34
-; GFX11-GISEL-NEXT: s_mov_b32 s34, s5
; GFX11-GISEL-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-GISEL-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX11-GISEL-NEXT: scratch_load_b32 v2, off, s33 offset:64
@@ -2698,7 +2667,7 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0
; GFX11-GISEL-NEXT: scratch_load_b32 v4, off, s33 offset:72
; GFX11-GISEL-NEXT: scratch_load_b32 v5, off, s33 offset:76
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-GISEL-NEXT: s_mov_b32 s33, s4
+; GFX11-GISEL-NEXT: s_mov_b32 s33, s5
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2928,11 +2897,11 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) #0 {
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_readlane_b32 s2, v2, 31
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 0x7ff
+; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 63
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 2
-; GFX11-SDAG-NEXT: s_and_b32 s1, s1, 0xfffff800
+; GFX11-SDAG-NEXT: s_and_not1_b32 s1, s1, 63
; GFX11-SDAG-NEXT: ; implicit-def: $vgpr31
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s2, 5, s1
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s1, s2
; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -2961,7 +2930,7 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) #0 {
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s1
; GFX11-SDAG-NEXT: s_mov_b32 s1, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s2, 5, s1
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s1, s2
; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -3013,14 +2982,13 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v3, v2 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v2, v2, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v2, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 2
-; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0x7ff
-; GFX11-GISEL-NEXT: s_lshl_b32 s2, s2, 5
-; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff800
+; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 63
; GFX11-GISEL-NEXT: ; implicit-def: $vgpr31
+; GFX11-GISEL-NEXT: s_and_not1_b32 s1, s1, 63
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s2
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc
@@ -3046,12 +3014,11 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) #0 {
; GFX11-GISEL-NEXT: ds_swizzle_b32 v3, v2 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v2, v2, v3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s3, v2, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s2
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 1
-; GFX11-GISEL-NEXT: s_lshl_b32 s2, s3, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s2
+; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s3
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: .LBB15_4: ; %bb.2
@@ -3202,7 +3169,7 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x29a
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -3245,12 +3212,11 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16
; GFX11-GISEL-NEXT: ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
; GFX11-GISEL-NEXT: s_mov_b32 s32, s33
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
@@ -3383,7 +3349,7 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64
; GFX11-SDAG-NEXT: s_mov_b32 exec_lo, s0
; GFX11-SDAG-NEXT: s_mov_b32 s0, s32
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x29a
-; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0
+; GFX11-SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1
; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s0 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0
@@ -3424,12 +3390,11 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64
; GFX11-GISEL-NEXT: ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15)
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_max_u32_e32 v1, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readlane_b32 s2, v1, 31
; GFX11-GISEL-NEXT: s_mov_b32 exec_lo, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a
-; GFX11-GISEL-NEXT: s_lshl_b32 s1, s2, 5
-; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1
+; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s2
; GFX11-GISEL-NEXT: s_mov_b32 s32, s33
; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
index 618a4c294cae5a..b215d75009c02d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
@@ -346,7 +346,7 @@ define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_dyn_alloc(i32 %val) #0 {
; DAGISEL-NEXT: s_mov_b32 exec_lo, s0
; DAGISEL-NEXT: s_mov_b32 s0, s32
; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; DAGISEL-NEXT: v_lshl_add_u32 v3, s1, 5, s0
+; DAGISEL-NEXT: v_add_nc_u32_e64 v3, s0, s1
; DAGISEL-NEXT: s_wait_storecnt 0x0
; DAGISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; DAGISEL-NEXT: s_wait_storecnt 0x0
@@ -400,12 +400,10 @@ define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_dyn_alloc(i32 %val) #0 {
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_readlane_b32 s2, v1, 31
; GISEL-NEXT: s_mov_b32 exec_lo, s1
-; GISEL-NEXT: s_lshl_b32 s1, s2, 5
+; GISEL-NEXT: s_add_co_u32 s32, s0, s2
; GISEL-NEXT: s_wait_storecnt 0x0
; GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; GISEL-NEXT: s_wait_storecnt 0x0
-; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GISEL-NEXT: s_add_co_u32 s32, s0, s1
; GISEL-NEXT: v_mov_b32_e32 v0, s33
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: s_xor_saveexec_b32 s0, -1
@@ -555,7 +553,7 @@ define amdgpu_cs_chain void @sponentry_cs_chain_dyn_alloc(i32 %val) #0 {
; DAGISEL-NEXT: s_mov_b32 s0, s32
; DAGISEL-NEXT: v_mov_b32_e32 v3, s33
; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; DAGISEL-NEXT: v_lshl_add_u32 v2, s1, 5, s0
+; DAGISEL-NEXT: v_add_nc_u32_e64 v2, s0, s1
; DAGISEL-NEXT: s_wait_storecnt 0x0
; DAGISEL-NEXT: scratch_store_b32 off, v8, s0 scope:SCOPE_SYS
; DAGISEL-NEXT: s_wait_storecnt 0x0
@@ -594,12 +592,10 @@ define amdgpu_cs_chain void @sponentry_cs_chain_dyn_alloc(i32 %val) #0 {
; GISEL-NEXT: v_readlane_b32 s2, v0, 31
; GISEL-NEXT: s_mov_b32 exec_lo, s1
; GISEL-NEXT: v_mov_b32_e32 v2, s33
-; GISEL-NEXT: s_lshl_b32 s1, s2, 5
; GISEL-NEXT: s_wait_storecnt 0x0
; GISEL-NEXT: scratch_store_b32 off, v8, s0 scope:SCOPE_SYS
; GISEL-NEXT: s_wait_storecnt 0x0
-; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GISEL-NEXT: s_add_co_u32 s32, s0, s1
+; GISEL-NEXT: s_add_co_u32 s32, s0, s2
; GISEL-NEXT: scratch_store_b32 off, v2, s0 scope:SCOPE_SYS
; GISEL-NEXT: s_wait_storecnt 0x0
; GISEL-NEXT: s_alloc_vgpr 0
diff --git a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
index 154a75a674890f..70095e4e5932a1 100644
--- a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
+++ b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
@@ -66,7 +66,7 @@ define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reache
; FLATSCR-NEXT: s_mov_b32 s2, s32
; FLATSCR-NEXT: v_mov_b32_e32 v1, 0
; FLATSCR-NEXT: v_mov_b32_e32 v2, 1
-; FLATSCR-NEXT: s_add_i32 s32, s2, 0x1000
+; FLATSCR-NEXT: s_add_i32 s32, s2, 64
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s2
; FLATSCR-NEXT: s_lshl2_add_u32 s2, s6, s2
; FLATSCR-NEXT: scratch_load_dword v2, off, s2
@@ -160,11 +160,11 @@ define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reache
; FLATSCR-NEXT: s_cmp_lg_u32 s0, 0
; FLATSCR-NEXT: s_cbranch_scc1 .LBB1_2
; FLATSCR-NEXT: ; %bb.1: ; %bb.0
-; FLATSCR-NEXT: s_add_i32 s0, s32, 0xfff
+; FLATSCR-NEXT: s_add_i32 s0, s32, 63
; FLATSCR-NEXT: v_mov_b32_e32 v1, 0
-; FLATSCR-NEXT: s_and_b32 s0, s0, 0xfffff000
+; FLATSCR-NEXT: s_andn2_b32 s0, s0, 63
; FLATSCR-NEXT: v_mov_b32_e32 v2, 1
-; FLATSCR-NEXT: s_add_i32 s32, s0, 0x1000
+; FLATSCR-NEXT: s_add_i32 s32, s0, 64
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s0
; FLATSCR-NEXT: s_lshl2_add_u32 s0, s1, s0
; FLATSCR-NEXT: scratch_load_dword v2, off, s0
@@ -266,7 +266,7 @@ define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i3
; FLATSCR-NEXT: v_lshl_add_u32 v2, v4, 2, s2
; FLATSCR-NEXT: scratch_load_dword v2, v2, off
; FLATSCR-NEXT: v_and_b32_e32 v3, 0x3ff, v31
-; FLATSCR-NEXT: s_add_i32 s32, s2, 0x1000
+; FLATSCR-NEXT: s_add_i32 s32, s2, 64
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3
; FLATSCR-NEXT: global_store_dword v[0:1], v2, off
@@ -356,15 +356,15 @@ define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i
; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc
; FLATSCR-NEXT: s_cbranch_execz .LBB3_2
; FLATSCR-NEXT: ; %bb.1: ; %bb.0
-; FLATSCR-NEXT: s_add_i32 s2, s32, 0xfff
-; FLATSCR-NEXT: s_and_b32 s2, s2, 0xfffff000
+; FLATSCR-NEXT: s_add_i32 s2, s32, 63
+; FLATSCR-NEXT: s_andn2_b32 s2, s2, 63
; FLATSCR-NEXT: v_mov_b32_e32 v4, 0
; FLATSCR-NEXT: v_mov_b32_e32 v5, 1
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[4:5], s2
; FLATSCR-NEXT: v_lshl_add_u32 v2, v3, 2, s2
; FLATSCR-NEXT: scratch_load_dword v2, v2, off
; FLATSCR-NEXT: v_and_b32_e32 v3, 0x3ff, v31
-; FLATSCR-NEXT: s_add_i32 s32, s2, 0x1000
+; FLATSCR-NEXT: s_add_i32 s32, s2, 64
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3
; FLATSCR-NEXT: global_store_dword v[0:1], v2, off
>From b3a9c8df9e7eb3e4b3629b149ec109d82b4763d3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Wed, 3 Jun 2026 11:01:05 +0200
Subject: [PATCH 2/5] [Review] up !
---
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 8 ++++----
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 +--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 540447890dfd25..7419743263b819 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1174,8 +1174,7 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
Register AllocSize = MI.getOperand(1).getReg();
Align Alignment = assumeAligned(MI.getOperand(2).getImm());
- // When using flat-scratch, the stack offset is already scaled by the
- // wave-size by the hardware instructions.
+ // When using flat-scratch, the stack offset unscaled.
const bool HasFlatScratch = ST.hasFlatScratchEnabled();
const unsigned WavefrontSizeLog2 = ST.getWavefrontSizeLog2();
@@ -1205,8 +1204,9 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
auto OldSP = B.buildCopy(PtrTy, SPReg);
if (Alignment > TFI.getStackAlign()) {
const uint64_t ScaledAlignment =
- Alignment.value() << (HasFlatScratch ? 0u : WavefrontSizeLog2);
- auto StackAlignMask = ScaledAlignment - 1;
+ HasFlatScratch ? Alignment.value()
+ : (Alignment.value() << WavefrontSizeLog2);
+ const uint64_t StackAlignMask = ScaledAlignment - 1;
auto Tmp1 = B.buildPtrAdd(PtrTy, OldSP,
B.buildConstant(LLT::scalar(32), StackAlignMask));
B.buildMaskLowPtrBits(Dst, Tmp1,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 4603e6cac6bde8..218aa43646edab 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4680,8 +4680,7 @@ SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
"Stack grows upwards for AMDGPU");
Chain = BaseAddr.getValue(1);
- // When using flat-scratch, the stack offset is already is scaled by the
- // wave-size by the hardware instructions.
+ // When using flat-scratch, the stack offset is already unscaled.
const bool HasFlatScratch = Subtarget->hasFlatScratchEnabled();
const unsigned WavefrontSizeLog2 = Subtarget->getWavefrontSizeLog2();
>From 82bc4cd2915212678c6801863e384171708223cb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Wed, 3 Jun 2026 13:16:27 +0200
Subject: [PATCH 3/5] Update llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
---
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 7419743263b819..10cf87c8ef2b6a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1174,7 +1174,7 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
Register AllocSize = MI.getOperand(1).getReg();
Align Alignment = assumeAligned(MI.getOperand(2).getImm());
- // When using flat-scratch, the stack offset unscaled.
+ // When using flat-scratch, the stack offset is unscaled.
const bool HasFlatScratch = ST.hasFlatScratchEnabled();
const unsigned WavefrontSizeLog2 = ST.getWavefrontSizeLog2();
>From b5da64f40673c200f1c54a8eb119f24da3c0ccbc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Wed, 3 Jun 2026 13:16:38 +0200
Subject: [PATCH 4/5] Update llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 218aa43646edab..2da450705649af 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4680,7 +4680,7 @@ SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
"Stack grows upwards for AMDGPU");
Chain = BaseAddr.getValue(1);
- // When using flat-scratch, the stack offset is already unscaled.
+ // When using flat-scratch, the stack offset is unscaled.
const bool HasFlatScratch = Subtarget->hasFlatScratchEnabled();
const unsigned WavefrontSizeLog2 = Subtarget->getWavefrontSizeLog2();
>From 13b689a0a627c6a4175412b546a251f56bc5c081 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Wed, 3 Jun 2026 13:17:02 +0200
Subject: [PATCH 5/5] Update llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 2da450705649af..8694d2cd8651bb 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4700,12 +4700,9 @@ SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
if (isa<ConstantSDNode>(Size)) {
// Increase the stack pointer by the size of the alloca.
// If not using flat-scratch, we have to scale the size by the wave-size.
- SDValue ScaledSize = Size;
- if (!HasFlatScratch) {
- ScaledSize =
+ SDValue ScaledSize = HasFlatScratch ? Size :
DAG.getNode(ISD::SHL, dl, VT, Size,
DAG.getConstant(WavefrontSizeLog2, dl, MVT::i32));
- }
NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value
} else {
// For dynamic sized alloca, perform wave-wide reduction to get max of
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