[llvm] c958962 - [LoopInterchange] Assume LCSSA PHI incoming value may not be instruction (#201069)

[via llvm-commits]

Author: Ryotaro Kasuga
Date: 2026-06-03T10:46:51Z
New Revision: c958962c157b728e153b6232b800cbf556812545

URL: https://github.com/llvm/llvm-project/commit/c958962c157b728e153b6232b800cbf556812545
DIFF: https://github.com/llvm/llvm-project/commit/c958962c157b728e153b6232b800cbf556812545.diff

LOG: [LoopInterchange] Assume LCSSA PHI incoming value may not be instruction (#201069)

This patch fixes one of the assertion failures reported in #200819. The
root cause in this case is that `moveLCSSAPhis` assumes the incoming
values of LCSSA PHIs are always instructions and unconditionally casts
them to `Instruction`.
This assumption does not always hold, especially when the incoming value
is a constant. For such LCSSA PHI nodes, it's enough to merely replace
all the uses with its incoming value.

Added: 
    llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll

Modified: 
    llvm/lib/Transforms/Scalar/LoopInterchange.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
index 5143e2f497bc5..707d44c8411e8 100644
--- a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
@@ -2200,8 +2200,19 @@ static void moveLCSSAPhis(BasicBlock *InnerExit, BasicBlock *InnerHeader,
     assert(P.getNumIncomingValues() == 1 &&
            "Only loops with a single exit are supported!");
 
-    // Incoming values are guaranteed be instructions currently.
-    auto IncI = cast<Instruction>(P.getIncomingValueForBlock(InnerLatch));
+    Value *IncomingValue = P.getIncomingValueForBlock(InnerLatch);
+    auto *IncI = dyn_cast<Instruction>(IncomingValue);
+    if (!IncI) {
+      // If the incoming value is not an instruction, it must be loop invariant.
+      // In that case, we can just replace the PHI with the incoming value and
+      // remove the PHI.
+      assert(InnerLoop->isLoopInvariant(IncomingValue) &&
+             "Expected non-instruction incoming value to be loop invariant");
+      P.replaceAllUsesWith(IncomingValue);
+      P.eraseFromParent();
+      continue;
+    }
+
     // In case of multi-level nested loops, follow LCSSA to find the incoming
     // value defined from the innermost loop.
     auto IncIInnerMost = cast<Instruction>(followLCSSA(IncI));

diff  --git a/llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll b/llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
new file mode 100644
index 0000000000000..9624ed7d38ed7
--- /dev/null
+++ b/llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=loop-interchange -loop-interchange-profitabilities=ignore -S | FileCheck %s
+
+; Ensure that we can handle LCSSA PHI whose incoming value is not an
+; instruction.
+
+define i32 @f() {
+; CHECK-LABEL: define i32 @f() {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    br label %[[INNER_PREHEADER:.*]]
+; CHECK:       [[OUTER_HEADER_PREHEADER:.*]]:
+; CHECK-NEXT:    br label %[[OUTER_HEADER:.*]]
+; CHECK:       [[OUTER_HEADER]]:
+; CHECK-NEXT:    [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[OUTER_HEADER_PREHEADER]] ]
+; CHECK-NEXT:    br label %[[INNER_SPLIT1:.*]]
+; CHECK:       [[INNER_PREHEADER]]:
+; CHECK-NEXT:    br label %[[INNER:.*]]
+; CHECK:       [[INNER]]:
+; CHECK-NEXT:    [[J:%.*]] = phi i64 [ [[TMP0:%.*]], %[[INNER_SPLIT:.*]] ], [ 0, %[[INNER_PREHEADER]] ]
+; CHECK-NEXT:    br label %[[OUTER_HEADER_PREHEADER]]
+; CHECK:       [[INNER_SPLIT1]]:
+; CHECK-NEXT:    [[J_NEXT:%.*]] = add i64 [[J]], 1
+; CHECK-NEXT:    [[EC_J:%.*]] = icmp eq i64 [[J_NEXT]], 2
+; CHECK-NEXT:    br label %[[INNER_EXIT:.*]]
+; CHECK:       [[INNER_SPLIT]]:
+; CHECK-NEXT:    [[TMP0]] = add i64 [[J]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 2
+; CHECK-NEXT:    br i1 [[TMP1]], label %[[EXIT:.*]], label %[[INNER]]
+; CHECK:       [[INNER_EXIT]]:
+; CHECK-NEXT:    br label %[[OUTER_LATCH]]
+; CHECK:       [[OUTER_LATCH]]:
+; CHECK-NEXT:    [[I_NEXT]] = add i64 [[I]], 1
+; CHECK-NEXT:    [[EC_I:%.*]] = icmp eq i64 [[I_NEXT]], 2
+; CHECK-NEXT:    br i1 [[EC_I]], label %[[INNER_SPLIT]], label %[[OUTER_HEADER]]
+; CHECK:       [[EXIT]]:
+; CHECK-NEXT:    [[CST_LCSSA:%.*]] = phi i32 [ 42, %[[INNER_SPLIT]] ]
+; CHECK-NEXT:    ret i32 [[CST_LCSSA]]
+;
+entry:
+  br label %outer.header
+
+outer.header:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %outer.latch ]
+  br label %inner
+
+inner:
+  %j = phi i64 [ 0, %outer.header ], [ %j.next, %inner ]
+  %j.next = add i64 %j, 1
+  %ec.j = icmp eq i64 %j.next, 2
+  br i1 %ec.j, label %inner.exit, label %inner
+
+inner.exit:
+  %cst = phi i32 [ 42, %inner ]
+  br label %outer.latch
+
+outer.latch:
+  %i.next = add i64 %i, 1
+  %ec.i = icmp eq i64 %i.next, 2
+  br i1 %ec.i, label %exit, label %outer.header
+
+exit:
+  %cst.lcssa = phi i32 [ %cst, %outer.latch ]
+  ret i32 %cst.lcssa
+}