[llvm] [AMDGPU] Remove definition of hi16 for scalar registers (PR #197467)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> cannot represent required subregister defs

This is a pain. I wish MIR had a more direct way to represent the liveness of a register + lane mask instead of building these COPY bundles with a sequence of subregister operands. Something like a COPY_LANEMASK that directly encodes the live lanes. Ultimately we'd still need to lower that into a register RMW for the cases that only preserve unallocatable pieces of registers to encode the instruction 

https://github.com/llvm/llvm-project/pull/197467