[llvm] 5d00743 - [AMDGPU] Fix LowerDIVREM24 for the unsigned case (#196418)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 3 03:03:27 PDT 2026
Author: Manuel Carrasco
Date: 2026-06-03T11:03:22+01:00
New Revision: 5d0074316a86de1019c5850584f5b5cdde9edefa
URL: https://github.com/llvm/llvm-project/commit/5d0074316a86de1019c5850584f5b5cdde9edefa
DIFF: https://github.com/llvm/llvm-project/commit/5d0074316a86de1019c5850584f5b5cdde9edefa.diff
LOG: [AMDGPU] Fix LowerDIVREM24 for the unsigned case (#196418)
This PR fixes the miscompilation bug found in
https://github.com/llvm/llvm-project/issues/194829.
The test revealed that there were missing checks for the unsigned case
in LowerDIVREM24. Without those checks, the optimization is wrongly
applied assuming that the division operands do fit in 24-bit integers,
triggering the miscompilation. One of the operands was 0xFFFFFFFF.
The bug is a regression introduced in
https://github.com/llvm/llvm-project/commit/81a709503d378c188462465918df161d664c4205.
The commit refactored the conditions that validated whether the
optimization could be applied. It moved them from each call site (signed
and unsigned cases) into the function, but missed the ones for the
unsigned case.
---------
Co-authored-by: Carlo Bertolli <carlo.bertolli at amd.com>
Added:
llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
Modified:
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/test/CodeGen/AMDGPU/udiv.ll
llvm/test/CodeGen/AMDGPU/udivrem24.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index f0918a86be757..267e7b0b53fab 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2001,23 +2001,35 @@ SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
// This is a shortcut for integer division because we have fast i32<->f32
// conversions, and fast f32 reciprocal instructions. The fractional part of a
-// float is enough to accurately represent up to a 24-bit signed integer.
+// float is enough to accurately represent up to a 24-bit integer.
SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
bool Sign) const {
SDLoc DL(Op);
EVT VT = Op.getValueType();
+ assert(VT == MVT::i32 && "LowerDIVREM24 expects an i32");
+
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
MVT IntVT = MVT::i32;
MVT FltVT = MVT::f32;
- unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
- if (LHSSignBits < 9)
- return SDValue();
-
- unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
- if (RHSSignBits < 9)
- return SDValue();
+ unsigned LHSSignBits;
+ unsigned RHSSignBits;
+ if (Sign) {
+ LHSSignBits = DAG.ComputeNumSignBits(LHS);
+ RHSSignBits = DAG.ComputeNumSignBits(RHS);
+ if (LHSSignBits < 9 || RHSSignBits < 9)
+ return SDValue();
+ } else {
+ KnownBits LHSKnown = DAG.computeKnownBits(LHS);
+ KnownBits RHSKnown = DAG.computeKnownBits(RHS);
+ APInt U24Max = APInt::getLowBitsSet(32, 24);
+ if (LHSKnown.getMaxValue().ugt(U24Max) ||
+ RHSKnown.getMaxValue().ugt(U24Max))
+ return SDValue();
+ LHSSignBits = LHSKnown.countMinLeadingZeros();
+ RHSSignBits = RHSKnown.countMinLeadingZeros();
+ }
unsigned BitSize = VT.getSizeInBits();
unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
diff --git a/llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll b/llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
new file mode 100644
index 0000000000000..ebd75e7e60552
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
@@ -0,0 +1,694 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefix GFX950 %s
+; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck --check-prefix GFX90A %s
+
+; Verify div/rem lowering at -O0 for operands that do or do not qualify for the
+; float-reciprocal fast path.
+
+define amdgpu_kernel void @udiv_i32_i16_no_fast_path(ptr addrspace(1) %out, i32 %input) {
+; GFX950-LABEL: udiv_i32_i16_no_fast_path:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_sext_i32_i16 s4, s2
+; GFX950-NEXT: s_mov_b32 s2, 1
+; GFX950-NEXT: s_or_b32 s5, s4, s2
+; GFX950-NEXT: s_mov_b32 s3, 0
+; GFX950-NEXT: s_sub_i32 s3, s3, s5
+; GFX950-NEXT: v_cvt_f32_u32_e32 v1, s5
+; GFX950-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX950-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_readfirstlane_b32 s6, v1
+; GFX950-NEXT: s_mul_i32 s6, s3, s6
+; GFX950-NEXT: v_readfirstlane_b32 s3, v1
+; GFX950-NEXT: s_mul_hi_u32 s6, s3, s6
+; GFX950-NEXT: v_readfirstlane_b32 s3, v1
+; GFX950-NEXT: s_add_i32 s3, s3, s6
+; GFX950-NEXT: s_mul_hi_u32 s6, s4, s3
+; GFX950-NEXT: s_add_i32 s3, s6, s2
+; GFX950-NEXT: s_mul_i32 s7, s6, s5
+; GFX950-NEXT: s_sub_i32 s7, s4, s7
+; GFX950-NEXT: s_sub_i32 s4, s7, s5
+; GFX950-NEXT: s_cmp_ge_u32 s7, s5
+; GFX950-NEXT: s_cselect_b32 s4, s4, s7
+; GFX950-NEXT: s_cselect_b32 s3, s3, s6
+; GFX950-NEXT: s_add_i32 s2, s3, s2
+; GFX950-NEXT: s_cmp_ge_u32 s4, s5
+; GFX950-NEXT: s_cselect_b32 s2, s2, s3
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX90A-LABEL: udiv_i32_i16_no_fast_path:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_sext_i32_i16 s4, s2
+; GFX90A-NEXT: s_mov_b32 s2, 1
+; GFX90A-NEXT: s_or_b32 s5, s4, s2
+; GFX90A-NEXT: s_mov_b32 s3, 0
+; GFX90A-NEXT: s_sub_i32 s3, s3, s5
+; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s5
+; GFX90A-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX90A-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX90A-NEXT: v_readfirstlane_b32 s6, v1
+; GFX90A-NEXT: s_mul_i32 s6, s3, s6
+; GFX90A-NEXT: v_readfirstlane_b32 s3, v1
+; GFX90A-NEXT: s_mul_hi_u32 s6, s3, s6
+; GFX90A-NEXT: v_readfirstlane_b32 s3, v1
+; GFX90A-NEXT: s_add_i32 s3, s3, s6
+; GFX90A-NEXT: s_mul_hi_u32 s6, s4, s3
+; GFX90A-NEXT: s_add_i32 s3, s6, s2
+; GFX90A-NEXT: s_mul_i32 s7, s6, s5
+; GFX90A-NEXT: s_sub_i32 s7, s4, s7
+; GFX90A-NEXT: s_sub_i32 s4, s7, s5
+; GFX90A-NEXT: s_cmp_ge_u32 s7, s5
+; GFX90A-NEXT: s_cselect_b32 s4, s4, s7
+; GFX90A-NEXT: s_cselect_b32 s3, s3, s6
+; GFX90A-NEXT: s_add_i32 s2, s3, s2
+; GFX90A-NEXT: s_cmp_ge_u32 s4, s5
+; GFX90A-NEXT: s_cselect_b32 s2, s2, s3
+; GFX90A-NEXT: v_mov_b32_e32 v1, s2
+; GFX90A-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90A-NEXT: s_endpgm
+ %trunc_i16 = trunc i32 %input to i16
+ %dividend = sext i16 %trunc_i16 to i32
+ %divisor = or i32 %dividend, 1
+ %result = udiv i32 %dividend, %divisor
+ store i32 %result, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @udiv_i32_and_i24_fast_path(ptr addrspace(1) %out, i32 %input) {
+; GFX950-LABEL: udiv_i32_and_i24_fast_path:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX950-NEXT: s_mov_b32 s2, 0xffffff
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_and_b32 s5, s3, s2
+; GFX950-NEXT: s_mov_b32 s3, 1
+; GFX950-NEXT: s_or_b32 s4, s5, s3
+; GFX950-NEXT: v_cvt_f32_u32_e64 v2, s5
+; GFX950-NEXT: v_cvt_f32_u32_e64 v3, s4
+; GFX950-NEXT: v_rcp_f32_e64 v1, v3
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_mul_f32_e64 v1, v2, v1
+; GFX950-NEXT: v_trunc_f32_e64 v1, v1
+; GFX950-NEXT: v_fma_f32 v2, -v1, v3, v2
+; GFX950-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v3|
+; GFX950-NEXT: s_mov_b32 s4, 0
+; GFX950-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX950-NEXT: s_cselect_b32 s3, s3, s4
+; GFX950-NEXT: v_cvt_u32_f32_e64 v1, v1
+; GFX950-NEXT: v_add_u32_e64 v1, v1, s3
+; GFX950-NEXT: v_and_b32_e64 v1, v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX90A-LABEL: udiv_i32_and_i24_fast_path:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX90A-NEXT: s_mov_b32 s2, 0xffffff
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_and_b32 s5, s3, s2
+; GFX90A-NEXT: s_mov_b32 s3, 1
+; GFX90A-NEXT: s_or_b32 s4, s5, s3
+; GFX90A-NEXT: v_cvt_f32_u32_e64 v2, s5
+; GFX90A-NEXT: v_cvt_f32_u32_e64 v3, s4
+; GFX90A-NEXT: v_rcp_f32_e64 v1, v3
+; GFX90A-NEXT: v_mul_f32_e64 v1, v2, v1
+; GFX90A-NEXT: v_trunc_f32_e64 v1, v1
+; GFX90A-NEXT: v_mad_f32 v2, -v1, v3, v2
+; GFX90A-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v3|
+; GFX90A-NEXT: s_mov_b32 s4, 0
+; GFX90A-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX90A-NEXT: s_cselect_b32 s3, s3, s4
+; GFX90A-NEXT: v_cvt_u32_f32_e64 v1, v1
+; GFX90A-NEXT: v_add_u32_e64 v1, v1, s3
+; GFX90A-NEXT: v_and_b32_e64 v1, v1, s2
+; GFX90A-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90A-NEXT: s_endpgm
+ %dividend = and i32 %input, u0xffffff
+ %divisor = or i32 %dividend, 1
+ %result = udiv i32 %dividend, %divisor
+ store i32 %result, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @sdiv_i32_i16_no_fast_path(ptr addrspace(1) %out, i32 %input) {
+; GFX950-LABEL: sdiv_i32_i16_no_fast_path:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_mov_b32 s3, s2
+; GFX950-NEXT: s_sext_i32_i16 s5, s3
+; GFX950-NEXT: s_mov_b32 s6, 0
+; GFX950-NEXT: s_cmp_lt_i32 s2, s6
+; GFX950-NEXT: s_mov_b32 s3, -1
+; GFX950-NEXT: s_cselect_b32 s4, s3, s6
+; GFX950-NEXT: s_add_i32 s2, s2, s4
+; GFX950-NEXT: s_xor_b32 s7, s2, s4
+; GFX950-NEXT: s_sub_i32 s2, s6, s7
+; GFX950-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX950-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX950-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_readfirstlane_b32 s8, v1
+; GFX950-NEXT: s_mul_i32 s8, s2, s8
+; GFX950-NEXT: v_readfirstlane_b32 s2, v1
+; GFX950-NEXT: s_mul_hi_u32 s8, s2, s8
+; GFX950-NEXT: v_readfirstlane_b32 s2, v1
+; GFX950-NEXT: s_add_i32 s2, s2, s8
+; GFX950-NEXT: s_cmp_lt_i32 s5, s6
+; GFX950-NEXT: s_cselect_b32 s3, s3, s6
+; GFX950-NEXT: s_add_i32 s5, s5, s3
+; GFX950-NEXT: s_xor_b32 s6, s5, s3
+; GFX950-NEXT: s_mul_hi_u32 s8, s6, s2
+; GFX950-NEXT: s_mov_b32 s2, 1
+; GFX950-NEXT: s_add_i32 s5, s8, s2
+; GFX950-NEXT: s_mul_i32 s9, s8, s7
+; GFX950-NEXT: s_sub_i32 s9, s6, s9
+; GFX950-NEXT: s_sub_i32 s6, s9, s7
+; GFX950-NEXT: s_cmp_ge_u32 s9, s7
+; GFX950-NEXT: s_cselect_b32 s6, s6, s9
+; GFX950-NEXT: s_cselect_b32 s5, s5, s8
+; GFX950-NEXT: s_add_i32 s2, s5, s2
+; GFX950-NEXT: s_cmp_ge_u32 s6, s7
+; GFX950-NEXT: s_cselect_b32 s2, s2, s5
+; GFX950-NEXT: s_xor_b32 s3, s3, s4
+; GFX950-NEXT: s_xor_b32 s2, s2, s3
+; GFX950-NEXT: s_sub_i32 s2, s2, s3
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX90A-LABEL: sdiv_i32_i16_no_fast_path:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_mov_b32 s3, s2
+; GFX90A-NEXT: s_sext_i32_i16 s5, s3
+; GFX90A-NEXT: s_mov_b32 s6, 0
+; GFX90A-NEXT: s_cmp_lt_i32 s2, s6
+; GFX90A-NEXT: s_mov_b32 s3, -1
+; GFX90A-NEXT: s_cselect_b32 s4, s3, s6
+; GFX90A-NEXT: s_add_i32 s2, s2, s4
+; GFX90A-NEXT: s_xor_b32 s7, s2, s4
+; GFX90A-NEXT: s_sub_i32 s2, s6, s7
+; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX90A-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX90A-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX90A-NEXT: v_readfirstlane_b32 s8, v1
+; GFX90A-NEXT: s_mul_i32 s8, s2, s8
+; GFX90A-NEXT: v_readfirstlane_b32 s2, v1
+; GFX90A-NEXT: s_mul_hi_u32 s8, s2, s8
+; GFX90A-NEXT: v_readfirstlane_b32 s2, v1
+; GFX90A-NEXT: s_add_i32 s2, s2, s8
+; GFX90A-NEXT: s_cmp_lt_i32 s5, s6
+; GFX90A-NEXT: s_cselect_b32 s3, s3, s6
+; GFX90A-NEXT: s_add_i32 s5, s5, s3
+; GFX90A-NEXT: s_xor_b32 s6, s5, s3
+; GFX90A-NEXT: s_mul_hi_u32 s8, s6, s2
+; GFX90A-NEXT: s_mov_b32 s2, 1
+; GFX90A-NEXT: s_add_i32 s5, s8, s2
+; GFX90A-NEXT: s_mul_i32 s9, s8, s7
+; GFX90A-NEXT: s_sub_i32 s9, s6, s9
+; GFX90A-NEXT: s_sub_i32 s6, s9, s7
+; GFX90A-NEXT: s_cmp_ge_u32 s9, s7
+; GFX90A-NEXT: s_cselect_b32 s6, s6, s9
+; GFX90A-NEXT: s_cselect_b32 s5, s5, s8
+; GFX90A-NEXT: s_add_i32 s2, s5, s2
+; GFX90A-NEXT: s_cmp_ge_u32 s6, s7
+; GFX90A-NEXT: s_cselect_b32 s2, s2, s5
+; GFX90A-NEXT: s_xor_b32 s3, s3, s4
+; GFX90A-NEXT: s_xor_b32 s2, s2, s3
+; GFX90A-NEXT: s_sub_i32 s2, s2, s3
+; GFX90A-NEXT: v_mov_b32_e32 v1, s2
+; GFX90A-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90A-NEXT: s_endpgm
+ %trunc_i16 = trunc i32 %input to i16
+ %dividend = sext i16 %trunc_i16 to i32
+ %result = sdiv i32 %dividend, %input
+ store i32 %result, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @sdiv_i32_i16_fast_path(ptr addrspace(1) %out, i32 %input) {
+; GFX950-LABEL: sdiv_i32_i16_fast_path:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_sext_i32_i16 s2, s2
+; GFX950-NEXT: s_mov_b32 s3, 1
+; GFX950-NEXT: s_or_b32 s6, s2, s3
+; GFX950-NEXT: v_cvt_f32_i32_e64 v3, s6
+; GFX950-NEXT: v_rcp_f32_e64 v1, v3
+; GFX950-NEXT: v_cvt_f32_i32_e64 v2, s2
+; GFX950-NEXT: v_mul_f32_e64 v1, v2, v1
+; GFX950-NEXT: v_trunc_f32_e64 v1, v1
+; GFX950-NEXT: v_fma_f32 v2, -v1, v3, v2
+; GFX950-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v3|
+; GFX950-NEXT: s_xor_b32 s2, s2, s6
+; GFX950-NEXT: s_mov_b32 s6, 30
+; GFX950-NEXT: s_ashr_i32 s2, s2, s6
+; GFX950-NEXT: s_or_b32 s2, s2, s3
+; GFX950-NEXT: s_mov_b32 s3, 0
+; GFX950-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX950-NEXT: s_cselect_b32 s2, s2, s3
+; GFX950-NEXT: v_cvt_i32_f32_e64 v1, v1
+; GFX950-NEXT: v_add_u32_e64 v1, v1, s2
+; GFX950-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX90A-LABEL: sdiv_i32_i16_fast_path:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_sext_i32_i16 s2, s2
+; GFX90A-NEXT: s_mov_b32 s3, 1
+; GFX90A-NEXT: s_or_b32 s6, s2, s3
+; GFX90A-NEXT: v_cvt_f32_i32_e64 v3, s6
+; GFX90A-NEXT: v_rcp_f32_e64 v1, v3
+; GFX90A-NEXT: v_cvt_f32_i32_e64 v2, s2
+; GFX90A-NEXT: v_mul_f32_e64 v1, v2, v1
+; GFX90A-NEXT: v_trunc_f32_e64 v1, v1
+; GFX90A-NEXT: v_mad_f32 v2, -v1, v3, v2
+; GFX90A-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v3|
+; GFX90A-NEXT: s_xor_b32 s2, s2, s6
+; GFX90A-NEXT: s_mov_b32 s6, 30
+; GFX90A-NEXT: s_ashr_i32 s2, s2, s6
+; GFX90A-NEXT: s_or_b32 s2, s2, s3
+; GFX90A-NEXT: s_mov_b32 s3, 0
+; GFX90A-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX90A-NEXT: s_cselect_b32 s2, s2, s3
+; GFX90A-NEXT: v_cvt_i32_f32_e64 v1, v1
+; GFX90A-NEXT: v_add_u32_e64 v1, v1, s2
+; GFX90A-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX90A-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90A-NEXT: s_endpgm
+ %trunc_i16 = trunc i32 %input to i16
+ %dividend = sext i16 %trunc_i16 to i32
+ %divisor = or i32 %dividend, 1
+ %result = sdiv i32 %dividend, %divisor
+ store i32 %result, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @urem_i32_i16_no_fast_path(ptr addrspace(1) %out, i32 %input) {
+; GFX950-LABEL: urem_i32_i16_no_fast_path:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_sext_i32_i16 s2, s2
+; GFX950-NEXT: s_mov_b32 s3, 1
+; GFX950-NEXT: s_or_b32 s4, s2, s3
+; GFX950-NEXT: s_mov_b32 s3, 0
+; GFX950-NEXT: s_sub_i32 s3, s3, s4
+; GFX950-NEXT: v_cvt_f32_u32_e32 v1, s4
+; GFX950-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX950-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_readfirstlane_b32 s5, v1
+; GFX950-NEXT: s_mul_i32 s5, s3, s5
+; GFX950-NEXT: v_readfirstlane_b32 s3, v1
+; GFX950-NEXT: s_mul_hi_u32 s5, s3, s5
+; GFX950-NEXT: v_readfirstlane_b32 s3, v1
+; GFX950-NEXT: s_add_i32 s3, s3, s5
+; GFX950-NEXT: s_mul_hi_u32 s3, s2, s3
+; GFX950-NEXT: s_mul_i32 s3, s3, s4
+; GFX950-NEXT: s_sub_i32 s3, s2, s3
+; GFX950-NEXT: s_sub_i32 s2, s3, s4
+; GFX950-NEXT: s_cmp_ge_u32 s3, s4
+; GFX950-NEXT: s_cselect_b32 s3, s2, s3
+; GFX950-NEXT: s_sub_i32 s2, s3, s4
+; GFX950-NEXT: s_cmp_ge_u32 s3, s4
+; GFX950-NEXT: s_cselect_b32 s2, s2, s3
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX90A-LABEL: urem_i32_i16_no_fast_path:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_sext_i32_i16 s2, s2
+; GFX90A-NEXT: s_mov_b32 s3, 1
+; GFX90A-NEXT: s_or_b32 s4, s2, s3
+; GFX90A-NEXT: s_mov_b32 s3, 0
+; GFX90A-NEXT: s_sub_i32 s3, s3, s4
+; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s4
+; GFX90A-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX90A-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX90A-NEXT: v_readfirstlane_b32 s5, v1
+; GFX90A-NEXT: s_mul_i32 s5, s3, s5
+; GFX90A-NEXT: v_readfirstlane_b32 s3, v1
+; GFX90A-NEXT: s_mul_hi_u32 s5, s3, s5
+; GFX90A-NEXT: v_readfirstlane_b32 s3, v1
+; GFX90A-NEXT: s_add_i32 s3, s3, s5
+; GFX90A-NEXT: s_mul_hi_u32 s3, s2, s3
+; GFX90A-NEXT: s_mul_i32 s3, s3, s4
+; GFX90A-NEXT: s_sub_i32 s3, s2, s3
+; GFX90A-NEXT: s_sub_i32 s2, s3, s4
+; GFX90A-NEXT: s_cmp_ge_u32 s3, s4
+; GFX90A-NEXT: s_cselect_b32 s3, s2, s3
+; GFX90A-NEXT: s_sub_i32 s2, s3, s4
+; GFX90A-NEXT: s_cmp_ge_u32 s3, s4
+; GFX90A-NEXT: s_cselect_b32 s2, s2, s3
+; GFX90A-NEXT: v_mov_b32_e32 v1, s2
+; GFX90A-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90A-NEXT: s_endpgm
+ %trunc_i16 = trunc i32 %input to i16
+ %dividend = sext i16 %trunc_i16 to i32
+ %divisor = or i32 %dividend, 1
+ %result = urem i32 %dividend, %divisor
+ store i32 %result, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @urem_i32_and_i24_fast_path(ptr addrspace(1) %out, i32 %input) {
+; GFX950-LABEL: urem_i32_and_i24_fast_path:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX950-NEXT: s_mov_b32 s2, 0xffffff
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_and_b32 s3, s3, s2
+; GFX950-NEXT: s_mov_b32 s5, 1
+; GFX950-NEXT: s_or_b32 s4, s3, s5
+; GFX950-NEXT: v_cvt_f32_u32_e64 v2, s3
+; GFX950-NEXT: v_cvt_f32_u32_e64 v3, s4
+; GFX950-NEXT: v_rcp_f32_e64 v1, v3
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_mul_f32_e64 v1, v2, v1
+; GFX950-NEXT: v_trunc_f32_e64 v1, v1
+; GFX950-NEXT: v_fma_f32 v2, -v1, v3, v2
+; GFX950-NEXT: v_cmp_ge_f32_e64 s[8:9], |v2|, |v3|
+; GFX950-NEXT: s_mov_b32 s6, 0
+; GFX950-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX950-NEXT: s_cselect_b32 s5, s5, s6
+; GFX950-NEXT: v_cvt_u32_f32_e64 v1, v1
+; GFX950-NEXT: v_add_u32_e64 v1, v1, s5
+; GFX950-NEXT: v_mul_lo_u32 v1, v1, s4
+; GFX950-NEXT: v_sub_u32_e64 v1, s3, v1
+; GFX950-NEXT: v_and_b32_e64 v1, v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX90A-LABEL: urem_i32_and_i24_fast_path:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX90A-NEXT: s_mov_b32 s2, 0xffffff
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_and_b32 s3, s3, s2
+; GFX90A-NEXT: s_mov_b32 s5, 1
+; GFX90A-NEXT: s_or_b32 s4, s3, s5
+; GFX90A-NEXT: v_cvt_f32_u32_e64 v2, s3
+; GFX90A-NEXT: v_cvt_f32_u32_e64 v3, s4
+; GFX90A-NEXT: v_rcp_f32_e64 v1, v3
+; GFX90A-NEXT: v_mul_f32_e64 v1, v2, v1
+; GFX90A-NEXT: v_trunc_f32_e64 v1, v1
+; GFX90A-NEXT: v_mad_f32 v2, -v1, v3, v2
+; GFX90A-NEXT: v_cmp_ge_f32_e64 s[8:9], |v2|, |v3|
+; GFX90A-NEXT: s_mov_b32 s6, 0
+; GFX90A-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX90A-NEXT: s_cselect_b32 s5, s5, s6
+; GFX90A-NEXT: v_cvt_u32_f32_e64 v1, v1
+; GFX90A-NEXT: v_add_u32_e64 v1, v1, s5
+; GFX90A-NEXT: v_mul_lo_u32 v1, v1, s4
+; GFX90A-NEXT: v_sub_u32_e64 v1, s3, v1
+; GFX90A-NEXT: v_and_b32_e64 v1, v1, s2
+; GFX90A-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90A-NEXT: s_endpgm
+ %dividend = and i32 %input, u0xffffff
+ %divisor = or i32 %dividend, 1
+ %result = urem i32 %dividend, %divisor
+ store i32 %result, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @srem_i32_i16_fast_path(ptr addrspace(1) %out, i32 %input) {
+; GFX950-LABEL: srem_i32_i16_fast_path:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_sext_i32_i16 s2, s2
+; GFX950-NEXT: s_mov_b32 s5, 1
+; GFX950-NEXT: s_or_b32 s3, s2, s5
+; GFX950-NEXT: v_cvt_f32_i32_e64 v3, s3
+; GFX950-NEXT: v_rcp_f32_e64 v1, v3
+; GFX950-NEXT: v_cvt_f32_i32_e64 v2, s2
+; GFX950-NEXT: v_mul_f32_e64 v1, v2, v1
+; GFX950-NEXT: v_trunc_f32_e64 v1, v1
+; GFX950-NEXT: v_fma_f32 v2, -v1, v3, v2
+; GFX950-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v3|
+; GFX950-NEXT: s_xor_b32 s4, s2, s3
+; GFX950-NEXT: s_mov_b32 s8, 30
+; GFX950-NEXT: s_ashr_i32 s4, s4, s8
+; GFX950-NEXT: s_or_b32 s4, s4, s5
+; GFX950-NEXT: s_mov_b32 s5, 0
+; GFX950-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX950-NEXT: s_cselect_b32 s4, s4, s5
+; GFX950-NEXT: v_cvt_i32_f32_e64 v1, v1
+; GFX950-NEXT: v_add_u32_e64 v1, v1, s4
+; GFX950-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX950-NEXT: v_sub_u32_e64 v1, s2, v1
+; GFX950-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX90A-LABEL: srem_i32_i16_fast_path:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_sext_i32_i16 s2, s2
+; GFX90A-NEXT: s_mov_b32 s5, 1
+; GFX90A-NEXT: s_or_b32 s3, s2, s5
+; GFX90A-NEXT: v_cvt_f32_i32_e64 v3, s3
+; GFX90A-NEXT: v_rcp_f32_e64 v1, v3
+; GFX90A-NEXT: v_cvt_f32_i32_e64 v2, s2
+; GFX90A-NEXT: v_mul_f32_e64 v1, v2, v1
+; GFX90A-NEXT: v_trunc_f32_e64 v1, v1
+; GFX90A-NEXT: v_mad_f32 v2, -v1, v3, v2
+; GFX90A-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v3|
+; GFX90A-NEXT: s_xor_b32 s4, s2, s3
+; GFX90A-NEXT: s_mov_b32 s8, 30
+; GFX90A-NEXT: s_ashr_i32 s4, s4, s8
+; GFX90A-NEXT: s_or_b32 s4, s4, s5
+; GFX90A-NEXT: s_mov_b32 s5, 0
+; GFX90A-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX90A-NEXT: s_cselect_b32 s4, s4, s5
+; GFX90A-NEXT: v_cvt_i32_f32_e64 v1, v1
+; GFX90A-NEXT: v_add_u32_e64 v1, v1, s4
+; GFX90A-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX90A-NEXT: v_sub_u32_e64 v1, s2, v1
+; GFX90A-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX90A-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90A-NEXT: s_endpgm
+ %trunc_i16 = trunc i32 %input to i16
+ %dividend = sext i16 %trunc_i16 to i32
+ %divisor = or i32 %dividend, 1
+ %result = srem i32 %dividend, %divisor
+ store i32 %result, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @srem_i32_i16_no_fast_path(ptr addrspace(1) %out, i32 %input) {
+; GFX950-LABEL: srem_i32_i16_no_fast_path:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX950-NEXT: v_mov_b32_e32 v0, 0
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: s_load_dword s4, s[4:5], 0x2c
+; GFX950-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-NEXT: s_mov_b32 s2, s4
+; GFX950-NEXT: s_sext_i32_i16 s2, s2
+; GFX950-NEXT: s_mov_b32 s6, 0
+; GFX950-NEXT: s_cmp_lt_i32 s4, s6
+; GFX950-NEXT: s_mov_b32 s3, -1
+; GFX950-NEXT: s_cselect_b32 s5, s3, s6
+; GFX950-NEXT: s_add_i32 s4, s4, s5
+; GFX950-NEXT: s_xor_b32 s5, s4, s5
+; GFX950-NEXT: s_sub_i32 s4, s6, s5
+; GFX950-NEXT: v_cvt_f32_u32_e32 v1, s5
+; GFX950-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX950-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_readfirstlane_b32 s7, v1
+; GFX950-NEXT: s_mul_i32 s7, s4, s7
+; GFX950-NEXT: v_readfirstlane_b32 s4, v1
+; GFX950-NEXT: s_mul_hi_u32 s7, s4, s7
+; GFX950-NEXT: v_readfirstlane_b32 s4, v1
+; GFX950-NEXT: s_add_i32 s4, s4, s7
+; GFX950-NEXT: s_cmp_lt_i32 s2, s6
+; GFX950-NEXT: s_cselect_b32 s3, s3, s6
+; GFX950-NEXT: s_add_i32 s2, s2, s3
+; GFX950-NEXT: s_xor_b32 s2, s2, s3
+; GFX950-NEXT: s_mul_hi_u32 s4, s2, s4
+; GFX950-NEXT: s_mul_i32 s4, s4, s5
+; GFX950-NEXT: s_sub_i32 s4, s2, s4
+; GFX950-NEXT: s_sub_i32 s2, s4, s5
+; GFX950-NEXT: s_cmp_ge_u32 s4, s5
+; GFX950-NEXT: s_cselect_b32 s4, s2, s4
+; GFX950-NEXT: s_sub_i32 s2, s4, s5
+; GFX950-NEXT: s_cmp_ge_u32 s4, s5
+; GFX950-NEXT: s_cselect_b32 s2, s2, s4
+; GFX950-NEXT: s_xor_b32 s2, s2, s3
+; GFX950-NEXT: s_sub_i32 s2, s2, s3
+; GFX950-NEXT: v_mov_b32_e32 v1, s2
+; GFX950-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX950-NEXT: s_endpgm
+;
+; GFX90A-LABEL: srem_i32_i16_no_fast_path:
+; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-NEXT: s_nop 0
+; GFX90A-NEXT: s_load_dword s4, s[4:5], 0x2c
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_mov_b32 s2, s4
+; GFX90A-NEXT: s_sext_i32_i16 s2, s2
+; GFX90A-NEXT: s_mov_b32 s6, 0
+; GFX90A-NEXT: s_cmp_lt_i32 s4, s6
+; GFX90A-NEXT: s_mov_b32 s3, -1
+; GFX90A-NEXT: s_cselect_b32 s5, s3, s6
+; GFX90A-NEXT: s_add_i32 s4, s4, s5
+; GFX90A-NEXT: s_xor_b32 s5, s4, s5
+; GFX90A-NEXT: s_sub_i32 s4, s6, s5
+; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s5
+; GFX90A-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX90A-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX90A-NEXT: v_readfirstlane_b32 s7, v1
+; GFX90A-NEXT: s_mul_i32 s7, s4, s7
+; GFX90A-NEXT: v_readfirstlane_b32 s4, v1
+; GFX90A-NEXT: s_mul_hi_u32 s7, s4, s7
+; GFX90A-NEXT: v_readfirstlane_b32 s4, v1
+; GFX90A-NEXT: s_add_i32 s4, s4, s7
+; GFX90A-NEXT: s_cmp_lt_i32 s2, s6
+; GFX90A-NEXT: s_cselect_b32 s3, s3, s6
+; GFX90A-NEXT: s_add_i32 s2, s2, s3
+; GFX90A-NEXT: s_xor_b32 s2, s2, s3
+; GFX90A-NEXT: s_mul_hi_u32 s4, s2, s4
+; GFX90A-NEXT: s_mul_i32 s4, s4, s5
+; GFX90A-NEXT: s_sub_i32 s4, s2, s4
+; GFX90A-NEXT: s_sub_i32 s2, s4, s5
+; GFX90A-NEXT: s_cmp_ge_u32 s4, s5
+; GFX90A-NEXT: s_cselect_b32 s4, s2, s4
+; GFX90A-NEXT: s_sub_i32 s2, s4, s5
+; GFX90A-NEXT: s_cmp_ge_u32 s4, s5
+; GFX90A-NEXT: s_cselect_b32 s2, s2, s4
+; GFX90A-NEXT: s_xor_b32 s2, s2, s3
+; GFX90A-NEXT: s_sub_i32 s2, s2, s3
+; GFX90A-NEXT: v_mov_b32_e32 v1, s2
+; GFX90A-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90A-NEXT: s_endpgm
+ %trunc_i16 = trunc i32 %input to i16
+ %dividend = sext i16 %trunc_i16 to i32
+ %result = srem i32 %dividend, %input
+ store i32 %result, ptr addrspace(1) %out, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index c0918dd78be5f..50b863f974138 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -2031,7 +2031,7 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 3 @6
-; EG-NEXT: ALU 23, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 20, @15, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@@ -2045,28 +2045,25 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; EG-NEXT: ALU clause starting at 15:
; EG-NEXT: LSHL * T0.W, T1.X, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: OR_INT * T0.W, T0.X, PV.W,
-; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,
-; EG-NEXT: RECIP_UINT * T0.X, PV.W,
-; EG-NEXT: MULLO_INT * T0.Y, PV.W, PS,
-; EG-NEXT: LSHL T1.W, T3.X, literal.x,
-; EG-NEXT: MULHI * T0.Y, T0.X, PS,
+; EG-NEXT: OR_INT T0.W, T0.X, PV.W,
+; EG-NEXT: LSHL * T1.W, T3.X, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: ADD_INT T2.W, T0.X, PS,
-; EG-NEXT: OR_INT * T1.W, T2.X, PV.W,
-; EG-NEXT: MULHI * T0.X, PS, PV.W,
-; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,
-; EG-NEXT: SUB_INT * T1.W, T1.W, PS,
-; EG-NEXT: ADD_INT T0.Z, T0.X, 1,
-; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
-; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,
-; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,
-; EG-NEXT: ADD_INT T3.W, PS, 1,
-; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,
-; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
-; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: UINT_TO_FLT * T0.X, PV.W,
+; EG-NEXT: OR_INT T0.W, T2.X, T1.W,
+; EG-NEXT: RECIP_IEEE * T0.Y, PS,
+; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,
+; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Y,
+; EG-NEXT: TRUNC * T0.W, PV.W,
+; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.X, T0.Z,
+; EG-NEXT: TRUNC * T0.W, PV.W,
+; EG-NEXT: SETGE * T1.W, |PV.W|, T0.X,
+; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,
+; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,
+; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
+; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 16777215(2.350989e-38), 2(2.802597e-45)
%den_ptr = getelementptr i24, ptr addrspace(1) %in, i24 1
%num = load i24, ptr addrspace(1) %in
%den = load i24, ptr addrspace(1) %den_ptr
diff --git a/llvm/test/CodeGen/AMDGPU/udivrem24.ll b/llvm/test/CodeGen/AMDGPU/udivrem24.ll
index 4d9ece813c402..a075418b3bd91 100644
--- a/llvm/test/CodeGen/AMDGPU/udivrem24.ll
+++ b/llvm/test/CodeGen/AMDGPU/udivrem24.ll
@@ -660,7 +660,7 @@ define amdgpu_kernel void @udiv24_i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
-; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 18, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@@ -671,26 +671,23 @@ define amdgpu_kernel void @udiv24_i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,
; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)
-; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,
-; EG-NEXT: RECIP_UINT * T0.Y, PV.W,
-; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,
-; EG-NEXT: MULHI * T0.Z, T0.Y, PS,
-; EG-NEXT: ADD_INT T1.W, T0.Y, PS,
-; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
+; EG-NEXT: UINT_TO_FLT * T0.Y, PV.W,
+; EG-NEXT: AND_INT T0.W, T0.X, literal.x,
+; EG-NEXT: RECIP_IEEE * T0.X, PS,
; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)
-; EG-NEXT: MULHI * T0.X, PS, PV.W,
-; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,
-; EG-NEXT: SUB_INT * T1.W, T2.W, PS,
-; EG-NEXT: ADD_INT T0.Z, T0.X, 1,
-; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
-; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,
-; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,
-; EG-NEXT: ADD_INT T3.W, PS, 1,
-; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,
-; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
-; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,
+; EG-NEXT: MUL_IEEE * T0.W, PS, T0.X,
+; EG-NEXT: TRUNC * T0.W, PV.W,
+; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.Z,
+; EG-NEXT: TRUNC * T0.W, PV.W,
+; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,
+; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,
+; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,
+; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
+; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 16777215(2.350989e-38), 2(2.802597e-45)
%den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
%num = load i32, ptr addrspace(1) %in, align 4
%den = load i32, ptr addrspace(1) %den_ptr, align 4
@@ -754,7 +751,7 @@ define amdgpu_kernel void @no_udiv24_u23_u24_i32(ptr addrspace(1) %out, ptr addr
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
-; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 18, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@@ -765,26 +762,23 @@ define amdgpu_kernel void @no_udiv24_u23_u24_i32(ptr addrspace(1) %out, ptr addr
; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,
; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)
-; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,
-; EG-NEXT: RECIP_UINT * T0.Y, PV.W,
-; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,
-; EG-NEXT: MULHI * T0.Z, T0.Y, PS,
-; EG-NEXT: ADD_INT T1.W, T0.Y, PS,
-; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
+; EG-NEXT: UINT_TO_FLT * T0.Y, PV.W,
+; EG-NEXT: AND_INT T0.W, T0.X, literal.x,
+; EG-NEXT: RECIP_IEEE * T0.X, PS,
; EG-NEXT: 8388607(1.175494e-38), 0(0.000000e+00)
-; EG-NEXT: MULHI * T0.X, PS, PV.W,
-; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,
-; EG-NEXT: SUB_INT * T1.W, T2.W, PS,
-; EG-NEXT: ADD_INT T0.Z, T0.X, 1,
-; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
-; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,
-; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,
-; EG-NEXT: ADD_INT T3.W, PS, 1,
-; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,
-; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
-; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,
+; EG-NEXT: MUL_IEEE * T0.W, PS, T0.X,
+; EG-NEXT: TRUNC * T0.W, PV.W,
+; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.Z,
+; EG-NEXT: TRUNC * T0.W, PV.W,
+; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,
+; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,
+; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,
+; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
+; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 16777215(2.350989e-38), 2(2.802597e-45)
%den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
%num = load i32, ptr addrspace(1) %in, align 4
%den = load i32, ptr addrspace(1) %den_ptr, align 4
@@ -848,7 +842,7 @@ define amdgpu_kernel void @no_udiv24_u24_u23_i32(ptr addrspace(1) %out, ptr addr
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
-; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 18, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@@ -859,26 +853,23 @@ define amdgpu_kernel void @no_udiv24_u24_u23_i32(ptr addrspace(1) %out, ptr addr
; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,
; EG-NEXT: 8388607(1.175494e-38), 0(0.000000e+00)
-; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,
-; EG-NEXT: RECIP_UINT * T0.Y, PV.W,
-; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,
-; EG-NEXT: MULHI * T0.Z, T0.Y, PS,
-; EG-NEXT: ADD_INT T1.W, T0.Y, PS,
-; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
+; EG-NEXT: UINT_TO_FLT * T0.Y, PV.W,
+; EG-NEXT: AND_INT T0.W, T0.X, literal.x,
+; EG-NEXT: RECIP_IEEE * T0.X, PS,
; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)
-; EG-NEXT: MULHI * T0.X, PS, PV.W,
-; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,
-; EG-NEXT: SUB_INT * T1.W, T2.W, PS,
-; EG-NEXT: ADD_INT T0.Z, T0.X, 1,
-; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
-; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,
-; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,
-; EG-NEXT: ADD_INT T3.W, PS, 1,
-; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,
-; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
-; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,
+; EG-NEXT: MUL_IEEE * T0.W, PS, T0.X,
+; EG-NEXT: TRUNC * T0.W, PV.W,
+; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.Z,
+; EG-NEXT: TRUNC * T0.W, PV.W,
+; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,
+; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,
+; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,
+; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
+; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 16777215(2.350989e-38), 2(2.802597e-45)
%den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
%num = load i32, ptr addrspace(1) %in, align 4
%den = load i32, ptr addrspace(1) %den_ptr, align 4
@@ -1518,7 +1509,7 @@ define amdgpu_kernel void @urem24_i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
-; EG-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 20, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@@ -1529,24 +1520,25 @@ define amdgpu_kernel void @urem24_i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,
; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)
-; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,
-; EG-NEXT: RECIP_UINT * T0.Y, PV.W,
-; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,
-; EG-NEXT: MULHI * T0.Z, T0.Y, PS,
-; EG-NEXT: ADD_INT T1.W, T0.Y, PS,
-; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
+; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,
+; EG-NEXT: AND_INT T0.W, T0.X, literal.x,
+; EG-NEXT: RECIP_IEEE * T1.X, PS,
; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)
-; EG-NEXT: MULHI * T0.X, PS, PV.W,
-; EG-NEXT: MULLO_INT * T0.X, PS, T0.W,
-; EG-NEXT: SUB_INT * T1.W, T2.W, PS,
-; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
-; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT * T1.W, PV.W, T1.W, PS,
-; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,
-; EG-NEXT: SUB_INT * T0.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS,
-; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
-; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: UINT_TO_FLT * T0.W, PV.W,
+; EG-NEXT: MUL_IEEE * T1.W, PS, T1.X,
+; EG-NEXT: TRUNC * T1.W, PV.W,
+; EG-NEXT: MULADD_IEEE T0.W, -PV.W, T0.Z, T0.W,
+; EG-NEXT: TRUNC * T1.W, PV.W,
+; EG-NEXT: SETGE * T0.W, |PV.W|, T0.Z,
+; EG-NEXT: CNDE T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: FLT_TO_UINT * T0.Z, T1.W,
+; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
+; EG-NEXT: MULLO_INT * T0.Y, PV.W, T0.Y,
+; EG-NEXT: SUB_INT * T0.W, T0.X, PS,
+; EG-NEXT: AND_INT T0.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 16777215(2.350989e-38), 2(2.802597e-45)
%den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
%num = load i32, ptr addrspace(1) %in, align 4
%den = load i32, ptr addrspace(1) %den_ptr, align 4
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