[llvm] [TSan] Add dominance-based redundant instrumentation elimination (PR #169897)

[Alexey Paznikov via llvm-commits]

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@@ -670,16 +1254,27 @@ bool ThreadSanitizer::instrumentLoadOrStore(const InstructionInfo &II,
 static ConstantInt *createOrdering(IRBuilder<> *IRB, AtomicOrdering ord) {
   uint32_t v = 0;
   switch (ord) {
-    case AtomicOrdering::NotAtomic:
-      llvm_unreachable("unexpected atomic ordering!");
-    case AtomicOrdering::Unordered:              [[fallthrough]];
-    case AtomicOrdering::Monotonic:              v = 0; break;
-    // Not specified yet:
-    // case AtomicOrdering::Consume:                v = 1; break;
-    case AtomicOrdering::Acquire:                v = 2; break;
-    case AtomicOrdering::Release:                v = 3; break;
-    case AtomicOrdering::AcquireRelease:         v = 4; break;
-    case AtomicOrdering::SequentiallyConsistent: v = 5; break;
+  case AtomicOrdering::NotAtomic:
+    llvm_unreachable("unexpected atomic ordering!");
+  case AtomicOrdering::Unordered:
+    [[fallthrough]];
+  case AtomicOrdering::Monotonic:
+    v = 0;
+    break;
+  // Not specified yet:
+  // case AtomicOrdering::Consume:                v = 1; break;
+  case AtomicOrdering::Acquire:
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apaznikov wrote:

@vitalybuka Thank you for the review!
To address your feedback about decomposing the main change into smaller, obvious patches, I have performed a massive refactoring:

1. Removed Post-Dominance completely. This PR now strictly focuses on simple Dominance.
2. Removed path caching. The implementation is now much leaner and easier to verify.
3. Reverted all unrelated formatting changes (NFCs).
4. Moved the implementation details from the PR description directly into Doxygen comments above the class.

Note: Because the scope of the patch changed so drastically, I squashed the changes into a single clean commit and force-pushed. It should be much easier to review from scratch now.

Let me know if this simplified version looks better!

https://github.com/llvm/llvm-project/pull/169897