[llvm] [SelectionDAG] Pass dest and src alignments separately to memcpy and memmove lowering functions (PR #201119)
Ömer Sinan Ağacan via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 3 00:52:16 PDT 2026
https://github.com/osa1 updated https://github.com/llvm/llvm-project/pull/201119
>From 83169ec0020e80fe465470b0d7edcc2d22458112 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Mon, 1 Jun 2026 15:19:07 +0100
Subject: [PATCH 01/10] [SelectionDAG] Pass dst and src alignments separately
in memcpy and memove lowering functions
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 9 +-
.../llvm/CodeGen/SelectionDAGTargetInfo.h | 6 +-
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 100 +++++++++---------
.../SelectionDAG/SelectionDAGBuilder.cpp | 22 ++--
.../Target/AArch64/AArch64ISelLowering.cpp | 9 +-
.../AArch64/AArch64SelectionDAGInfo.cpp | 23 ++--
.../Target/AArch64/AArch64SelectionDAGInfo.h | 6 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 +
llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp | 7 +-
llvm/lib/Target/ARM/ARMSelectionDAGInfo.h | 2 +-
llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp | 13 ++-
llvm/lib/Target/BPF/BPFSelectionDAGInfo.h | 2 +-
.../Target/Hexagon/HexagonISelLowering.cpp | 12 ++-
.../Hexagon/HexagonSelectionDAGInfo.cpp | 5 +-
.../Target/Hexagon/HexagonSelectionDAGInfo.h | 2 +-
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 2 +-
.../LoongArch/LoongArchISelLowering.cpp | 2 +-
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 4 +-
llvm/lib/Target/Mips/MipsISelLowering.cpp | 6 +-
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
llvm/lib/Target/Sparc/SparcISelLowering.cpp | 11 +-
.../Target/SystemZ/SystemZISelLowering.cpp | 5 +-
.../WebAssembly/WebAssemblyISelLowering.cpp | 4 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 3 +-
25 files changed, 139 insertions(+), 130 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 8da46aa0e1411..0e4ee1aba75a3 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1334,8 +1334,9 @@ class SelectionDAG {
* \p OverrideTailCall is an optional parameter that can be used to override
* the tail call optimization decision. */
LLVM_ABI SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst,
- SDValue Src, SDValue Size, Align Alignment,
- bool isVol, bool AlwaysInline, const CallInst *CI,
+ SDValue Src, SDValue Size, Align DstAlign,
+ Align SrcAlign, bool isVol, bool AlwaysInline,
+ const CallInst *CI,
std::optional<bool> OverrideTailCall,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo,
@@ -1346,8 +1347,8 @@ class SelectionDAG {
* \p OverrideTailCall is an optional parameter that can be used to override
* the tail call optimization decision. */
LLVM_ABI SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
- SDValue Src, SDValue Size, Align Alignment,
- bool isVol, const CallInst *CI,
+ SDValue Src, SDValue Size, Align DstAlign,
+ Align SrcAlign, bool isVol, const CallInst *CI,
std::optional<bool> OverrideTailCall,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
index 8051d2e714072..f3775bc50c4dd 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
@@ -76,8 +76,8 @@ class LLVM_ABI SelectionDAGTargetInfo {
virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Op1,
SDValue Op2, SDValue Op3,
- Align Alignment, bool isVolatile,
- bool AlwaysInline,
+ Align DstAlign, Align SrcAlign,
+ bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const {
return SDValue();
@@ -91,7 +91,7 @@ class LLVM_ABI SelectionDAGTargetInfo {
/// lowering strategy should be used.
virtual SDValue EmitTargetCodeForMemmove(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1,
- SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile,
+ SDValue Op2, SDValue Op3, Align DstAlign, Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
return SDValue();
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 75d550801315b..f65f933d1e668 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9255,11 +9255,13 @@ static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
}
}
-static SDValue getMemcpyLoadsAndStores(
- SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo,
- const AAMDNodes &AAInfo, BatchAAResults *BatchAA) {
+static SDValue
+getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
+ SDValue Dst, SDValue Src, uint64_t Size, Align DstAlign,
+ Align SrcAlign, bool isVol, bool AlwaysInline,
+ MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo,
+ BatchAAResults *BatchAA) {
// Turn a memcpy of undef to nop.
// FIXME: We need to honor volatile even is Src is undef.
if (Src.isUndef())
@@ -9280,20 +9282,17 @@ static SDValue getMemcpyLoadsAndStores(
FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Dst);
if (FI && !MFI.isFixedObjectIndex(FI->getIndex()))
DstAlignCanChange = true;
- MaybeAlign SrcAlign = DAG.InferPtrAlign(Src);
- if (!SrcAlign || Alignment > *SrcAlign)
- SrcAlign = Alignment;
- assert(SrcAlign && "SrcAlign must be set");
+ SrcAlign = std::max(SrcAlign, DAG.InferPtrAlign(Src).valueOrOne());
ConstantDataArraySlice Slice;
// If marked as volatile, perform a copy even when marked as constant.
bool CopyFromConstant = !isVol && isMemSrcFromConstant(Src, Slice);
bool isZeroConstant = CopyFromConstant && Slice.Array == nullptr;
unsigned Limit = AlwaysInline ? ~0U : TLI.getMaxStoresPerMemcpy(OptSize);
const MemOp Op = isZeroConstant
- ? MemOp::Set(Size, DstAlignCanChange, Alignment,
+ ? MemOp::Set(Size, DstAlignCanChange, DstAlign,
/*IsZeroMemset*/ true, isVol)
- : MemOp::Copy(Size, DstAlignCanChange, Alignment,
- *SrcAlign, isVol, CopyFromConstant);
+ : MemOp::Copy(Size, DstAlignCanChange, DstAlign,
+ SrcAlign, isVol, CopyFromConstant);
if (!TLI.findOptimalMemOpLowering(
C, MemOps, Limit, Op, DstPtrInfo.getAddrSpace(),
SrcPtrInfo.getAddrSpace(), MF.getFunction().getAttributes(), nullptr))
@@ -9301,7 +9300,7 @@ static SDValue getMemcpyLoadsAndStores(
if (DstAlignCanChange) {
Type *Ty = MemOps[0].getTypeForEVT(C);
- Align NewAlign = DL.getABITypeAlign(Ty);
+ Align NewDstAlign = DL.getABITypeAlign(Ty);
// Don't promote to an alignment that would require dynamic stack
// realignment which may conflict with optimizations such as tail call
@@ -9309,13 +9308,13 @@ static SDValue getMemcpyLoadsAndStores(
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!TRI->hasStackRealignment(MF))
if (MaybeAlign StackAlign = DL.getStackAlignment())
- NewAlign = std::min(NewAlign, *StackAlign);
+ NewDstAlign = std::min(NewDstAlign, *StackAlign);
- if (NewAlign > Alignment) {
+ if (NewDstAlign > DstAlign) {
// Give the stack frame object a larger alignment if needed.
- if (MFI.getObjectAlign(FI->getIndex()) < NewAlign)
- MFI.setObjectAlignment(FI->getIndex(), NewAlign);
- Alignment = NewAlign;
+ if (MFI.getObjectAlign(FI->getIndex()) < NewDstAlign)
+ MFI.setObjectAlignment(FI->getIndex(), NewDstAlign);
+ DstAlign = NewDstAlign;
}
}
@@ -9370,7 +9369,7 @@ static SDValue getMemcpyLoadsAndStores(
Store = DAG.getStore(
Chain, dl, Value,
DAG.getObjectPtrOffset(dl, Dst, TypeSize::getFixed(DstOff)),
- DstPtrInfo.getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
+ DstPtrInfo.getWithOffset(DstOff), DstAlign, MMOFlags, NewAAInfo);
OutChains.push_back(Store);
}
}
@@ -9396,13 +9395,13 @@ static SDValue getMemcpyLoadsAndStores(
ISD::EXTLOAD, dl, NVT, Chain,
DAG.getObjectPtrOffset(dl, Src, TypeSize::getFixed(SrcOff)),
SrcPtrInfo.getWithOffset(SrcOff), VT,
- commonAlignment(*SrcAlign, SrcOff), SrcMMOFlags, NewAAInfo);
+ commonAlignment(SrcAlign, SrcOff), SrcMMOFlags, NewAAInfo);
OutLoadChains.push_back(Value.getValue(1));
Store = DAG.getTruncStore(
Chain, dl, Value,
DAG.getObjectPtrOffset(dl, Dst, TypeSize::getFixed(DstOff)),
- DstPtrInfo.getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
+ DstPtrInfo.getWithOffset(DstOff), VT, DstAlign, MMOFlags, NewAAInfo);
OutStoreChains.push_back(Store);
}
SrcOff += VTSize;
@@ -9458,7 +9457,7 @@ static SDValue getMemcpyLoadsAndStores(
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
- uint64_t Size, Align Alignment,
+ uint64_t Size, Align DstAlign, Align SrcAlign,
bool isVol, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo,
@@ -9481,21 +9480,18 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Dst);
if (FI && !MFI.isFixedObjectIndex(FI->getIndex()))
DstAlignCanChange = true;
- MaybeAlign SrcAlign = DAG.InferPtrAlign(Src);
- if (!SrcAlign || Alignment > *SrcAlign)
- SrcAlign = Alignment;
- assert(SrcAlign && "SrcAlign must be set");
+ SrcAlign = std::max(SrcAlign, DAG.InferPtrAlign(Src).valueOrOne());
unsigned Limit = AlwaysInline ? ~0U : TLI.getMaxStoresPerMemmove(OptSize);
if (!TLI.findOptimalMemOpLowering(
C, MemOps, Limit,
- MemOp::Copy(Size, DstAlignCanChange, Alignment, *SrcAlign, isVol),
+ MemOp::Copy(Size, DstAlignCanChange, DstAlign, SrcAlign, isVol),
DstPtrInfo.getAddrSpace(), SrcPtrInfo.getAddrSpace(),
MF.getFunction().getAttributes(), nullptr))
return SDValue();
if (DstAlignCanChange) {
Type *Ty = MemOps[0].getTypeForEVT(C);
- Align NewAlign = DL.getABITypeAlign(Ty);
+ Align NewDstAlign = DL.getABITypeAlign(Ty);
// Don't promote to an alignment that would require dynamic stack
// realignment which may conflict with optimizations such as tail call
@@ -9503,13 +9499,13 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!TRI->hasStackRealignment(MF))
if (MaybeAlign StackAlign = DL.getStackAlignment())
- NewAlign = std::min(NewAlign, *StackAlign);
+ NewDstAlign = std::min(NewDstAlign, *StackAlign);
- if (NewAlign > Alignment) {
+ if (NewDstAlign > DstAlign) {
// Give the stack frame object a larger alignment if needed.
- if (MFI.getObjectAlign(FI->getIndex()) < NewAlign)
- MFI.setObjectAlignment(FI->getIndex(), NewAlign);
- Alignment = NewAlign;
+ if (MFI.getObjectAlign(FI->getIndex()) < NewDstAlign)
+ MFI.setObjectAlignment(FI->getIndex(), NewDstAlign);
+ DstAlign = NewDstAlign;
}
}
@@ -9540,7 +9536,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
// Calculate the actual alignment at the current offset. The alignment at
// SrcOff may be lower than the base alignment, especially when using
// overlapping loads.
- Align SrcAlignAtOffset = commonAlignment(*SrcAlign, SrcOff);
+ Align SrcAlignAtOffset = commonAlignment(SrcAlign, SrcOff);
if (IsOverlapping) {
// Verify that the target allows misaligned memory accesses at the
// adjusted offset when using overlapping loads.
@@ -9588,7 +9584,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
// Calculate the actual alignment at the current offset. The alignment at
// DstOff may be lower than the base alignment, especially when using
// overlapping stores.
- Align DstAlignAtOffset = commonAlignment(Alignment, DstOff);
+ Align DstAlignAtOffset = commonAlignment(DstAlign, DstOff);
if (IsOverlapping) {
// Verify that the target allows misaligned memory accesses at the
// adjusted offset when using overlapping stores.
@@ -9887,10 +9883,10 @@ std::pair<SDValue, SDValue> SelectionDAG::getStrlen(SDValue Chain,
SDValue SelectionDAG::getMemcpy(
SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size,
- Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI,
- std::optional<bool> OverrideTailCall, MachinePointerInfo DstPtrInfo,
- MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo,
- BatchAAResults *BatchAA) {
+ Align DstAlign, Align SrcAlign, bool isVol, bool AlwaysInline,
+ const CallInst *CI, std::optional<bool> OverrideTailCall,
+ MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo,
+ const AAMDNodes &AAInfo, BatchAAResults *BatchAA) {
// Check to see if we should lower the memcpy to loads and stores first.
// For cases within the target-specified limits, this is the best choice.
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -9900,8 +9896,8 @@ SDValue SelectionDAG::getMemcpy(
return Chain;
SDValue Result = getMemcpyLoadsAndStores(
- *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment,
- isVol, false, DstPtrInfo, SrcPtrInfo, AAInfo, BatchAA);
+ *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), DstAlign,
+ SrcAlign, isVol, false, DstPtrInfo, SrcPtrInfo, AAInfo, BatchAA);
if (Result.getNode())
return Result;
}
@@ -9910,8 +9906,8 @@ SDValue SelectionDAG::getMemcpy(
// code. If the target chooses to do this, this is the next best.
if (TSI) {
SDValue Result = TSI->EmitTargetCodeForMemcpy(
- *this, dl, Chain, Dst, Src, Size, Alignment, isVol, AlwaysInline,
- DstPtrInfo, SrcPtrInfo);
+ *this, dl, Chain, Dst, Src, Size, DstAlign, SrcAlign, isVol,
+ AlwaysInline, DstPtrInfo, SrcPtrInfo);
if (Result.getNode())
return Result;
}
@@ -9921,8 +9917,8 @@ SDValue SelectionDAG::getMemcpy(
if (AlwaysInline) {
assert(ConstantSize && "AlwaysInline requires a constant size!");
return getMemcpyLoadsAndStores(
- *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment,
- isVol, true, DstPtrInfo, SrcPtrInfo, AAInfo, BatchAA);
+ *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), DstAlign,
+ SrcAlign, isVol, true, DstPtrInfo, SrcPtrInfo, AAInfo, BatchAA);
}
checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace());
@@ -10001,8 +9997,8 @@ SDValue SelectionDAG::getAtomicMemcpy(SDValue Chain, const SDLoc &dl,
}
SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
- SDValue Src, SDValue Size, Align Alignment,
- bool isVol, const CallInst *CI,
+ SDValue Src, SDValue Size, Align DstAlign,
+ Align SrcAlign, bool isVol, const CallInst *CI,
std::optional<bool> OverrideTailCall,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo,
@@ -10017,8 +10013,8 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
return Chain;
SDValue Result = getMemmoveLoadsAndStores(
- *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment,
- isVol, false, DstPtrInfo, SrcPtrInfo, AAInfo);
+ *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), DstAlign,
+ SrcAlign, isVol, false, DstPtrInfo, SrcPtrInfo, AAInfo);
if (Result.getNode())
return Result;
}
@@ -10026,9 +10022,9 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
// Then check to see if we should lower the memmove with target-specific
// code. If the target chooses to do this, this is the next best.
if (TSI) {
- SDValue Result =
- TSI->EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size,
- Alignment, isVol, DstPtrInfo, SrcPtrInfo);
+ SDValue Result = TSI->EmitTargetCodeForMemmove(
+ *this, dl, Chain, Dst, Src, Size, DstAlign, SrcAlign, isVol, DstPtrInfo,
+ SrcPtrInfo);
if (Result.getNode())
return Result;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index eca5bb1598ae0..d92cde9b1cc1a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6732,13 +6732,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
// @llvm.memcpy.inline defines 0 and 1 to both mean no alignment.
Align DstAlign = MCI.getDestAlign().valueOrOne();
Align SrcAlign = MCI.getSourceAlign().valueOrOne();
- Align Alignment = std::min(DstAlign, SrcAlign);
bool isVol = MCI.isVolatile();
// FIXME: Support passing different dest/src alignments to the memcpy DAG
// node.
SDValue Root = isVol ? getRoot() : getMemoryRoot();
- SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, Alignment, isVol,
- MCI.isForceInlined(), &I, std::nullopt,
+ SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, DstAlign, SrcAlign,
+ isVol, MCI.isForceInlined(), &I, std::nullopt,
MachinePointerInfo(I.getArgOperand(0)),
MachinePointerInfo(I.getArgOperand(1)),
I.getAAMetadata(), BatchAA);
@@ -6771,16 +6770,15 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
// @llvm.memmove defines 0 and 1 to both mean no alignment.
Align DstAlign = MMI.getDestAlign().valueOrOne();
Align SrcAlign = MMI.getSourceAlign().valueOrOne();
- Align Alignment = std::min(DstAlign, SrcAlign);
bool isVol = MMI.isVolatile();
// FIXME: Support passing different dest/src alignments to the memmove DAG
// node.
SDValue Root = isVol ? getRoot() : getMemoryRoot();
- SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, &I,
- /* OverrideTailCall */ std::nullopt,
- MachinePointerInfo(I.getArgOperand(0)),
- MachinePointerInfo(I.getArgOperand(1)),
- I.getAAMetadata(), BatchAA);
+ SDValue MM = DAG.getMemmove(
+ Root, sdl, Op1, Op2, Op3, DstAlign, SrcAlign, isVol, &I,
+ /* OverrideTailCall */ std::nullopt,
+ MachinePointerInfo(I.getArgOperand(0)),
+ MachinePointerInfo(I.getArgOperand(1)), I.getAAMetadata(), BatchAA);
updateDAGForMaybeTailCall(MM);
return;
}
@@ -9506,8 +9504,6 @@ bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
Align DstAlign = DAG.InferPtrAlign(Dst).valueOrOne();
Align SrcAlign = DAG.InferPtrAlign(Src).valueOrOne();
- // DAG::getMemcpy needs Alignment to be defined.
- Align Alignment = std::min(DstAlign, SrcAlign);
SDLoc sdl = getCurSDLoc();
@@ -9516,8 +9512,8 @@ bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
// the copied memory.
SDValue Root = getMemoryRoot();
SDValue MC = DAG.getMemcpy(
- Root, sdl, Dst, Src, Size, Alignment, false, false, /*CI=*/nullptr,
- std::nullopt, MachinePointerInfo(I.getArgOperand(0)),
+ Root, sdl, Dst, Src, Size, DstAlign, SrcAlign, false, false,
+ /*CI=*/nullptr, std::nullopt, MachinePointerInfo(I.getArgOperand(0)),
MachinePointerInfo(I.getArgOperand(1)), I.getAAMetadata());
assert(MC.getNode() != nullptr &&
"** memcpy should not be lowered as TailCall in mempcpy context **");
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 89466adf7d4f3..34e8959c3c51f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6468,8 +6468,8 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
const auto &SDI =
static_cast<const AArch64SelectionDAGInfo &>(DAG.getSelectionDAGInfo());
SDValue MS = SDI.EmitMOPS(AArch64::MOPSMemorySetTaggingPseudo, DAG, DL,
- Chain, Dst, Val, Size, Alignment, IsVol,
- DstPtrInfo, MachinePointerInfo{});
+ Chain, Dst, Val, Size, Alignment, Alignment,
+ IsVol, DstPtrInfo, MachinePointerInfo{});
// MOPS_MEMSET_TAGGING has 3 results (DstWb, SizeWb, Chain) whereas the
// intrinsic has 2. So hide SizeWb using MERGE_VALUES. Otherwise
@@ -10374,6 +10374,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
SDValue Cpy = DAG.getMemcpy(
Chain, DL, DstAddr, Arg, SizeNode,
Outs[i].Flags.getNonZeroByValAlign(),
+ Outs[i].Flags.getNonZeroByValAlign(),
/*isVol = */ false, /*AlwaysInline = */ false,
/*CI=*/nullptr, std::nullopt, DstInfo, MachinePointerInfo());
@@ -13027,8 +13028,8 @@ SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1), Op.getOperand(2),
DAG.getConstant(VaListSize, DL, MVT::i32),
- Align(PtrSize), false, false, /*CI=*/nullptr,
- std::nullopt, MachinePointerInfo(DestSV),
+ Align(PtrSize), Align(PtrSize), false, false,
+ /*CI=*/nullptr, std::nullopt, MachinePointerInfo(DestSV),
MachinePointerInfo(SrcSV));
}
diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
index 336fc3d32887b..286e5638fc088 100644
--- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
@@ -121,8 +121,8 @@ void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
const SDLoc &DL, SDValue Chain,
SDValue Dst, SDValue SrcOrValue,
- SDValue Size, Align Alignment,
- bool isVolatile,
+ SDValue Size, Align DstAlign,
+ Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const {
@@ -140,7 +140,7 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
isVolatile ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
auto DstFlags = MachineMemOperand::MOStore | Vol;
auto *DstOp =
- MF.getMachineMemOperand(DstPtrInfo, DstFlags, MemSize, Alignment);
+ MF.getMachineMemOperand(DstPtrInfo, DstFlags, MemSize, DstAlign);
if (IsSet) {
// Extend value to i64, if required.
@@ -158,7 +158,7 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
auto SrcFlags = MachineMemOperand::MOLoad | Vol;
auto *SrcOp =
- MF.getMachineMemOperand(SrcPtrInfo, SrcFlags, MemSize, Alignment);
+ MF.getMachineMemOperand(SrcPtrInfo, SrcFlags, MemSize, SrcAlign);
DAG.setNodeMemRefs(Node, {DstOp, SrcOp});
return SDValue(Node, 3);
}
@@ -223,14 +223,16 @@ SDValue AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(
SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo) const {
const AArch64Subtarget &STI =
DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
if (UseMOPS && STI.hasMOPS())
return EmitMOPS(AArch64::MOPSMemoryCopyPseudo, DAG, DL, Chain, Dst, Src,
- Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo);
+ Size, DstAlign, SrcAlign, isVolatile, DstPtrInfo,
+ SrcPtrInfo);
auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
SMEAttrs Attrs = AFI->getSMEFnAttrs();
@@ -249,7 +251,7 @@ SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemset(
if (UseMOPS && STI.hasMOPS())
return EmitMOPS(AArch64::MOPSMemorySetPseudo, DAG, dl, Chain, Dst, Src,
- Size, Alignment, isVolatile, DstPtrInfo,
+ Size, Alignment, Alignment, isVolatile, DstPtrInfo,
MachinePointerInfo{});
auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
@@ -262,14 +264,15 @@ SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemset(
SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemmove(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool isVolatile,
+ SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
const AArch64Subtarget &STI =
DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
if (UseMOPS && STI.hasMOPS())
return EmitMOPS(AArch64::MOPSMemoryMovePseudo, DAG, dl, Chain, Dst, Src,
- Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo);
+ Size, DstAlign, SrcAlign, isVolatile, DstPtrInfo,
+ SrcPtrInfo);
auto *AFI = DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
SMEAttrs Attrs = AFI->getSMEFnAttrs();
diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
index 656a58c1dc1bf..52448d34a0f99 100644
--- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
@@ -31,13 +31,13 @@ class AArch64SelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue EmitMOPS(unsigned Opcode, SelectionDAG &DAG, const SDLoc &DL,
SDValue Chain, SDValue Dst, SDValue SrcOrValue, SDValue Size,
- Align Alignment, bool isVolatile,
+ Align DstAlign, Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const;
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment,
+ SDValue Size, Align DstAlign, Align SrcAlign,
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
@@ -49,7 +49,7 @@ class AArch64SelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue
EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Size,
- Align Alignment, bool isVolatile,
+ Align DstAlign, Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 86f2479490c29..6c4ace4f6cd80 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4488,6 +4488,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
SDValue Cpy =
DAG.getMemcpy(Chain, DL, DstAddr, Arg, SizeNode,
+ Outs[i].Flags.getNonZeroByValAlign(),
Outs[i].Flags.getNonZeroByValAlign(),
/*isVol = */ false, /*AlwaysInline = */ true,
/*CI=*/nullptr, std::nullopt, DstInfo,
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
index 981264aac372d..ce12dc3138c5d 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
@@ -254,8 +254,9 @@ static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget,
SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo) const {
const ARMSubtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -372,7 +373,7 @@ SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(
SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemmove(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool isVolatile,
+ SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size,
Alignment.value(), RTLIB::MEMMOVE);
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
index 38d2a6555c1be..b0a01325a1840 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
@@ -103,7 +103,7 @@ class ARMSelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment,
+ SDValue Size, Align DstAlign, Align SrcAlign,
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
diff --git a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
index ba93c868c2c8b..54ed14a04f304 100644
--- a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
@@ -35,24 +35,27 @@ unsigned BPFSelectionDAGInfo::getCommonMaxStoresPerMemFunc() const {
SDValue BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo) const {
+ // TODO: Not sure which alignment to use below.
+
// Requires the copy size to be a constant.
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (!ConstantSize)
return SDValue();
// BPF::MEMCPY supports alignment up to 8 bytes.
- if (Alignment.value() > 8)
+ if (DstAlign.value() > 8)
return SDValue();
unsigned CopyLen = ConstantSize->getZExtValue();
- unsigned StoresNumEstimate = alignTo(CopyLen, Alignment) >> Log2(Alignment);
+ unsigned StoresNumEstimate = alignTo(CopyLen, DstAlign) >> Log2(DstAlign);
// Impose the same copy length limit as MaxStoresPerMemcpy.
if (StoresNumEstimate > getCommonMaxStoresPerMemFunc())
return SDValue();
return DAG.getNode(BPFISD::MEMCPY, dl, MVT::Other, Chain, Dst, Src,
DAG.getConstant(CopyLen, dl, MVT::i64),
- DAG.getConstant(Alignment.value(), dl, MVT::i64));
+ DAG.getConstant(DstAlign.value(), dl, MVT::i64));
}
diff --git a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.h b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.h
index eebea78435d16..2034461262ff5 100644
--- a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.h
+++ b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.h
@@ -26,7 +26,7 @@ class BPFSelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment,
+ SDValue Size, Align DstAlign, Align SrcAlign,
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 79c0c534e8872..ec3c30007341b 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -215,8 +215,9 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SDValue Chain, ISD::ArgFlagsTy Flags,
SelectionDAG &DAG, const SDLoc &dl) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
+ Align Align = Flags.getNonZeroByValAlign();
return DAG.getMemcpy(
- Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
+ Chain, dl, Dst, Src, SizeNode, Align, Align,
/*isVolatile=*/false, /*AlwaysInline=*/false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
}
@@ -1046,10 +1047,11 @@ HexagonTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
// Size of the va_list is 12 bytes as it has 3 pointers. Therefore,
// we need to memcopy 12 bytes from va_list to another similar list.
- return DAG.getMemcpy(
- Chain, DL, DestPtr, SrcPtr, DAG.getIntPtrConstant(12, DL), Align(4),
- /*isVolatile*/ false, false, /*CI=*/nullptr, std::nullopt,
- MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
+ return DAG.getMemcpy(Chain, DL, DestPtr, SrcPtr,
+ DAG.getIntPtrConstant(12, DL), Align(4), Align(4),
+ /*isVolatile*/ false, false, /*CI=*/nullptr,
+ std::nullopt, MachinePointerInfo(DestSV),
+ MachinePointerInfo(SrcSV));
}
SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
diff --git a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
index 1d1d433b761c3..99a433d9c6403 100644
--- a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
@@ -64,8 +64,9 @@ void HexagonSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
SDValue HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo) const {
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (AlwaysInline || Alignment < Align(4) || !ConstantSize)
return SDValue();
diff --git a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
index d1d5b0c7ac0ee..d5df3573a68c8 100644
--- a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
@@ -70,7 +70,7 @@ class HexagonSelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment,
+ SDValue Size, Align DstAlign, Align SrcAlign,
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index 631a8de035ac2..ff35d981d6291 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -629,7 +629,7 @@ SDValue LanaiTargetLowering::LowerCCCCallTo(
SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
- Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
+ Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, Alignment,
/*IsVolatile=*/false,
/*AlwaysInline=*/false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 561064b3e1090..968436d26a23b 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -9627,7 +9627,7 @@ LoongArchTargetLowering::LowerCall(CallLoweringInfo &CLI,
SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
SDValue SizeNode = DAG.getConstant(Size, DL, GRLenVT);
- Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
+ Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, Alignment,
/*IsVolatile=*/false,
/*AlwaysInline=*/false, /*CI=*/nullptr, std::nullopt,
MachinePointerInfo(), MachinePointerInfo());
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index d915969630966..5516c21685f05 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -685,8 +685,8 @@ SDValue MSP430TargetLowering::LowerCCCCallTo(
if (Flags.isByVal()) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
- MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
- Flags.getNonZeroByValAlign(),
+ Align Align = Flags.getNonZeroByValAlign();
+ MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, Align, Align,
/*isVolatile*/ false,
/*AlwaysInline=*/true,
/*CI=*/nullptr, std::nullopt,
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 298b525e48cff..e9a3120110ba1 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3873,7 +3873,7 @@ SDValue MipsTargetLowering::LowerFormalArguments(
assert(!VA.needsCustom() && "unexpected custom memory argument");
- // Only arguments pased on the stack should make it here.
+ // Only arguments pased on the stack should make it here.
assert(VA.isMemLoc());
// The stack pointer offset is relative to the caller stack frame.
@@ -4661,8 +4661,8 @@ void MipsTargetLowering::passByValArg(
SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
Chain = DAG.getMemcpy(
- Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy),
- Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false,
+ Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), Alignment,
+ Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
MemOpChains.push_back(Chain);
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 57ac8965aee7b..4b44dbdc8750b 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3780,7 +3780,7 @@ SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
// 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2),
DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8),
- false, true, /*CI=*/nullptr, std::nullopt,
+ Align(8), false, true, /*CI=*/nullptr, std::nullopt,
MachinePointerInfo(), MachinePointerInfo());
}
@@ -5194,8 +5194,9 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SDValue Chain, ISD::ArgFlagsTy Flags,
SelectionDAG &DAG, const SDLoc &dl) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
+ Align Align = Flags.getNonZeroByValAlign();
return DAG.getMemcpy(
- Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(), false, false,
+ Chain, dl, Dst, Src, SizeNode, Align, Align, false, false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
}
@@ -6451,7 +6452,7 @@ SDValue PPCTargetLowering::LowerCall_64SVR4(
ArgOffset += PtrByteSize;
continue;
}
- // Copy the object to parameter save area if it can not be entirely passed
+ // Copy the object to parameter save area if it can not be entirely passed
// by registers.
// FIXME: we only need to copy the parts which need to be passed in
// parameter save area. For the parts passed by registers, we don't need
@@ -7101,7 +7102,7 @@ static unsigned mapArgRegToOffsetAIX(unsigned Reg, const PPCFrameLowering *FL) {
//
// Low Memory +--------------------------------------------+
// SP +---> | Back chain | ---+
-// | +--------------------------------------------+ |
+// | +--------------------------------------------+ |
// | | Saved Condition Register | |
// | +--------------------------------------------+ |
// | | Saved Linkage Register | |
@@ -8135,7 +8136,7 @@ SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
return SDValue();
SDValue N1 = Op.getOperand(0);
- EVT SrcVT = N1.getValueType();
+ EVT SrcVT = N1.getValueType();
unsigned SrcSize = SrcVT.getSizeInBits();
if (SrcSize > 256 || !isPowerOf2_32(SrcVT.getVectorNumElements()) ||
!llvm::has_single_bit<uint32_t>(
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 19a13183dc8cb..df8adae631099 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -24898,7 +24898,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
- Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
+ Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, Alignment,
/*IsVolatile=*/false,
/*AlwaysInline=*/false, /*CI*/ nullptr, IsTailCall,
MachinePointerInfo(), MachinePointerInfo());
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 3d37517a65eda..4badb2f17bd98 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -884,11 +884,12 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
- Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment,
- false, // isVolatile,
- (Size <= 32), // AlwaysInline if size <= 32,
- /*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
- MachinePointerInfo());
+ Chain =
+ DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment, Alignment,
+ false, // isVolatile,
+ (Size <= 32), // AlwaysInline if size <= 32,
+ /*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
+ MachinePointerInfo());
ByValArgs.push_back(FIPtr);
}
else {
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 8723075d131b0..e56a449cd455d 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -4539,7 +4539,8 @@ SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
uint32_t Sz =
Subtarget.isTargetXPLINK64() ? getTargetMachine().getPointerSize(0) : 32;
return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(Sz, DL),
- Align(8), /*isVolatile*/ false, /*AlwaysInline*/ false,
+ Align(8), Align(8), /*isVolatile*/ false,
+ /*AlwaysInline*/ false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(DstSV),
MachinePointerInfo(SrcSV));
}
@@ -11472,4 +11473,4 @@ void SystemZTargetLowering::insertSSPDeclarations(
// Otherwise (in the global case), insert the appropriate global variable.
TargetLowering::insertSSPDeclarations(M, Libcalls);
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 81ea2d516c5bc..8cad41dc81d8f 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1392,8 +1392,8 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
SDValue SizeNode =
DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32);
SDValue FINode = DAG.getFrameIndex(FI, getPointerTy(Layout));
- Chain = DAG.getMemcpy(Chain, DL, FINode, OutVal, SizeNode,
- Out.Flags.getNonZeroByValAlign(),
+ Align Align = Out.Flags.getNonZeroByValAlign();
+ Chain = DAG.getMemcpy(Chain, DL, FINode, OutVal, SizeNode, Align, Align,
/*isVolatile*/ false, /*AlwaysInline=*/false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
MachinePointerInfo());
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6c5e682a41542..fdc2261b7be13 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -26870,11 +26870,12 @@ static SDValue LowerVACOPY(SDValue Op, const X86Subtarget &Subtarget,
const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
SDLoc DL(Op);
+ Align Alignment = Align(Subtarget.isTarget64BitLP64() ? 8 : 4);
return DAG.getMemcpy(
Chain, DL, DstPtr, SrcPtr,
DAG.getIntPtrConstant(Subtarget.isTarget64BitLP64() ? 24 : 16, DL),
- Align(Subtarget.isTarget64BitLP64() ? 8 : 4), /*isVolatile*/ false, false,
+ Alignment, Alignment, /*isVolatile*/ false, false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(DstSV),
MachinePointerInfo(SrcSV));
}
>From d9d06b53bfd8250026cb0c34982441a2b10d7025 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Tue, 2 Jun 2026 09:57:39 +0100
Subject: [PATCH 02/10] Update rest of the backends
---
llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp | 2 ++
llvm/lib/Target/ARM/ARMSelectionDAGInfo.h | 2 +-
llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp | 1 +
llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp | 4 ++--
llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h | 2 +-
llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp | 5 +++--
llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h | 2 +-
.../WebAssembly/WebAssemblySelectionDAGInfo.cpp | 9 +++++----
.../WebAssembly/WebAssemblySelectionDAGInfo.h | 6 +++---
llvm/lib/Target/X86/X86ISelLoweringCall.cpp | 4 ++--
llvm/lib/Target/X86/X86SelectionDAGInfo.cpp | 13 ++++++++-----
llvm/lib/Target/X86/X86SelectionDAGInfo.h | 2 +-
llvm/lib/Target/XCore/XCoreISelLowering.cpp | 6 +++---
llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp | 6 ++++--
llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h | 4 ++--
15 files changed, 39 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
index ce12dc3138c5d..a8274a839158a 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
@@ -257,6 +257,7 @@ SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(
SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
bool AlwaysInline, MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const {
+ Align Alignment = std::min(DstAlign, SrcAlign);
const ARMSubtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -375,6 +376,7 @@ SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemmove(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ Align Alignment = std::min(DstAlign, SrcAlign);
return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size,
Alignment.value(), RTLIB::MEMMOVE);
}
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
index b0a01325a1840..0ffad30ba7b8c 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
@@ -111,7 +111,7 @@ class ARMSelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue
EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Size,
- Align Alignment, bool isVolatile,
+ Align DstAlign, Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
diff --git a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
index 99a433d9c6403..8cccbd42188e3 100644
--- a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
@@ -67,6 +67,7 @@ SDValue HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(
SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
bool AlwaysInline, MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const {
+ Align Alignment = std::min(DstAlign, SrcAlign);
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (AlwaysInline || Alignment < Align(4) || !ConstantSize)
return SDValue();
diff --git a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
index 77e01c6dfe6e8..6ceda73d93b7f 100644
--- a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
@@ -24,8 +24,8 @@ LanaiSelectionDAGInfo::LanaiSelectionDAGInfo()
SDValue LanaiSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG & /*DAG*/, const SDLoc & /*dl*/, SDValue /*Chain*/,
- SDValue /*Dst*/, SDValue /*Src*/, SDValue Size, Align /*Alignment*/,
- bool /*isVolatile*/, bool /*AlwaysInline*/,
+ SDValue /*Dst*/, SDValue /*Src*/, SDValue Size, Align /*DstAlign*/,
+ Align /*SrcAlign*/, bool /*isVolatile*/, bool /*AlwaysInline*/,
MachinePointerInfo /*DstPtrInfo*/,
MachinePointerInfo /*SrcPtrInfo*/) const {
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
diff --git a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h
index 41549082d6fcc..58413d65f096d 100644
--- a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h
@@ -27,7 +27,7 @@ class LanaiSelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment,
+ SDValue Size, Align DstAlign, Align SrcAlign,
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
diff --git a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
index eec37a9df386f..fec23fef51383 100644
--- a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
@@ -75,8 +75,9 @@ static SDValue emitMemMemReg(SelectionDAG &DAG, const SDLoc &DL, unsigned Op,
SDValue SystemZSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool IsVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SDValue Size, Align DstAlign, Align SrcAlign, bool IsVolatile,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo) const {
if (IsVolatile)
return SDValue();
diff --git a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
index 8e6da4fe8b0ae..57364dc0760cd 100644
--- a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
@@ -46,7 +46,7 @@ class SystemZSelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &DL,
SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment,
+ SDValue Size, Align DstAlign, Align SrcAlign,
bool IsVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
index cf5cc41ea565b..2a1555afda896 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
@@ -40,8 +40,9 @@ WebAssemblySelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool IsVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SDValue Size, Align DstAlign, Align SrcAlign, bool IsVolatile,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo) const {
auto &ST = DAG.getMachineFunction().getSubtarget<WebAssemblySubtarget>();
if (!ST.hasBulkMemoryOpt())
return SDValue();
@@ -59,10 +60,10 @@ SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(
SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemmove(
SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2,
- SDValue Op3, Align Alignment, bool IsVolatile,
+ SDValue Op3, Align DstAlign, Align SrcAlign, bool IsVolatile,
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3,
- Alignment, IsVolatile, false,
+ DstAlign, SrcAlign, IsVolatile, false,
DstPtrInfo, SrcPtrInfo);
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h
index 8775f4946d88d..d1823e025a22e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h
@@ -40,14 +40,14 @@ class WebAssemblySelectionDAGInfo final : public SelectionDAGGenTargetInfo {
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Op1, SDValue Op2,
- SDValue Op3, Align Alignment, bool isVolatile,
- bool AlwaysInline,
+ SDValue Op3, Align DstAlign, Align SrcAlign,
+ bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
SDValue
EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
SDValue Op1, SDValue Op2, SDValue Op3,
- Align Alignment, bool isVolatile,
+ Align DstAlign, Align SrcAlign, bool isVolatile,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &DL,
diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
index 079f7687bdb0b..33d0a37a7636d 100644
--- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
@@ -1239,9 +1239,9 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SDValue Chain, ISD::ArgFlagsTy Flags,
SelectionDAG &DAG, const SDLoc &dl) {
SDValue SizeNode = DAG.getIntPtrConstant(Flags.getByValSize(), dl);
-
+ Align Alignment = Flags.getNonZeroByValAlign();
return DAG.getMemcpy(
- Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
+ Chain, dl, Dst, Src, SizeNode, Alignment, Alignment,
/*isVolatile*/ false, /*AlwaysInline=*/true,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
}
diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
index dedae127476cf..8b9782be0ea41 100644
--- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
@@ -374,7 +374,7 @@ static SDValue emitConstantSizeRepmov(
Chain, dl,
DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)),
DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)),
- DAG.getConstant(BytesLeft, dl, SizeVT), Alignment, isVolatile,
+ DAG.getConstant(BytesLeft, dl, SizeVT), Alignment, Alignment, isVolatile,
/*AlwaysInline*/ true, /*CI=*/nullptr, std::nullopt,
DstPtrInfo.getWithOffset(Offset), SrcPtrInfo.getWithOffset(Offset)));
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
@@ -382,8 +382,9 @@ static SDValue emitConstantSizeRepmov(
SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo) const {
const X86Subtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<X86Subtarget>();
@@ -407,12 +408,14 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
if (UseFSRMForMemcpy && Subtarget.hasFSRM())
return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, Size, MVT::i8);
- /// Handle constant sizes
- if (ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size))
+ // Handle constant sizes
+ if (ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size)) {
+ Align Alignment = std::min(DstAlign, SrcAlign);
return emitConstantSizeRepmov(DAG, Subtarget, dl, Chain, Dst, Src,
ConstantSize->getZExtValue(),
Size.getValueType(), Alignment, isVolatile,
AlwaysInline, DstPtrInfo, SrcPtrInfo);
+ }
return SDValue();
}
diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.h b/llvm/lib/Target/X86/X86SelectionDAGInfo.h
index 19c5986982614..1bf8a75733da5 100644
--- a/llvm/lib/Target/X86/X86SelectionDAGInfo.h
+++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.h
@@ -86,7 +86,7 @@ class X86SelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment,
+ SDValue Size, Align DstAlign, Align SrcAlign,
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 7c49e5b620bdf..f54862a804a45 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -1183,7 +1183,7 @@ SDValue XCoreTargetLowering::LowerCCCArguments(
CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
}
} else {
- // Only arguments passed on the stack should make it here.
+ // Only arguments passed on the stack should make it here.
assert(VA.isMemLoc());
// Load the argument to a virtual register
unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
@@ -1262,7 +1262,7 @@ SDValue XCoreTargetLowering::LowerCCCArguments(
InVals.push_back(FIN);
MemOps.push_back(DAG.getMemcpy(
Chain, dl, FIN, ArgDI.SDV, DAG.getConstant(Size, dl, MVT::i32),
- Alignment, false, false, /*CI=*/nullptr, std::nullopt,
+ Alignment, Alignment, false, false, /*CI=*/nullptr, std::nullopt,
MachinePointerInfo(), MachinePointerInfo()));
} else {
InVals.push_back(ArgDI.SDV);
@@ -1665,7 +1665,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
bool isTail = isInTailCallPosition(DAG, ST, Chain);
return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(),
DAG.getConstant(StoreBits / 8, dl, MVT::i32),
- Alignment, false, nullptr, isTail,
+ Alignment, Alignment, false, nullptr, isTail,
ST->getPointerInfo(), LD->getPointerInfo());
}
}
diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
index 57074d6ed1c08..1a8c69c890a6b 100644
--- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
@@ -25,8 +25,10 @@ XCoreSelectionDAGInfo::XCoreSelectionDAGInfo()
SDValue XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
- SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
+ SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo) const {
+ Align Alignment = std::min(DstAlign, SrcAlign);
unsigned SizeBitWidth = Size.getValueSizeInBits();
// Call __memcpy_4 if the src, dst and size are all 4 byte aligned.
if (!AlwaysInline && Alignment >= Align(4) &&
diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
index 4a2848229aca9..b4607b175d5a8 100644
--- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
+++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
@@ -26,8 +26,8 @@ class XCoreSelectionDAGInfo : public SelectionDAGGenTargetInfo {
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Op1, SDValue Op2,
- SDValue Op3, Align Alignment, bool isVolatile,
- bool AlwaysInline,
+ SDValue Op3, Align DstAlign, Align SrcAlign,
+ bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
};
>From 1221c095575148edf33b512209326a2e697312ee Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Tue, 2 Jun 2026 10:09:34 +0100
Subject: [PATCH 03/10] Update experimental backends
---
llvm/lib/Target/ARC/ARCISelLowering.cpp | 4 ++--
llvm/lib/Target/CSKY/CSKYISelLowering.cpp | 2 +-
llvm/lib/Target/M68k/M68kISelLowering.cpp | 3 ++-
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 6 ++++--
4 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp
index 730dbaa8ef655..cbe9fb6239f7b 100644
--- a/llvm/lib/Target/ARC/ARCISelLowering.cpp
+++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp
@@ -591,8 +591,8 @@ SDValue ARCTargetLowering::LowerCallArguments(
InVals.push_back(FIN);
MemOps.push_back(DAG.getMemcpy(
Chain, dl, FIN, ArgDI.SDV, DAG.getConstant(Size, dl, MVT::i32),
- Alignment, false, false, /*CI=*/nullptr, false, MachinePointerInfo(),
- MachinePointerInfo()));
+ Alignment, Alignment, false, false, /*CI=*/nullptr, false,
+ MachinePointerInfo(), MachinePointerInfo()));
} else {
InVals.push_back(ArgDI.SDV);
}
diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index 09b91240907f9..738dcfb167e48 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -555,7 +555,7 @@ SDValue CSKYTargetLowering::LowerCall(CallLoweringInfo &CLI,
SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
- Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
+ Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, Alignment,
/*IsVolatile=*/false,
/*AlwaysInline=*/false, /*CI=*/nullptr, IsTailCall,
MachinePointerInfo(), MachinePointerInfo());
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 05bf44dd90e73..f38e95846dd1d 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -268,9 +268,10 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SDValue Chain, ISD::ArgFlagsTy Flags,
SelectionDAG &DAG, const SDLoc &DL) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32);
+ Align Alignment = Flags.getNonZeroByValAlign();
return DAG.getMemcpy(
- Chain, DL, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
+ Chain, DL, Dst, Src, SizeNode, Alignment, Alignment,
/*isVolatile=*/false, /*AlwaysInline=*/true,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 090037c28704f..fbec7e8e56614 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -643,8 +643,9 @@ XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI,
SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
DAG.getIntPtrConstant(Offset, DL));
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32);
+ Align Alignment = Flags.getNonZeroByValAlign();
SDValue Memcpy = DAG.getMemcpy(
- Chain, DL, Address, ArgValue, SizeNode, Flags.getNonZeroByValAlign(),
+ Chain, DL, Address, ArgValue, SizeNode, Alignment, Alignment,
/*isVolatile=*/false, /*AlwaysInline=*/false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
MachinePointerInfo());
@@ -1269,7 +1270,8 @@ SDValue XtensaTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
DAG.getConstant(VAListSize, SDLoc(Op), MVT::i32),
- Align(4), /*isVolatile*/ false, /*AlwaysInline*/ true,
+ Align(4), Align(4), /*isVolatile*/ false,
+ /*AlwaysInline*/ true,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(DstSV),
MachinePointerInfo(SrcSV));
}
>From e5dc46f4ee54a9a0552b224ef0a53e9dbc32f785 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Tue, 2 Jun 2026 10:13:16 +0100
Subject: [PATCH 04/10] Refactoring and fixups
---
llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp | 8 ++++----
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 4 ++--
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 5 +++--
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 ++--
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 5 +++--
5 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
index 54ed14a04f304..f8f036544534e 100644
--- a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
@@ -38,7 +38,7 @@ SDValue BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(
SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
bool AlwaysInline, MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const {
- // TODO: Not sure which alignment to use below.
+ Align Alignment = std::min(DstAlign, SrcAlign);
// Requires the copy size to be a constant.
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -46,16 +46,16 @@ SDValue BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(
return SDValue();
// BPF::MEMCPY supports alignment up to 8 bytes.
- if (DstAlign.value() > 8)
+ if (Alignment.value() > 8)
return SDValue();
unsigned CopyLen = ConstantSize->getZExtValue();
- unsigned StoresNumEstimate = alignTo(CopyLen, DstAlign) >> Log2(DstAlign);
+ unsigned StoresNumEstimate = alignTo(CopyLen, Alignment) >> Log2(Alignment);
// Impose the same copy length limit as MaxStoresPerMemcpy.
if (StoresNumEstimate > getCommonMaxStoresPerMemFunc())
return SDValue();
return DAG.getNode(BPFISD::MEMCPY, dl, MVT::Other, Chain, Dst, Src,
DAG.getConstant(CopyLen, dl, MVT::i64),
- DAG.getConstant(DstAlign.value(), dl, MVT::i64));
+ DAG.getConstant(Alignment.value(), dl, MVT::i64));
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index ec3c30007341b..354559f6780f4 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -215,9 +215,9 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SDValue Chain, ISD::ArgFlagsTy Flags,
SelectionDAG &DAG, const SDLoc &dl) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
- Align Align = Flags.getNonZeroByValAlign();
+ Align Alignment = Flags.getNonZeroByValAlign();
return DAG.getMemcpy(
- Chain, dl, Dst, Src, SizeNode, Align, Align,
+ Chain, dl, Dst, Src, SizeNode, Alignment, Alignment,
/*isVolatile=*/false, /*AlwaysInline=*/false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
}
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 5516c21685f05..db716f02899b5 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -685,8 +685,9 @@ SDValue MSP430TargetLowering::LowerCCCCallTo(
if (Flags.isByVal()) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
- Align Align = Flags.getNonZeroByValAlign();
- MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, Align, Align,
+ Align Alignment = Flags.getNonZeroByValAlign();
+ MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, Alignment,
+ Alignment,
/*isVolatile*/ false,
/*AlwaysInline=*/true,
/*CI=*/nullptr, std::nullopt,
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4b44dbdc8750b..ee4de18c543a8 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -5194,9 +5194,9 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SDValue Chain, ISD::ArgFlagsTy Flags,
SelectionDAG &DAG, const SDLoc &dl) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
- Align Align = Flags.getNonZeroByValAlign();
+ Align Alignment = Flags.getNonZeroByValAlign();
return DAG.getMemcpy(
- Chain, dl, Dst, Src, SizeNode, Align, Align, false, false,
+ Chain, dl, Dst, Src, SizeNode, Alignment, Alignment, false, false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 8cad41dc81d8f..bba3a34b08df8 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1392,8 +1392,9 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
SDValue SizeNode =
DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32);
SDValue FINode = DAG.getFrameIndex(FI, getPointerTy(Layout));
- Align Align = Out.Flags.getNonZeroByValAlign();
- Chain = DAG.getMemcpy(Chain, DL, FINode, OutVal, SizeNode, Align, Align,
+ Align Alignment = Out.Flags.getNonZeroByValAlign();
+ Chain = DAG.getMemcpy(Chain, DL, FINode, OutVal, SizeNode, Alignment,
+ Alignment,
/*isVolatile*/ false, /*AlwaysInline=*/false,
/*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
MachinePointerInfo());
>From 7997a593e65f7184dfcee3f6588a14585fe55ab8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Tue, 2 Jun 2026 12:00:16 +0100
Subject: [PATCH 05/10] Fixups and test updates
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 24 ++++++-----
llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll | 32 +++++++--------
llvm/test/CodeGen/X86/pr57673.ll | 40 +++++++++----------
3 files changed, 50 insertions(+), 46 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 55602b0496a87..10901d2cafb5f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -218,21 +218,25 @@ bool TargetLowering::findOptimalMemOpLowering(
LLVMContext &Context, std::vector<EVT> &MemOps, unsigned Limit,
const MemOp &Op, unsigned DstAS, unsigned SrcAS,
const AttributeList &FuncAttributes, EVT *LargestVT) const {
- if (Limit != ~unsigned(0) && Op.isMemcpyWithFixedDstAlign() &&
- Op.getSrcAlign() < Op.getDstAlign())
- return false;
-
EVT VT = getOptimalMemOpType(Context, Op, FuncAttributes);
if (VT == MVT::Other) {
// Use the largest integer type whose alignment constraints are satisfied.
- // We only need to check DstAlign here as SrcAlign is always greater or
- // equal to DstAlign (or zero).
VT = MVT::LAST_INTEGER_VALUETYPE;
- if (Op.isFixedDstAlign())
- while (Op.getDstAlign() < (VT.getSizeInBits() / 8) &&
- !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign()))
+ if (Op.isFixedDstAlign()) {
+ bool LoadsFromSrc = Op.isMemcpy() && !Op.isMemcpyStrSrc();
+ while (VT != MVT::i8) {
+ unsigned VTSize = VT.getSizeInBits() / 8;
+ bool DstOk = Op.getDstAlign() >= VTSize ||
+ allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign());
+ bool SrcOk =
+ !LoadsFromSrc || Op.getSrcAlign() >= VTSize ||
+ allowsMisalignedMemoryAccesses(VT, SrcAS, Op.getSrcAlign());
+ if (DstOk && SrcOk)
+ break;
VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
+ }
+ }
assert(VT.isInteger());
// Find the largest legal integer type.
@@ -242,7 +246,7 @@ bool TargetLowering::findOptimalMemOpLowering(
assert(LVT.isInteger());
// If the type we've chosen is larger than the largest legal integer type
- // then use that instead.
+ // then use the largest legal type.
if (VT.bitsGT(LVT))
VT = LVT;
}
diff --git a/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll b/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
index 5b7c36559a366..073f682f222e9 100644
--- a/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
+++ b/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
@@ -237,23 +237,23 @@ define amdgpu_kernel void @memcpy_p3_p4_minsize(ptr addrspace(4) %0) #0 {
; CHECK-NEXT: global_load_dwordx4 v[16:19], v24, s[0:1] offset:64
; CHECK-NEXT: global_load_dwordx4 v[20:23], v24, s[0:1] offset:80
; CHECK-NEXT: s_waitcnt vmcnt(5)
-; CHECK-NEXT: ds_write2_b64 v24, v[0:1], v[2:3] offset1:1
+; CHECK-NEXT: ds_write_b128 v24, v[0:3]
; CHECK-NEXT: s_waitcnt vmcnt(4)
-; CHECK-NEXT: ds_write2_b64 v24, v[4:5], v[6:7] offset0:2 offset1:3
+; CHECK-NEXT: ds_write_b128 v24, v[4:7] offset:16
; CHECK-NEXT: global_load_dwordx4 v[0:3], v24, s[0:1] offset:96
; CHECK-NEXT: global_load_dwordx4 v[4:7], v24, s[0:1] offset:112
; CHECK-NEXT: s_waitcnt vmcnt(5)
-; CHECK-NEXT: ds_write2_b64 v24, v[8:9], v[10:11] offset0:4 offset1:5
+; CHECK-NEXT: ds_write_b128 v24, v[8:11] offset:32
; CHECK-NEXT: s_waitcnt vmcnt(4)
-; CHECK-NEXT: ds_write2_b64 v24, v[12:13], v[14:15] offset0:6 offset1:7
+; CHECK-NEXT: ds_write_b128 v24, v[12:15] offset:48
; CHECK-NEXT: s_waitcnt vmcnt(3)
-; CHECK-NEXT: ds_write2_b64 v24, v[16:17], v[18:19] offset0:8 offset1:9
+; CHECK-NEXT: ds_write_b128 v24, v[16:19] offset:64
; CHECK-NEXT: s_waitcnt vmcnt(2)
-; CHECK-NEXT: ds_write2_b64 v24, v[20:21], v[22:23] offset0:10 offset1:11
+; CHECK-NEXT: ds_write_b128 v24, v[20:23] offset:80
; CHECK-NEXT: s_waitcnt vmcnt(1)
-; CHECK-NEXT: ds_write2_b64 v24, v[0:1], v[2:3] offset0:12 offset1:13
+; CHECK-NEXT: ds_write_b128 v24, v[0:3] offset:96
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: ds_write2_b64 v24, v[4:5], v[6:7] offset0:14 offset1:15
+; CHECK-NEXT: ds_write_b128 v24, v[4:7] offset:112
; CHECK-NEXT: s_endpgm
entry:
tail call void @llvm.memcpy.p3.p4.i64(ptr addrspace(3) @shared, ptr addrspace(4) %0, i64 128, i1 false)
@@ -525,23 +525,23 @@ define amdgpu_kernel void @memcpy_p3_p4_optsize(ptr addrspace(4) %0) #1 {
; CHECK-NEXT: global_load_dwordx4 v[16:19], v24, s[0:1] offset:64
; CHECK-NEXT: global_load_dwordx4 v[20:23], v24, s[0:1] offset:80
; CHECK-NEXT: s_waitcnt vmcnt(5)
-; CHECK-NEXT: ds_write2_b64 v24, v[0:1], v[2:3] offset1:1
+; CHECK-NEXT: ds_write_b128 v24, v[0:3]
; CHECK-NEXT: s_waitcnt vmcnt(4)
-; CHECK-NEXT: ds_write2_b64 v24, v[4:5], v[6:7] offset0:2 offset1:3
+; CHECK-NEXT: ds_write_b128 v24, v[4:7] offset:16
; CHECK-NEXT: global_load_dwordx4 v[0:3], v24, s[0:1] offset:96
; CHECK-NEXT: global_load_dwordx4 v[4:7], v24, s[0:1] offset:112
; CHECK-NEXT: s_waitcnt vmcnt(5)
-; CHECK-NEXT: ds_write2_b64 v24, v[8:9], v[10:11] offset0:4 offset1:5
+; CHECK-NEXT: ds_write_b128 v24, v[8:11] offset:32
; CHECK-NEXT: s_waitcnt vmcnt(4)
-; CHECK-NEXT: ds_write2_b64 v24, v[12:13], v[14:15] offset0:6 offset1:7
+; CHECK-NEXT: ds_write_b128 v24, v[12:15] offset:48
; CHECK-NEXT: s_waitcnt vmcnt(3)
-; CHECK-NEXT: ds_write2_b64 v24, v[16:17], v[18:19] offset0:8 offset1:9
+; CHECK-NEXT: ds_write_b128 v24, v[16:19] offset:64
; CHECK-NEXT: s_waitcnt vmcnt(2)
-; CHECK-NEXT: ds_write2_b64 v24, v[20:21], v[22:23] offset0:10 offset1:11
+; CHECK-NEXT: ds_write_b128 v24, v[20:23] offset:80
; CHECK-NEXT: s_waitcnt vmcnt(1)
-; CHECK-NEXT: ds_write2_b64 v24, v[0:1], v[2:3] offset0:12 offset1:13
+; CHECK-NEXT: ds_write_b128 v24, v[0:3] offset:96
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: ds_write2_b64 v24, v[4:5], v[6:7] offset0:14 offset1:15
+; CHECK-NEXT: ds_write_b128 v24, v[4:7] offset:112
; CHECK-NEXT: s_endpgm
entry:
tail call void @llvm.memcpy.p3.p4.i64(ptr addrspace(3) @shared, ptr addrspace(4) %0, i64 128, i1 false)
diff --git a/llvm/test/CodeGen/X86/pr57673.ll b/llvm/test/CodeGen/X86/pr57673.ll
index 0071ada715afb..3be10a7535de4 100644
--- a/llvm/test/CodeGen/X86/pr57673.ll
+++ b/llvm/test/CodeGen/X86/pr57673.ll
@@ -20,16 +20,16 @@ define void @foo() {
; NORMAL: bb.0.bb_entry:
; NORMAL-NEXT: successors: %bb.1(0x80000000)
; NORMAL-NEXT: {{ $}}
- ; NORMAL-NEXT: [[MOV32r0_:%[0-9]+]]:gr8 = IMPLICIT_DEF
- ; NORMAL-NEXT: [[COPY:%[0-9]+]]:gr8 = IMPLICIT_DEF
- ; NORMAL-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
+ ; NORMAL-NEXT: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
+ ; NORMAL-NEXT: [[DEF1:%[0-9]+]]:gr8 = IMPLICIT_DEF
+ ; NORMAL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; NORMAL-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.1.i, 1, $noreg, 0, $noreg
- ; NORMAL-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+ ; NORMAL-NEXT: [[DEF2:%[0-9]+]]:gr64 = IMPLICIT_DEF
; NORMAL-NEXT: {{ $}}
; NORMAL-NEXT: bb.1.bb_8:
; NORMAL-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; NORMAL-NEXT: {{ $}}
- ; NORMAL-NEXT: TEST8rr [[MOV32r0_]], [[COPY]], implicit-def $eflags
+ ; NORMAL-NEXT: TEST8rr [[DEF]], [[DEF1]], implicit-def $eflags
; NORMAL-NEXT: JCC_1 %bb.3, 5, implicit $eflags
; NORMAL-NEXT: JMP_1 %bb.2
; NORMAL-NEXT: {{ $}}
@@ -37,22 +37,22 @@ define void @foo() {
; NORMAL-NEXT: successors: %bb.3(0x80000000)
; NORMAL-NEXT: {{ $}}
; NORMAL-NEXT: [[MOVUPSrm:%[0-9]+]]:vr128 = MOVUPSrm %stack.1.i, 1, $noreg, 40, $noreg :: (load (s128) from %ir.i4, align 8)
- ; NORMAL-NEXT: MOVUPSmr $noreg, 1, $noreg, 0, $noreg, killed [[MOVUPSrm]] :: (store (s128) into `ptr null`, align 8)
+ ; NORMAL-NEXT: MOVAPSmr $noreg, 1, $noreg, 0, $noreg, killed [[MOVUPSrm]] :: (store (s128) into `ptr null`, align 4294967296)
; NORMAL-NEXT: DBG_VALUE_LIST !3, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_plus_uconst, 40, DW_OP_stack_value), %stack.1.i, %stack.1.i, debug-location !10
; NORMAL-NEXT: [[MOVUPSrm1:%[0-9]+]]:vr128 = MOVUPSrm %stack.1.i, 1, $noreg, 40, $noreg :: (load (s128) from %ir.i6, align 8)
- ; NORMAL-NEXT: MOVUPSmr $noreg, 1, $noreg, 0, $noreg, killed [[MOVUPSrm1]] :: (store (s128) into `ptr null`, align 8)
+ ; NORMAL-NEXT: MOVAPSmr $noreg, 1, $noreg, 0, $noreg, killed [[MOVUPSrm1]] :: (store (s128) into `ptr null`, align 4294967296)
; NORMAL-NEXT: {{ $}}
; NORMAL-NEXT: bb.3.bb_last:
; NORMAL-NEXT: successors: %bb.1(0x80000000)
; NORMAL-NEXT: {{ $}}
; NORMAL-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- ; NORMAL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32r0_1]], %subreg.sub_32bit
+ ; NORMAL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32r0_]], %subreg.sub_32bit
; NORMAL-NEXT: $rdi = COPY [[SUBREG_TO_REG]]
; NORMAL-NEXT: $rsi = COPY [[SUBREG_TO_REG]]
; NORMAL-NEXT: $rdx = COPY [[SUBREG_TO_REG]]
- ; NORMAL-NEXT: $ecx = COPY [[MOV32r0_1]]
+ ; NORMAL-NEXT: $ecx = COPY [[MOV32r0_]]
; NORMAL-NEXT: $r8 = COPY [[LEA64r]]
- ; NORMAL-NEXT: CALL64r [[DEF]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $ecx, implicit $r8, implicit-def $rsp, implicit-def $ssp
+ ; NORMAL-NEXT: CALL64r [[DEF2]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $ecx, implicit $r8, implicit-def $rsp, implicit-def $ssp
; NORMAL-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; NORMAL-NEXT: JMP_1 %bb.1
;
@@ -60,16 +60,16 @@ define void @foo() {
; INSTRREF: bb.0.bb_entry:
; INSTRREF-NEXT: successors: %bb.1(0x80000000)
; INSTRREF-NEXT: {{ $}}
- ; INSTRREF-NEXT: [[MOV32r0_:%[0-9]+]]:gr8 = IMPLICIT_DEF
- ; INSTRREF-NEXT: [[COPY:%[0-9]+]]:gr8 = IMPLICIT_DEF
- ; INSTRREF-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
+ ; INSTRREF-NEXT: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
+ ; INSTRREF-NEXT: [[DEF1:%[0-9]+]]:gr8 = IMPLICIT_DEF
+ ; INSTRREF-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; INSTRREF-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.1.i, 1, $noreg, 0, $noreg
- ; INSTRREF-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+ ; INSTRREF-NEXT: [[DEF2:%[0-9]+]]:gr64 = IMPLICIT_DEF
; INSTRREF-NEXT: {{ $}}
; INSTRREF-NEXT: bb.1.bb_8:
; INSTRREF-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; INSTRREF-NEXT: {{ $}}
- ; INSTRREF-NEXT: TEST8rr [[MOV32r0_]], [[COPY]], implicit-def $eflags
+ ; INSTRREF-NEXT: TEST8rr [[DEF]], [[DEF1]], implicit-def $eflags
; INSTRREF-NEXT: JCC_1 %bb.3, 5, implicit $eflags
; INSTRREF-NEXT: JMP_1 %bb.2
; INSTRREF-NEXT: {{ $}}
@@ -77,22 +77,22 @@ define void @foo() {
; INSTRREF-NEXT: successors: %bb.3(0x80000000)
; INSTRREF-NEXT: {{ $}}
; INSTRREF-NEXT: [[MOVUPSrm:%[0-9]+]]:vr128 = MOVUPSrm %stack.1.i, 1, $noreg, 40, $noreg :: (load (s128) from %ir.i4, align 8)
- ; INSTRREF-NEXT: MOVUPSmr $noreg, 1, $noreg, 0, $noreg, killed [[MOVUPSrm]] :: (store (s128) into `ptr null`, align 8)
+ ; INSTRREF-NEXT: MOVAPSmr $noreg, 1, $noreg, 0, $noreg, killed [[MOVUPSrm]] :: (store (s128) into `ptr null`, align 4294967296)
; INSTRREF-NEXT: DBG_VALUE_LIST !3, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_plus_uconst, 40, DW_OP_stack_value), %stack.1.i, %stack.1.i, debug-location !10
; INSTRREF-NEXT: [[MOVUPSrm1:%[0-9]+]]:vr128 = MOVUPSrm %stack.1.i, 1, $noreg, 40, $noreg :: (load (s128) from %ir.i6, align 8)
- ; INSTRREF-NEXT: MOVUPSmr $noreg, 1, $noreg, 0, $noreg, killed [[MOVUPSrm1]] :: (store (s128) into `ptr null`, align 8)
+ ; INSTRREF-NEXT: MOVAPSmr $noreg, 1, $noreg, 0, $noreg, killed [[MOVUPSrm1]] :: (store (s128) into `ptr null`, align 4294967296)
; INSTRREF-NEXT: {{ $}}
; INSTRREF-NEXT: bb.3.bb_last:
; INSTRREF-NEXT: successors: %bb.1(0x80000000)
; INSTRREF-NEXT: {{ $}}
; INSTRREF-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- ; INSTRREF-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32r0_1]], %subreg.sub_32bit
+ ; INSTRREF-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32r0_]], %subreg.sub_32bit
; INSTRREF-NEXT: $rdi = COPY [[SUBREG_TO_REG]]
; INSTRREF-NEXT: $rsi = COPY [[SUBREG_TO_REG]]
; INSTRREF-NEXT: $rdx = COPY [[SUBREG_TO_REG]]
- ; INSTRREF-NEXT: $ecx = COPY [[MOV32r0_1]]
+ ; INSTRREF-NEXT: $ecx = COPY [[MOV32r0_]]
; INSTRREF-NEXT: $r8 = COPY [[LEA64r]]
- ; INSTRREF-NEXT: CALL64r [[DEF]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $ecx, implicit $r8, implicit-def $rsp, implicit-def $ssp
+ ; INSTRREF-NEXT: CALL64r [[DEF2]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $ecx, implicit $r8, implicit-def $rsp, implicit-def $ssp
; INSTRREF-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; INSTRREF-NEXT: JMP_1 %bb.1
bb_entry:
>From 577777729d105b9bb43ebff721249a1cad54d89b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Tue, 2 Jun 2026 12:06:05 +0100
Subject: [PATCH 06/10] Formatting
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 15 ++++++---------
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 +++++-------
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 +++--
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 8 ++++----
llvm/lib/Target/M68k/M68kISelLowering.cpp | 8 ++++----
.../WebAssembly/WebAssemblySelectionDAGInfo.cpp | 6 +++---
llvm/lib/Target/X86/X86ISelLoweringCall.cpp | 8 ++++----
7 files changed, 29 insertions(+), 33 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 0e4ee1aba75a3..abc2e1f0ebe4f 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1333,15 +1333,12 @@ class SelectionDAG {
/* \p CI if not null is the memset call being lowered.
* \p OverrideTailCall is an optional parameter that can be used to override
* the tail call optimization decision. */
- LLVM_ABI SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst,
- SDValue Src, SDValue Size, Align DstAlign,
- Align SrcAlign, bool isVol, bool AlwaysInline,
- const CallInst *CI,
- std::optional<bool> OverrideTailCall,
- MachinePointerInfo DstPtrInfo,
- MachinePointerInfo SrcPtrInfo,
- const AAMDNodes &AAInfo = AAMDNodes(),
- BatchAAResults *BatchAA = nullptr);
+ LLVM_ABI SDValue getMemcpy(
+ SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size,
+ Align DstAlign, Align SrcAlign, bool isVol, bool AlwaysInline,
+ const CallInst *CI, std::optional<bool> OverrideTailCall,
+ MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo,
+ const AAMDNodes &AAInfo = AAMDNodes(), BatchAAResults *BatchAA = nullptr);
/* \p CI if not null is the memset call being lowered.
* \p OverrideTailCall is an optional parameter that can be used to override
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f65f933d1e668..ba698d8d2fe4c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9455,13 +9455,11 @@ getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
}
-static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
- SDValue Chain, SDValue Dst, SDValue Src,
- uint64_t Size, Align DstAlign, Align SrcAlign,
- bool isVol, bool AlwaysInline,
- MachinePointerInfo DstPtrInfo,
- MachinePointerInfo SrcPtrInfo,
- const AAMDNodes &AAInfo) {
+static SDValue getMemmoveLoadsAndStores(
+ SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
+ uint64_t Size, Align DstAlign, Align SrcAlign, bool isVol,
+ bool AlwaysInline, MachinePointerInfo DstPtrInfo,
+ MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo) {
// Turn a memmove of undef to nop.
// FIXME: We need to honor volatile even is Src is undef.
if (Src.isUndef())
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 10901d2cafb5f..1376276aa0f88 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -227,8 +227,9 @@ bool TargetLowering::findOptimalMemOpLowering(
bool LoadsFromSrc = Op.isMemcpy() && !Op.isMemcpyStrSrc();
while (VT != MVT::i8) {
unsigned VTSize = VT.getSizeInBits() / 8;
- bool DstOk = Op.getDstAlign() >= VTSize ||
- allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign());
+ bool DstOk =
+ Op.getDstAlign() >= VTSize ||
+ allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign());
bool SrcOk =
!LoadsFromSrc || Op.getSrcAlign() >= VTSize ||
allowsMisalignedMemoryAccesses(VT, SrcAS, Op.getSrcAlign());
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 354559f6780f4..b369bdff477d6 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -216,10 +216,10 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SelectionDAG &DAG, const SDLoc &dl) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
Align Alignment = Flags.getNonZeroByValAlign();
- return DAG.getMemcpy(
- Chain, dl, Dst, Src, SizeNode, Alignment, Alignment,
- /*isVolatile=*/false, /*AlwaysInline=*/false,
- /*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
+ return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Alignment, Alignment,
+ /*isVolatile=*/false, /*AlwaysInline=*/false,
+ /*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
+ MachinePointerInfo());
}
bool
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index f38e95846dd1d..3621580d6ad35 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -270,10 +270,10 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32);
Align Alignment = Flags.getNonZeroByValAlign();
- return DAG.getMemcpy(
- Chain, DL, Dst, Src, SizeNode, Alignment, Alignment,
- /*isVolatile=*/false, /*AlwaysInline=*/true,
- /*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
+ return DAG.getMemcpy(Chain, DL, Dst, Src, SizeNode, Alignment, Alignment,
+ /*isVolatile=*/false, /*AlwaysInline=*/true,
+ /*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
+ MachinePointerInfo());
}
/// Return true if the calling convention is one that we can guarantee TCO for.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
index 2a1555afda896..37019eb1ec941 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
@@ -62,9 +62,9 @@ SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemmove(
SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2,
SDValue Op3, Align DstAlign, Align SrcAlign, bool IsVolatile,
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
- return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3,
- DstAlign, SrcAlign, IsVolatile, false,
- DstPtrInfo, SrcPtrInfo);
+ return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, DstAlign,
+ SrcAlign, IsVolatile, false, DstPtrInfo,
+ SrcPtrInfo);
}
SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(
diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
index 33d0a37a7636d..05d86f1d7ba0f 100644
--- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
@@ -1240,10 +1240,10 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
SelectionDAG &DAG, const SDLoc &dl) {
SDValue SizeNode = DAG.getIntPtrConstant(Flags.getByValSize(), dl);
Align Alignment = Flags.getNonZeroByValAlign();
- return DAG.getMemcpy(
- Chain, dl, Dst, Src, SizeNode, Alignment, Alignment,
- /*isVolatile*/ false, /*AlwaysInline=*/true,
- /*CI=*/nullptr, std::nullopt, MachinePointerInfo(), MachinePointerInfo());
+ return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Alignment, Alignment,
+ /*isVolatile*/ false, /*AlwaysInline=*/true,
+ /*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
+ MachinePointerInfo());
}
/// Return true if the calling convention is one that we can guarantee TCO for.
>From 25a74fe86a281f3051d9385d2a7f24be385843b4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Tue, 2 Jun 2026 12:07:25 +0100
Subject: [PATCH 07/10] Clarify a comment
---
llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
index f8f036544534e..8b7ac6a4730f7 100644
--- a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
@@ -45,7 +45,7 @@ SDValue BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(
if (!ConstantSize)
return SDValue();
- // BPF::MEMCPY supports alignment up to 8 bytes.
+ // `BPFInstrInfo::expandMEMCPY` supports alignment up to 8 bytes.
if (Alignment.value() > 8)
return SDValue();
>From 6c2680595aa1fb705e5833053d17763d617c8045 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Tue, 2 Jun 2026 12:21:21 +0100
Subject: [PATCH 08/10] Remove redundant std::min
---
llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
index 1a8c69c890a6b..2884f54af3477 100644
--- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
@@ -28,10 +28,9 @@ SDValue XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(
SDValue Size, Align DstAlign, Align SrcAlign, bool isVolatile,
bool AlwaysInline, MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const {
- Align Alignment = std::min(DstAlign, SrcAlign);
unsigned SizeBitWidth = Size.getValueSizeInBits();
// Call __memcpy_4 if the src, dst and size are all 4 byte aligned.
- if (!AlwaysInline && Alignment >= Align(4) &&
+ if (!AlwaysInline && SrcAlign >= Align(4) && DstAlign >= Align(4) &&
DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) {
const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering();
TargetLowering::ArgListTy Args;
>From 2051e307e077b795ae58616eee06fbc9f524e38d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Tue, 2 Jun 2026 14:23:52 +0100
Subject: [PATCH 09/10] Update ARM cost model test
---
llvm/test/Analysis/CostModel/ARM/memcpy.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/Analysis/CostModel/ARM/memcpy.ll b/llvm/test/Analysis/CostModel/ARM/memcpy.ll
index f397397125c05..690d6b5a1bf8a 100644
--- a/llvm/test/Analysis/CostModel/ARM/memcpy.ll
+++ b/llvm/test/Analysis/CostModel/ARM/memcpy.ll
@@ -742,7 +742,7 @@ define void @memcpy_1_al41(ptr %d, ptr %s) {
; strb r1, [r0]
;
; COMMON-LABEL: 'memcpy_1_al41'
-; COMMON-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.memcpy.p0.p0.i32(ptr align 4 %d, ptr align 1 %s, i32 1, i1 false)
+; COMMON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.memcpy.p0.p0.i32(ptr align 4 %d, ptr align 1 %s, i32 1, i1 false)
; COMMON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
entry:
>From f0c70f841cc698b6e5c09c79de18ea318f370a8f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Wed, 3 Jun 2026 08:51:32 +0100
Subject: [PATCH 10/10] Remove FIXMEs
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 ----
1 file changed, 4 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index d92cde9b1cc1a..48f52344491b7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6733,8 +6733,6 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
Align DstAlign = MCI.getDestAlign().valueOrOne();
Align SrcAlign = MCI.getSourceAlign().valueOrOne();
bool isVol = MCI.isVolatile();
- // FIXME: Support passing different dest/src alignments to the memcpy DAG
- // node.
SDValue Root = isVol ? getRoot() : getMemoryRoot();
SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, DstAlign, SrcAlign,
isVol, MCI.isForceInlined(), &I, std::nullopt,
@@ -6771,8 +6769,6 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
Align DstAlign = MMI.getDestAlign().valueOrOne();
Align SrcAlign = MMI.getSourceAlign().valueOrOne();
bool isVol = MMI.isVolatile();
- // FIXME: Support passing different dest/src alignments to the memmove DAG
- // node.
SDValue Root = isVol ? getRoot() : getMemoryRoot();
SDValue MM = DAG.getMemmove(
Root, sdl, Op1, Op2, Op3, DstAlign, SrcAlign, isVol, &I,
More information about the llvm-commits
mailing list