[llvm] [RISCV] Add Asserts for FP/CalleeSavedInfo (PR #201277)

[Sam Elliott via llvm-commits]

https://github.com/lenary created https://github.com/llvm/llvm-project/pull/201277

These should help diagnose some invariants that the code assumes, which should have been fixed by #200623.

>From 1c25cdfe6fb6d71d0437d447493d526d694a293a Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Tue, 2 Jun 2026 23:58:01 -0700
Subject: [PATCH] [RISCV] Add Asserts for FP/CalleeSavedInfo

These should help diagnose some invariants that the code assumes, which
should have been fixed by #200623.
---
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 46e4a8b959ef6..12d3a4bc0b0f3 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -2224,6 +2224,16 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
 bool RISCVFrameLowering::spillCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
     ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
+
+#ifdef EXPENSIVE_CHECKS
+  {
+    [[maybe_unused]] bool hasFPCSI = llvm::any_of(
+        CSI, [](CalleeSavedInfo &CSI) -> bool { return CSI.Reg == FPReg; });
+    assert((!hasFP(*MF) || hasFPCSI) &&
+           "Must have CalleeSavedInfo for FP if hasFP");
+  }
+#endif
+
   if (CSI.empty())
     return true;
 
@@ -2251,6 +2261,8 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
   if (RVFI->isPushable(*MF)) {
     // Emit CM.PUSH with base StackAdj & evaluate Push stack
     unsigned PushedRegNum = RVFI->getRVPushRegs();
+    assert((!hasFP(*MF) || PushedRegNum >= 2) &&
+           "Must push at least two registers if there is a frame pointer");
     if (PushedRegNum > 0) {
       // Use encoded number to represent registers to spill.
       unsigned Opcode = getPushOpcode(