[llvm] [CodeGen][AMDGPU] Remove premature empty subrange elimination (PR #201263)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 2 21:19:39 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-regalloc
@llvm/pr-subscribers-backend-amdgpu
Author: Steffen Larsen (steffenlarsen)
<details>
<summary>Changes</summary>
This commit removes a call to `removeEmptySubRanges` inside `SplitEditor::rewriteAssigned` which removes empty subranges that may be expected at a later stage. The empty subranges are eliminated by a later call to `removeEmptySubRanges`.
Fixes https://github.com/llvm/llvm-project/issues/199337.
---
Patch is 199.18 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/201263.diff
2 Files Affected:
- (modified) llvm/lib/CodeGen/SplitKit.cpp (-1)
- (added) llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll (+1524)
``````````diff
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index d8da81c307f31..7dbd9b5f31d56 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -1477,7 +1477,6 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
if (!LI.hasSubRanges())
continue;
LI.clear();
- LI.removeEmptySubRanges();
LIS.constructMainRangeFromSubranges(LI);
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
new file mode 100644
index 0000000000000..388633fe5bb56
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
@@ -0,0 +1,1524 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stop-after=greedy,2 < %s | FileCheck %s
+
+declare <16 x i63> @llvm.masked.load.v16i63.p0(ptr, <16 x i1>, <16 x i63>)
+
+define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
+ ; CHECK-LABEL: name: f
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr63, $sgpr30_sgpr31
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr34, 0, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr34, $vgpr63, 0, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr35, 1, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr35, $vgpr63, 1, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr36, 2, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr36, $vgpr63, 2, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr37, 3, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr37, $vgpr63, 3, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr38, 4, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr38, $vgpr63, 4, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr39, 5, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr39, $vgpr63, 5, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr48, 6, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr48, $vgpr63, 6, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr49, 7, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr49, $vgpr63, 7, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr50, 8, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr50, $vgpr63, 8, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr51, 9, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr51, $vgpr63, 9, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr52, 10, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr52, $vgpr63, 10, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr53, 11, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr53, $vgpr63, 11, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr54, 12, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr54, $vgpr63, 12, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr55, 13, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr55, $vgpr63, 13, 32
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr30, 14, $vgpr63, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 15, $vgpr63, implicit killed $sgpr30_sgpr31
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr63, 14, 32, $vgpr63, 15, 32
+ ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr30
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY]], %stack.16, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.16, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr29
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY1]], %stack.18, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.18, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr28
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY2]], %stack.31, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.31, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr27
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY3]], %stack.19, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.19, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY4:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr26
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY4]], %stack.20, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.20, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY5:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr25
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY5]], %stack.22, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.22, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY6:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr24
+ ; CHECK-NEXT: undef [[COPY7:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr23
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY7]], %stack.21, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.21, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY8:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr22
+ ; CHECK-NEXT: undef [[COPY9:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr21
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY9]], %stack.23, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.23, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY10:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr20
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY10]], %stack.24, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.24, align 4, addrspace 5)
+ ; CHECK-NEXT: undef [[COPY11:%[0-9]+]].sub2:av_128_align2 = COPY $vgpr19
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]].sub0:av_128_align2 = COPY $vgpr18
+ ; CHECK-NEXT: undef [[COPY12:%[0-9]+]].sub0:av_128_align2 = COPY [[COPY11]].sub0 {
+ ; CHECK-NEXT: internal [[COPY12]].sub2:av_128_align2 = COPY [[COPY11]].sub2
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: SI_SPILL_AV128_SAVE [[COPY12]], %stack.26, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.26, align 4, addrspace 5)
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY $vgpr17
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY $vgpr16
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY $vgpr15
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY $vgpr14
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY $vgpr13
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY $vgpr12
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY $vgpr11
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY $vgpr10
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY $vgpr9
+ ; CHECK-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+ ; CHECK-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY $vgpr7
+ ; CHECK-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY $vgpr6
+ ; CHECK-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; CHECK-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; CHECK-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; CHECK-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; CHECK-NEXT: undef [[COPY29:%[0-9]+]].sub1:av_64_align2 = COPY $vgpr1
+ ; CHECK-NEXT: [[COPY29:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr0
+ ; CHECK-NEXT: SI_SPILL_AV64_SAVE [[COPY29]], %stack.25, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.25, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.164, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.164, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.165, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.165, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.166, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.166, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.167, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.167, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN4:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.168, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.168, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN5:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.169, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.169, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN6:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.170, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.170, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN7:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.171, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.171, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN8:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.172, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.172, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN9:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.173, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.173, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN10:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.174, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.174, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN11:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.175, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.175, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN12:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.176, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.176, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN13:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.177, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.177, align 4, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN14:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.178, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.178, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_USHORT_OFFEN15:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN %fixed-stack.179, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16) from %fixed-stack.179, align 4, addrspace 5)
+ ; CHECK-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY13]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY14]], implicit $exec
+ ; CHECK-NEXT: renamable $vcc = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_2:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_3:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN1]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_4:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN2]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_5:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN3]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_6:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN4]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_7:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN5]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_8:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN6]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_9:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN7]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_10:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN8]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_11:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN9]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_12:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN10]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_13:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN11]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_14:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN12]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_15:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN13]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_16:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN14]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_17:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[BUFFER_LOAD_USHORT_OFFEN15]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr40_sgpr41 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_2]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr44_sgpr45 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_3]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr26_sgpr27 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_4]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr42_sgpr43 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_5]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr22_sgpr23 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_6]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr28_sgpr29 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_7]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr18_sgpr19 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_8]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr24_sgpr25 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_9]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr14_sgpr15 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_10]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr20_sgpr21 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_11]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr10_sgpr11 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_12]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr16_sgpr17 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_13]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr6_sgpr7 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_14]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr12_sgpr13 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_15]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr8_sgpr9 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_16]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_17]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr56_sgpr57 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_1]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_18:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY15]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr58_sgpr59 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_18]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_19:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY16]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr60_sgpr61 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_19]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_20:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY17]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr62_sgpr63 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_20]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_21:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY18]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr72_sgpr73 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_21]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_22:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY19]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr74_sgpr75 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_22]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_23:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY20]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr76_sgpr77 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_23]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_24:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY21]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr78_sgpr79 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_24]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_25:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY22]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr88_sgpr89 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_25]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_26:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY23]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr90_sgpr91 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_26]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_27:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY24]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr92_sgpr93 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_27]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_28:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY25]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr94_sgpr95 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_28]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_29:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY26]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr30_sgpr31 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_29]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_30:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY27]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr34_sgpr35 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_30]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e32_31:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY28]], implicit $exec
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37 = V_CMP_EQ_U32_e64 1, [[V_AND_B32_e32_31]], implicit $exec
+ ; CHECK-NEXT: undef [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub31:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.100, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.100, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub30:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.101, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.101, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub29:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.102, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.102, align 16, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub28:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.103, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.103, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub27:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.104, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.104, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]].sub26:av_1024_align2 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.105, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.105, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN %fixed-stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8) from %fixed-stack.0, align 8, addrspace 5)
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %fixed-stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.1, addrspace 5)
+ ; CHECK-NEXT: [[V_AND_B32_e32_32:%[0-9]+]]:vg...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/201263
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