[llvm] [AMDGPU] Add hint for MFMA Dst and OpC (PR #185218)

[Josh Hutton via llvm-commits]

================
@@ -107,6 +108,11 @@ class MachineRegisterInfo {
              VirtReg2IndexFunctor>
       RegAllocHints;
 
+  /// ChainHints - This equivalence class stores hints that are meant to only be
+  /// applied if all of the involved register classes are compatible, otherwise
+  /// none of them are applied.
+  EquivalenceClasses<Register> ChainHints;
+
----------------
JoshHuttonCode wrote:

Is your suggestion to extend RegAllocHints to store a type with each hint, rather than the current model of one typed hint plus more simple hints?

The main concern I have with that approach is that it would require touching every callsite of `MachineRegisterInfo::getRegAllocationHints()` across all targets that inspect the hint type/at any place where one target hint is assumed, which is fairly broad for what is otherwise a localized feature. Happy to proceed that way if you think it's the right direction, just wanted to check the scope before going further.

I think the desired functionality requires changing RegAllocHints or tracking these hints separately. If we wanted to keep the current API, we would have to assign the type and treat all hints for that VReg to be of that type. However, not being able to distinguish between simple hints and typed hints on a VReg means that the simple hints get removed if there's incompatibility with any typed hints.

Additionally, since the comments explicitly state that only one target hint is allowed, do you know if this was decided for a particular reason?

https://github.com/llvm/llvm-project/pull/185218