[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for llvm.amdgcn.frexp.exp (PR #201178)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 2 12:00:01 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: vangthao95
<details>
<summary>Changes</summary>
---
Patch is 352.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/201178.diff
8 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll (+3092-2392)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll (+578-409)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll (+126-14)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll (+360-16)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.frexp.ll (+7-7)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index db24bde2986ed..5c914f2f59f37 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2125,6 +2125,14 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S16, {{Vgpr16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
+ addRulesForIOpcs({amdgcn_frexp_exp})
+ .Any({{UniS16}, {{UniInVgprS16}, {IntrId, Vgpr16}}})
+ .Any({{DivS16}, {{Vgpr16}, {IntrId, Vgpr16}}})
+ .Any({{UniS32, _, S32}, {{UniInVgprS32}, {IntrId, Vgpr32}}})
+ .Any({{DivS32, _, S32}, {{Vgpr32}, {IntrId, Vgpr32}}})
+ .Any({{UniS32, _, S64}, {{UniInVgprS32}, {IntrId, Vgpr64}}})
+ .Any({{DivS32, _, S64}, {{Vgpr32}, {IntrId, Vgpr64}}});
+
addRulesForIOpcs({amdgcn_div_fmas}, Standard)
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vcc}})
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vcc}})
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
index 152bb9c91c618..784a1b27ff494 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
@@ -2,23 +2,23 @@
; RUN: sed 's/DEFAULT_MODE/ieee/g' %s > %t.ieee
; RUN: sed 's/DEFAULT_MODE/preservesign/g' %s > %t.preservesign
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=pitcairn < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=pitcairn < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %t.ieee | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %t.preservesign | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %t.ieee | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %t.preservesign | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %t.ieee | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %t.preservesign | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %t.ieee | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %t.preservesign | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s
define float @v_fdiv_f32(float %a, float %b) #1 {
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
index 5f18c0cd2aca5..6fc08d5d52e62 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
@@ -1,197 +1,241 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=CI %s
-; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=VI %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=CI %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=VI %s
define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {
; CI-LABEL: frem_f16:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
-; CI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0xd
-; CI-NEXT: ; implicit-def: $vgpr1
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_load_dword s0, s[10:11], 0x0
-; CI-NEXT: s_load_dword s1, s[2:3], 0x2
-; CI-NEXT: s_mov_b32 s2, 1
+; CI-NEXT: s_load_dword s2, s[2:3], 0x0
+; CI-NEXT: s_load_dword s3, s[4:5], 0x2
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s0|
-; CI-NEXT: v_cvt_f32_f16_e64 v0, |s1|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v0
-; CI-NEXT: s_cbranch_vccz .LBB0_2
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; CI-NEXT: s_mov_b32 s5, 1
+; CI-NEXT: ; implicit-def: $sgpr4
+; CI-NEXT: s_cbranch_scc0 .LBB0_2
; CI-NEXT: ; %bb.1: ; %frem.else
-; CI-NEXT: s_and_b32 s2, s0, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0
-; CI-NEXT: v_mov_b32_e32 v1, s2
-; CI-NEXT: v_mov_b32_e32 v3, s0
-; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: s_and_b32 s6, s2, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; CI-NEXT: s_cselect_b32 s4, s6, s2
+; CI-NEXT: s_mov_b32 s5, 0
; CI-NEXT: .LBB0_2: ; %Flow18
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s5, s5, 1
+; CI-NEXT: s_cmp_lg_u32 s5, 0
; CI-NEXT: s_cbranch_scc1 .LBB0_8
; CI-NEXT: ; %bb.3: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f32_e32 v1, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v1, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; CI-NEXT: v_readfirstlane_b32 s7, v1
+; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11
+; CI-NEXT: v_readfirstlane_b32 s6, v1
; CI-NEXT: v_frexp_mant_f32_e32 v1, v0
-; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1
-; CI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5
-; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; CI-NEXT: v_rcp_f32_e32 v8, v3
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1
+; CI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s5, s7, -1
+; CI-NEXT: s_add_i32 s4, s8, -1
+; CI-NEXT: s_sub_i32 s5, s5, s4
+; CI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; CI-NEXT: v_fma_f32 v8, v9, v8, v8
-; CI-NEXT: v_mul_f32_e32 v9, v7, v8
-; CI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; CI-NEXT: v_fma_f32 v9, v10, v8, v9
-; CI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2
-; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB0_6
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s5, 11
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB0_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v2, vcc, 11, v5
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; CI-NEXT: s_add_i32 s7, s7, 11
+; CI-NEXT: s_sub_i32 s5, s7, s8
; CI-NEXT: .LBB0_5: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v5, v4
-; CI-NEXT: v_mul_f32_e32 v4, v5, v3
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v6, v4, v1
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2
-; CI-NEXT: s_cbranch_vccnz .LBB0_5
+; CI-NEXT: v_mul_f32_e32 v2, s6, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s6
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s7, v2
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: s_cselect_b32 s7, s8, s7
+; CI-NEXT: v_ldexp_f32_e64 v2, s7, 11
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: s_add_i32 s5, s5, -11
+; CI-NEXT: s_cmp_gt_i32 s5, 11
+; CI-NEXT: s_mov_b32 s7, s6
+; CI-NEXT: s_mov_b32 s6, s8
+; CI-NEXT: s_cbranch_scc1 .LBB0_5
; CI-NEXT: s_branch .LBB0_7
; CI-NEXT: .LBB0_6:
-; CI-NEXT: v_mov_b32_e32 v5, v4
+; CI-NEXT: s_mov_b32 s7, s6
; CI-NEXT: .LBB0_7: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v2, vcc, -10, v2
-; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2
-; CI-NEXT: v_mul_f32_e32 v3, v2, v3
-; CI-NEXT: v_rndne_f32_e32 v3, v3
-; CI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; CI-NEXT: v_add_f32_e32 v1, v2, v1
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0
+; CI-NEXT: s_add_i32 s5, s5, -10
+; CI-NEXT: v_mov_b32_e32 v2, s5
+; CI-NEXT: v_ldexp_f32_e32 v2, s7, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s5, v1
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: s_cselect_b32 s5, s6, s5
+; CI-NEXT: v_mov_b32_e32 v0, s4
+; CI-NEXT: v_ldexp_f32_e32 v0, s5, v0
; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: s_and_b32 s2, s0, 0x8000
-; CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; CI-NEXT: v_or_b32_e32 v1, s2, v0
+; CI-NEXT: s_and_b32 s5, s2, 0xffff8000
+; CI-NEXT: v_readfirstlane_b32 s4, v0
+; CI-NEXT: s_and_b32 s4, s4, 0x7fff
+; CI-NEXT: s_or_b32 s4, s4, s5
; CI-NEXT: .LBB0_8: ; %Flow19
-; CI-NEXT: v_cvt_f32_f16_e32 v0, s1
-; CI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; CI-NEXT: s_mov_b32 s10, -1
-; CI-NEXT: s_mov_b32 s11, 0xf000
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s3
+; CI-NEXT: v_mov_b32_e32 v1, 0x7f800000
; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v0, |s0|
-; CI-NEXT: v_cmp_nge_f32_e64 s[0:1], v0, v2
-; CI-NEXT: v_mov_b32_e32 v0, 0x7e00
-; CI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
-; CI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; CI-NEXT: buffer_store_short v0, off, s[8:11], 0
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s2|
+; CI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; CI-NEXT: s_cselect_b32 s5, 1, 0
+; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; CI-NEXT: s_or_b64 s[2:3], vcc, vcc
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s5, 0
+; CI-NEXT: s_cselect_b32 s3, 0x7e00, s4
+; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_cselect_b32 s2, s3, 0x7e00
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: buffer_store_short v0, off, s[0:3], 0
; CI-NEXT: s_endpgm
;
; VI-LABEL: frem_f16:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
-; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34
-; VI-NEXT: ; implicit-def: $vgpr2
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_load_dword s0, s[10:11], 0x0
-; VI-NEXT: s_load_dword s1, s[2:3], 0x8
-; VI-NEXT: s_mov_b32 s2, 1
+; VI-NEXT: s_load_dword s2, s[2:3], 0x0
+; VI-NEXT: s_load_dword s3, s[4:5], 0x8
+; VI-NEXT: s_mov_b32 s5, 1
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v1, |s0|
-; VI-NEXT: v_cvt_f32_f16_e64 v0, |s1|
+; VI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
-; VI-NEXT: s_cbranch_vccz .LBB0_2
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cbranch_scc0 .LBB0_2
; VI-NEXT: ; %bb.1: ; %frem.else
-; VI-NEXT: s_and_b32 s2, s0, 0x8000
+; VI-NEXT: s_and_b32 s4, s2, 0xffff8000
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v3, s0
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cselect_b32 s4, s4, s2
+; VI-NEXT: s_mov_b32 s5, 0
; VI-NEXT: .LBB0_2: ; %Flow18
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s5, s5, 1
+; VI-NEXT: s_cmp_lg_u32 s5, 0
; VI-NEXT: s_cbranch_scc1 .LBB0_8
; VI-NEXT: ; %bb.3: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e32 v2, v1
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v1
+; VI-NEXT: v_ldexp_f32 v1, v2, 11
+; VI-NEXT: v_readfirstlane_b32 s6, v1
; VI-NEXT: v_frexp_mant_f32_e32 v1, v0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
-; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v5
-; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6
-; VI-NEXT: v_ldexp_f32 v1, v1, 1
-; VI-NEXT: v_ldexp_f32 v4, v2, 11
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v3, v0
-; VI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; VI-NEXT: v_rcp_f32_e32 v8, v3
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; VI-NEXT: v_readfirstlane_b32 s8, v0
+; VI-NEXT: v_ldexp_f32 v0, v1, 1
+; VI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s5, s7, -1
+; VI-NEXT: s_add_i32 s4, s8, -1
+; VI-NEXT: s_sub_i32 s5, s5, s4
+; VI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[10:11], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; VI-NEXT: v_fma_f32 v8, v9, v8, v8
-; VI-NEXT: v_mul_f32_e32 v9, v7, v8
-; VI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; VI-NEXT: v_fma_f32 v9, v10, v8, v9
-; VI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2
-; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB0_6
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s5, 11
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB0_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v2, vcc, 11, v5
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6
+; VI-NEXT: s_add_i32 s7, s7, 11
+; VI-NEXT: s_sub_i32 s5, s7, s8
; VI-NEXT: .LBB0_5: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v5, v4
-; VI-NEXT: v_mul_f32_e32 v4, v5, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v6, v4, v1
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2
-; VI-NEXT: v_ldexp_f32 v4, v4, 11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2
-; VI-NEXT: s_cbranch_vccnz .LBB0_5
+; VI-NEXT: v_mul_f32_e32 v2, s6, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s6
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: s_cselect_b32 s7, s8, s7
+; VI-NEXT: v_ldexp_f32 v2, s7, 11
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: s_add_i32 s5, s5, -11
+; VI-NEXT: s_cmp_gt_i32 s5, 11
+; VI-NEXT: s_mov_b32 s7, s6
+; VI-NEXT: s_mov_b32 s6, s8
+; VI-NEXT: s_cbranch_scc1 .LBB0_5
; VI-NEXT: s_branch .LBB0_7
; VI-NEXT: .LBB0_6:
-; VI-NEXT: v_mov_b32_e32 v5, v4
+; VI-NEXT: s_mov_b32 s7, s6
; VI-NEXT: .LBB0_7: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v2, vcc, -10, v2
-; VI-NEXT: v_ldexp_f32 v2, v5, v2
-; VI-NEXT: v_mul_f32_e32 v3, v2, v3
-; VI-NEXT: v_rndne_f32_e32 v3, v3
-; VI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_ldexp_f32 v0, v1, v0
+; VI-NEXT: s_add_i32 s5, s5, -10
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: v_ldexp_f32 v2, s7, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s5, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: s_cselect_b32 s5, s6, s5
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_ldexp_f32 v0, s5, v0
; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-NEXT: s_and_b32 s2, s0, 0x8000
-; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; VI-NEXT: v_or_b32_e32 v2, s2, v0
+; VI-NEXT: s_and_b32 s5, s2, 0xffff8000
+; VI-NEXT: v_readfirstlane_b32 s4, v0
+; VI-NEXT: s_and_b32 s4, s4, 0x7fff
+; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: .L...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/201178
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