[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for llvm.amdgcn.frexp.exp (PR #201178)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 2 11:59:29 PDT 2026
https://github.com/vangthao95 created https://github.com/llvm/llvm-project/pull/201178
None
>From aacb0560eb6a79bb7bf45bbbdab1665ad76f95d3 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Fri, 15 May 2026 19:11:37 -0400
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for
llvm.amdgcn.frexp.exp
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 8 +
.../CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll | 24 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll | 5484 ++++++++++-------
llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll | 8 +-
llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll | 987 +--
.../AMDGPU/llvm.amdgcn.frexp.exp.f16.ll | 140 +-
.../CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll | 376 +-
llvm/test/CodeGen/AMDGPU/llvm.frexp.ll | 14 +-
8 files changed, 4187 insertions(+), 2854 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index db24bde2986ed..5c914f2f59f37 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2125,6 +2125,14 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S16, {{Vgpr16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
+ addRulesForIOpcs({amdgcn_frexp_exp})
+ .Any({{UniS16}, {{UniInVgprS16}, {IntrId, Vgpr16}}})
+ .Any({{DivS16}, {{Vgpr16}, {IntrId, Vgpr16}}})
+ .Any({{UniS32, _, S32}, {{UniInVgprS32}, {IntrId, Vgpr32}}})
+ .Any({{DivS32, _, S32}, {{Vgpr32}, {IntrId, Vgpr32}}})
+ .Any({{UniS32, _, S64}, {{UniInVgprS32}, {IntrId, Vgpr64}}})
+ .Any({{DivS32, _, S64}, {{Vgpr32}, {IntrId, Vgpr64}}});
+
addRulesForIOpcs({amdgcn_div_fmas}, Standard)
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vcc}})
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vcc}})
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
index 152bb9c91c618..784a1b27ff494 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
@@ -2,23 +2,23 @@
; RUN: sed 's/DEFAULT_MODE/ieee/g' %s > %t.ieee
; RUN: sed 's/DEFAULT_MODE/preservesign/g' %s > %t.preservesign
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=pitcairn < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=pitcairn < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %t.ieee | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %t.preservesign | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %t.ieee | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %t.preservesign | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %t.ieee | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %t.preservesign | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %t.ieee | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %t.preservesign | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s
define float @v_fdiv_f32(float %a, float %b) #1 {
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
index 5f18c0cd2aca5..6fc08d5d52e62 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
@@ -1,197 +1,241 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=CI %s
-; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=VI %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=CI %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=VI %s
define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {
; CI-LABEL: frem_f16:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
-; CI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0xd
-; CI-NEXT: ; implicit-def: $vgpr1
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_load_dword s0, s[10:11], 0x0
-; CI-NEXT: s_load_dword s1, s[2:3], 0x2
-; CI-NEXT: s_mov_b32 s2, 1
+; CI-NEXT: s_load_dword s2, s[2:3], 0x0
+; CI-NEXT: s_load_dword s3, s[4:5], 0x2
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s0|
-; CI-NEXT: v_cvt_f32_f16_e64 v0, |s1|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v0
-; CI-NEXT: s_cbranch_vccz .LBB0_2
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; CI-NEXT: s_mov_b32 s5, 1
+; CI-NEXT: ; implicit-def: $sgpr4
+; CI-NEXT: s_cbranch_scc0 .LBB0_2
; CI-NEXT: ; %bb.1: ; %frem.else
-; CI-NEXT: s_and_b32 s2, s0, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0
-; CI-NEXT: v_mov_b32_e32 v1, s2
-; CI-NEXT: v_mov_b32_e32 v3, s0
-; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: s_and_b32 s6, s2, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; CI-NEXT: s_cselect_b32 s4, s6, s2
+; CI-NEXT: s_mov_b32 s5, 0
; CI-NEXT: .LBB0_2: ; %Flow18
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s5, s5, 1
+; CI-NEXT: s_cmp_lg_u32 s5, 0
; CI-NEXT: s_cbranch_scc1 .LBB0_8
; CI-NEXT: ; %bb.3: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f32_e32 v1, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v1, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; CI-NEXT: v_readfirstlane_b32 s7, v1
+; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11
+; CI-NEXT: v_readfirstlane_b32 s6, v1
; CI-NEXT: v_frexp_mant_f32_e32 v1, v0
-; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1
-; CI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5
-; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; CI-NEXT: v_rcp_f32_e32 v8, v3
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1
+; CI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s5, s7, -1
+; CI-NEXT: s_add_i32 s4, s8, -1
+; CI-NEXT: s_sub_i32 s5, s5, s4
+; CI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; CI-NEXT: v_fma_f32 v8, v9, v8, v8
-; CI-NEXT: v_mul_f32_e32 v9, v7, v8
-; CI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; CI-NEXT: v_fma_f32 v9, v10, v8, v9
-; CI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2
-; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB0_6
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s5, 11
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB0_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v2, vcc, 11, v5
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; CI-NEXT: s_add_i32 s7, s7, 11
+; CI-NEXT: s_sub_i32 s5, s7, s8
; CI-NEXT: .LBB0_5: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v5, v4
-; CI-NEXT: v_mul_f32_e32 v4, v5, v3
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v6, v4, v1
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2
-; CI-NEXT: s_cbranch_vccnz .LBB0_5
+; CI-NEXT: v_mul_f32_e32 v2, s6, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s6
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s7, v2
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: s_cselect_b32 s7, s8, s7
+; CI-NEXT: v_ldexp_f32_e64 v2, s7, 11
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: s_add_i32 s5, s5, -11
+; CI-NEXT: s_cmp_gt_i32 s5, 11
+; CI-NEXT: s_mov_b32 s7, s6
+; CI-NEXT: s_mov_b32 s6, s8
+; CI-NEXT: s_cbranch_scc1 .LBB0_5
; CI-NEXT: s_branch .LBB0_7
; CI-NEXT: .LBB0_6:
-; CI-NEXT: v_mov_b32_e32 v5, v4
+; CI-NEXT: s_mov_b32 s7, s6
; CI-NEXT: .LBB0_7: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v2, vcc, -10, v2
-; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2
-; CI-NEXT: v_mul_f32_e32 v3, v2, v3
-; CI-NEXT: v_rndne_f32_e32 v3, v3
-; CI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; CI-NEXT: v_add_f32_e32 v1, v2, v1
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0
+; CI-NEXT: s_add_i32 s5, s5, -10
+; CI-NEXT: v_mov_b32_e32 v2, s5
+; CI-NEXT: v_ldexp_f32_e32 v2, s7, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s5, v1
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: s_cselect_b32 s5, s6, s5
+; CI-NEXT: v_mov_b32_e32 v0, s4
+; CI-NEXT: v_ldexp_f32_e32 v0, s5, v0
; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: s_and_b32 s2, s0, 0x8000
-; CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; CI-NEXT: v_or_b32_e32 v1, s2, v0
+; CI-NEXT: s_and_b32 s5, s2, 0xffff8000
+; CI-NEXT: v_readfirstlane_b32 s4, v0
+; CI-NEXT: s_and_b32 s4, s4, 0x7fff
+; CI-NEXT: s_or_b32 s4, s4, s5
; CI-NEXT: .LBB0_8: ; %Flow19
-; CI-NEXT: v_cvt_f32_f16_e32 v0, s1
-; CI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; CI-NEXT: s_mov_b32 s10, -1
-; CI-NEXT: s_mov_b32 s11, 0xf000
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s3
+; CI-NEXT: v_mov_b32_e32 v1, 0x7f800000
; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v0, |s0|
-; CI-NEXT: v_cmp_nge_f32_e64 s[0:1], v0, v2
-; CI-NEXT: v_mov_b32_e32 v0, 0x7e00
-; CI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
-; CI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; CI-NEXT: buffer_store_short v0, off, s[8:11], 0
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s2|
+; CI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; CI-NEXT: s_cselect_b32 s5, 1, 0
+; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; CI-NEXT: s_or_b64 s[2:3], vcc, vcc
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s5, 0
+; CI-NEXT: s_cselect_b32 s3, 0x7e00, s4
+; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_cselect_b32 s2, s3, 0x7e00
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: buffer_store_short v0, off, s[0:3], 0
; CI-NEXT: s_endpgm
;
; VI-LABEL: frem_f16:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
-; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34
-; VI-NEXT: ; implicit-def: $vgpr2
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_load_dword s0, s[10:11], 0x0
-; VI-NEXT: s_load_dword s1, s[2:3], 0x8
-; VI-NEXT: s_mov_b32 s2, 1
+; VI-NEXT: s_load_dword s2, s[2:3], 0x0
+; VI-NEXT: s_load_dword s3, s[4:5], 0x8
+; VI-NEXT: s_mov_b32 s5, 1
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v1, |s0|
-; VI-NEXT: v_cvt_f32_f16_e64 v0, |s1|
+; VI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
-; VI-NEXT: s_cbranch_vccz .LBB0_2
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cbranch_scc0 .LBB0_2
; VI-NEXT: ; %bb.1: ; %frem.else
-; VI-NEXT: s_and_b32 s2, s0, 0x8000
+; VI-NEXT: s_and_b32 s4, s2, 0xffff8000
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v3, s0
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cselect_b32 s4, s4, s2
+; VI-NEXT: s_mov_b32 s5, 0
; VI-NEXT: .LBB0_2: ; %Flow18
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s5, s5, 1
+; VI-NEXT: s_cmp_lg_u32 s5, 0
; VI-NEXT: s_cbranch_scc1 .LBB0_8
; VI-NEXT: ; %bb.3: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e32 v2, v1
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v1
+; VI-NEXT: v_ldexp_f32 v1, v2, 11
+; VI-NEXT: v_readfirstlane_b32 s6, v1
; VI-NEXT: v_frexp_mant_f32_e32 v1, v0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
-; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v5
-; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6
-; VI-NEXT: v_ldexp_f32 v1, v1, 1
-; VI-NEXT: v_ldexp_f32 v4, v2, 11
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v3, v0
-; VI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; VI-NEXT: v_rcp_f32_e32 v8, v3
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; VI-NEXT: v_readfirstlane_b32 s8, v0
+; VI-NEXT: v_ldexp_f32 v0, v1, 1
+; VI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s5, s7, -1
+; VI-NEXT: s_add_i32 s4, s8, -1
+; VI-NEXT: s_sub_i32 s5, s5, s4
+; VI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[10:11], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; VI-NEXT: v_fma_f32 v8, v9, v8, v8
-; VI-NEXT: v_mul_f32_e32 v9, v7, v8
-; VI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; VI-NEXT: v_fma_f32 v9, v10, v8, v9
-; VI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2
-; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB0_6
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s5, 11
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB0_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v2, vcc, 11, v5
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6
+; VI-NEXT: s_add_i32 s7, s7, 11
+; VI-NEXT: s_sub_i32 s5, s7, s8
; VI-NEXT: .LBB0_5: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v5, v4
-; VI-NEXT: v_mul_f32_e32 v4, v5, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v6, v4, v1
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2
-; VI-NEXT: v_ldexp_f32 v4, v4, 11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2
-; VI-NEXT: s_cbranch_vccnz .LBB0_5
+; VI-NEXT: v_mul_f32_e32 v2, s6, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s6
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: s_cselect_b32 s7, s8, s7
+; VI-NEXT: v_ldexp_f32 v2, s7, 11
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: s_add_i32 s5, s5, -11
+; VI-NEXT: s_cmp_gt_i32 s5, 11
+; VI-NEXT: s_mov_b32 s7, s6
+; VI-NEXT: s_mov_b32 s6, s8
+; VI-NEXT: s_cbranch_scc1 .LBB0_5
; VI-NEXT: s_branch .LBB0_7
; VI-NEXT: .LBB0_6:
-; VI-NEXT: v_mov_b32_e32 v5, v4
+; VI-NEXT: s_mov_b32 s7, s6
; VI-NEXT: .LBB0_7: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v2, vcc, -10, v2
-; VI-NEXT: v_ldexp_f32 v2, v5, v2
-; VI-NEXT: v_mul_f32_e32 v3, v2, v3
-; VI-NEXT: v_rndne_f32_e32 v3, v3
-; VI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_ldexp_f32 v0, v1, v0
+; VI-NEXT: s_add_i32 s5, s5, -10
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: v_ldexp_f32 v2, s7, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s5, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: s_cselect_b32 s5, s6, s5
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_ldexp_f32 v0, s5, v0
; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-NEXT: s_and_b32 s2, s0, 0x8000
-; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; VI-NEXT: v_or_b32_e32 v2, s2, v0
+; VI-NEXT: s_and_b32 s5, s2, 0xffff8000
+; VI-NEXT: v_readfirstlane_b32 s4, v0
+; VI-NEXT: s_and_b32 s4, s4, 0x7fff
+; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: .LBB0_8: ; %Flow19
+; VI-NEXT: v_cmp_nlg_f16_e64 s[6:7], s3, 0
; VI-NEXT: v_mov_b32_e32 v0, 0x7c00
-; VI-NEXT: v_cmp_nlg_f16_e64 vcc, s1, 0
-; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |s0|, v0
-; VI-NEXT: v_mov_b32_e32 v0, 0x7e00
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc
-; VI-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
-; VI-NEXT: v_mov_b32_e32 v0, s8
-; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s2|, v0
+; VI-NEXT: s_cselect_b32 s5, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s5, 0
+; VI-NEXT: s_cselect_b32 s3, 0x7e00, s4
+; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_cselect_b32 s2, s3, 0x7e00
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
%gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4
@@ -214,7 +258,8 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; CI-NEXT: v_cvt_f32_f16_e32 v0, s6
; CI-NEXT: v_cvt_f32_f16_e32 v1, s4
; CI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0
-; CI-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; CI-NEXT: v_div_scale_f32 v3, s[2:3], v0, v1, v0
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
; CI-NEXT: v_rcp_f32_e32 v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0
@@ -224,6 +269,7 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; CI-NEXT: v_fma_f32 v5, v6, v4, v5
; CI-NEXT: v_fma_f32 v2, -v2, v5, v3
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
@@ -258,8 +304,9 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; VI-NEXT: v_mac_f32_e32 v4, v5, v3
; VI-NEXT: v_mad_f32 v0, -v2, v4, v0
; VI-NEXT: v_mul_f32_e32 v0, v0, v3
-; VI-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; VI-NEXT: v_add_f32_e32 v0, v0, v4
+; VI-NEXT: v_readfirstlane_b32 s3, v0
+; VI-NEXT: s_and_b32 s3, s3, 0xff800000
+; VI-NEXT: v_add_f32_e32 v0, s3, v4
; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
; VI-NEXT: v_div_fixup_f16 v0, v0, v1, s2
; VI-NEXT: v_trunc_f16_e32 v0, v0
@@ -288,7 +335,8 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; CI-NEXT: v_cvt_f32_f16_e32 v0, s6
; CI-NEXT: v_cvt_f32_f16_e32 v1, s4
; CI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0
-; CI-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; CI-NEXT: v_div_scale_f32 v3, s[2:3], v0, v1, v0
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
; CI-NEXT: v_rcp_f32_e32 v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0
@@ -298,6 +346,7 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; CI-NEXT: v_fma_f32 v5, v6, v4, v5
; CI-NEXT: v_fma_f32 v2, -v2, v5, v3
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
@@ -332,8 +381,9 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: v_mac_f32_e32 v4, v5, v3
; VI-NEXT: v_mad_f32 v0, -v2, v4, v0
; VI-NEXT: v_mul_f32_e32 v0, v0, v3
-; VI-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; VI-NEXT: v_add_f32_e32 v0, v0, v4
+; VI-NEXT: v_readfirstlane_b32 s3, v0
+; VI-NEXT: s_and_b32 s3, s3, 0xff800000
+; VI-NEXT: v_add_f32_e32 v0, s3, v4
; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
; VI-NEXT: v_div_fixup_f16 v0, v0, v1, s2
; VI-NEXT: v_trunc_f16_e32 v0, v0
@@ -358,88 +408,106 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dword s2, s[2:3], 0x0
; CI-NEXT: s_load_dword s3, s[4:5], 0x4
-; CI-NEXT: s_mov_b32 s4, 1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3
-; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s2|, |v0|
-; CI-NEXT: ; implicit-def: $vgpr0
-; CI-NEXT: s_cbranch_vccz .LBB3_2
+; CI-NEXT: v_cmp_ngt_f32_e64 s[4:5], |s2|, |v0|
+; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; CI-NEXT: s_mov_b32 s5, 1
+; CI-NEXT: ; implicit-def: $sgpr4
+; CI-NEXT: s_cbranch_scc0 .LBB3_2
; CI-NEXT: ; %bb.1: ; %frem.else
-; CI-NEXT: s_and_b32 s4, s2, 0x80000000
-; CI-NEXT: v_mov_b32_e32 v1, s3
-; CI-NEXT: v_mov_b32_e32 v0, s2
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s2|, |v1|
-; CI-NEXT: v_mov_b32_e32 v1, s4
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CI-NEXT: s_mov_b32 s4, 0
+; CI-NEXT: v_mov_b32_e32 v0, s3
+; CI-NEXT: s_and_b32 s6, s2, 0x80000000
+; CI-NEXT: v_cmp_eq_f32_e64 s[4:5], |s2|, |v0|
+; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; CI-NEXT: s_cselect_b32 s4, s6, s2
+; CI-NEXT: s_mov_b32 s5, 0
; CI-NEXT: .LBB3_2: ; %Flow16
-; CI-NEXT: s_xor_b32 s4, s4, 1
-; CI-NEXT: s_cmp_lg_u32 s4, 0
+; CI-NEXT: s_xor_b32 s5, s5, 1
+; CI-NEXT: s_cmp_lg_u32 s5, 0
; CI-NEXT: s_cbranch_scc1 .LBB3_8
; CI-NEXT: ; %bb.3: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f32_e64 v1, |s3|
-; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1
-; CI-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v0, |s2|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s2|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s3|
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5
-; CI-NEXT: v_ldexp_f32_e64 v4, v0, 12
-; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; CI-NEXT: v_rcp_f32_e32 v8, v3
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s2|
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s3|
+; CI-NEXT: v_readfirstlane_b32 s7, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s3|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1
+; CI-NEXT: v_readfirstlane_b32 s8, v1
+; CI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s5, s7, -1
+; CI-NEXT: s_add_i32 s4, s8, -1
+; CI-NEXT: s_sub_i32 s5, s5, s4
+; CI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; CI-NEXT: v_fma_f32 v8, v9, v8, v8
-; CI-NEXT: v_mul_f32_e32 v9, v7, v8
-; CI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; CI-NEXT: v_fma_f32 v9, v10, v8, v9
-; CI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2
-; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB3_6
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s5, 12
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB3_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v2, vcc, 12, v5
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; CI-NEXT: s_add_i32 s7, s7, 12
+; CI-NEXT: s_sub_i32 s5, s7, s8
; CI-NEXT: .LBB3_5: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v5, v4
-; CI-NEXT: v_mul_f32_e32 v4, v5, v3
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v6, v4, v1
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_add_i32_e32 v2, vcc, -12, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 12
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2
-; CI-NEXT: s_cbranch_vccnz .LBB3_5
+; CI-NEXT: v_mul_f32_e32 v2, s6, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s6
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s7, v2
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: s_cselect_b32 s7, s8, s7
+; CI-NEXT: v_ldexp_f32_e64 v2, s7, 12
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: s_add_i32 s5, s5, -12
+; CI-NEXT: s_cmp_gt_i32 s5, 12
+; CI-NEXT: s_mov_b32 s7, s6
+; CI-NEXT: s_mov_b32 s6, s8
+; CI-NEXT: s_cbranch_scc1 .LBB3_5
; CI-NEXT: s_branch .LBB3_7
; CI-NEXT: .LBB3_6:
-; CI-NEXT: v_mov_b32_e32 v5, v4
+; CI-NEXT: s_mov_b32 s7, s6
; CI-NEXT: .LBB3_7: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2
-; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2
-; CI-NEXT: v_mul_f32_e32 v3, v2, v3
-; CI-NEXT: v_rndne_f32_e32 v3, v3
-; CI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; CI-NEXT: v_add_f32_e32 v1, v2, v1
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0
-; CI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; CI-NEXT: s_and_b32 s4, s2, 0x80000000
-; CI-NEXT: v_or_b32_e32 v0, s4, v0
+; CI-NEXT: s_add_i32 s5, s5, -11
+; CI-NEXT: v_mov_b32_e32 v2, s5
+; CI-NEXT: v_ldexp_f32_e32 v2, s7, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s5, v1
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: s_cselect_b32 s5, s6, s5
+; CI-NEXT: v_mov_b32_e32 v0, s4
+; CI-NEXT: v_ldexp_f32_e32 v0, s5, v0
+; CI-NEXT: v_readfirstlane_b32 s4, v0
+; CI-NEXT: s_bitset0_b32 s4, 31
+; CI-NEXT: s_and_b32 s5, s2, 0x80000000
+; CI-NEXT: s_or_b32 s4, s4, s5
; CI-NEXT: .LBB3_8: ; %Flow17
-; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s3, 0
-; CI-NEXT: v_mov_b32_e32 v1, 0x7fc00000
-; CI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s2|, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; CI-NEXT: v_cmp_nlg_f32_e64 s[6:7], s3, 0
+; CI-NEXT: v_mov_b32_e32 v0, 0x7f800000
+; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s2|, v0
+; CI-NEXT: s_cselect_b32 s4, 0x7fc00000, s4
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000
+; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
@@ -452,89 +520,107 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[2:3], 0x0
; VI-NEXT: s_load_dword s3, s[4:5], 0x10
-; VI-NEXT: s_mov_b32 s4, 1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s2|, |v0|
-; VI-NEXT: ; implicit-def: $vgpr0
-; VI-NEXT: s_cbranch_vccz .LBB3_2
+; VI-NEXT: v_cmp_ngt_f32_e64 s[4:5], |s2|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: s_mov_b32 s5, 1
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: s_cbranch_scc0 .LBB3_2
; VI-NEXT: ; %bb.1: ; %frem.else
-; VI-NEXT: s_and_b32 s4, s2, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s2|, |v1|
-; VI-NEXT: v_mov_b32_e32 v1, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_mov_b32 s4, 0
+; VI-NEXT: v_mov_b32_e32 v0, s3
+; VI-NEXT: s_and_b32 s6, s2, 0x80000000
+; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], |s2|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: s_cselect_b32 s4, s6, s2
+; VI-NEXT: s_mov_b32 s5, 0
; VI-NEXT: .LBB3_2: ; %Flow16
-; VI-NEXT: s_xor_b32 s4, s4, 1
-; VI-NEXT: s_cmp_lg_u32 s4, 0
+; VI-NEXT: s_xor_b32 s5, s5, 1
+; VI-NEXT: s_cmp_lg_u32 s5, 0
; VI-NEXT: s_cbranch_scc1 .LBB3_8
; VI-NEXT: ; %bb.3: ; %frem.compute
-; VI-NEXT: v_frexp_mant_f32_e64 v1, |s3|
-; VI-NEXT: v_ldexp_f32 v1, v1, 1
-; VI-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v0, |s2|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s2|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s3|
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5
-; VI-NEXT: v_ldexp_f32 v4, v0, 12
-; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; VI-NEXT: v_rcp_f32_e32 v8, v3
+; VI-NEXT: v_ldexp_f32 v0, v0, 12
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s2|
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s3|
+; VI-NEXT: v_readfirstlane_b32 s7, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s3|
+; VI-NEXT: v_ldexp_f32 v0, v0, 1
+; VI-NEXT: v_readfirstlane_b32 s8, v1
+; VI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s5, s7, -1
+; VI-NEXT: s_add_i32 s4, s8, -1
+; VI-NEXT: s_sub_i32 s5, s5, s4
+; VI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[10:11], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; VI-NEXT: v_fma_f32 v8, v9, v8, v8
-; VI-NEXT: v_mul_f32_e32 v9, v7, v8
-; VI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; VI-NEXT: v_fma_f32 v9, v10, v8, v9
-; VI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2
-; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB3_6
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s5, 12
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB3_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v5
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6
+; VI-NEXT: s_add_i32 s7, s7, 12
+; VI-NEXT: s_sub_i32 s5, s7, s8
; VI-NEXT: .LBB3_5: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v5, v4
-; VI-NEXT: v_mul_f32_e32 v4, v5, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v6, v4, v1
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, -12, v2
-; VI-NEXT: v_ldexp_f32 v4, v4, 12
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2
-; VI-NEXT: s_cbranch_vccnz .LBB3_5
+; VI-NEXT: v_mul_f32_e32 v2, s6, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s6
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: s_cselect_b32 s7, s8, s7
+; VI-NEXT: v_ldexp_f32 v2, s7, 12
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: s_add_i32 s5, s5, -12
+; VI-NEXT: s_cmp_gt_i32 s5, 12
+; VI-NEXT: s_mov_b32 s7, s6
+; VI-NEXT: s_mov_b32 s6, s8
+; VI-NEXT: s_cbranch_scc1 .LBB3_5
; VI-NEXT: s_branch .LBB3_7
; VI-NEXT: .LBB3_6:
-; VI-NEXT: v_mov_b32_e32 v5, v4
+; VI-NEXT: s_mov_b32 s7, s6
; VI-NEXT: .LBB3_7: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2
-; VI-NEXT: v_ldexp_f32 v2, v5, v2
-; VI-NEXT: v_mul_f32_e32 v3, v2, v3
-; VI-NEXT: v_rndne_f32_e32 v3, v3
-; VI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_ldexp_f32 v0, v1, v0
-; VI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; VI-NEXT: s_and_b32 s4, s2, 0x80000000
-; VI-NEXT: v_or_b32_e32 v0, s4, v0
+; VI-NEXT: s_add_i32 s5, s5, -11
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: v_ldexp_f32 v2, s7, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s5, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: s_cselect_b32 s5, s6, s5
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_ldexp_f32 v0, s5, v0
+; VI-NEXT: v_readfirstlane_b32 s4, v0
+; VI-NEXT: s_bitset0_b32 s4, 31
+; VI-NEXT: s_and_b32 s5, s2, 0x80000000
+; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: .LBB3_8: ; %Flow17
-; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s3, 0
-; VI-NEXT: v_mov_b32_e32 v1, 0x7fc00000
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s2|, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc
+; VI-NEXT: v_cmp_nlg_f32_e64 s[6:7], s3, 0
+; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000
+; VI-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s2|, v0
+; VI-NEXT: s_cselect_b32 s4, 0x7fc00000, s4
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000
; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -557,7 +643,8 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6
-; CI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; CI-NEXT: v_div_scale_f32 v2, s[2:3], s6, v0, s6
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
@@ -567,6 +654,7 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
; CI-NEXT: v_fma_f32 v4, v5, v3, v4
; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
@@ -586,7 +674,8 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6
-; VI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; VI-NEXT: v_div_scale_f32 v2, s[2:3], s6, v0, s6
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
@@ -596,6 +685,7 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
; VI-NEXT: v_fma_f32 v4, v5, v3, v4
; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; VI-NEXT: v_div_fixup_f32 v1, v1, v0, s6
; VI-NEXT: v_trunc_f32_e32 v1, v1
@@ -623,7 +713,8 @@ define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6
-; CI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; CI-NEXT: v_div_scale_f32 v2, s[2:3], s6, v0, s6
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
@@ -633,6 +724,7 @@ define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(
; CI-NEXT: v_fma_f32 v4, v5, v3, v4
; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
@@ -652,7 +744,8 @@ define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6
-; VI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; VI-NEXT: v_div_scale_f32 v2, s[2:3], s6, v0, s6
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
@@ -662,6 +755,7 @@ define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: v_fma_f32 v4, v5, v3, v4
; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; VI-NEXT: v_div_fixup_f32 v1, v1, v0, s6
; VI-NEXT: v_trunc_f32_e32 v1, v1
@@ -683,108 +777,126 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; CI-NEXT: s_mov_b32 s6, 1
+; CI-NEXT: s_mov_b32 s8, 1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
-; CI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[2:3]|, |v[0:1]|
-; CI-NEXT: ; implicit-def: $vgpr0_vgpr1
-; CI-NEXT: s_cbranch_vccz .LBB6_2
+; CI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[2:3]|, |v[0:1]|
+; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; CI-NEXT: ; implicit-def: $sgpr6_sgpr7
+; CI-NEXT: s_cbranch_scc0 .LBB6_2
; CI-NEXT: ; %bb.1: ; %frem.else
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |s[2:3]|, |v[0:1]|
+; CI-NEXT: v_cmp_eq_f64_e64 s[8:9], |s[2:3]|, |v[0:1]|
; CI-NEXT: s_mov_b32 s6, 0
; CI-NEXT: s_brev_b32 s7, 1
; CI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7]
-; CI-NEXT: v_mov_b32_e32 v0, s6
-; CI-NEXT: v_mov_b32_e32 v1, s7
-; CI-NEXT: v_mov_b32_e32 v2, s2
-; CI-NEXT: v_mov_b32_e32 v3, s3
-; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; CI-NEXT: s_mov_b32 s6, 0
+; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9]
+; CI-NEXT: s_cselect_b64 s[6:7], s[6:7], s[2:3]
+; CI-NEXT: s_mov_b32 s8, 0
; CI-NEXT: .LBB6_2: ; %Flow16
-; CI-NEXT: s_xor_b32 s6, s6, 1
-; CI-NEXT: s_cmp_lg_u32 s6, 0
+; CI-NEXT: s_xor_b32 s8, s8, 1
+; CI-NEXT: s_cmp_lg_u32 s8, 0
; CI-NEXT: s_cbranch_scc1 .LBB6_8
; CI-NEXT: ; %bb.3: ; %frem.compute
; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
-; CI-NEXT: v_frexp_exp_i32_f64_e64 v6, |s[2:3]|
-; CI-NEXT: v_frexp_exp_i32_f64_e64 v7, |s[4:5]|
-; CI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
+; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[2:3]|
+; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[4:5]|
+; CI-NEXT: s_add_i32 s11, s8, -1
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: v_readfirstlane_b32 s7, v1
; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]|
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v6
-; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v7
-; CI-NEXT: v_sub_i32_e32 v9, vcc, v2, v8
+; CI-NEXT: v_readfirstlane_b32 s9, v2
+; CI-NEXT: s_add_i32 s10, s9, -1
+; CI-NEXT: s_sub_i32 s11, s11, s10
; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
-; CI-NEXT: v_div_scale_f64 v[2:3], s[6:7], v[0:1], v[0:1], 1.0
-; CI-NEXT: v_div_scale_f64 v[14:15], vcc, 1.0, v[0:1], 1.0
-; CI-NEXT: v_rcp_f64_e32 v[10:11], v[2:3]
-; CI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
-; CI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; CI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
-; CI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; CI-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
-; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15]
-; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[12:13]
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v9
+; CI-NEXT: v_div_scale_f64 v[2:3], s[12:13], v[0:1], v[0:1], 1.0
+; CI-NEXT: v_div_scale_f64 v[8:9], s[12:13], 1.0, v[0:1], 1.0
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: s_cmp_le_i32 s11, 26
+; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
+; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
+; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
+; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB6_6
+; CI-NEXT: s_cbranch_scc1 .LBB6_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v6, vcc, 26, v6
-; CI-NEXT: v_sub_i32_e32 v9, vcc, v6, v7
+; CI-NEXT: s_add_i32 s8, s8, 26
+; CI-NEXT: s_sub_i32 s11, s8, s9
; CI-NEXT: .LBB6_5: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mov_b32_e32 v6, v4
-; CI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3]
+; CI-NEXT: v_mul_f64 v[4:5], s[6:7], v[2:3]
; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
-; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
+; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[6:7]
; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; CI-NEXT: v_add_f64 v[10:11], v[4:5], v[0:1]
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
-; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; CI-NEXT: v_add_i32_e32 v9, vcc, 0xffffffe6, v9
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v9
-; CI-NEXT: s_cbranch_vccnz .LBB6_5
+; CI-NEXT: v_readfirstlane_b32 s8, v4
+; CI-NEXT: v_readfirstlane_b32 s9, v5
+; CI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1]
+; CI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; CI-NEXT: v_readfirstlane_b32 s12, v4
+; CI-NEXT: v_readfirstlane_b32 s13, v5
+; CI-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
+; CI-NEXT: v_ldexp_f64 v[4:5], s[8:9], 26
+; CI-NEXT: s_sub_i32 s11, s11, 26
+; CI-NEXT: s_cmp_gt_i32 s11, 26
+; CI-NEXT: s_mov_b64 s[8:9], s[6:7]
+; CI-NEXT: v_readfirstlane_b32 s12, v4
+; CI-NEXT: v_readfirstlane_b32 s13, v5
+; CI-NEXT: s_mov_b64 s[6:7], s[12:13]
+; CI-NEXT: s_cbranch_scc1 .LBB6_5
; CI-NEXT: s_branch .LBB6_7
; CI-NEXT: .LBB6_6:
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mov_b32_e32 v6, v4
+; CI-NEXT: s_mov_b64 s[8:9], s[6:7]
; CI-NEXT: .LBB6_7: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v4, vcc, 0xffffffe7, v9
-; CI-NEXT: v_ldexp_f64 v[4:5], v[6:7], v4
-; CI-NEXT: s_mov_b32 s6, 0
-; CI-NEXT: s_brev_b32 s7, 1
-; CI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7]
+; CI-NEXT: s_sub_i32 s6, s11, 25
+; CI-NEXT: v_mov_b32_e32 v4, s6
+; CI-NEXT: v_ldexp_f64 v[4:5], s[8:9], v4
; CI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
; CI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; CI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
-; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
-; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; CI-NEXT: v_or_b32_e32 v0, s6, v0
-; CI-NEXT: v_or_b32_e32 v1, s7, v1
+; CI-NEXT: v_readfirstlane_b32 s6, v2
+; CI-NEXT: v_readfirstlane_b32 s7, v3
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: v_readfirstlane_b32 s9, v1
+; CI-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
+; CI-NEXT: v_mov_b32_e32 v0, s10
+; CI-NEXT: v_ldexp_f64 v[0:1], s[6:7], v0
+; CI-NEXT: s_mov_b32 s8, 0
+; CI-NEXT: s_brev_b32 s9, 1
+; CI-NEXT: s_and_b64 s[8:9], s[2:3], s[8:9]
+; CI-NEXT: v_readfirstlane_b32 s7, v1
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: s_bitset0_b32 s7, 31
+; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; CI-NEXT: .LBB6_8: ; %Flow17
-; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[4:5], 0
-; CI-NEXT: v_mov_b32_e32 v2, 0x7ff80000
-; CI-NEXT: v_cndmask_b32_e64 v3, v0, 0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
+; CI-NEXT: v_cmp_nlg_f64_e64 s[4:5], s[4:5], 0
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, 0x7ff00000
-; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[0:1]
+; CI-NEXT: v_cmp_nge_f64_e64 s[2:3], |s[2:3]|, v[0:1]
+; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; CI-NEXT: s_mov_b32 s4, 0
+; CI-NEXT: s_mov_b32 s5, 0x7ff80000
+; CI-NEXT: s_cselect_b64 s[6:7], s[4:5], s[6:7]
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: s_cselect_b64 s[2:3], s[6:7], s[4:5]
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; CI-NEXT: s_endpgm
;
@@ -792,108 +904,126 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NEXT: s_mov_b32 s6, 1
+; VI-NEXT: s_mov_b32 s8, 1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
-; VI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[2:3]|, |v[0:1]|
-; VI-NEXT: ; implicit-def: $vgpr0_vgpr1
-; VI-NEXT: s_cbranch_vccz .LBB6_2
+; VI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[2:3]|, |v[0:1]|
+; VI-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-NEXT: ; implicit-def: $sgpr6_sgpr7
+; VI-NEXT: s_cbranch_scc0 .LBB6_2
; VI-NEXT: ; %bb.1: ; %frem.else
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |s[2:3]|, |v[0:1]|
+; VI-NEXT: v_cmp_eq_f64_e64 s[8:9], |s[2:3]|, |v[0:1]|
; VI-NEXT: s_mov_b32 s6, 0
; VI-NEXT: s_brev_b32 s7, 1
; VI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7]
-; VI-NEXT: v_mov_b32_e32 v0, s6
-; VI-NEXT: v_mov_b32_e32 v1, s7
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v3, s3
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-NEXT: s_mov_b32 s6, 0
+; VI-NEXT: s_cmp_lg_u64 s[8:9], 0
+; VI-NEXT: s_cselect_b64 s[6:7], s[6:7], s[2:3]
+; VI-NEXT: s_mov_b32 s8, 0
; VI-NEXT: .LBB6_2: ; %Flow16
-; VI-NEXT: s_xor_b32 s6, s6, 1
-; VI-NEXT: s_cmp_lg_u32 s6, 0
+; VI-NEXT: s_xor_b32 s8, s8, 1
+; VI-NEXT: s_cmp_lg_u32 s8, 0
; VI-NEXT: s_cbranch_scc1 .LBB6_8
; VI-NEXT: ; %bb.3: ; %frem.compute
; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
-; VI-NEXT: v_frexp_exp_i32_f64_e64 v6, |s[2:3]|
-; VI-NEXT: v_frexp_exp_i32_f64_e64 v7, |s[4:5]|
-; VI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
+; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[2:3]|
+; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[4:5]|
+; VI-NEXT: s_add_i32 s11, s8, -1
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: v_readfirstlane_b32 s7, v1
; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]|
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v6
-; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v7
-; VI-NEXT: v_sub_u32_e32 v9, vcc, v2, v8
+; VI-NEXT: v_readfirstlane_b32 s9, v2
+; VI-NEXT: s_add_i32 s10, s9, -1
+; VI-NEXT: s_sub_i32 s11, s11, s10
; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
-; VI-NEXT: v_div_scale_f64 v[2:3], s[6:7], v[0:1], v[0:1], 1.0
-; VI-NEXT: v_div_scale_f64 v[14:15], vcc, 1.0, v[0:1], 1.0
-; VI-NEXT: v_rcp_f64_e32 v[10:11], v[2:3]
-; VI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
-; VI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; VI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
-; VI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; VI-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
-; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15]
-; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[12:13]
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v9
+; VI-NEXT: v_div_scale_f64 v[2:3], s[12:13], v[0:1], v[0:1], 1.0
+; VI-NEXT: v_div_scale_f64 v[8:9], s[12:13], 1.0, v[0:1], 1.0
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: s_cmp_le_i32 s11, 26
+; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
+; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
+; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
+; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB6_6
+; VI-NEXT: s_cbranch_scc1 .LBB6_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v6, vcc, 26, v6
-; VI-NEXT: v_sub_u32_e32 v9, vcc, v6, v7
+; VI-NEXT: s_add_i32 s8, s8, 26
+; VI-NEXT: s_sub_i32 s11, s8, s9
; VI-NEXT: .LBB6_5: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: v_mov_b32_e32 v6, v4
-; VI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3]
+; VI-NEXT: v_mul_f64 v[4:5], s[6:7], v[2:3]
; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
-; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
+; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[6:7]
+; VI-NEXT: v_readfirstlane_b32 s8, v4
+; VI-NEXT: v_readfirstlane_b32 s9, v5
; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; VI-NEXT: v_add_f64 v[10:11], v[4:5], v[0:1]
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
-; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0xffffffe6, v9
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v9
-; VI-NEXT: s_cbranch_vccnz .LBB6_5
+; VI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1]
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s12, v4
+; VI-NEXT: v_readfirstlane_b32 s13, v5
+; VI-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
+; VI-NEXT: v_ldexp_f64 v[4:5], s[8:9], 26
+; VI-NEXT: s_sub_i32 s11, s11, 26
+; VI-NEXT: s_cmp_gt_i32 s11, 26
+; VI-NEXT: s_mov_b64 s[8:9], s[6:7]
+; VI-NEXT: v_readfirstlane_b32 s12, v4
+; VI-NEXT: v_readfirstlane_b32 s13, v5
+; VI-NEXT: s_mov_b64 s[6:7], s[12:13]
+; VI-NEXT: s_cbranch_scc1 .LBB6_5
; VI-NEXT: s_branch .LBB6_7
; VI-NEXT: .LBB6_6:
-; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: v_mov_b32_e32 v6, v4
+; VI-NEXT: s_mov_b64 s[8:9], s[6:7]
; VI-NEXT: .LBB6_7: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0xffffffe7, v9
-; VI-NEXT: v_ldexp_f64 v[4:5], v[6:7], v4
-; VI-NEXT: s_mov_b32 s6, 0
-; VI-NEXT: s_brev_b32 s7, 1
-; VI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7]
+; VI-NEXT: s_sub_i32 s6, s11, 25
+; VI-NEXT: v_mov_b32_e32 v4, s6
+; VI-NEXT: v_ldexp_f64 v[4:5], s[8:9], v4
; VI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; VI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
-; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; VI-NEXT: v_or_b32_e32 v0, s6, v0
-; VI-NEXT: v_or_b32_e32 v1, s7, v1
+; VI-NEXT: v_readfirstlane_b32 s6, v2
+; VI-NEXT: v_readfirstlane_b32 s7, v3
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s8, v0
+; VI-NEXT: v_readfirstlane_b32 s9, v1
+; VI-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
+; VI-NEXT: v_mov_b32_e32 v0, s10
+; VI-NEXT: v_ldexp_f64 v[0:1], s[6:7], v0
+; VI-NEXT: s_mov_b32 s8, 0
+; VI-NEXT: s_brev_b32 s9, 1
+; VI-NEXT: s_and_b64 s[8:9], s[2:3], s[8:9]
+; VI-NEXT: v_readfirstlane_b32 s7, v1
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: s_bitset0_b32 s7, 31
+; VI-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; VI-NEXT: .LBB6_8: ; %Flow17
-; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[4:5], 0
-; VI-NEXT: v_mov_b32_e32 v2, 0x7ff80000
-; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
+; VI-NEXT: v_cmp_nlg_f64_e64 s[4:5], s[4:5], 0
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0x7ff00000
-; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[0:1]
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
+; VI-NEXT: v_cmp_nge_f64_e64 s[2:3], |s[2:3]|, v[0:1]
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: s_mov_b32 s4, 0
+; VI-NEXT: s_mov_b32 s5, 0x7ff80000
+; VI-NEXT: s_cselect_b64 s[6:7], s[4:5], s[6:7]
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b64 s[2:3], s[6:7], s[4:5]
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
%r0 = load double, ptr addrspace(1) %in1, align 8
@@ -915,7 +1045,9 @@ define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1)
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3]
-; CI-NEXT: v_div_scale_f64 v[8:9], vcc, s[2:3], v[0:1], s[2:3]
+; CI-NEXT: v_div_scale_f64 v[8:9], s[4:5], s[2:3], v[0:1], s[2:3]
+; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
@@ -943,7 +1075,9 @@ define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1)
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3]
-; VI-NEXT: v_div_scale_f64 v[8:9], vcc, s[2:3], v[0:1], s[2:3]
+; VI-NEXT: v_div_scale_f64 v[8:9], s[4:5], s[2:3], v[0:1], s[2:3]
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
@@ -978,7 +1112,9 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3]
-; CI-NEXT: v_div_scale_f64 v[8:9], vcc, s[2:3], v[0:1], s[2:3]
+; CI-NEXT: v_div_scale_f64 v[8:9], s[4:5], s[2:3], v[0:1], s[2:3]
+; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
@@ -1006,7 +1142,9 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3]
-; VI-NEXT: v_div_scale_f64 v[8:9], vcc, s[2:3], v[0:1], s[2:3]
+; VI-NEXT: v_div_scale_f64 v[8:9], s[4:5], s[2:3], v[0:1], s[2:3]
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
@@ -1033,366 +1171,455 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {
; CI-LABEL: frem_v2f16:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
-; CI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0xd
-; CI-NEXT: ; implicit-def: $vgpr0
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_load_dword s0, s[10:11], 0x0
-; CI-NEXT: s_load_dword s1, s[2:3], 0x4
-; CI-NEXT: s_mov_b32 s2, 1
+; CI-NEXT: s_load_dword s2, s[2:3], 0x0
+; CI-NEXT: s_load_dword s3, s[4:5], 0x4
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s0|
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |s1|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v1
-; CI-NEXT: s_cbranch_vccz .LBB9_2
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; CI-NEXT: s_mov_b32 s5, 1
+; CI-NEXT: ; implicit-def: $sgpr4
+; CI-NEXT: s_cbranch_scc0 .LBB9_2
; CI-NEXT: ; %bb.1: ; %frem.else20
-; CI-NEXT: s_and_b32 s2, s0, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v1
-; CI-NEXT: v_mov_b32_e32 v0, s2
-; CI-NEXT: v_mov_b32_e32 v3, s0
-; CI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: s_and_b32 s6, s2, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; CI-NEXT: s_cselect_b32 s4, s6, s2
+; CI-NEXT: s_mov_b32 s5, 0
; CI-NEXT: .LBB9_2: ; %Flow57
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s5, s5, 1
+; CI-NEXT: s_cmp_lg_u32 s5, 0
; CI-NEXT: s_cbranch_scc1 .LBB9_8
; CI-NEXT: ; %bb.3: ; %frem.compute19
-; CI-NEXT: v_frexp_mant_f32_e32 v3, v1
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v1
-; CI-NEXT: v_ldexp_f32_e64 v1, v3, 1
-; CI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0
-; CI-NEXT: v_frexp_mant_f32_e32 v0, v2
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5
-; CI-NEXT: v_ldexp_f32_e64 v4, v0, 11
-; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; CI-NEXT: v_rcp_f32_e32 v8, v3
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; CI-NEXT: v_readfirstlane_b32 s7, v1
+; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11
+; CI-NEXT: v_readfirstlane_b32 s6, v1
+; CI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1
+; CI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s5, s7, -1
+; CI-NEXT: s_add_i32 s4, s8, -1
+; CI-NEXT: s_sub_i32 s5, s5, s4
+; CI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[10:11], s[10:11], s[10:11]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; CI-NEXT: v_fma_f32 v8, v9, v8, v8
-; CI-NEXT: v_mul_f32_e32 v9, v7, v8
-; CI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; CI-NEXT: v_fma_f32 v9, v10, v8, v9
-; CI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2
-; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB9_6
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s5, 11
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB9_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
-; CI-NEXT: v_add_i32_e32 v2, vcc, 11, v5
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; CI-NEXT: s_add_i32 s7, s7, 11
+; CI-NEXT: s_sub_i32 s5, s7, s8
; CI-NEXT: .LBB9_5: ; %frem.loop_body27
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v5, v4
-; CI-NEXT: v_mul_f32_e32 v4, v5, v3
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v6, v4, v1
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2
-; CI-NEXT: s_cbranch_vccnz .LBB9_5
+; CI-NEXT: v_mul_f32_e32 v2, s6, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s6
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s7, v2
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: s_cselect_b32 s7, s8, s7
+; CI-NEXT: v_ldexp_f32_e64 v2, s7, 11
+; CI-NEXT: v_readfirstlane_b32 s8, v2
+; CI-NEXT: s_add_i32 s5, s5, -11
+; CI-NEXT: s_cmp_gt_i32 s5, 11
+; CI-NEXT: s_mov_b32 s7, s6
+; CI-NEXT: s_mov_b32 s6, s8
+; CI-NEXT: s_cbranch_scc1 .LBB9_5
; CI-NEXT: s_branch .LBB9_7
; CI-NEXT: .LBB9_6:
-; CI-NEXT: v_mov_b32_e32 v5, v4
+; CI-NEXT: s_mov_b32 s7, s6
; CI-NEXT: .LBB9_7: ; %frem.loop_exit28
-; CI-NEXT: v_add_i32_e32 v2, vcc, -10, v2
-; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2
-; CI-NEXT: v_mul_f32_e32 v3, v2, v3
-; CI-NEXT: v_rndne_f32_e32 v3, v3
-; CI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; CI-NEXT: v_add_f32_e32 v1, v2, v1
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0
+; CI-NEXT: s_add_i32 s5, s5, -10
+; CI-NEXT: v_mov_b32_e32 v2, s5
+; CI-NEXT: v_ldexp_f32_e32 v2, s7, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s5, v1
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: s_cselect_b32 s5, s6, s5
+; CI-NEXT: v_mov_b32_e32 v0, s4
+; CI-NEXT: v_ldexp_f32_e32 v0, s5, v0
; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: s_and_b32 s2, s0, 0x8000
-; CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; CI-NEXT: v_or_b32_e32 v0, s2, v0
+; CI-NEXT: s_and_b32 s5, s2, 0xffff8000
+; CI-NEXT: v_readfirstlane_b32 s4, v0
+; CI-NEXT: s_and_b32 s4, s4, 0x7fff
+; CI-NEXT: s_or_b32 s4, s4, s5
; CI-NEXT: .LBB9_8: ; %Flow58
-; CI-NEXT: s_lshr_b32 s4, s0, 16
-; CI-NEXT: s_lshr_b32 s2, s1, 16
-; CI-NEXT: v_cvt_f32_f16_e64 v3, |s4|
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s2|
-; CI-NEXT: s_mov_b32 s3, 1
-; CI-NEXT: ; implicit-def: $vgpr1
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
-; CI-NEXT: s_cbranch_vccz .LBB9_10
+; CI-NEXT: s_lshr_b32 s5, s2, 16
+; CI-NEXT: s_lshr_b32 s6, s3, 16
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |s5|
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s6|
+; CI-NEXT: ; implicit-def: $sgpr7
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: s_mov_b32 s8, 1
+; CI-NEXT: s_cbranch_scc0 .LBB9_10
; CI-NEXT: ; %bb.9: ; %frem.else
-; CI-NEXT: s_and_b32 s3, s4, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; CI-NEXT: v_mov_b32_e32 v1, s3
-; CI-NEXT: v_mov_b32_e32 v4, s4
-; CI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; CI-NEXT: s_mov_b32 s3, 0
+; CI-NEXT: s_and_b32 s7, s5, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: s_cselect_b32 s7, s7, s5
+; CI-NEXT: s_mov_b32 s8, 0
; CI-NEXT: .LBB9_10: ; %Flow53
-; CI-NEXT: s_xor_b32 s3, s3, 1
-; CI-NEXT: s_cmp_lg_u32 s3, 0
+; CI-NEXT: s_xor_b32 s8, s8, 1
+; CI-NEXT: s_cmp_lg_u32 s8, 0
; CI-NEXT: s_cbranch_scc1 .LBB9_16
; CI-NEXT: ; %bb.11: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f32_e32 v4, v2
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v2
-; CI-NEXT: v_ldexp_f32_e64 v2, v4, 1
-; CI-NEXT: v_div_scale_f32 v4, s[6:7], v2, v2, 1.0
-; CI-NEXT: v_frexp_mant_f32_e32 v1, v3
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v3
-; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v6
-; CI-NEXT: v_ldexp_f32_e64 v5, v1, 11
-; CI-NEXT: v_add_i32_e32 v1, vcc, -1, v7
-; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v1
-; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0
-; CI-NEXT: v_rcp_f32_e32 v9, v4
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; CI-NEXT: v_readfirstlane_b32 s10, v1
+; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11
+; CI-NEXT: v_readfirstlane_b32 s9, v1
+; CI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; CI-NEXT: v_readfirstlane_b32 s11, v0
+; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1
+; CI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s8, s10, -1
+; CI-NEXT: s_add_i32 s7, s11, -1
+; CI-NEXT: s_sub_i32 s8, s8, s7
+; CI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v10, -v4, v9, 1.0
-; CI-NEXT: v_fma_f32 v9, v10, v9, v9
-; CI-NEXT: v_mul_f32_e32 v10, v8, v9
-; CI-NEXT: v_fma_f32 v11, -v4, v10, v8
-; CI-NEXT: v_fma_f32 v10, v11, v9, v10
-; CI-NEXT: v_fma_f32 v4, -v4, v10, v8
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v4, v4, v9, v10
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v3
-; CI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB9_14
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s8, 11
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB9_14
; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v3, vcc, 11, v6
-; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
+; CI-NEXT: s_add_i32 s10, s10, 11
+; CI-NEXT: s_sub_i32 s8, s10, s11
; CI-NEXT: .LBB9_13: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v6, v5
-; CI-NEXT: v_mul_f32_e32 v5, v6, v4
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v5, -v5, v2, v6
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v7, v5, v2
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; CI-NEXT: v_add_i32_e32 v3, vcc, -11, v3
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v3
-; CI-NEXT: s_cbranch_vccnz .LBB9_13
+; CI-NEXT: v_mul_f32_e32 v2, s9, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s9
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s12, v2
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s10, v2
+; CI-NEXT: s_cselect_b32 s10, s10, s12
+; CI-NEXT: v_ldexp_f32_e64 v2, s10, 11
+; CI-NEXT: v_readfirstlane_b32 s11, v2
+; CI-NEXT: s_add_i32 s8, s8, -11
+; CI-NEXT: s_cmp_gt_i32 s8, 11
+; CI-NEXT: s_mov_b32 s10, s9
+; CI-NEXT: s_mov_b32 s9, s11
+; CI-NEXT: s_cbranch_scc1 .LBB9_13
; CI-NEXT: s_branch .LBB9_15
; CI-NEXT: .LBB9_14:
-; CI-NEXT: v_mov_b32_e32 v6, v5
+; CI-NEXT: s_mov_b32 s10, s9
; CI-NEXT: .LBB9_15: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v3, vcc, -10, v3
-; CI-NEXT: v_ldexp_f32_e32 v3, v6, v3
-; CI-NEXT: v_mul_f32_e32 v4, v3, v4
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; CI-NEXT: v_add_f32_e32 v2, v3, v2
-; CI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; CI-NEXT: v_ldexp_f32_e32 v1, v2, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: s_and_b32 s3, s4, 0x8000
-; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; CI-NEXT: v_or_b32_e32 v1, s3, v1
+; CI-NEXT: s_add_i32 s8, s8, -10
+; CI-NEXT: v_mov_b32_e32 v2, s8
+; CI-NEXT: v_ldexp_f32_e32 v2, s10, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s10, v1
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: s_cselect_b32 s8, s8, s10
+; CI-NEXT: v_mov_b32_e32 v0, s7
+; CI-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_and_b32 s8, s5, 0xffff8000
+; CI-NEXT: v_readfirstlane_b32 s7, v0
+; CI-NEXT: s_and_b32 s7, s7, 0x7fff
+; CI-NEXT: s_or_b32 s7, s7, s8
; CI-NEXT: .LBB9_16: ; %Flow54
-; CI-NEXT: v_cvt_f32_f16_e32 v2, s1
-; CI-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v2
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s0|
-; CI-NEXT: s_mov_b32 s10, -1
-; CI-NEXT: s_mov_b32 s11, 0xf000
-; CI-NEXT: v_cmp_nge_f32_e64 s[0:1], v2, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v2, s2
-; CI-NEXT: v_cmp_nlg_f32_e64 s[2:3], 0, v2
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s4|
-; CI-NEXT: v_cmp_nge_f32_e64 s[4:5], v2, v3
-; CI-NEXT: v_mov_b32_e32 v2, 0x7e00
-; CI-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[2:3]
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]
-; CI-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
-; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; CI-NEXT: v_or_b32_e32 v0, v0, v1
-; CI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s3
+; CI-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s2|
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: s_cselect_b32 s8, 1, 0
+; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s6
+; CI-NEXT: s_or_b64 s[2:3], vcc, vcc
+; CI-NEXT: s_cselect_b32 s9, 1, 0
+; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s5|
+; CI-NEXT: s_or_b64 s[2:3], vcc, vcc
+; CI-NEXT: s_cselect_b32 s6, 1, 0
+; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; CI-NEXT: s_or_b64 s[2:3], vcc, vcc
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_and_b32 s3, 0xffff, s4
+; CI-NEXT: s_cmp_lg_u32 s8, 0
+; CI-NEXT: s_cselect_b32 s3, 0x7e00, s3
+; CI-NEXT: s_cmp_lg_u32 s9, 0
+; CI-NEXT: s_cselect_b32 s3, s3, 0x7e00
+; CI-NEXT: s_and_b32 s4, 0xffff, s7
+; CI-NEXT: s_cmp_lg_u32 s6, 0
+; CI-NEXT: s_cselect_b32 s4, 0x7e00, s4
+; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_cselect_b32 s2, s4, 0x7e00
+; CI-NEXT: s_lshl_b32 s2, s2, 16
+; CI-NEXT: s_or_b32 s2, s3, s2
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; CI-NEXT: s_endpgm
;
; VI-LABEL: frem_v2f16:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
-; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34
-; VI-NEXT: ; implicit-def: $vgpr0
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_load_dword s0, s[10:11], 0x0
-; VI-NEXT: s_load_dword s1, s[2:3], 0x10
-; VI-NEXT: s_mov_b32 s2, 1
+; VI-NEXT: s_load_dword s2, s[2:3], 0x0
+; VI-NEXT: s_load_dword s3, s[4:5], 0x10
+; VI-NEXT: s_mov_b32 s5, 1
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v2, |s0|
-; VI-NEXT: v_cvt_f32_f16_e64 v1, |s1|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v1
-; VI-NEXT: s_cbranch_vccz .LBB9_2
+; VI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cbranch_scc0 .LBB9_2
; VI-NEXT: ; %bb.1: ; %frem.else20
-; VI-NEXT: s_and_b32 s2, s0, 0x8000
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v1
-; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v3, s0
-; VI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: s_and_b32 s4, s2, 0xffff8000
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cselect_b32 s4, s4, s2
+; VI-NEXT: s_mov_b32 s5, 0
; VI-NEXT: .LBB9_2: ; %Flow57
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s5, s5, 1
+; VI-NEXT: s_cmp_lg_u32 s5, 0
; VI-NEXT: s_cbranch_scc1 .LBB9_8
; VI-NEXT: ; %bb.3: ; %frem.compute19
-; VI-NEXT: v_frexp_mant_f32_e32 v3, v1
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v1
-; VI-NEXT: v_ldexp_f32 v1, v3, 1
-; VI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0
-; VI-NEXT: v_frexp_mant_f32_e32 v0, v2
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5
-; VI-NEXT: v_ldexp_f32 v4, v0, 11
-; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; VI-NEXT: v_rcp_f32_e32 v8, v3
+; VI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; VI-NEXT: v_readfirstlane_b32 s7, v1
+; VI-NEXT: v_ldexp_f32 v1, v2, 11
+; VI-NEXT: v_readfirstlane_b32 s6, v1
+; VI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; VI-NEXT: v_readfirstlane_b32 s8, v0
+; VI-NEXT: v_ldexp_f32 v0, v1, 1
+; VI-NEXT: v_div_scale_f32 v1, s[10:11], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s5, s7, -1
+; VI-NEXT: s_add_i32 s4, s8, -1
+; VI-NEXT: s_sub_i32 s5, s5, s4
+; VI-NEXT: v_div_scale_f32 v2, s[10:11], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[10:11], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; VI-NEXT: v_fma_f32 v8, v9, v8, v8
-; VI-NEXT: v_mul_f32_e32 v9, v7, v8
-; VI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; VI-NEXT: v_fma_f32 v9, v10, v8, v9
-; VI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2
-; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB9_6
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s5, 11
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB9_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
-; VI-NEXT: v_add_u32_e32 v2, vcc, 11, v5
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6
+; VI-NEXT: s_add_i32 s7, s7, 11
+; VI-NEXT: s_sub_i32 s5, s7, s8
; VI-NEXT: .LBB9_5: ; %frem.loop_body27
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v5, v4
-; VI-NEXT: v_mul_f32_e32 v4, v5, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v6, v4, v1
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2
-; VI-NEXT: v_ldexp_f32 v4, v4, 11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2
-; VI-NEXT: s_cbranch_vccnz .LBB9_5
+; VI-NEXT: v_mul_f32_e32 v2, s6, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s6
+; VI-NEXT: v_readfirstlane_b32 s7, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: s_cselect_b32 s7, s8, s7
+; VI-NEXT: v_ldexp_f32 v2, s7, 11
+; VI-NEXT: v_readfirstlane_b32 s8, v2
+; VI-NEXT: s_add_i32 s5, s5, -11
+; VI-NEXT: s_cmp_gt_i32 s5, 11
+; VI-NEXT: s_mov_b32 s7, s6
+; VI-NEXT: s_mov_b32 s6, s8
+; VI-NEXT: s_cbranch_scc1 .LBB9_5
; VI-NEXT: s_branch .LBB9_7
; VI-NEXT: .LBB9_6:
-; VI-NEXT: v_mov_b32_e32 v5, v4
+; VI-NEXT: s_mov_b32 s7, s6
; VI-NEXT: .LBB9_7: ; %frem.loop_exit28
-; VI-NEXT: v_add_u32_e32 v2, vcc, -10, v2
-; VI-NEXT: v_ldexp_f32 v2, v5, v2
-; VI-NEXT: v_mul_f32_e32 v3, v2, v3
-; VI-NEXT: v_rndne_f32_e32 v3, v3
-; VI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_ldexp_f32 v0, v1, v0
+; VI-NEXT: s_add_i32 s5, s5, -10
+; VI-NEXT: v_mov_b32_e32 v2, s5
+; VI-NEXT: v_ldexp_f32 v2, s7, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s5, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: s_cselect_b32 s5, s6, s5
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_ldexp_f32 v0, s5, v0
; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-NEXT: s_and_b32 s2, s0, 0x8000
-; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; VI-NEXT: v_or_b32_e32 v0, s2, v0
+; VI-NEXT: s_and_b32 s5, s2, 0xffff8000
+; VI-NEXT: v_readfirstlane_b32 s4, v0
+; VI-NEXT: s_and_b32 s4, s4, 0x7fff
+; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: .LBB9_8: ; %Flow58
-; VI-NEXT: s_lshr_b32 s4, s0, 16
-; VI-NEXT: s_lshr_b32 s2, s1, 16
-; VI-NEXT: v_cvt_f32_f16_e64 v3, |s4|
-; VI-NEXT: v_cvt_f32_f16_e64 v2, |s2|
-; VI-NEXT: s_mov_b32 s3, 1
-; VI-NEXT: ; implicit-def: $vgpr1
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
-; VI-NEXT: s_cbranch_vccz .LBB9_10
+; VI-NEXT: s_lshr_b32 s5, s2, 16
+; VI-NEXT: s_lshr_b32 s6, s3, 16
+; VI-NEXT: v_cvt_f32_f16_e64 v1, |s5|
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |s6|
+; VI-NEXT: s_mov_b32 s8, 1
+; VI-NEXT: ; implicit-def: $sgpr7
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cbranch_scc0 .LBB9_10
; VI-NEXT: ; %bb.9: ; %frem.else
-; VI-NEXT: s_and_b32 s3, s4, 0x8000
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; VI-NEXT: s_mov_b32 s3, 0
+; VI-NEXT: s_and_b32 s7, s5, 0xffff8000
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cselect_b32 s7, s7, s5
+; VI-NEXT: s_mov_b32 s8, 0
; VI-NEXT: .LBB9_10: ; %Flow53
-; VI-NEXT: s_xor_b32 s3, s3, 1
-; VI-NEXT: s_cmp_lg_u32 s3, 0
+; VI-NEXT: s_xor_b32 s8, s8, 1
+; VI-NEXT: s_cmp_lg_u32 s8, 0
; VI-NEXT: s_cbranch_scc1 .LBB9_16
; VI-NEXT: ; %bb.11: ; %frem.compute
-; VI-NEXT: v_frexp_mant_f32_e32 v4, v2
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v2
-; VI-NEXT: v_ldexp_f32 v2, v4, 1
-; VI-NEXT: v_div_scale_f32 v4, s[6:7], v2, v2, 1.0
-; VI-NEXT: v_frexp_mant_f32_e32 v1, v3
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v3
-; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v6
-; VI-NEXT: v_ldexp_f32 v5, v1, 11
-; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v7
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0
-; VI-NEXT: v_rcp_f32_e32 v9, v4
+; VI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; VI-NEXT: v_readfirstlane_b32 s10, v1
+; VI-NEXT: v_ldexp_f32 v1, v2, 11
+; VI-NEXT: v_readfirstlane_b32 s9, v1
+; VI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; VI-NEXT: v_readfirstlane_b32 s11, v0
+; VI-NEXT: v_ldexp_f32 v0, v1, 1
+; VI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s8, s10, -1
+; VI-NEXT: s_add_i32 s7, s11, -1
+; VI-NEXT: s_sub_i32 s8, s8, s7
+; VI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v10, -v4, v9, 1.0
-; VI-NEXT: v_fma_f32 v9, v10, v9, v9
-; VI-NEXT: v_mul_f32_e32 v10, v8, v9
-; VI-NEXT: v_fma_f32 v11, -v4, v10, v8
-; VI-NEXT: v_fma_f32 v10, v11, v9, v10
-; VI-NEXT: v_fma_f32 v4, -v4, v10, v8
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v4, v4, v9, v10
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v3
-; VI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB9_14
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s8, 11
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB9_14
; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v3, vcc, 11, v6
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v7
+; VI-NEXT: s_add_i32 s10, s10, 11
+; VI-NEXT: s_sub_i32 s8, s10, s11
; VI-NEXT: .LBB9_13: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v6, v5
-; VI-NEXT: v_mul_f32_e32 v5, v6, v4
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v5, -v5, v2, v6
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v7, v5, v2
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; VI-NEXT: v_add_u32_e32 v3, vcc, -11, v3
-; VI-NEXT: v_ldexp_f32 v5, v5, 11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v3
-; VI-NEXT: s_cbranch_vccnz .LBB9_13
+; VI-NEXT: v_mul_f32_e32 v2, s9, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s9
+; VI-NEXT: v_readfirstlane_b32 s10, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s11, v2
+; VI-NEXT: s_cselect_b32 s10, s11, s10
+; VI-NEXT: v_ldexp_f32 v2, s10, 11
+; VI-NEXT: v_readfirstlane_b32 s11, v2
+; VI-NEXT: s_add_i32 s8, s8, -11
+; VI-NEXT: s_cmp_gt_i32 s8, 11
+; VI-NEXT: s_mov_b32 s10, s9
+; VI-NEXT: s_mov_b32 s9, s11
+; VI-NEXT: s_cbranch_scc1 .LBB9_13
; VI-NEXT: s_branch .LBB9_15
; VI-NEXT: .LBB9_14:
-; VI-NEXT: v_mov_b32_e32 v6, v5
+; VI-NEXT: s_mov_b32 s10, s9
; VI-NEXT: .LBB9_15: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v3, vcc, -10, v3
-; VI-NEXT: v_ldexp_f32 v3, v6, v3
-; VI-NEXT: v_mul_f32_e32 v4, v3, v4
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; VI-NEXT: v_ldexp_f32 v1, v2, v1
-; VI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; VI-NEXT: s_and_b32 s3, s4, 0x8000
-; VI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; VI-NEXT: v_or_b32_e32 v1, s3, v1
+; VI-NEXT: s_add_i32 s8, s8, -10
+; VI-NEXT: v_mov_b32_e32 v2, s8
+; VI-NEXT: v_ldexp_f32 v2, s10, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s8, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s9, v0
+; VI-NEXT: s_cselect_b32 s8, s9, s8
+; VI-NEXT: v_mov_b32_e32 v0, s7
+; VI-NEXT: v_ldexp_f32 v0, s8, v0
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_and_b32 s8, s5, 0xffff8000
+; VI-NEXT: v_readfirstlane_b32 s7, v0
+; VI-NEXT: s_and_b32 s7, s7, 0x7fff
+; VI-NEXT: s_or_b32 s7, s7, s8
; VI-NEXT: .LBB9_16: ; %Flow54
-; VI-NEXT: v_mov_b32_e32 v2, 0x7c00
-; VI-NEXT: v_cmp_nlg_f16_e64 vcc, s1, 0
-; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |s0|, v2
-; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, 0
-; VI-NEXT: v_cmp_nge_f16_e64 s[4:5], |s4|, v2
-; VI-NEXT: v_mov_b32_e32 v2, 0x7e00
-; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: s_mov_b64 vcc, s[2:3]
-; VI-NEXT: v_cndmask_b32_sdwa v1, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: s_mov_b64 vcc, s[4:5]
-; VI-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1]
-; VI-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v2, v0, v1
-; VI-NEXT: v_mov_b32_e32 v0, s8
-; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_cmp_nlg_f16_e64 s[8:9], s3, 0
+; VI-NEXT: v_mov_b32_e32 v0, 0x7c00
+; VI-NEXT: s_cmp_lg_u64 s[8:9], 0
+; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s2|, v0
+; VI-NEXT: s_cselect_b32 s8, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s6, 0
+; VI-NEXT: s_cselect_b32 s9, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s5|, v0
+; VI-NEXT: s_cselect_b32 s6, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_and_b32 s3, 0xffff, s4
+; VI-NEXT: s_cmp_lg_u32 s8, 0
+; VI-NEXT: s_cselect_b32 s3, 0x7e00, s3
+; VI-NEXT: s_cmp_lg_u32 s9, 0
+; VI-NEXT: s_cselect_b32 s3, s3, 0x7e00
+; VI-NEXT: s_and_b32 s4, 0xffff, s7
+; VI-NEXT: s_cmp_lg_u32 s6, 0
+; VI-NEXT: s_cselect_b32 s4, 0x7e00, s4
+; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_cselect_b32 s2, s4, 0x7e00
+; VI-NEXT: s_lshl_b32 s2, s2, 16
+; VI-NEXT: s_or_b32 s2, s3, s2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%gep2 = getelementptr <2 x half>, ptr addrspace(1) %in2, i32 4
@@ -1406,702 +1633,881 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 {
; CI-LABEL: frem_v4f16:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x9
-; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
-; CI-NEXT: ; implicit-def: $vgpr0
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_load_dwordx2 s[8:9], s[18:19], 0x0
-; CI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x8
-; CI-NEXT: s_mov_b32 s0, 1
+; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x8
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s8|
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |s6|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v1
-; CI-NEXT: s_cbranch_vccz .LBB10_2
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s4|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; CI-NEXT: s_mov_b32 s7, 1
+; CI-NEXT: ; implicit-def: $sgpr6
+; CI-NEXT: s_cbranch_scc0 .LBB10_2
; CI-NEXT: ; %bb.1: ; %frem.else86
-; CI-NEXT: s_and_b32 s0, s8, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v1
-; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: v_mov_b32_e32 v3, s8
-; CI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
-; CI-NEXT: s_mov_b32 s0, 0
+; CI-NEXT: s_and_b32 s8, s2, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; CI-NEXT: s_cselect_b32 s6, s8, s2
+; CI-NEXT: s_mov_b32 s7, 0
; CI-NEXT: .LBB10_2: ; %Flow135
-; CI-NEXT: s_xor_b32 s0, s0, 1
-; CI-NEXT: s_cmp_lg_u32 s0, 0
+; CI-NEXT: s_xor_b32 s7, s7, 1
+; CI-NEXT: s_cmp_lg_u32 s7, 0
; CI-NEXT: s_cbranch_scc1 .LBB10_8
; CI-NEXT: ; %bb.3: ; %frem.compute85
-; CI-NEXT: v_frexp_mant_f32_e32 v3, v1
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v1
-; CI-NEXT: v_ldexp_f32_e64 v1, v3, 1
-; CI-NEXT: v_div_scale_f32 v3, s[0:1], v1, v1, 1.0
-; CI-NEXT: v_frexp_mant_f32_e32 v0, v2
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5
-; CI-NEXT: v_ldexp_f32_e64 v4, v0, 11
-; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; CI-NEXT: v_rcp_f32_e32 v8, v3
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; CI-NEXT: v_readfirstlane_b32 s9, v1
+; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11
+; CI-NEXT: v_readfirstlane_b32 s8, v1
+; CI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; CI-NEXT: v_readfirstlane_b32 s10, v0
+; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1
+; CI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s7, s9, -1
+; CI-NEXT: s_add_i32 s6, s10, -1
+; CI-NEXT: s_sub_i32 s7, s7, s6
+; CI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; CI-NEXT: v_fma_f32 v8, v9, v8, v8
-; CI-NEXT: v_mul_f32_e32 v9, v7, v8
-; CI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; CI-NEXT: v_fma_f32 v9, v10, v8, v9
-; CI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2
-; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_6
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s7, 11
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB10_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
-; CI-NEXT: v_add_i32_e32 v2, vcc, 11, v5
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; CI-NEXT: s_add_i32 s9, s9, 11
+; CI-NEXT: s_sub_i32 s7, s9, s10
; CI-NEXT: .LBB10_5: ; %frem.loop_body93
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v5, v4
-; CI-NEXT: v_mul_f32_e32 v4, v5, v3
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v6, v4, v1
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2
-; CI-NEXT: s_cbranch_vccnz .LBB10_5
+; CI-NEXT: v_mul_f32_e32 v2, s8, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s8
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s9, v2
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s10, v2
+; CI-NEXT: s_cselect_b32 s9, s10, s9
+; CI-NEXT: v_ldexp_f32_e64 v2, s9, 11
+; CI-NEXT: v_readfirstlane_b32 s10, v2
+; CI-NEXT: s_add_i32 s7, s7, -11
+; CI-NEXT: s_cmp_gt_i32 s7, 11
+; CI-NEXT: s_mov_b32 s9, s8
+; CI-NEXT: s_mov_b32 s8, s10
+; CI-NEXT: s_cbranch_scc1 .LBB10_5
; CI-NEXT: s_branch .LBB10_7
; CI-NEXT: .LBB10_6:
-; CI-NEXT: v_mov_b32_e32 v5, v4
+; CI-NEXT: s_mov_b32 s9, s8
; CI-NEXT: .LBB10_7: ; %frem.loop_exit94
-; CI-NEXT: v_add_i32_e32 v2, vcc, -10, v2
-; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2
-; CI-NEXT: v_mul_f32_e32 v3, v2, v3
-; CI-NEXT: v_rndne_f32_e32 v3, v3
-; CI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; CI-NEXT: v_add_f32_e32 v1, v2, v1
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0
+; CI-NEXT: s_add_i32 s7, s7, -10
+; CI-NEXT: v_mov_b32_e32 v2, s7
+; CI-NEXT: v_ldexp_f32_e32 v2, s9, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s7, v1
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: s_cselect_b32 s7, s8, s7
+; CI-NEXT: v_mov_b32_e32 v0, s6
+; CI-NEXT: v_ldexp_f32_e32 v0, s7, v0
; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: s_and_b32 s0, s8, 0x8000
-; CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; CI-NEXT: v_or_b32_e32 v0, s0, v0
+; CI-NEXT: s_and_b32 s7, s2, 0xffff8000
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: s_and_b32 s6, s6, 0x7fff
+; CI-NEXT: s_or_b32 s6, s6, s7
; CI-NEXT: .LBB10_8: ; %Flow136
-; CI-NEXT: s_lshr_b32 s4, s8, 16
-; CI-NEXT: s_lshr_b32 s2, s6, 16
-; CI-NEXT: v_cvt_f32_f16_e64 v3, |s4|
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s2|
-; CI-NEXT: s_mov_b32 s0, 1
-; CI-NEXT: ; implicit-def: $vgpr1
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
-; CI-NEXT: s_cbranch_vccz .LBB10_10
+; CI-NEXT: s_lshr_b32 s7, s2, 16
+; CI-NEXT: s_lshr_b32 s8, s4, 16
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |s7|
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s8|
+; CI-NEXT: ; implicit-def: $sgpr9
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: s_mov_b32 s10, 1
+; CI-NEXT: s_cbranch_scc0 .LBB10_10
; CI-NEXT: ; %bb.9: ; %frem.else53
-; CI-NEXT: s_and_b32 s0, s4, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; CI-NEXT: v_mov_b32_e32 v1, s0
-; CI-NEXT: v_mov_b32_e32 v4, s4
-; CI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; CI-NEXT: s_mov_b32 s0, 0
+; CI-NEXT: s_and_b32 s9, s7, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: s_cselect_b32 s9, s9, s7
+; CI-NEXT: s_mov_b32 s10, 0
; CI-NEXT: .LBB10_10: ; %Flow131
-; CI-NEXT: s_xor_b32 s0, s0, 1
-; CI-NEXT: s_cmp_lg_u32 s0, 0
+; CI-NEXT: s_xor_b32 s10, s10, 1
+; CI-NEXT: s_cmp_lg_u32 s10, 0
; CI-NEXT: s_cbranch_scc1 .LBB10_16
; CI-NEXT: ; %bb.11: ; %frem.compute52
-; CI-NEXT: v_frexp_mant_f32_e32 v4, v2
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v2
-; CI-NEXT: v_ldexp_f32_e64 v2, v4, 1
-; CI-NEXT: v_div_scale_f32 v4, s[0:1], v2, v2, 1.0
-; CI-NEXT: v_frexp_mant_f32_e32 v1, v3
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v3
-; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v6
-; CI-NEXT: v_ldexp_f32_e64 v5, v1, 11
-; CI-NEXT: v_add_i32_e32 v1, vcc, -1, v7
-; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v1
-; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0
-; CI-NEXT: v_rcp_f32_e32 v9, v4
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; CI-NEXT: v_readfirstlane_b32 s12, v1
+; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11
+; CI-NEXT: v_readfirstlane_b32 s11, v1
+; CI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; CI-NEXT: v_readfirstlane_b32 s13, v0
+; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1
+; CI-NEXT: v_div_scale_f32 v1, s[14:15], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s10, s12, -1
+; CI-NEXT: s_add_i32 s9, s13, -1
+; CI-NEXT: s_sub_i32 s10, s10, s9
+; CI-NEXT: v_div_scale_f32 v2, s[14:15], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v10, -v4, v9, 1.0
-; CI-NEXT: v_fma_f32 v9, v10, v9, v9
-; CI-NEXT: v_mul_f32_e32 v10, v8, v9
-; CI-NEXT: v_fma_f32 v11, -v4, v10, v8
-; CI-NEXT: v_fma_f32 v10, v11, v9, v10
-; CI-NEXT: v_fma_f32 v4, -v4, v10, v8
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v4, v4, v9, v10
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v3
-; CI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_14
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s10, 11
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB10_14
; CI-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
-; CI-NEXT: v_add_i32_e32 v3, vcc, 11, v6
-; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
+; CI-NEXT: s_add_i32 s12, s12, 11
+; CI-NEXT: s_sub_i32 s10, s12, s13
; CI-NEXT: .LBB10_13: ; %frem.loop_body60
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v6, v5
-; CI-NEXT: v_mul_f32_e32 v5, v6, v4
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v5, -v5, v2, v6
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v7, v5, v2
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; CI-NEXT: v_add_i32_e32 v3, vcc, -11, v3
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v3
-; CI-NEXT: s_cbranch_vccnz .LBB10_13
+; CI-NEXT: v_mul_f32_e32 v2, s11, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s11
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s14, v2
+; CI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s12, v2
+; CI-NEXT: s_cselect_b32 s12, s12, s14
+; CI-NEXT: v_ldexp_f32_e64 v2, s12, 11
+; CI-NEXT: v_readfirstlane_b32 s13, v2
+; CI-NEXT: s_add_i32 s10, s10, -11
+; CI-NEXT: s_cmp_gt_i32 s10, 11
+; CI-NEXT: s_mov_b32 s12, s11
+; CI-NEXT: s_mov_b32 s11, s13
+; CI-NEXT: s_cbranch_scc1 .LBB10_13
; CI-NEXT: s_branch .LBB10_15
; CI-NEXT: .LBB10_14:
-; CI-NEXT: v_mov_b32_e32 v6, v5
+; CI-NEXT: s_mov_b32 s12, s11
; CI-NEXT: .LBB10_15: ; %frem.loop_exit61
-; CI-NEXT: v_add_i32_e32 v3, vcc, -10, v3
-; CI-NEXT: v_ldexp_f32_e32 v3, v6, v3
-; CI-NEXT: v_mul_f32_e32 v4, v3, v4
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; CI-NEXT: v_add_f32_e32 v2, v3, v2
-; CI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; CI-NEXT: v_ldexp_f32_e32 v1, v2, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: s_and_b32 s0, s4, 0x8000
-; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; CI-NEXT: v_or_b32_e32 v1, s0, v1
+; CI-NEXT: s_add_i32 s10, s10, -10
+; CI-NEXT: v_mov_b32_e32 v2, s10
+; CI-NEXT: v_ldexp_f32_e32 v2, s12, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s12, v1
+; CI-NEXT: v_readfirstlane_b32 s10, v0
+; CI-NEXT: s_cselect_b32 s10, s10, s12
+; CI-NEXT: v_mov_b32_e32 v0, s9
+; CI-NEXT: v_ldexp_f32_e32 v0, s10, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_and_b32 s10, s7, 0xffff8000
+; CI-NEXT: v_readfirstlane_b32 s9, v0
+; CI-NEXT: s_and_b32 s9, s9, 0x7fff
+; CI-NEXT: s_or_b32 s9, s9, s10
; CI-NEXT: .LBB10_16: ; %Flow132
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s9|
-; CI-NEXT: v_cvt_f32_f16_e64 v3, |s7|
-; CI-NEXT: s_mov_b32 s0, 1
-; CI-NEXT: ; implicit-def: $vgpr2
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
-; CI-NEXT: s_cbranch_vccz .LBB10_18
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |s3|
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s5|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: s_mov_b32 s11, 1
+; CI-NEXT: ; implicit-def: $sgpr10
+; CI-NEXT: s_cbranch_scc0 .LBB10_18
; CI-NEXT: ; %bb.17: ; %frem.else20
-; CI-NEXT: s_and_b32 s0, s9, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; CI-NEXT: v_mov_b32_e32 v2, s0
-; CI-NEXT: v_mov_b32_e32 v5, s9
-; CI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; CI-NEXT: s_mov_b32 s0, 0
+; CI-NEXT: s_and_b32 s12, s3, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: s_cselect_b32 s10, s12, s3
+; CI-NEXT: s_mov_b32 s11, 0
; CI-NEXT: .LBB10_18: ; %Flow127
-; CI-NEXT: s_xor_b32 s0, s0, 1
-; CI-NEXT: s_cmp_lg_u32 s0, 0
+; CI-NEXT: s_xor_b32 s11, s11, 1
+; CI-NEXT: s_cmp_lg_u32 s11, 0
; CI-NEXT: s_cbranch_scc1 .LBB10_24
; CI-NEXT: ; %bb.19: ; %frem.compute19
-; CI-NEXT: v_frexp_mant_f32_e32 v5, v3
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
-; CI-NEXT: v_ldexp_f32_e64 v3, v5, 1
-; CI-NEXT: v_div_scale_f32 v5, s[0:1], v3, v3, 1.0
-; CI-NEXT: v_frexp_mant_f32_e32 v2, v4
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
-; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v7
-; CI-NEXT: v_ldexp_f32_e64 v6, v2, 11
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
-; CI-NEXT: v_sub_i32_e32 v4, vcc, v4, v2
-; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v3, 1.0
-; CI-NEXT: v_rcp_f32_e32 v10, v5
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; CI-NEXT: v_readfirstlane_b32 s13, v1
+; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11
+; CI-NEXT: v_readfirstlane_b32 s12, v1
+; CI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; CI-NEXT: v_readfirstlane_b32 s14, v0
+; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1
+; CI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s11, s13, -1
+; CI-NEXT: s_add_i32 s10, s14, -1
+; CI-NEXT: s_sub_i32 s11, s11, s10
+; CI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v11, -v5, v10, 1.0
-; CI-NEXT: v_fma_f32 v10, v11, v10, v10
-; CI-NEXT: v_mul_f32_e32 v11, v9, v10
-; CI-NEXT: v_fma_f32 v12, -v5, v11, v9
-; CI-NEXT: v_fma_f32 v11, v12, v10, v11
-; CI-NEXT: v_fma_f32 v5, -v5, v11, v9
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v4
-; CI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_22
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s11, 11
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB10_22
; CI-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
-; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v7
-; CI-NEXT: v_sub_i32_e32 v4, vcc, v4, v8
+; CI-NEXT: s_add_i32 s13, s13, 11
+; CI-NEXT: s_sub_i32 s11, s13, s14
; CI-NEXT: .LBB10_21: ; %frem.loop_body27
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v6
-; CI-NEXT: v_mul_f32_e32 v6, v7, v5
-; CI-NEXT: v_rndne_f32_e32 v6, v6
-; CI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; CI-NEXT: v_add_f32_e32 v8, v6, v3
-; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
-; CI-NEXT: v_ldexp_f32_e64 v6, v6, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; CI-NEXT: s_cbranch_vccnz .LBB10_21
+; CI-NEXT: v_mul_f32_e32 v2, s12, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s12
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s13, v2
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s14, v2
+; CI-NEXT: s_cselect_b32 s13, s14, s13
+; CI-NEXT: v_ldexp_f32_e64 v2, s13, 11
+; CI-NEXT: v_readfirstlane_b32 s14, v2
+; CI-NEXT: s_add_i32 s11, s11, -11
+; CI-NEXT: s_cmp_gt_i32 s11, 11
+; CI-NEXT: s_mov_b32 s13, s12
+; CI-NEXT: s_mov_b32 s12, s14
+; CI-NEXT: s_cbranch_scc1 .LBB10_21
; CI-NEXT: s_branch .LBB10_23
; CI-NEXT: .LBB10_22:
-; CI-NEXT: v_mov_b32_e32 v7, v6
+; CI-NEXT: s_mov_b32 s13, s12
; CI-NEXT: .LBB10_23: ; %frem.loop_exit28
-; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
-; CI-NEXT: v_ldexp_f32_e32 v4, v7, v4
-; CI-NEXT: v_mul_f32_e32 v5, v4, v5
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v3, v4, v3
-; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: s_and_b32 s0, s9, 0x8000
-; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; CI-NEXT: v_or_b32_e32 v2, s0, v2
+; CI-NEXT: s_add_i32 s11, s11, -10
+; CI-NEXT: v_mov_b32_e32 v2, s11
+; CI-NEXT: v_ldexp_f32_e32 v2, s13, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s11, v1
+; CI-NEXT: v_readfirstlane_b32 s12, v0
+; CI-NEXT: s_cselect_b32 s11, s12, s11
+; CI-NEXT: v_mov_b32_e32 v0, s10
+; CI-NEXT: v_ldexp_f32_e32 v0, s11, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_and_b32 s11, s3, 0xffff8000
+; CI-NEXT: v_readfirstlane_b32 s10, v0
+; CI-NEXT: s_and_b32 s10, s10, 0x7fff
+; CI-NEXT: s_or_b32 s10, s10, s11
; CI-NEXT: .LBB10_24: ; %Flow128
-; CI-NEXT: s_lshr_b32 s12, s9, 16
-; CI-NEXT: s_lshr_b32 s10, s7, 16
-; CI-NEXT: v_cvt_f32_f16_e64 v5, |s12|
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s10|
-; CI-NEXT: s_mov_b32 s0, 1
-; CI-NEXT: ; implicit-def: $vgpr3
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v5, v4
-; CI-NEXT: s_cbranch_vccz .LBB10_26
+; CI-NEXT: s_lshr_b32 s11, s3, 16
+; CI-NEXT: s_lshr_b32 s12, s5, 16
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |s11|
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s12|
+; CI-NEXT: ; implicit-def: $sgpr13
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: s_mov_b32 s14, 1
+; CI-NEXT: s_cbranch_scc0 .LBB10_26
; CI-NEXT: ; %bb.25: ; %frem.else
-; CI-NEXT: s_and_b32 s0, s12, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; CI-NEXT: v_mov_b32_e32 v3, s0
-; CI-NEXT: v_mov_b32_e32 v6, s12
-; CI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; CI-NEXT: s_mov_b32 s0, 0
+; CI-NEXT: s_and_b32 s13, s11, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: s_cselect_b32 s13, s13, s11
+; CI-NEXT: s_mov_b32 s14, 0
; CI-NEXT: .LBB10_26: ; %Flow123
-; CI-NEXT: s_xor_b32 s0, s0, 1
-; CI-NEXT: s_cmp_lg_u32 s0, 0
+; CI-NEXT: s_xor_b32 s14, s14, 1
+; CI-NEXT: s_cmp_lg_u32 s14, 0
; CI-NEXT: s_cbranch_scc1 .LBB10_32
; CI-NEXT: ; %bb.27: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f32_e32 v6, v4
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v4
-; CI-NEXT: v_ldexp_f32_e64 v4, v6, 1
-; CI-NEXT: v_div_scale_f32 v6, s[0:1], v4, v4, 1.0
-; CI-NEXT: v_frexp_mant_f32_e32 v3, v5
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v5
-; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v8
-; CI-NEXT: v_ldexp_f32_e64 v7, v3, 11
-; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v9
-; CI-NEXT: v_sub_i32_e32 v5, vcc, v5, v3
-; CI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v4, 1.0
-; CI-NEXT: v_rcp_f32_e32 v11, v6
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; CI-NEXT: v_readfirstlane_b32 s16, v1
+; CI-NEXT: v_ldexp_f32_e64 v1, v2, 11
+; CI-NEXT: v_readfirstlane_b32 s15, v1
+; CI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; CI-NEXT: v_readfirstlane_b32 s17, v0
+; CI-NEXT: v_ldexp_f32_e64 v0, v1, 1
+; CI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s14, s16, -1
+; CI-NEXT: s_add_i32 s13, s17, -1
+; CI-NEXT: s_sub_i32 s14, s14, s13
+; CI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[18:19], s[18:19], s[18:19]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v12, -v6, v11, 1.0
-; CI-NEXT: v_fma_f32 v11, v12, v11, v11
-; CI-NEXT: v_mul_f32_e32 v12, v10, v11
-; CI-NEXT: v_fma_f32 v13, -v6, v12, v10
-; CI-NEXT: v_fma_f32 v12, v13, v11, v12
-; CI-NEXT: v_fma_f32 v6, -v6, v12, v10
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v6, v6, v11, v12
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v5
-; CI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_30
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s14, 11
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB10_30
; CI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v5, vcc, 11, v8
-; CI-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
+; CI-NEXT: s_add_i32 s16, s16, 11
+; CI-NEXT: s_sub_i32 s14, s16, s17
; CI-NEXT: .LBB10_29: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v8, v7
-; CI-NEXT: v_mul_f32_e32 v7, v8, v6
-; CI-NEXT: v_rndne_f32_e32 v7, v7
-; CI-NEXT: v_fma_f32 v7, -v7, v4, v8
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; CI-NEXT: v_add_f32_e32 v9, v7, v4
-; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; CI-NEXT: v_add_i32_e32 v5, vcc, -11, v5
-; CI-NEXT: v_ldexp_f32_e64 v7, v7, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v5
-; CI-NEXT: s_cbranch_vccnz .LBB10_29
+; CI-NEXT: v_mul_f32_e32 v2, s15, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s15
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s18, v2
+; CI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s16, v2
+; CI-NEXT: s_cselect_b32 s16, s16, s18
+; CI-NEXT: v_ldexp_f32_e64 v2, s16, 11
+; CI-NEXT: v_readfirstlane_b32 s17, v2
+; CI-NEXT: s_add_i32 s14, s14, -11
+; CI-NEXT: s_cmp_gt_i32 s14, 11
+; CI-NEXT: s_mov_b32 s16, s15
+; CI-NEXT: s_mov_b32 s15, s17
+; CI-NEXT: s_cbranch_scc1 .LBB10_29
; CI-NEXT: s_branch .LBB10_31
; CI-NEXT: .LBB10_30:
-; CI-NEXT: v_mov_b32_e32 v8, v7
+; CI-NEXT: s_mov_b32 s16, s15
; CI-NEXT: .LBB10_31: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v5, vcc, -10, v5
-; CI-NEXT: v_ldexp_f32_e32 v5, v8, v5
-; CI-NEXT: v_mul_f32_e32 v6, v5, v6
-; CI-NEXT: v_rndne_f32_e32 v6, v6
-; CI-NEXT: v_fma_f32 v5, -v6, v4, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v4, v5, v4
-; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; CI-NEXT: v_ldexp_f32_e32 v3, v4, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: s_and_b32 s0, s12, 0x8000
-; CI-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; CI-NEXT: v_or_b32_e32 v3, s0, v3
+; CI-NEXT: s_add_i32 s14, s14, -10
+; CI-NEXT: v_mov_b32_e32 v2, s14
+; CI-NEXT: v_ldexp_f32_e32 v2, s16, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s16, v1
+; CI-NEXT: v_readfirstlane_b32 s14, v0
+; CI-NEXT: s_cselect_b32 s14, s14, s16
+; CI-NEXT: v_mov_b32_e32 v0, s13
+; CI-NEXT: v_ldexp_f32_e32 v0, s14, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: s_and_b32 s14, s11, 0xffff8000
+; CI-NEXT: v_readfirstlane_b32 s13, v0
+; CI-NEXT: s_and_b32 s13, s13, 0x7fff
+; CI-NEXT: s_or_b32 s13, s13, s14
; CI-NEXT: .LBB10_32: ; %Flow124
-; CI-NEXT: v_cvt_f32_f16_e32 v4, s6
-; CI-NEXT: v_mov_b32_e32 v5, 0x7f800000
-; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v4
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s8|
-; CI-NEXT: s_mov_b32 s18, -1
-; CI-NEXT: s_mov_b32 s19, 0xf000
-; CI-NEXT: v_cmp_nge_f32_e64 s[0:1], v4, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v4, s2
-; CI-NEXT: v_cmp_nlg_f32_e64 s[2:3], 0, v4
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s4|
-; CI-NEXT: v_cmp_nge_f32_e64 s[4:5], v4, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v4, s7
-; CI-NEXT: v_cmp_nlg_f32_e64 s[6:7], 0, v4
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s9|
-; CI-NEXT: v_cmp_nge_f32_e64 s[8:9], v4, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v4, s10
-; CI-NEXT: v_cmp_nlg_f32_e64 s[10:11], 0, v4
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s12|
-; CI-NEXT: v_cmp_nge_f32_e64 s[12:13], v4, v5
-; CI-NEXT: v_mov_b32_e32 v4, 0x7e00
-; CI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[2:3]
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; CI-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
-; CI-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[0:1]
-; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; CI-NEXT: v_or_b32_e32 v0, v0, v1
-; CI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; CI-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; CI-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[10:11]
-; CI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[6:7]
-; CI-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[12:13]
-; CI-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[8:9]
-; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; CI-NEXT: v_or_b32_e32 v1, v1, v2
-; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[16:19], 0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s4
+; CI-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s2|
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: s_cselect_b32 s16, 1, 0
+; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s8
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: s_cselect_b32 s17, 1, 0
+; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s7|
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: s_cselect_b32 s8, 1, 0
+; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s5
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: s_cselect_b32 s7, 1, 0
+; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
+; CI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; CI-NEXT: s_cselect_b32 s4, 1, 0
+; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s12
+; CI-NEXT: s_or_b64 s[2:3], vcc, vcc
+; CI-NEXT: s_cselect_b32 s5, 1, 0
+; CI-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s11|
+; CI-NEXT: s_or_b64 s[2:3], vcc, vcc
+; CI-NEXT: s_cselect_b32 s12, 1, 0
+; CI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; CI-NEXT: s_or_b64 s[2:3], vcc, vcc
+; CI-NEXT: s_cselect_b32 s3, 1, 0
+; CI-NEXT: s_and_b32 s2, 0xffff, s6
+; CI-NEXT: s_cmp_lg_u32 s16, 0
+; CI-NEXT: s_cselect_b32 s2, 0x7e00, s2
+; CI-NEXT: s_cmp_lg_u32 s17, 0
+; CI-NEXT: s_cselect_b32 s2, s2, 0x7e00
+; CI-NEXT: s_and_b32 s6, 0xffff, s9
+; CI-NEXT: s_cmp_lg_u32 s8, 0
+; CI-NEXT: s_cselect_b32 s6, 0x7e00, s6
+; CI-NEXT: s_cmp_lg_u32 s7, 0
+; CI-NEXT: s_cselect_b32 s6, s6, 0x7e00
+; CI-NEXT: s_lshl_b32 s6, s6, 16
+; CI-NEXT: s_or_b32 s2, s2, s6
+; CI-NEXT: s_and_b32 s6, 0xffff, s10
+; CI-NEXT: s_cmp_lg_u32 s4, 0
+; CI-NEXT: s_cselect_b32 s4, 0x7e00, s6
+; CI-NEXT: s_cmp_lg_u32 s5, 0
+; CI-NEXT: s_cselect_b32 s4, s4, 0x7e00
+; CI-NEXT: s_and_b32 s5, 0xffff, s13
+; CI-NEXT: s_cmp_lg_u32 s12, 0
+; CI-NEXT: s_cselect_b32 s5, 0x7e00, s5
+; CI-NEXT: s_cmp_lg_u32 s3, 0
+; CI-NEXT: s_cselect_b32 s3, s5, 0x7e00
+; CI-NEXT: s_lshl_b32 s3, s3, 16
+; CI-NEXT: s_or_b32 s3, s4, s3
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: v_mov_b32_e32 v1, s3
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; CI-NEXT: s_endpgm
;
; VI-LABEL: frem_v4f16:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x24
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34
-; VI-NEXT: ; implicit-def: $vgpr0
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: s_mov_b32 s7, 1
+; VI-NEXT: ; implicit-def: $sgpr6
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_load_dwordx2 s[8:9], s[18:19], 0x0
-; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x20
-; VI-NEXT: s_mov_b32 s0, 1
+; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x20
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v2, |s8|
-; VI-NEXT: v_cvt_f32_f16_e64 v1, |s6|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v1
-; VI-NEXT: s_cbranch_vccz .LBB10_2
+; VI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |s4|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cbranch_scc0 .LBB10_2
; VI-NEXT: ; %bb.1: ; %frem.else86
-; VI-NEXT: s_and_b32 s0, s8, 0x8000
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v1
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v3, s8
-; VI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
-; VI-NEXT: s_mov_b32 s0, 0
+; VI-NEXT: s_and_b32 s6, s2, 0xffff8000
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cselect_b32 s6, s6, s2
+; VI-NEXT: s_mov_b32 s7, 0
; VI-NEXT: .LBB10_2: ; %Flow135
-; VI-NEXT: s_xor_b32 s0, s0, 1
-; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_xor_b32 s7, s7, 1
+; VI-NEXT: s_cmp_lg_u32 s7, 0
; VI-NEXT: s_cbranch_scc1 .LBB10_8
; VI-NEXT: ; %bb.3: ; %frem.compute85
-; VI-NEXT: v_frexp_mant_f32_e32 v3, v1
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v1
-; VI-NEXT: v_ldexp_f32 v1, v3, 1
-; VI-NEXT: v_div_scale_f32 v3, s[0:1], v1, v1, 1.0
-; VI-NEXT: v_frexp_mant_f32_e32 v0, v2
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5
-; VI-NEXT: v_ldexp_f32 v4, v0, 11
-; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; VI-NEXT: v_rcp_f32_e32 v8, v3
+; VI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; VI-NEXT: v_readfirstlane_b32 s9, v1
+; VI-NEXT: v_ldexp_f32 v1, v2, 11
+; VI-NEXT: v_readfirstlane_b32 s8, v1
+; VI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; VI-NEXT: v_readfirstlane_b32 s10, v0
+; VI-NEXT: v_ldexp_f32 v0, v1, 1
+; VI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s7, s9, -1
+; VI-NEXT: s_add_i32 s6, s10, -1
+; VI-NEXT: s_sub_i32 s7, s7, s6
+; VI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; VI-NEXT: v_fma_f32 v8, v9, v8, v8
-; VI-NEXT: v_mul_f32_e32 v9, v7, v8
-; VI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; VI-NEXT: v_fma_f32 v9, v10, v8, v9
-; VI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2
-; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_6
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s7, 11
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB10_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
-; VI-NEXT: v_add_u32_e32 v2, vcc, 11, v5
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6
+; VI-NEXT: s_add_i32 s9, s9, 11
+; VI-NEXT: s_sub_i32 s7, s9, s10
; VI-NEXT: .LBB10_5: ; %frem.loop_body93
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v5, v4
-; VI-NEXT: v_mul_f32_e32 v4, v5, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v6, v4, v1
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2
-; VI-NEXT: v_ldexp_f32 v4, v4, 11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2
-; VI-NEXT: s_cbranch_vccnz .LBB10_5
+; VI-NEXT: v_mul_f32_e32 v2, s8, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s8
+; VI-NEXT: v_readfirstlane_b32 s9, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s10, v2
+; VI-NEXT: s_cselect_b32 s9, s10, s9
+; VI-NEXT: v_ldexp_f32 v2, s9, 11
+; VI-NEXT: v_readfirstlane_b32 s10, v2
+; VI-NEXT: s_add_i32 s7, s7, -11
+; VI-NEXT: s_cmp_gt_i32 s7, 11
+; VI-NEXT: s_mov_b32 s9, s8
+; VI-NEXT: s_mov_b32 s8, s10
+; VI-NEXT: s_cbranch_scc1 .LBB10_5
; VI-NEXT: s_branch .LBB10_7
; VI-NEXT: .LBB10_6:
-; VI-NEXT: v_mov_b32_e32 v5, v4
+; VI-NEXT: s_mov_b32 s9, s8
; VI-NEXT: .LBB10_7: ; %frem.loop_exit94
-; VI-NEXT: v_add_u32_e32 v2, vcc, -10, v2
-; VI-NEXT: v_ldexp_f32 v2, v5, v2
-; VI-NEXT: v_mul_f32_e32 v3, v2, v3
-; VI-NEXT: v_rndne_f32_e32 v3, v3
-; VI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_ldexp_f32 v0, v1, v0
+; VI-NEXT: s_add_i32 s7, s7, -10
+; VI-NEXT: v_mov_b32_e32 v2, s7
+; VI-NEXT: v_ldexp_f32 v2, s9, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s7, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s8, v0
+; VI-NEXT: s_cselect_b32 s7, s8, s7
+; VI-NEXT: v_mov_b32_e32 v0, s6
+; VI-NEXT: v_ldexp_f32 v0, s7, v0
; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-NEXT: s_and_b32 s0, s8, 0x8000
-; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; VI-NEXT: v_or_b32_e32 v0, s0, v0
+; VI-NEXT: s_and_b32 s7, s2, 0xffff8000
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: s_and_b32 s6, s6, 0x7fff
+; VI-NEXT: s_or_b32 s6, s6, s7
; VI-NEXT: .LBB10_8: ; %Flow136
-; VI-NEXT: s_lshr_b32 s4, s8, 16
-; VI-NEXT: s_lshr_b32 s2, s6, 16
-; VI-NEXT: v_cvt_f32_f16_e64 v3, |s4|
-; VI-NEXT: v_cvt_f32_f16_e64 v2, |s2|
-; VI-NEXT: s_mov_b32 s0, 1
-; VI-NEXT: ; implicit-def: $vgpr1
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
-; VI-NEXT: s_cbranch_vccz .LBB10_10
+; VI-NEXT: s_lshr_b32 s7, s2, 16
+; VI-NEXT: s_lshr_b32 s8, s4, 16
+; VI-NEXT: v_cvt_f32_f16_e64 v1, |s7|
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |s8|
+; VI-NEXT: s_mov_b32 s10, 1
+; VI-NEXT: ; implicit-def: $sgpr9
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cbranch_scc0 .LBB10_10
; VI-NEXT: ; %bb.9: ; %frem.else53
-; VI-NEXT: s_and_b32 s0, s4, 0x8000
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; VI-NEXT: v_mov_b32_e32 v1, s0
-; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; VI-NEXT: s_mov_b32 s0, 0
+; VI-NEXT: s_and_b32 s9, s7, 0xffff8000
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cselect_b32 s9, s9, s7
+; VI-NEXT: s_mov_b32 s10, 0
; VI-NEXT: .LBB10_10: ; %Flow131
-; VI-NEXT: s_xor_b32 s0, s0, 1
-; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_xor_b32 s10, s10, 1
+; VI-NEXT: s_cmp_lg_u32 s10, 0
; VI-NEXT: s_cbranch_scc1 .LBB10_16
; VI-NEXT: ; %bb.11: ; %frem.compute52
-; VI-NEXT: v_frexp_mant_f32_e32 v4, v2
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v2
-; VI-NEXT: v_ldexp_f32 v2, v4, 1
-; VI-NEXT: v_div_scale_f32 v4, s[0:1], v2, v2, 1.0
-; VI-NEXT: v_frexp_mant_f32_e32 v1, v3
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v3
-; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v6
-; VI-NEXT: v_ldexp_f32 v5, v1, 11
-; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v7
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0
-; VI-NEXT: v_rcp_f32_e32 v9, v4
+; VI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; VI-NEXT: v_readfirstlane_b32 s12, v1
+; VI-NEXT: v_ldexp_f32 v1, v2, 11
+; VI-NEXT: v_readfirstlane_b32 s11, v1
+; VI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; VI-NEXT: v_readfirstlane_b32 s13, v0
+; VI-NEXT: v_ldexp_f32 v0, v1, 1
+; VI-NEXT: v_div_scale_f32 v1, s[14:15], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s10, s12, -1
+; VI-NEXT: s_add_i32 s9, s13, -1
+; VI-NEXT: s_sub_i32 s10, s10, s9
+; VI-NEXT: v_div_scale_f32 v2, s[14:15], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v10, -v4, v9, 1.0
-; VI-NEXT: v_fma_f32 v9, v10, v9, v9
-; VI-NEXT: v_mul_f32_e32 v10, v8, v9
-; VI-NEXT: v_fma_f32 v11, -v4, v10, v8
-; VI-NEXT: v_fma_f32 v10, v11, v9, v10
-; VI-NEXT: v_fma_f32 v4, -v4, v10, v8
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v4, v4, v9, v10
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v3
-; VI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_14
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s10, 11
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB10_14
; VI-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
-; VI-NEXT: v_add_u32_e32 v3, vcc, 11, v6
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v7
+; VI-NEXT: s_add_i32 s12, s12, 11
+; VI-NEXT: s_sub_i32 s10, s12, s13
; VI-NEXT: .LBB10_13: ; %frem.loop_body60
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v6, v5
-; VI-NEXT: v_mul_f32_e32 v5, v6, v4
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v5, -v5, v2, v6
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v7, v5, v2
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; VI-NEXT: v_add_u32_e32 v3, vcc, -11, v3
-; VI-NEXT: v_ldexp_f32 v5, v5, 11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v3
-; VI-NEXT: s_cbranch_vccnz .LBB10_13
+; VI-NEXT: v_mul_f32_e32 v2, s11, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s11
+; VI-NEXT: v_readfirstlane_b32 s12, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s13, v2
+; VI-NEXT: s_cselect_b32 s12, s13, s12
+; VI-NEXT: v_ldexp_f32 v2, s12, 11
+; VI-NEXT: v_readfirstlane_b32 s13, v2
+; VI-NEXT: s_add_i32 s10, s10, -11
+; VI-NEXT: s_cmp_gt_i32 s10, 11
+; VI-NEXT: s_mov_b32 s12, s11
+; VI-NEXT: s_mov_b32 s11, s13
+; VI-NEXT: s_cbranch_scc1 .LBB10_13
; VI-NEXT: s_branch .LBB10_15
; VI-NEXT: .LBB10_14:
-; VI-NEXT: v_mov_b32_e32 v6, v5
+; VI-NEXT: s_mov_b32 s12, s11
; VI-NEXT: .LBB10_15: ; %frem.loop_exit61
-; VI-NEXT: v_add_u32_e32 v3, vcc, -10, v3
-; VI-NEXT: v_ldexp_f32 v3, v6, v3
-; VI-NEXT: v_mul_f32_e32 v4, v3, v4
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; VI-NEXT: v_ldexp_f32 v1, v2, v1
-; VI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; VI-NEXT: s_and_b32 s0, s4, 0x8000
-; VI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; VI-NEXT: v_or_b32_e32 v1, s0, v1
+; VI-NEXT: s_add_i32 s10, s10, -10
+; VI-NEXT: v_mov_b32_e32 v2, s10
+; VI-NEXT: v_ldexp_f32 v2, s12, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s10, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s11, v0
+; VI-NEXT: s_cselect_b32 s10, s11, s10
+; VI-NEXT: v_mov_b32_e32 v0, s9
+; VI-NEXT: v_ldexp_f32 v0, s10, v0
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_and_b32 s10, s7, 0xffff8000
+; VI-NEXT: v_readfirstlane_b32 s9, v0
+; VI-NEXT: s_and_b32 s9, s9, 0x7fff
+; VI-NEXT: s_or_b32 s9, s9, s10
; VI-NEXT: .LBB10_16: ; %Flow132
-; VI-NEXT: v_cvt_f32_f16_e64 v4, |s9|
-; VI-NEXT: v_cvt_f32_f16_e64 v3, |s7|
-; VI-NEXT: s_mov_b32 s0, 1
-; VI-NEXT: ; implicit-def: $vgpr2
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
-; VI-NEXT: s_cbranch_vccz .LBB10_18
+; VI-NEXT: v_cvt_f32_f16_e64 v1, |s3|
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |s5|
+; VI-NEXT: s_mov_b32 s11, 1
+; VI-NEXT: ; implicit-def: $sgpr10
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cbranch_scc0 .LBB10_18
; VI-NEXT: ; %bb.17: ; %frem.else20
-; VI-NEXT: s_and_b32 s0, s9, 0x8000
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; VI-NEXT: v_mov_b32_e32 v2, s0
-; VI-NEXT: v_mov_b32_e32 v5, s9
-; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; VI-NEXT: s_mov_b32 s0, 0
+; VI-NEXT: s_and_b32 s10, s3, 0xffff8000
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cselect_b32 s10, s10, s3
+; VI-NEXT: s_mov_b32 s11, 0
; VI-NEXT: .LBB10_18: ; %Flow127
-; VI-NEXT: s_xor_b32 s0, s0, 1
-; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_xor_b32 s11, s11, 1
+; VI-NEXT: s_cmp_lg_u32 s11, 0
; VI-NEXT: s_cbranch_scc1 .LBB10_24
; VI-NEXT: ; %bb.19: ; %frem.compute19
-; VI-NEXT: v_frexp_mant_f32_e32 v5, v3
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
-; VI-NEXT: v_ldexp_f32 v3, v5, 1
-; VI-NEXT: v_div_scale_f32 v5, s[0:1], v3, v3, 1.0
-; VI-NEXT: v_frexp_mant_f32_e32 v2, v4
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
-; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v7
-; VI-NEXT: v_ldexp_f32 v6, v2, 11
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8
-; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v3, 1.0
-; VI-NEXT: v_rcp_f32_e32 v10, v5
+; VI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; VI-NEXT: v_readfirstlane_b32 s13, v1
+; VI-NEXT: v_ldexp_f32 v1, v2, 11
+; VI-NEXT: v_readfirstlane_b32 s12, v1
+; VI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; VI-NEXT: v_readfirstlane_b32 s14, v0
+; VI-NEXT: v_ldexp_f32 v0, v1, 1
+; VI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s11, s13, -1
+; VI-NEXT: s_add_i32 s10, s14, -1
+; VI-NEXT: s_sub_i32 s11, s11, s10
+; VI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[16:17], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v11, -v5, v10, 1.0
-; VI-NEXT: v_fma_f32 v10, v11, v10, v10
-; VI-NEXT: v_mul_f32_e32 v11, v9, v10
-; VI-NEXT: v_fma_f32 v12, -v5, v11, v9
-; VI-NEXT: v_fma_f32 v11, v12, v10, v11
-; VI-NEXT: v_fma_f32 v5, -v5, v11, v9
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v4
-; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_22
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s11, 11
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB10_22
; VI-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
-; VI-NEXT: v_add_u32_e32 v4, vcc, 11, v7
-; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v8
+; VI-NEXT: s_add_i32 s13, s13, 11
+; VI-NEXT: s_sub_i32 s11, s13, s14
; VI-NEXT: .LBB10_21: ; %frem.loop_body27
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v6
-; VI-NEXT: v_mul_f32_e32 v6, v7, v5
-; VI-NEXT: v_rndne_f32_e32 v6, v6
-; VI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; VI-NEXT: v_add_f32_e32 v8, v6, v3
-; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
-; VI-NEXT: v_ldexp_f32 v6, v6, 11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; VI-NEXT: s_cbranch_vccnz .LBB10_21
+; VI-NEXT: v_mul_f32_e32 v2, s12, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s12
+; VI-NEXT: v_readfirstlane_b32 s13, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s14, v2
+; VI-NEXT: s_cselect_b32 s13, s14, s13
+; VI-NEXT: v_ldexp_f32 v2, s13, 11
+; VI-NEXT: v_readfirstlane_b32 s14, v2
+; VI-NEXT: s_add_i32 s11, s11, -11
+; VI-NEXT: s_cmp_gt_i32 s11, 11
+; VI-NEXT: s_mov_b32 s13, s12
+; VI-NEXT: s_mov_b32 s12, s14
+; VI-NEXT: s_cbranch_scc1 .LBB10_21
; VI-NEXT: s_branch .LBB10_23
; VI-NEXT: .LBB10_22:
-; VI-NEXT: v_mov_b32_e32 v7, v6
+; VI-NEXT: s_mov_b32 s13, s12
; VI-NEXT: .LBB10_23: ; %frem.loop_exit28
-; VI-NEXT: v_add_u32_e32 v4, vcc, -10, v4
-; VI-NEXT: v_ldexp_f32 v4, v7, v4
-; VI-NEXT: v_mul_f32_e32 v5, v4, v5
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v4, -v5, v3, v4
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: v_ldexp_f32 v2, v3, v2
-; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; VI-NEXT: s_and_b32 s0, s9, 0x8000
-; VI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; VI-NEXT: v_or_b32_e32 v2, s0, v2
+; VI-NEXT: s_add_i32 s11, s11, -10
+; VI-NEXT: v_mov_b32_e32 v2, s11
+; VI-NEXT: v_ldexp_f32 v2, s13, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s11, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s12, v0
+; VI-NEXT: s_cselect_b32 s11, s12, s11
+; VI-NEXT: v_mov_b32_e32 v0, s10
+; VI-NEXT: v_ldexp_f32 v0, s11, v0
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_and_b32 s11, s3, 0xffff8000
+; VI-NEXT: v_readfirstlane_b32 s10, v0
+; VI-NEXT: s_and_b32 s10, s10, 0x7fff
+; VI-NEXT: s_or_b32 s10, s10, s11
; VI-NEXT: .LBB10_24: ; %Flow128
-; VI-NEXT: s_lshr_b32 s12, s9, 16
-; VI-NEXT: s_lshr_b32 s10, s7, 16
-; VI-NEXT: v_cvt_f32_f16_e64 v5, |s12|
-; VI-NEXT: v_cvt_f32_f16_e64 v4, |s10|
-; VI-NEXT: s_mov_b32 s0, 1
-; VI-NEXT: ; implicit-def: $vgpr3
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v5, v4
-; VI-NEXT: s_cbranch_vccz .LBB10_26
+; VI-NEXT: s_lshr_b32 s11, s3, 16
+; VI-NEXT: s_lshr_b32 s12, s5, 16
+; VI-NEXT: v_cvt_f32_f16_e64 v1, |s11|
+; VI-NEXT: v_cvt_f32_f16_e64 v0, |s12|
+; VI-NEXT: s_mov_b32 s14, 1
+; VI-NEXT: ; implicit-def: $sgpr13
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cbranch_scc0 .LBB10_26
; VI-NEXT: ; %bb.25: ; %frem.else
-; VI-NEXT: s_and_b32 s0, s12, 0x8000
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; VI-NEXT: v_mov_b32_e32 v3, s0
-; VI-NEXT: v_mov_b32_e32 v6, s12
-; VI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; VI-NEXT: s_mov_b32 s0, 0
+; VI-NEXT: s_and_b32 s13, s11, 0xffff8000
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: s_cselect_b32 s13, s13, s11
+; VI-NEXT: s_mov_b32 s14, 0
; VI-NEXT: .LBB10_26: ; %Flow123
-; VI-NEXT: s_xor_b32 s0, s0, 1
-; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_xor_b32 s14, s14, 1
+; VI-NEXT: s_cmp_lg_u32 s14, 0
; VI-NEXT: s_cbranch_scc1 .LBB10_32
; VI-NEXT: ; %bb.27: ; %frem.compute
-; VI-NEXT: v_frexp_mant_f32_e32 v6, v4
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v4
-; VI-NEXT: v_ldexp_f32 v4, v6, 1
-; VI-NEXT: v_div_scale_f32 v6, s[0:1], v4, v4, 1.0
-; VI-NEXT: v_frexp_mant_f32_e32 v3, v5
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v5
-; VI-NEXT: v_add_u32_e32 v5, vcc, -1, v8
-; VI-NEXT: v_ldexp_f32 v7, v3, 11
-; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v9
-; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v3
-; VI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v4, 1.0
-; VI-NEXT: v_rcp_f32_e32 v11, v6
+; VI-NEXT: v_frexp_mant_f32_e32 v2, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; VI-NEXT: v_readfirstlane_b32 s16, v1
+; VI-NEXT: v_ldexp_f32 v1, v2, 11
+; VI-NEXT: v_readfirstlane_b32 s15, v1
+; VI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; VI-NEXT: v_readfirstlane_b32 s17, v0
+; VI-NEXT: v_ldexp_f32 v0, v1, 1
+; VI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s14, s16, -1
+; VI-NEXT: s_add_i32 s13, s17, -1
+; VI-NEXT: s_sub_i32 s14, s14, s13
+; VI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[18:19], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v12, -v6, v11, 1.0
-; VI-NEXT: v_fma_f32 v11, v12, v11, v11
-; VI-NEXT: v_mul_f32_e32 v12, v10, v11
-; VI-NEXT: v_fma_f32 v13, -v6, v12, v10
-; VI-NEXT: v_fma_f32 v12, v13, v11, v12
-; VI-NEXT: v_fma_f32 v6, -v6, v12, v10
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v6, v6, v11, v12
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v5
-; VI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_30
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s14, 11
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB10_30
; VI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v5, vcc, 11, v8
-; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v9
+; VI-NEXT: s_add_i32 s16, s16, 11
+; VI-NEXT: s_sub_i32 s14, s16, s17
; VI-NEXT: .LBB10_29: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v8, v7
-; VI-NEXT: v_mul_f32_e32 v7, v8, v6
-; VI-NEXT: v_rndne_f32_e32 v7, v7
-; VI-NEXT: v_fma_f32 v7, -v7, v4, v8
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; VI-NEXT: v_add_f32_e32 v9, v7, v4
-; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; VI-NEXT: v_add_u32_e32 v5, vcc, -11, v5
-; VI-NEXT: v_ldexp_f32 v7, v7, 11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v5
-; VI-NEXT: s_cbranch_vccnz .LBB10_29
+; VI-NEXT: v_mul_f32_e32 v2, s15, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s15
+; VI-NEXT: v_readfirstlane_b32 s16, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s17, v2
+; VI-NEXT: s_cselect_b32 s16, s17, s16
+; VI-NEXT: v_ldexp_f32 v2, s16, 11
+; VI-NEXT: v_readfirstlane_b32 s17, v2
+; VI-NEXT: s_add_i32 s14, s14, -11
+; VI-NEXT: s_cmp_gt_i32 s14, 11
+; VI-NEXT: s_mov_b32 s16, s15
+; VI-NEXT: s_mov_b32 s15, s17
+; VI-NEXT: s_cbranch_scc1 .LBB10_29
; VI-NEXT: s_branch .LBB10_31
; VI-NEXT: .LBB10_30:
-; VI-NEXT: v_mov_b32_e32 v8, v7
+; VI-NEXT: s_mov_b32 s16, s15
; VI-NEXT: .LBB10_31: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v5, vcc, -10, v5
-; VI-NEXT: v_ldexp_f32 v5, v8, v5
-; VI-NEXT: v_mul_f32_e32 v6, v5, v6
-; VI-NEXT: v_rndne_f32_e32 v6, v6
-; VI-NEXT: v_fma_f32 v5, -v6, v4, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v4, v5, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; VI-NEXT: v_ldexp_f32 v3, v4, v3
-; VI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; VI-NEXT: s_and_b32 s0, s12, 0x8000
-; VI-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; VI-NEXT: v_or_b32_e32 v3, s0, v3
+; VI-NEXT: s_add_i32 s14, s14, -10
+; VI-NEXT: v_mov_b32_e32 v2, s14
+; VI-NEXT: v_ldexp_f32 v2, s16, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s14, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s15, v0
+; VI-NEXT: s_cselect_b32 s14, s15, s14
+; VI-NEXT: v_mov_b32_e32 v0, s13
+; VI-NEXT: v_ldexp_f32 v0, s14, v0
+; VI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-NEXT: s_and_b32 s14, s11, 0xffff8000
+; VI-NEXT: v_readfirstlane_b32 s13, v0
+; VI-NEXT: s_and_b32 s13, s13, 0x7fff
+; VI-NEXT: s_or_b32 s13, s13, s14
; VI-NEXT: .LBB10_32: ; %Flow124
-; VI-NEXT: v_mov_b32_e32 v4, 0x7c00
-; VI-NEXT: v_cmp_nlg_f16_e64 vcc, s6, 0
-; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |s8|, v4
-; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, 0
-; VI-NEXT: v_cmp_nge_f16_e64 s[4:5], |s4|, v4
-; VI-NEXT: v_cmp_nge_f16_e64 s[8:9], |s9|, v4
-; VI-NEXT: v_cmp_nge_f16_e64 s[12:13], |s12|, v4
-; VI-NEXT: v_mov_b32_e32 v4, 0x7e00
-; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: s_mov_b64 vcc, s[2:3]
-; VI-NEXT: v_cmp_nlg_f16_e64 s[6:7], s7, 0
-; VI-NEXT: v_cndmask_b32_sdwa v1, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: s_mov_b64 vcc, s[4:5]
-; VI-NEXT: v_cmp_nlg_f16_e64 s[10:11], s10, 0
-; VI-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[0:1]
-; VI-NEXT: v_cndmask_b32_sdwa v1, v4, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT: s_mov_b64 vcc, s[6:7]
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_cndmask_b32_sdwa v1, v2, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: s_mov_b64 vcc, s[10:11]
-; VI-NEXT: v_cndmask_b32_sdwa v2, v3, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: s_mov_b64 vcc, s[12:13]
-; VI-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[8:9]
-; VI-NEXT: v_cndmask_b32_sdwa v2, v4, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
-; VI-NEXT: v_mov_b32_e32 v2, s16
-; VI-NEXT: v_mov_b32_e32 v3, s17
+; VI-NEXT: v_cmp_nlg_f16_e64 s[14:15], s4, 0
+; VI-NEXT: v_mov_b32_e32 v0, 0x7c00
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: v_cmp_nge_f16_e64 s[14:15], |s2|, v0
+; VI-NEXT: s_cselect_b32 s16, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: v_cmp_nlg_f16_e64 s[14:15], s8, 0
+; VI-NEXT: s_cselect_b32 s17, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: v_cmp_nge_f16_e64 s[14:15], |s7|, v0
+; VI-NEXT: s_cselect_b32 s8, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: v_cmp_nlg_f16_e64 s[4:5], s5, 0
+; VI-NEXT: s_cselect_b32 s7, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s3|, v0
+; VI-NEXT: s_cselect_b32 s4, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s12, 0
+; VI-NEXT: s_cselect_b32 s5, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |s11|, v0
+; VI-NEXT: s_cselect_b32 s12, 1, 0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b32 s3, 1, 0
+; VI-NEXT: s_and_b32 s2, 0xffff, s6
+; VI-NEXT: s_cmp_lg_u32 s16, 0
+; VI-NEXT: s_cselect_b32 s2, 0x7e00, s2
+; VI-NEXT: s_cmp_lg_u32 s17, 0
+; VI-NEXT: s_cselect_b32 s2, s2, 0x7e00
+; VI-NEXT: s_and_b32 s6, 0xffff, s9
+; VI-NEXT: s_cmp_lg_u32 s8, 0
+; VI-NEXT: s_cselect_b32 s6, 0x7e00, s6
+; VI-NEXT: s_cmp_lg_u32 s7, 0
+; VI-NEXT: s_cselect_b32 s6, s6, 0x7e00
+; VI-NEXT: s_lshl_b32 s6, s6, 16
+; VI-NEXT: s_or_b32 s2, s2, s6
+; VI-NEXT: s_and_b32 s6, 0xffff, s10
+; VI-NEXT: s_cmp_lg_u32 s4, 0
+; VI-NEXT: s_cselect_b32 s4, 0x7e00, s6
+; VI-NEXT: s_cmp_lg_u32 s5, 0
+; VI-NEXT: s_cselect_b32 s4, s4, 0x7e00
+; VI-NEXT: s_and_b32 s5, 0xffff, s13
+; VI-NEXT: s_cmp_lg_u32 s12, 0
+; VI-NEXT: s_cselect_b32 s5, 0x7e00, s5
+; VI-NEXT: s_cmp_lg_u32 s3, 0
+; VI-NEXT: s_cselect_b32 s3, s5, 0x7e00
+; VI-NEXT: s_lshl_b32 s3, s3, 16
+; VI-NEXT: s_or_b32 s3, s4, s3
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
%gep2 = getelementptr <4 x half>, ptr addrspace(1) %in2, i32 4
@@ -2117,170 +2523,207 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; CI-NEXT: s_mov_b32 s6, 1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x8
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s4
-; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s2|, |v0|
-; CI-NEXT: ; implicit-def: $vgpr0
-; CI-NEXT: s_cbranch_vccz .LBB11_2
+; CI-NEXT: v_cmp_ngt_f32_e64 s[6:7], |s2|, |v0|
+; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; CI-NEXT: s_mov_b32 s7, 1
+; CI-NEXT: ; implicit-def: $sgpr6
+; CI-NEXT: s_cbranch_scc0 .LBB11_2
; CI-NEXT: ; %bb.1: ; %frem.else16
-; CI-NEXT: s_and_b32 s6, s2, 0x80000000
-; CI-NEXT: v_mov_b32_e32 v1, s4
-; CI-NEXT: v_mov_b32_e32 v0, s2
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s2|, |v1|
-; CI-NEXT: v_mov_b32_e32 v1, s6
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CI-NEXT: s_mov_b32 s6, 0
+; CI-NEXT: v_mov_b32_e32 v0, s4
+; CI-NEXT: s_and_b32 s8, s2, 0x80000000
+; CI-NEXT: v_cmp_eq_f32_e64 s[6:7], |s2|, |v0|
+; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; CI-NEXT: s_cselect_b32 s6, s8, s2
+; CI-NEXT: s_mov_b32 s7, 0
; CI-NEXT: .LBB11_2: ; %Flow53
-; CI-NEXT: s_xor_b32 s6, s6, 1
-; CI-NEXT: s_cmp_lg_u32 s6, 0
+; CI-NEXT: s_xor_b32 s7, s7, 1
+; CI-NEXT: s_cmp_lg_u32 s7, 0
; CI-NEXT: s_cbranch_scc1 .LBB11_8
; CI-NEXT: ; %bb.3: ; %frem.compute15
-; CI-NEXT: v_frexp_mant_f32_e64 v1, |s4|
-; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1
-; CI-NEXT: v_div_scale_f32 v3, s[6:7], v1, v1, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v0, |s2|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s2|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s4|
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5
-; CI-NEXT: v_ldexp_f32_e64 v4, v0, 12
-; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; CI-NEXT: v_rcp_f32_e32 v8, v3
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s2|
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s4|
+; CI-NEXT: v_readfirstlane_b32 s9, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s4|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1
+; CI-NEXT: v_readfirstlane_b32 s10, v1
+; CI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s7, s9, -1
+; CI-NEXT: s_add_i32 s6, s10, -1
+; CI-NEXT: s_sub_i32 s7, s7, s6
+; CI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; CI-NEXT: v_fma_f32 v8, v9, v8, v8
-; CI-NEXT: v_mul_f32_e32 v9, v7, v8
-; CI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; CI-NEXT: v_fma_f32 v9, v10, v8, v9
-; CI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2
-; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB11_6
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s7, 12
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB11_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
-; CI-NEXT: v_add_i32_e32 v2, vcc, 12, v5
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; CI-NEXT: s_add_i32 s9, s9, 12
+; CI-NEXT: s_sub_i32 s7, s9, s10
; CI-NEXT: .LBB11_5: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v5, v4
-; CI-NEXT: v_mul_f32_e32 v4, v5, v3
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v6, v4, v1
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_add_i32_e32 v2, vcc, -12, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 12
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2
-; CI-NEXT: s_cbranch_vccnz .LBB11_5
+; CI-NEXT: v_mul_f32_e32 v2, s8, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s8
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s9, v2
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s10, v2
+; CI-NEXT: s_cselect_b32 s9, s10, s9
+; CI-NEXT: v_ldexp_f32_e64 v2, s9, 12
+; CI-NEXT: v_readfirstlane_b32 s10, v2
+; CI-NEXT: s_add_i32 s7, s7, -12
+; CI-NEXT: s_cmp_gt_i32 s7, 12
+; CI-NEXT: s_mov_b32 s9, s8
+; CI-NEXT: s_mov_b32 s8, s10
+; CI-NEXT: s_cbranch_scc1 .LBB11_5
; CI-NEXT: s_branch .LBB11_7
; CI-NEXT: .LBB11_6:
-; CI-NEXT: v_mov_b32_e32 v5, v4
+; CI-NEXT: s_mov_b32 s9, s8
; CI-NEXT: .LBB11_7: ; %frem.loop_exit24
-; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2
-; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2
-; CI-NEXT: v_mul_f32_e32 v3, v2, v3
-; CI-NEXT: v_rndne_f32_e32 v3, v3
-; CI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; CI-NEXT: v_add_f32_e32 v1, v2, v1
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0
-; CI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; CI-NEXT: s_and_b32 s6, s2, 0x80000000
-; CI-NEXT: v_or_b32_e32 v0, s6, v0
+; CI-NEXT: s_add_i32 s7, s7, -11
+; CI-NEXT: v_mov_b32_e32 v2, s7
+; CI-NEXT: v_ldexp_f32_e32 v2, s9, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s7, v1
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: s_cselect_b32 s7, s8, s7
+; CI-NEXT: v_mov_b32_e32 v0, s6
+; CI-NEXT: v_ldexp_f32_e32 v0, s7, v0
+; CI-NEXT: v_readfirstlane_b32 s6, v0
+; CI-NEXT: s_bitset0_b32 s6, 31
+; CI-NEXT: s_and_b32 s7, s2, 0x80000000
+; CI-NEXT: s_or_b32 s6, s6, s7
; CI-NEXT: .LBB11_8: ; %Flow54
-; CI-NEXT: v_mov_b32_e32 v1, s5
-; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s3|, |v1|
-; CI-NEXT: s_mov_b32 s6, 1
-; CI-NEXT: ; implicit-def: $vgpr1
-; CI-NEXT: s_cbranch_vccz .LBB11_10
+; CI-NEXT: v_mov_b32_e32 v0, s5
+; CI-NEXT: v_cmp_ngt_f32_e64 s[8:9], |s3|, |v0|
+; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9]
+; CI-NEXT: s_mov_b32 s8, 1
+; CI-NEXT: ; implicit-def: $sgpr7
+; CI-NEXT: s_cbranch_scc0 .LBB11_10
; CI-NEXT: ; %bb.9: ; %frem.else
-; CI-NEXT: s_and_b32 s6, s3, 0x80000000
-; CI-NEXT: v_mov_b32_e32 v2, s5
-; CI-NEXT: v_mov_b32_e32 v1, s3
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s3|, |v2|
-; CI-NEXT: v_mov_b32_e32 v2, s6
-; CI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; CI-NEXT: s_mov_b32 s6, 0
+; CI-NEXT: v_mov_b32_e32 v0, s5
+; CI-NEXT: s_and_b32 s7, s3, 0x80000000
+; CI-NEXT: v_cmp_eq_f32_e64 s[8:9], |s3|, |v0|
+; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9]
+; CI-NEXT: s_cselect_b32 s7, s7, s3
+; CI-NEXT: s_mov_b32 s8, 0
; CI-NEXT: .LBB11_10: ; %Flow49
-; CI-NEXT: s_xor_b32 s6, s6, 1
-; CI-NEXT: s_cmp_lg_u32 s6, 0
+; CI-NEXT: s_xor_b32 s8, s8, 1
+; CI-NEXT: s_cmp_lg_u32 s8, 0
; CI-NEXT: s_cbranch_scc1 .LBB11_16
; CI-NEXT: ; %bb.11: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f32_e64 v2, |s5|
-; CI-NEXT: v_ldexp_f32_e64 v2, v2, 1
-; CI-NEXT: v_div_scale_f32 v4, s[6:7], v2, v2, 1.0
-; CI-NEXT: v_frexp_mant_f32_e64 v1, |s3|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s3|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s5|
-; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v6
-; CI-NEXT: v_ldexp_f32_e64 v5, v1, 12
-; CI-NEXT: v_add_i32_e32 v1, vcc, -1, v7
-; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v1
-; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0
-; CI-NEXT: v_rcp_f32_e32 v9, v4
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s3|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s3|
+; CI-NEXT: v_readfirstlane_b32 s9, v0
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s5|
+; CI-NEXT: v_readfirstlane_b32 s10, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s5|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1
+; CI-NEXT: v_readfirstlane_b32 s11, v1
+; CI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s8, s10, -1
+; CI-NEXT: s_add_i32 s7, s11, -1
+; CI-NEXT: s_sub_i32 s8, s8, s7
+; CI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v10, -v4, v9, 1.0
-; CI-NEXT: v_fma_f32 v9, v10, v9, v9
-; CI-NEXT: v_mul_f32_e32 v10, v8, v9
-; CI-NEXT: v_fma_f32 v11, -v4, v10, v8
-; CI-NEXT: v_fma_f32 v10, v11, v9, v10
-; CI-NEXT: v_fma_f32 v4, -v4, v10, v8
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v4, v4, v9, v10
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v3
-; CI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB11_14
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s8, 12
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB11_14
; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v3, vcc, 12, v6
-; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
+; CI-NEXT: s_add_i32 s10, s10, 12
+; CI-NEXT: s_sub_i32 s8, s10, s11
; CI-NEXT: .LBB11_13: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v6, v5
-; CI-NEXT: v_mul_f32_e32 v5, v6, v4
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v5, -v5, v2, v6
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v7, v5, v2
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; CI-NEXT: v_add_i32_e32 v3, vcc, -12, v3
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 12
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v3
-; CI-NEXT: s_cbranch_vccnz .LBB11_13
+; CI-NEXT: v_mul_f32_e32 v2, s9, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s9
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s12, v2
+; CI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s10, v2
+; CI-NEXT: s_cselect_b32 s10, s10, s12
+; CI-NEXT: v_ldexp_f32_e64 v2, s10, 12
+; CI-NEXT: v_readfirstlane_b32 s11, v2
+; CI-NEXT: s_add_i32 s8, s8, -12
+; CI-NEXT: s_cmp_gt_i32 s8, 12
+; CI-NEXT: s_mov_b32 s10, s9
+; CI-NEXT: s_mov_b32 s9, s11
+; CI-NEXT: s_cbranch_scc1 .LBB11_13
; CI-NEXT: s_branch .LBB11_15
; CI-NEXT: .LBB11_14:
-; CI-NEXT: v_mov_b32_e32 v6, v5
+; CI-NEXT: s_mov_b32 s10, s9
; CI-NEXT: .LBB11_15: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v3, vcc, -11, v3
-; CI-NEXT: v_ldexp_f32_e32 v3, v6, v3
-; CI-NEXT: v_mul_f32_e32 v4, v3, v4
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; CI-NEXT: v_add_f32_e32 v2, v3, v2
-; CI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; CI-NEXT: v_ldexp_f32_e32 v1, v2, v1
-; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; CI-NEXT: s_and_b32 s6, s3, 0x80000000
-; CI-NEXT: v_or_b32_e32 v1, s6, v1
+; CI-NEXT: s_add_i32 s8, s8, -11
+; CI-NEXT: v_mov_b32_e32 v2, s8
+; CI-NEXT: v_ldexp_f32_e32 v2, s10, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s10, v1
+; CI-NEXT: v_readfirstlane_b32 s8, v0
+; CI-NEXT: s_cselect_b32 s8, s8, s10
+; CI-NEXT: v_mov_b32_e32 v0, s7
+; CI-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; CI-NEXT: v_readfirstlane_b32 s7, v0
+; CI-NEXT: s_bitset0_b32 s7, 31
+; CI-NEXT: s_and_b32 s8, s3, 0x80000000
+; CI-NEXT: s_or_b32 s7, s7, s8
; CI-NEXT: .LBB11_16: ; %Flow50
-; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s4, 0
-; CI-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; CI-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s2|, v3
-; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s5, 0
-; CI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s3|, v3
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; CI-NEXT: v_cmp_nlg_f32_e64 s[8:9], s4, 0
+; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9]
+; CI-NEXT: v_mov_b32_e32 v0, 0x7f800000
+; CI-NEXT: v_cmp_nge_f32_e64 s[8:9], |s2|, v0
+; CI-NEXT: s_cselect_b32 s4, 0x7fc00000, s6
+; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9]
+; CI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000
+; CI-NEXT: v_cmp_nlg_f32_e64 s[4:5], s5, 0
+; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; CI-NEXT: v_cmp_nge_f32_e64 s[4:5], |s3|, v0
+; CI-NEXT: s_cselect_b32 s6, 0x7fc00000, s7
+; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; CI-NEXT: s_cselect_b32 s3, s6, 0x7fc00000
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
@@ -2290,171 +2733,208 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NEXT: s_mov_b32 s6, 1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x20
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s4
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s2|, |v0|
-; VI-NEXT: ; implicit-def: $vgpr0
-; VI-NEXT: s_cbranch_vccz .LBB11_2
+; VI-NEXT: v_cmp_ngt_f32_e64 s[6:7], |s2|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-NEXT: s_mov_b32 s7, 1
+; VI-NEXT: ; implicit-def: $sgpr6
+; VI-NEXT: s_cbranch_scc0 .LBB11_2
; VI-NEXT: ; %bb.1: ; %frem.else16
-; VI-NEXT: s_and_b32 s6, s2, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v1, s4
-; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s2|, |v1|
-; VI-NEXT: v_mov_b32_e32 v1, s6
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_mov_b32 s6, 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: s_and_b32 s8, s2, 0x80000000
+; VI-NEXT: v_cmp_eq_f32_e64 s[6:7], |s2|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-NEXT: s_cselect_b32 s6, s8, s2
+; VI-NEXT: s_mov_b32 s7, 0
; VI-NEXT: .LBB11_2: ; %Flow53
-; VI-NEXT: s_xor_b32 s6, s6, 1
-; VI-NEXT: s_cmp_lg_u32 s6, 0
+; VI-NEXT: s_xor_b32 s7, s7, 1
+; VI-NEXT: s_cmp_lg_u32 s7, 0
; VI-NEXT: s_cbranch_scc1 .LBB11_8
; VI-NEXT: ; %bb.3: ; %frem.compute15
-; VI-NEXT: v_frexp_mant_f32_e64 v1, |s4|
-; VI-NEXT: v_ldexp_f32 v1, v1, 1
-; VI-NEXT: v_div_scale_f32 v3, s[6:7], v1, v1, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v0, |s2|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s2|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s4|
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5
-; VI-NEXT: v_ldexp_f32 v4, v0, 12
-; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; VI-NEXT: v_rcp_f32_e32 v8, v3
+; VI-NEXT: v_ldexp_f32 v0, v0, 12
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s2|
+; VI-NEXT: v_readfirstlane_b32 s8, v0
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s4|
+; VI-NEXT: v_readfirstlane_b32 s9, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s4|
+; VI-NEXT: v_ldexp_f32 v0, v0, 1
+; VI-NEXT: v_readfirstlane_b32 s10, v1
+; VI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s7, s9, -1
+; VI-NEXT: s_add_i32 s6, s10, -1
+; VI-NEXT: s_sub_i32 s7, s7, s6
+; VI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; VI-NEXT: v_fma_f32 v8, v9, v8, v8
-; VI-NEXT: v_mul_f32_e32 v9, v7, v8
-; VI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; VI-NEXT: v_fma_f32 v9, v10, v8, v9
-; VI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2
-; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB11_6
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s7, 12
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB11_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
-; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v5
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6
+; VI-NEXT: s_add_i32 s9, s9, 12
+; VI-NEXT: s_sub_i32 s7, s9, s10
; VI-NEXT: .LBB11_5: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v5, v4
-; VI-NEXT: v_mul_f32_e32 v4, v5, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v6, v4, v1
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, -12, v2
-; VI-NEXT: v_ldexp_f32 v4, v4, 12
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2
-; VI-NEXT: s_cbranch_vccnz .LBB11_5
+; VI-NEXT: v_mul_f32_e32 v2, s8, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s8
+; VI-NEXT: v_readfirstlane_b32 s9, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s10, v2
+; VI-NEXT: s_cselect_b32 s9, s10, s9
+; VI-NEXT: v_ldexp_f32 v2, s9, 12
+; VI-NEXT: v_readfirstlane_b32 s10, v2
+; VI-NEXT: s_add_i32 s7, s7, -12
+; VI-NEXT: s_cmp_gt_i32 s7, 12
+; VI-NEXT: s_mov_b32 s9, s8
+; VI-NEXT: s_mov_b32 s8, s10
+; VI-NEXT: s_cbranch_scc1 .LBB11_5
; VI-NEXT: s_branch .LBB11_7
; VI-NEXT: .LBB11_6:
-; VI-NEXT: v_mov_b32_e32 v5, v4
+; VI-NEXT: s_mov_b32 s9, s8
; VI-NEXT: .LBB11_7: ; %frem.loop_exit24
-; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2
-; VI-NEXT: v_ldexp_f32 v2, v5, v2
-; VI-NEXT: v_mul_f32_e32 v3, v2, v3
-; VI-NEXT: v_rndne_f32_e32 v3, v3
-; VI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_ldexp_f32 v0, v1, v0
-; VI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; VI-NEXT: s_and_b32 s6, s2, 0x80000000
-; VI-NEXT: v_or_b32_e32 v0, s6, v0
+; VI-NEXT: s_add_i32 s7, s7, -11
+; VI-NEXT: v_mov_b32_e32 v2, s7
+; VI-NEXT: v_ldexp_f32 v2, s9, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s7, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s8, v0
+; VI-NEXT: s_cselect_b32 s7, s8, s7
+; VI-NEXT: v_mov_b32_e32 v0, s6
+; VI-NEXT: v_ldexp_f32 v0, s7, v0
+; VI-NEXT: v_readfirstlane_b32 s6, v0
+; VI-NEXT: s_bitset0_b32 s6, 31
+; VI-NEXT: s_and_b32 s7, s2, 0x80000000
+; VI-NEXT: s_or_b32 s6, s6, s7
; VI-NEXT: .LBB11_8: ; %Flow54
-; VI-NEXT: v_mov_b32_e32 v1, s5
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s3|, |v1|
-; VI-NEXT: s_mov_b32 s6, 1
-; VI-NEXT: ; implicit-def: $vgpr1
-; VI-NEXT: s_cbranch_vccz .LBB11_10
+; VI-NEXT: v_mov_b32_e32 v0, s5
+; VI-NEXT: v_cmp_ngt_f32_e64 s[8:9], |s3|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[8:9], 0
+; VI-NEXT: s_mov_b32 s8, 1
+; VI-NEXT: ; implicit-def: $sgpr7
+; VI-NEXT: s_cbranch_scc0 .LBB11_10
; VI-NEXT: ; %bb.9: ; %frem.else
-; VI-NEXT: s_and_b32 s6, s3, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v2, s5
-; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s3|, |v2|
-; VI-NEXT: v_mov_b32_e32 v2, s6
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NEXT: s_mov_b32 s6, 0
+; VI-NEXT: v_mov_b32_e32 v0, s5
+; VI-NEXT: s_and_b32 s7, s3, 0x80000000
+; VI-NEXT: v_cmp_eq_f32_e64 s[8:9], |s3|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[8:9], 0
+; VI-NEXT: s_cselect_b32 s7, s7, s3
+; VI-NEXT: s_mov_b32 s8, 0
; VI-NEXT: .LBB11_10: ; %Flow49
-; VI-NEXT: s_xor_b32 s6, s6, 1
-; VI-NEXT: s_cmp_lg_u32 s6, 0
+; VI-NEXT: s_xor_b32 s8, s8, 1
+; VI-NEXT: s_cmp_lg_u32 s8, 0
; VI-NEXT: s_cbranch_scc1 .LBB11_16
; VI-NEXT: ; %bb.11: ; %frem.compute
-; VI-NEXT: v_frexp_mant_f32_e64 v2, |s5|
-; VI-NEXT: v_ldexp_f32 v2, v2, 1
-; VI-NEXT: v_div_scale_f32 v4, s[6:7], v2, v2, 1.0
-; VI-NEXT: v_frexp_mant_f32_e64 v1, |s3|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s3|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s5|
-; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v6
-; VI-NEXT: v_ldexp_f32 v5, v1, 12
-; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v7
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0
-; VI-NEXT: v_rcp_f32_e32 v9, v4
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s3|
+; VI-NEXT: v_ldexp_f32 v0, v0, 12
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s3|
+; VI-NEXT: v_readfirstlane_b32 s9, v0
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s5|
+; VI-NEXT: v_readfirstlane_b32 s10, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s5|
+; VI-NEXT: v_ldexp_f32 v0, v0, 1
+; VI-NEXT: v_readfirstlane_b32 s11, v1
+; VI-NEXT: v_div_scale_f32 v1, s[12:13], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s8, s10, -1
+; VI-NEXT: s_add_i32 s7, s11, -1
+; VI-NEXT: s_sub_i32 s8, s8, s7
+; VI-NEXT: v_div_scale_f32 v2, s[12:13], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v10, -v4, v9, 1.0
-; VI-NEXT: v_fma_f32 v9, v10, v9, v9
-; VI-NEXT: v_mul_f32_e32 v10, v8, v9
-; VI-NEXT: v_fma_f32 v11, -v4, v10, v8
-; VI-NEXT: v_fma_f32 v10, v11, v9, v10
-; VI-NEXT: v_fma_f32 v4, -v4, v10, v8
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v4, v4, v9, v10
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v3
-; VI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB11_14
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s8, 12
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB11_14
; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v6
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v7
+; VI-NEXT: s_add_i32 s10, s10, 12
+; VI-NEXT: s_sub_i32 s8, s10, s11
; VI-NEXT: .LBB11_13: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v6, v5
-; VI-NEXT: v_mul_f32_e32 v5, v6, v4
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v5, -v5, v2, v6
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v7, v5, v2
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; VI-NEXT: v_add_u32_e32 v3, vcc, -12, v3
-; VI-NEXT: v_ldexp_f32 v5, v5, 12
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v3
-; VI-NEXT: s_cbranch_vccnz .LBB11_13
+; VI-NEXT: v_mul_f32_e32 v2, s9, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s9
+; VI-NEXT: v_readfirstlane_b32 s10, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s11, v2
+; VI-NEXT: s_cselect_b32 s10, s11, s10
+; VI-NEXT: v_ldexp_f32 v2, s10, 12
+; VI-NEXT: v_readfirstlane_b32 s11, v2
+; VI-NEXT: s_add_i32 s8, s8, -12
+; VI-NEXT: s_cmp_gt_i32 s8, 12
+; VI-NEXT: s_mov_b32 s10, s9
+; VI-NEXT: s_mov_b32 s9, s11
+; VI-NEXT: s_cbranch_scc1 .LBB11_13
; VI-NEXT: s_branch .LBB11_15
; VI-NEXT: .LBB11_14:
-; VI-NEXT: v_mov_b32_e32 v6, v5
+; VI-NEXT: s_mov_b32 s10, s9
; VI-NEXT: .LBB11_15: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v3, vcc, -11, v3
-; VI-NEXT: v_ldexp_f32 v3, v6, v3
-; VI-NEXT: v_mul_f32_e32 v4, v3, v4
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; VI-NEXT: v_ldexp_f32 v1, v2, v1
-; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; VI-NEXT: s_and_b32 s6, s3, 0x80000000
-; VI-NEXT: v_or_b32_e32 v1, s6, v1
+; VI-NEXT: s_add_i32 s8, s8, -11
+; VI-NEXT: v_mov_b32_e32 v2, s8
+; VI-NEXT: v_ldexp_f32 v2, s10, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s8, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s9, v0
+; VI-NEXT: s_cselect_b32 s8, s9, s8
+; VI-NEXT: v_mov_b32_e32 v0, s7
+; VI-NEXT: v_ldexp_f32 v0, s8, v0
+; VI-NEXT: v_readfirstlane_b32 s7, v0
+; VI-NEXT: s_bitset0_b32 s7, 31
+; VI-NEXT: s_and_b32 s8, s3, 0x80000000
+; VI-NEXT: s_or_b32 s7, s7, s8
; VI-NEXT: .LBB11_16: ; %Flow50
-; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s4, 0
-; VI-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; VI-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s2|, v3
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s5, 0
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s3|, v3
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; VI-NEXT: v_cmp_nlg_f32_e64 s[8:9], s4, 0
+; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000
+; VI-NEXT: s_cmp_lg_u64 s[8:9], 0
+; VI-NEXT: v_cmp_nge_f32_e64 s[8:9], |s2|, v0
+; VI-NEXT: s_cselect_b32 s4, 0x7fc00000, s6
+; VI-NEXT: s_cmp_lg_u64 s[8:9], 0
+; VI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000
+; VI-NEXT: v_cmp_nlg_f32_e64 s[4:5], s5, 0
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: v_cmp_nge_f32_e64 s[4:5], |s3|, v0
+; VI-NEXT: s_cselect_b32 s6, 0x7fc00000, s7
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: s_cselect_b32 s3, s6, 0x7fc00000
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -2474,325 +2954,400 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; CI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10
-; CI-NEXT: s_mov_b32 s2, 1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s8
-; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s4|, |v0|
-; CI-NEXT: ; implicit-def: $vgpr0
-; CI-NEXT: s_cbranch_vccz .LBB12_2
+; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |s4|, |v0|
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: s_mov_b32 s3, 1
+; CI-NEXT: ; implicit-def: $sgpr2
+; CI-NEXT: s_cbranch_scc0 .LBB12_2
; CI-NEXT: ; %bb.1: ; %frem.else78
-; CI-NEXT: s_and_b32 s2, s4, 0x80000000
-; CI-NEXT: v_mov_b32_e32 v1, s8
-; CI-NEXT: v_mov_b32_e32 v0, s4
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s4|, |v1|
-; CI-NEXT: v_mov_b32_e32 v1, s2
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v0, s8
+; CI-NEXT: s_and_b32 s12, s4, 0x80000000
+; CI-NEXT: v_cmp_eq_f32_e64 s[2:3], |s4|, |v0|
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: s_cselect_b32 s2, s12, s4
+; CI-NEXT: s_mov_b32 s3, 0
; CI-NEXT: .LBB12_2: ; %Flow127
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s3, s3, 1
+; CI-NEXT: s_cmp_lg_u32 s3, 0
; CI-NEXT: s_cbranch_scc1 .LBB12_8
; CI-NEXT: ; %bb.3: ; %frem.compute77
-; CI-NEXT: v_frexp_mant_f32_e64 v1, |s8|
-; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1
-; CI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v0, |s4|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s4|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s8|
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5
-; CI-NEXT: v_ldexp_f32_e64 v4, v0, 12
-; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; CI-NEXT: v_rcp_f32_e32 v8, v3
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s4|
+; CI-NEXT: v_readfirstlane_b32 s12, v0
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s8|
+; CI-NEXT: v_readfirstlane_b32 s13, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s8|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1
+; CI-NEXT: v_readfirstlane_b32 s14, v1
+; CI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s3, s13, -1
+; CI-NEXT: s_add_i32 s2, s14, -1
+; CI-NEXT: s_sub_i32 s3, s3, s2
+; CI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; CI-NEXT: v_fma_f32 v8, v9, v8, v8
-; CI-NEXT: v_mul_f32_e32 v9, v7, v8
-; CI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; CI-NEXT: v_fma_f32 v9, v10, v8, v9
-; CI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2
-; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_6
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s3, 12
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB12_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
-; CI-NEXT: v_add_i32_e32 v2, vcc, 12, v5
-; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; CI-NEXT: s_add_i32 s13, s13, 12
+; CI-NEXT: s_sub_i32 s3, s13, s14
; CI-NEXT: .LBB12_5: ; %frem.loop_body85
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v5, v4
-; CI-NEXT: v_mul_f32_e32 v4, v5, v3
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v6, v4, v1
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_add_i32_e32 v2, vcc, -12, v2
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 12
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2
-; CI-NEXT: s_cbranch_vccnz .LBB12_5
+; CI-NEXT: v_mul_f32_e32 v2, s12, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s12
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s13, v2
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s14, v2
+; CI-NEXT: s_cselect_b32 s13, s14, s13
+; CI-NEXT: v_ldexp_f32_e64 v2, s13, 12
+; CI-NEXT: v_readfirstlane_b32 s14, v2
+; CI-NEXT: s_add_i32 s3, s3, -12
+; CI-NEXT: s_cmp_gt_i32 s3, 12
+; CI-NEXT: s_mov_b32 s13, s12
+; CI-NEXT: s_mov_b32 s12, s14
+; CI-NEXT: s_cbranch_scc1 .LBB12_5
; CI-NEXT: s_branch .LBB12_7
; CI-NEXT: .LBB12_6:
-; CI-NEXT: v_mov_b32_e32 v5, v4
+; CI-NEXT: s_mov_b32 s13, s12
; CI-NEXT: .LBB12_7: ; %frem.loop_exit86
-; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2
-; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2
-; CI-NEXT: v_mul_f32_e32 v3, v2, v3
-; CI-NEXT: v_rndne_f32_e32 v3, v3
-; CI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; CI-NEXT: v_add_f32_e32 v1, v2, v1
-; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0
-; CI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; CI-NEXT: s_and_b32 s2, s4, 0x80000000
-; CI-NEXT: v_or_b32_e32 v0, s2, v0
+; CI-NEXT: s_add_i32 s3, s3, -11
+; CI-NEXT: v_mov_b32_e32 v2, s3
+; CI-NEXT: v_ldexp_f32_e32 v2, s13, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s3, v1
+; CI-NEXT: v_readfirstlane_b32 s12, v0
+; CI-NEXT: s_cselect_b32 s3, s12, s3
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: v_ldexp_f32_e32 v0, s3, v0
+; CI-NEXT: v_readfirstlane_b32 s2, v0
+; CI-NEXT: s_bitset0_b32 s2, 31
+; CI-NEXT: s_and_b32 s3, s4, 0x80000000
+; CI-NEXT: s_or_b32 s2, s2, s3
; CI-NEXT: .LBB12_8: ; %Flow128
-; CI-NEXT: v_mov_b32_e32 v1, s9
-; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s5|, |v1|
-; CI-NEXT: s_mov_b32 s2, 1
-; CI-NEXT: ; implicit-def: $vgpr1
-; CI-NEXT: s_cbranch_vccz .LBB12_10
+; CI-NEXT: v_mov_b32_e32 v0, s9
+; CI-NEXT: v_cmp_ngt_f32_e64 s[12:13], |s5|, |v0|
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: s_mov_b32 s12, 1
+; CI-NEXT: ; implicit-def: $sgpr3
+; CI-NEXT: s_cbranch_scc0 .LBB12_10
; CI-NEXT: ; %bb.9: ; %frem.else47
-; CI-NEXT: s_and_b32 s2, s5, 0x80000000
-; CI-NEXT: v_mov_b32_e32 v2, s9
-; CI-NEXT: v_mov_b32_e32 v1, s5
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s5|, |v2|
-; CI-NEXT: v_mov_b32_e32 v2, s2
-; CI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v0, s9
+; CI-NEXT: s_and_b32 s3, s5, 0x80000000
+; CI-NEXT: v_cmp_eq_f32_e64 s[12:13], |s5|, |v0|
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: s_cselect_b32 s3, s3, s5
+; CI-NEXT: s_mov_b32 s12, 0
; CI-NEXT: .LBB12_10: ; %Flow123
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s12, s12, 1
+; CI-NEXT: s_cmp_lg_u32 s12, 0
; CI-NEXT: s_cbranch_scc1 .LBB12_16
; CI-NEXT: ; %bb.11: ; %frem.compute46
-; CI-NEXT: v_frexp_mant_f32_e64 v2, |s9|
-; CI-NEXT: v_ldexp_f32_e64 v2, v2, 1
-; CI-NEXT: v_div_scale_f32 v4, s[2:3], v2, v2, 1.0
-; CI-NEXT: v_frexp_mant_f32_e64 v1, |s5|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s5|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s9|
-; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v6
-; CI-NEXT: v_ldexp_f32_e64 v5, v1, 12
-; CI-NEXT: v_add_i32_e32 v1, vcc, -1, v7
-; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v1
-; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0
-; CI-NEXT: v_rcp_f32_e32 v9, v4
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s5|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s5|
+; CI-NEXT: v_readfirstlane_b32 s13, v0
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s9|
+; CI-NEXT: v_readfirstlane_b32 s14, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s9|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1
+; CI-NEXT: v_readfirstlane_b32 s15, v1
+; CI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s12, s14, -1
+; CI-NEXT: s_add_i32 s3, s15, -1
+; CI-NEXT: s_sub_i32 s12, s12, s3
+; CI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v10, -v4, v9, 1.0
-; CI-NEXT: v_fma_f32 v9, v10, v9, v9
-; CI-NEXT: v_mul_f32_e32 v10, v8, v9
-; CI-NEXT: v_fma_f32 v11, -v4, v10, v8
-; CI-NEXT: v_fma_f32 v10, v11, v9, v10
-; CI-NEXT: v_fma_f32 v4, -v4, v10, v8
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v4, v4, v9, v10
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v3
-; CI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_14
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s12, 12
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB12_14
; CI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
-; CI-NEXT: v_add_i32_e32 v3, vcc, 12, v6
-; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
+; CI-NEXT: s_add_i32 s14, s14, 12
+; CI-NEXT: s_sub_i32 s12, s14, s15
; CI-NEXT: .LBB12_13: ; %frem.loop_body54
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v6, v5
-; CI-NEXT: v_mul_f32_e32 v5, v6, v4
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v5, -v5, v2, v6
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v7, v5, v2
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; CI-NEXT: v_add_i32_e32 v3, vcc, -12, v3
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 12
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v3
-; CI-NEXT: s_cbranch_vccnz .LBB12_13
+; CI-NEXT: v_mul_f32_e32 v2, s13, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s13
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s16, v2
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s14, v2
+; CI-NEXT: s_cselect_b32 s14, s14, s16
+; CI-NEXT: v_ldexp_f32_e64 v2, s14, 12
+; CI-NEXT: v_readfirstlane_b32 s15, v2
+; CI-NEXT: s_add_i32 s12, s12, -12
+; CI-NEXT: s_cmp_gt_i32 s12, 12
+; CI-NEXT: s_mov_b32 s14, s13
+; CI-NEXT: s_mov_b32 s13, s15
+; CI-NEXT: s_cbranch_scc1 .LBB12_13
; CI-NEXT: s_branch .LBB12_15
; CI-NEXT: .LBB12_14:
-; CI-NEXT: v_mov_b32_e32 v6, v5
+; CI-NEXT: s_mov_b32 s14, s13
; CI-NEXT: .LBB12_15: ; %frem.loop_exit55
-; CI-NEXT: v_add_i32_e32 v3, vcc, -11, v3
-; CI-NEXT: v_ldexp_f32_e32 v3, v6, v3
-; CI-NEXT: v_mul_f32_e32 v4, v3, v4
-; CI-NEXT: v_rndne_f32_e32 v4, v4
-; CI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; CI-NEXT: v_add_f32_e32 v2, v3, v2
-; CI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; CI-NEXT: v_ldexp_f32_e32 v1, v2, v1
-; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; CI-NEXT: s_and_b32 s2, s5, 0x80000000
-; CI-NEXT: v_or_b32_e32 v1, s2, v1
+; CI-NEXT: s_add_i32 s12, s12, -11
+; CI-NEXT: v_mov_b32_e32 v2, s12
+; CI-NEXT: v_ldexp_f32_e32 v2, s14, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s14, v1
+; CI-NEXT: v_readfirstlane_b32 s12, v0
+; CI-NEXT: s_cselect_b32 s12, s12, s14
+; CI-NEXT: v_mov_b32_e32 v0, s3
+; CI-NEXT: v_ldexp_f32_e32 v0, s12, v0
+; CI-NEXT: v_readfirstlane_b32 s3, v0
+; CI-NEXT: s_bitset0_b32 s3, 31
+; CI-NEXT: s_and_b32 s12, s5, 0x80000000
+; CI-NEXT: s_or_b32 s3, s3, s12
; CI-NEXT: .LBB12_16: ; %Flow124
-; CI-NEXT: v_mov_b32_e32 v2, s10
-; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s6|, |v2|
-; CI-NEXT: s_mov_b32 s2, 1
-; CI-NEXT: ; implicit-def: $vgpr2
-; CI-NEXT: s_cbranch_vccz .LBB12_18
+; CI-NEXT: v_mov_b32_e32 v0, s10
+; CI-NEXT: v_cmp_ngt_f32_e64 s[12:13], |s6|, |v0|
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: s_mov_b32 s13, 1
+; CI-NEXT: ; implicit-def: $sgpr12
+; CI-NEXT: s_cbranch_scc0 .LBB12_18
; CI-NEXT: ; %bb.17: ; %frem.else16
-; CI-NEXT: s_and_b32 s2, s6, 0x80000000
-; CI-NEXT: v_mov_b32_e32 v3, s10
-; CI-NEXT: v_mov_b32_e32 v2, s6
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s6|, |v3|
-; CI-NEXT: v_mov_b32_e32 v3, s2
-; CI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v0, s10
+; CI-NEXT: s_and_b32 s14, s6, 0x80000000
+; CI-NEXT: v_cmp_eq_f32_e64 s[12:13], |s6|, |v0|
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: s_cselect_b32 s12, s14, s6
+; CI-NEXT: s_mov_b32 s13, 0
; CI-NEXT: .LBB12_18: ; %Flow119
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s13, s13, 1
+; CI-NEXT: s_cmp_lg_u32 s13, 0
; CI-NEXT: s_cbranch_scc1 .LBB12_24
; CI-NEXT: ; %bb.19: ; %frem.compute15
-; CI-NEXT: v_frexp_mant_f32_e64 v3, |s10|
-; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1
-; CI-NEXT: v_div_scale_f32 v5, s[2:3], v3, v3, 1.0
-; CI-NEXT: v_frexp_mant_f32_e64 v2, |s6|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s6|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v8, |s10|
-; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v7
-; CI-NEXT: v_ldexp_f32_e64 v6, v2, 12
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
-; CI-NEXT: v_sub_i32_e32 v4, vcc, v4, v2
-; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v3, 1.0
-; CI-NEXT: v_rcp_f32_e32 v10, v5
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s6|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s6|
+; CI-NEXT: v_readfirstlane_b32 s14, v0
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s10|
+; CI-NEXT: v_readfirstlane_b32 s15, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s10|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1
+; CI-NEXT: v_readfirstlane_b32 s16, v1
+; CI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s13, s15, -1
+; CI-NEXT: s_add_i32 s12, s16, -1
+; CI-NEXT: s_sub_i32 s13, s13, s12
+; CI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[18:19], s[18:19], s[18:19]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v11, -v5, v10, 1.0
-; CI-NEXT: v_fma_f32 v10, v11, v10, v10
-; CI-NEXT: v_mul_f32_e32 v11, v9, v10
-; CI-NEXT: v_fma_f32 v12, -v5, v11, v9
-; CI-NEXT: v_fma_f32 v11, v12, v10, v11
-; CI-NEXT: v_fma_f32 v5, -v5, v11, v9
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v4
-; CI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_22
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s13, 12
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB12_22
; CI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
-; CI-NEXT: v_add_i32_e32 v4, vcc, 12, v7
-; CI-NEXT: v_sub_i32_e32 v4, vcc, v4, v8
+; CI-NEXT: s_add_i32 s15, s15, 12
+; CI-NEXT: s_sub_i32 s13, s15, s16
; CI-NEXT: .LBB12_21: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v6
-; CI-NEXT: v_mul_f32_e32 v6, v7, v5
-; CI-NEXT: v_rndne_f32_e32 v6, v6
-; CI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; CI-NEXT: v_add_f32_e32 v8, v6, v3
-; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; CI-NEXT: v_add_i32_e32 v4, vcc, -12, v4
-; CI-NEXT: v_ldexp_f32_e64 v6, v6, 12
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; CI-NEXT: s_cbranch_vccnz .LBB12_21
+; CI-NEXT: v_mul_f32_e32 v2, s14, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s14
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s15, v2
+; CI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s16, v2
+; CI-NEXT: s_cselect_b32 s15, s16, s15
+; CI-NEXT: v_ldexp_f32_e64 v2, s15, 12
+; CI-NEXT: v_readfirstlane_b32 s16, v2
+; CI-NEXT: s_add_i32 s13, s13, -12
+; CI-NEXT: s_cmp_gt_i32 s13, 12
+; CI-NEXT: s_mov_b32 s15, s14
+; CI-NEXT: s_mov_b32 s14, s16
+; CI-NEXT: s_cbranch_scc1 .LBB12_21
; CI-NEXT: s_branch .LBB12_23
; CI-NEXT: .LBB12_22:
-; CI-NEXT: v_mov_b32_e32 v7, v6
+; CI-NEXT: s_mov_b32 s15, s14
; CI-NEXT: .LBB12_23: ; %frem.loop_exit24
-; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
-; CI-NEXT: v_ldexp_f32_e32 v4, v7, v4
-; CI-NEXT: v_mul_f32_e32 v5, v4, v5
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v3, v4, v3
-; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
-; CI-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; CI-NEXT: s_and_b32 s2, s6, 0x80000000
-; CI-NEXT: v_or_b32_e32 v2, s2, v2
+; CI-NEXT: s_add_i32 s13, s13, -11
+; CI-NEXT: v_mov_b32_e32 v2, s13
+; CI-NEXT: v_ldexp_f32_e32 v2, s15, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s13, v1
+; CI-NEXT: v_readfirstlane_b32 s14, v0
+; CI-NEXT: s_cselect_b32 s13, s14, s13
+; CI-NEXT: v_mov_b32_e32 v0, s12
+; CI-NEXT: v_ldexp_f32_e32 v0, s13, v0
+; CI-NEXT: v_readfirstlane_b32 s12, v0
+; CI-NEXT: s_bitset0_b32 s12, 31
+; CI-NEXT: s_and_b32 s13, s6, 0x80000000
+; CI-NEXT: s_or_b32 s12, s12, s13
; CI-NEXT: .LBB12_24: ; %Flow120
-; CI-NEXT: v_mov_b32_e32 v3, s11
-; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s7|, |v3|
-; CI-NEXT: s_mov_b32 s2, 1
-; CI-NEXT: ; implicit-def: $vgpr3
-; CI-NEXT: s_cbranch_vccz .LBB12_26
+; CI-NEXT: v_mov_b32_e32 v0, s11
+; CI-NEXT: v_cmp_ngt_f32_e64 s[14:15], |s7|, |v0|
+; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15]
+; CI-NEXT: s_mov_b32 s14, 1
+; CI-NEXT: ; implicit-def: $sgpr13
+; CI-NEXT: s_cbranch_scc0 .LBB12_26
; CI-NEXT: ; %bb.25: ; %frem.else
-; CI-NEXT: s_and_b32 s2, s7, 0x80000000
-; CI-NEXT: v_mov_b32_e32 v4, s11
-; CI-NEXT: v_mov_b32_e32 v3, s7
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s7|, |v4|
-; CI-NEXT: v_mov_b32_e32 v4, s2
-; CI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v0, s11
+; CI-NEXT: s_and_b32 s13, s7, 0x80000000
+; CI-NEXT: v_cmp_eq_f32_e64 s[14:15], |s7|, |v0|
+; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15]
+; CI-NEXT: s_cselect_b32 s13, s13, s7
+; CI-NEXT: s_mov_b32 s14, 0
; CI-NEXT: .LBB12_26: ; %Flow115
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s14, s14, 1
+; CI-NEXT: s_cmp_lg_u32 s14, 0
; CI-NEXT: s_cbranch_scc1 .LBB12_32
; CI-NEXT: ; %bb.27: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f32_e64 v4, |s11|
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 1
-; CI-NEXT: v_div_scale_f32 v6, s[2:3], v4, v4, 1.0
-; CI-NEXT: v_frexp_mant_f32_e64 v3, |s7|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v8, |s7|
-; CI-NEXT: v_frexp_exp_i32_f32_e64 v9, |s11|
-; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v8
-; CI-NEXT: v_ldexp_f32_e64 v7, v3, 12
-; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v9
-; CI-NEXT: v_sub_i32_e32 v5, vcc, v5, v3
-; CI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v4, 1.0
-; CI-NEXT: v_rcp_f32_e32 v11, v6
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s7|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 12
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s7|
+; CI-NEXT: v_readfirstlane_b32 s15, v0
+; CI-NEXT: v_frexp_mant_f32_e64 v0, |s11|
+; CI-NEXT: v_readfirstlane_b32 s16, v1
+; CI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s11|
+; CI-NEXT: v_ldexp_f32_e64 v0, v0, 1
+; CI-NEXT: v_readfirstlane_b32 s17, v1
+; CI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0
+; CI-NEXT: s_add_i32 s14, s16, -1
+; CI-NEXT: s_add_i32 s13, s17, -1
+; CI-NEXT: s_sub_i32 s14, s14, s13
+; CI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0
+; CI-NEXT: s_or_b64 s[18:19], s[18:19], s[18:19]
+; CI-NEXT: v_rcp_f32_e32 v3, v1
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v12, -v6, v11, 1.0
-; CI-NEXT: v_fma_f32 v11, v12, v11, v11
-; CI-NEXT: v_mul_f32_e32 v12, v10, v11
-; CI-NEXT: v_fma_f32 v13, -v6, v12, v10
-; CI-NEXT: v_fma_f32 v12, v13, v11, v12
-; CI-NEXT: v_fma_f32 v6, -v6, v12, v10
+; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; CI-NEXT: v_fma_f32 v3, v4, v3, v3
+; CI-NEXT: v_mul_f32_e32 v4, v2, v3
+; CI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; CI-NEXT: v_fma_f32 v4, v5, v3, v4
+; CI-NEXT: v_fma_f32 v1, -v1, v4, v2
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v6, v6, v11, v12
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v5
-; CI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_30
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; CI-NEXT: s_cmp_le_i32 s14, 12
+; CI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB12_30
; CI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v5, vcc, 12, v8
-; CI-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
+; CI-NEXT: s_add_i32 s16, s16, 12
+; CI-NEXT: s_sub_i32 s14, s16, s17
; CI-NEXT: .LBB12_29: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v8, v7
-; CI-NEXT: v_mul_f32_e32 v7, v8, v6
-; CI-NEXT: v_rndne_f32_e32 v7, v7
-; CI-NEXT: v_fma_f32 v7, -v7, v4, v8
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; CI-NEXT: v_add_f32_e32 v9, v7, v4
-; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; CI-NEXT: v_add_i32_e32 v5, vcc, -12, v5
-; CI-NEXT: v_ldexp_f32_e64 v7, v7, 12
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v5
-; CI-NEXT: s_cbranch_vccnz .LBB12_29
+; CI-NEXT: v_mul_f32_e32 v2, s15, v1
+; CI-NEXT: v_rndne_f32_e32 v2, v2
+; CI-NEXT: v_fma_f32 v2, -v2, v0, s15
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; CI-NEXT: v_readfirstlane_b32 s18, v2
+; CI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v2, v2, v0
+; CI-NEXT: v_readfirstlane_b32 s16, v2
+; CI-NEXT: s_cselect_b32 s16, s16, s18
+; CI-NEXT: v_ldexp_f32_e64 v2, s16, 12
+; CI-NEXT: v_readfirstlane_b32 s17, v2
+; CI-NEXT: s_add_i32 s14, s14, -12
+; CI-NEXT: s_cmp_gt_i32 s14, 12
+; CI-NEXT: s_mov_b32 s16, s15
+; CI-NEXT: s_mov_b32 s15, s17
+; CI-NEXT: s_cbranch_scc1 .LBB12_29
; CI-NEXT: s_branch .LBB12_31
; CI-NEXT: .LBB12_30:
-; CI-NEXT: v_mov_b32_e32 v8, v7
+; CI-NEXT: s_mov_b32 s16, s15
; CI-NEXT: .LBB12_31: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v5, vcc, -11, v5
-; CI-NEXT: v_ldexp_f32_e32 v5, v8, v5
-; CI-NEXT: v_mul_f32_e32 v6, v5, v6
-; CI-NEXT: v_rndne_f32_e32 v6, v6
-; CI-NEXT: v_fma_f32 v5, -v6, v4, v5
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v4, v5, v4
-; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; CI-NEXT: v_ldexp_f32_e32 v3, v4, v3
-; CI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; CI-NEXT: s_and_b32 s2, s7, 0x80000000
-; CI-NEXT: v_or_b32_e32 v3, s2, v3
+; CI-NEXT: s_add_i32 s14, s14, -11
+; CI-NEXT: v_mov_b32_e32 v2, s14
+; CI-NEXT: v_ldexp_f32_e32 v2, s16, v2
+; CI-NEXT: v_mul_f32_e32 v1, v2, v1
+; CI-NEXT: v_rndne_f32_e32 v1, v1
+; CI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: v_add_f32_e32 v0, v1, v0
+; CI-NEXT: v_readfirstlane_b32 s16, v1
+; CI-NEXT: v_readfirstlane_b32 s14, v0
+; CI-NEXT: s_cselect_b32 s14, s14, s16
+; CI-NEXT: v_mov_b32_e32 v0, s13
+; CI-NEXT: v_ldexp_f32_e32 v0, s14, v0
+; CI-NEXT: v_readfirstlane_b32 s13, v0
+; CI-NEXT: s_bitset0_b32 s13, 31
+; CI-NEXT: s_and_b32 s14, s7, 0x80000000
+; CI-NEXT: s_or_b32 s13, s13, s14
; CI-NEXT: .LBB12_32: ; %Flow116
-; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s8, 0
-; CI-NEXT: v_mov_b32_e32 v4, 0x7fc00000
-; CI-NEXT: v_mov_b32_e32 v5, 0x7f800000
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s4|, v5
-; CI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s9, 0
-; CI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s5|, v5
-; CI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s10, 0
-; CI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s6|, v5
-; CI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s11, 0
-; CI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s7|, v5
-; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; CI-NEXT: v_cmp_nlg_f32_e64 s[14:15], s8, 0
+; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15]
+; CI-NEXT: v_mov_b32_e32 v0, 0x7f800000
+; CI-NEXT: v_cmp_nge_f32_e64 s[14:15], |s4|, v0
+; CI-NEXT: s_cselect_b32 s2, 0x7fc00000, s2
+; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15]
+; CI-NEXT: v_cmp_nlg_f32_e64 s[8:9], s9, 0
+; CI-NEXT: s_cselect_b32 s4, s2, 0x7fc00000
+; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9]
+; CI-NEXT: s_cselect_b32 s8, 0x7fc00000, s3
+; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s5|, v0
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s10, 0
+; CI-NEXT: s_cselect_b32 s5, s8, 0x7fc00000
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s6|, v0
+; CI-NEXT: s_cselect_b32 s8, 0x7fc00000, s12
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s11, 0
+; CI-NEXT: s_cselect_b32 s6, s8, 0x7fc00000
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s7|, v0
+; CI-NEXT: s_cselect_b32 s8, 0x7fc00000, s13
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: s_cselect_b32 s7, s8, 0x7fc00000
+; CI-NEXT: v_mov_b32_e32 v0, s4
+; CI-NEXT: v_mov_b32_e32 v1, s5
+; CI-NEXT: v_mov_b32_e32 v2, s6
+; CI-NEXT: v_mov_b32_e32 v3, s7
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
@@ -2805,326 +3360,401 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x40
-; VI-NEXT: s_mov_b32 s2, 1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s8
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s4|, |v0|
-; VI-NEXT: ; implicit-def: $vgpr0
-; VI-NEXT: s_cbranch_vccz .LBB12_2
+; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |s4|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_mov_b32 s3, 1
+; VI-NEXT: ; implicit-def: $sgpr2
+; VI-NEXT: s_cbranch_scc0 .LBB12_2
; VI-NEXT: ; %bb.1: ; %frem.else78
-; VI-NEXT: s_and_b32 s2, s4, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v1, s8
-; VI-NEXT: v_mov_b32_e32 v0, s4
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s4|, |v1|
-; VI-NEXT: v_mov_b32_e32 v1, s2
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: v_mov_b32_e32 v0, s8
+; VI-NEXT: s_and_b32 s12, s4, 0x80000000
+; VI-NEXT: v_cmp_eq_f32_e64 s[2:3], |s4|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b32 s2, s12, s4
+; VI-NEXT: s_mov_b32 s3, 0
; VI-NEXT: .LBB12_2: ; %Flow127
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s3, s3, 1
+; VI-NEXT: s_cmp_lg_u32 s3, 0
; VI-NEXT: s_cbranch_scc1 .LBB12_8
; VI-NEXT: ; %bb.3: ; %frem.compute77
-; VI-NEXT: v_frexp_mant_f32_e64 v1, |s8|
-; VI-NEXT: v_ldexp_f32 v1, v1, 1
-; VI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v0, |s4|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s4|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s8|
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5
-; VI-NEXT: v_ldexp_f32 v4, v0, 12
-; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0
-; VI-NEXT: v_rcp_f32_e32 v8, v3
+; VI-NEXT: v_ldexp_f32 v0, v0, 12
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s4|
+; VI-NEXT: v_readfirstlane_b32 s12, v0
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s8|
+; VI-NEXT: v_readfirstlane_b32 s13, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s8|
+; VI-NEXT: v_ldexp_f32 v0, v0, 1
+; VI-NEXT: v_readfirstlane_b32 s14, v1
+; VI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s3, s13, -1
+; VI-NEXT: s_add_i32 s2, s14, -1
+; VI-NEXT: s_sub_i32 s3, s3, s2
+; VI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[16:17], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0
-; VI-NEXT: v_fma_f32 v8, v9, v8, v8
-; VI-NEXT: v_mul_f32_e32 v9, v7, v8
-; VI-NEXT: v_fma_f32 v10, -v3, v9, v7
-; VI-NEXT: v_fma_f32 v9, v10, v8, v9
-; VI-NEXT: v_fma_f32 v3, -v3, v9, v7
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2
-; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_6
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s3, 12
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB12_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
-; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v5
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6
+; VI-NEXT: s_add_i32 s13, s13, 12
+; VI-NEXT: s_sub_i32 s3, s13, s14
; VI-NEXT: .LBB12_5: ; %frem.loop_body85
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v5, v4
-; VI-NEXT: v_mul_f32_e32 v4, v5, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v4, -v4, v1, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v6, v4, v1
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_add_u32_e32 v2, vcc, -12, v2
-; VI-NEXT: v_ldexp_f32 v4, v4, 12
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2
-; VI-NEXT: s_cbranch_vccnz .LBB12_5
+; VI-NEXT: v_mul_f32_e32 v2, s12, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s12
+; VI-NEXT: v_readfirstlane_b32 s13, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s14, v2
+; VI-NEXT: s_cselect_b32 s13, s14, s13
+; VI-NEXT: v_ldexp_f32 v2, s13, 12
+; VI-NEXT: v_readfirstlane_b32 s14, v2
+; VI-NEXT: s_add_i32 s3, s3, -12
+; VI-NEXT: s_cmp_gt_i32 s3, 12
+; VI-NEXT: s_mov_b32 s13, s12
+; VI-NEXT: s_mov_b32 s12, s14
+; VI-NEXT: s_cbranch_scc1 .LBB12_5
; VI-NEXT: s_branch .LBB12_7
; VI-NEXT: .LBB12_6:
-; VI-NEXT: v_mov_b32_e32 v5, v4
+; VI-NEXT: s_mov_b32 s13, s12
; VI-NEXT: .LBB12_7: ; %frem.loop_exit86
-; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2
-; VI-NEXT: v_ldexp_f32 v2, v5, v2
-; VI-NEXT: v_mul_f32_e32 v3, v2, v3
-; VI-NEXT: v_rndne_f32_e32 v3, v3
-; VI-NEXT: v_fma_f32 v2, -v3, v1, v2
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_ldexp_f32 v0, v1, v0
-; VI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; VI-NEXT: s_and_b32 s2, s4, 0x80000000
-; VI-NEXT: v_or_b32_e32 v0, s2, v0
+; VI-NEXT: s_add_i32 s3, s3, -11
+; VI-NEXT: v_mov_b32_e32 v2, s3
+; VI-NEXT: v_ldexp_f32 v2, s13, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s3, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s12, v0
+; VI-NEXT: s_cselect_b32 s3, s12, s3
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_ldexp_f32 v0, s3, v0
+; VI-NEXT: v_readfirstlane_b32 s2, v0
+; VI-NEXT: s_bitset0_b32 s2, 31
+; VI-NEXT: s_and_b32 s3, s4, 0x80000000
+; VI-NEXT: s_or_b32 s2, s2, s3
; VI-NEXT: .LBB12_8: ; %Flow128
-; VI-NEXT: v_mov_b32_e32 v1, s9
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s5|, |v1|
-; VI-NEXT: s_mov_b32 s2, 1
-; VI-NEXT: ; implicit-def: $vgpr1
-; VI-NEXT: s_cbranch_vccz .LBB12_10
+; VI-NEXT: v_mov_b32_e32 v0, s9
+; VI-NEXT: v_cmp_ngt_f32_e64 s[12:13], |s5|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: s_mov_b32 s12, 1
+; VI-NEXT: ; implicit-def: $sgpr3
+; VI-NEXT: s_cbranch_scc0 .LBB12_10
; VI-NEXT: ; %bb.9: ; %frem.else47
-; VI-NEXT: s_and_b32 s2, s5, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v2, s9
-; VI-NEXT: v_mov_b32_e32 v1, s5
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s5|, |v2|
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: v_mov_b32_e32 v0, s9
+; VI-NEXT: s_and_b32 s3, s5, 0x80000000
+; VI-NEXT: v_cmp_eq_f32_e64 s[12:13], |s5|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: s_cselect_b32 s3, s3, s5
+; VI-NEXT: s_mov_b32 s12, 0
; VI-NEXT: .LBB12_10: ; %Flow123
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s12, s12, 1
+; VI-NEXT: s_cmp_lg_u32 s12, 0
; VI-NEXT: s_cbranch_scc1 .LBB12_16
; VI-NEXT: ; %bb.11: ; %frem.compute46
-; VI-NEXT: v_frexp_mant_f32_e64 v2, |s9|
-; VI-NEXT: v_ldexp_f32 v2, v2, 1
-; VI-NEXT: v_div_scale_f32 v4, s[2:3], v2, v2, 1.0
-; VI-NEXT: v_frexp_mant_f32_e64 v1, |s5|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s5|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s9|
-; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v6
-; VI-NEXT: v_ldexp_f32 v5, v1, 12
-; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v7
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0
-; VI-NEXT: v_rcp_f32_e32 v9, v4
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s5|
+; VI-NEXT: v_ldexp_f32 v0, v0, 12
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s5|
+; VI-NEXT: v_readfirstlane_b32 s13, v0
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s9|
+; VI-NEXT: v_readfirstlane_b32 s14, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s9|
+; VI-NEXT: v_ldexp_f32 v0, v0, 1
+; VI-NEXT: v_readfirstlane_b32 s15, v1
+; VI-NEXT: v_div_scale_f32 v1, s[16:17], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s12, s14, -1
+; VI-NEXT: s_add_i32 s3, s15, -1
+; VI-NEXT: s_sub_i32 s12, s12, s3
+; VI-NEXT: v_div_scale_f32 v2, s[16:17], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[16:17], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v10, -v4, v9, 1.0
-; VI-NEXT: v_fma_f32 v9, v10, v9, v9
-; VI-NEXT: v_mul_f32_e32 v10, v8, v9
-; VI-NEXT: v_fma_f32 v11, -v4, v10, v8
-; VI-NEXT: v_fma_f32 v10, v11, v9, v10
-; VI-NEXT: v_fma_f32 v4, -v4, v10, v8
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v4, v4, v9, v10
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v3
-; VI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_14
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s12, 12
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB12_14
; VI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
-; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v6
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v7
+; VI-NEXT: s_add_i32 s14, s14, 12
+; VI-NEXT: s_sub_i32 s12, s14, s15
; VI-NEXT: .LBB12_13: ; %frem.loop_body54
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v6, v5
-; VI-NEXT: v_mul_f32_e32 v5, v6, v4
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v5, -v5, v2, v6
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v7, v5, v2
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; VI-NEXT: v_add_u32_e32 v3, vcc, -12, v3
-; VI-NEXT: v_ldexp_f32 v5, v5, 12
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v3
-; VI-NEXT: s_cbranch_vccnz .LBB12_13
+; VI-NEXT: v_mul_f32_e32 v2, s13, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s13
+; VI-NEXT: v_readfirstlane_b32 s14, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s15, v2
+; VI-NEXT: s_cselect_b32 s14, s15, s14
+; VI-NEXT: v_ldexp_f32 v2, s14, 12
+; VI-NEXT: v_readfirstlane_b32 s15, v2
+; VI-NEXT: s_add_i32 s12, s12, -12
+; VI-NEXT: s_cmp_gt_i32 s12, 12
+; VI-NEXT: s_mov_b32 s14, s13
+; VI-NEXT: s_mov_b32 s13, s15
+; VI-NEXT: s_cbranch_scc1 .LBB12_13
; VI-NEXT: s_branch .LBB12_15
; VI-NEXT: .LBB12_14:
-; VI-NEXT: v_mov_b32_e32 v6, v5
+; VI-NEXT: s_mov_b32 s14, s13
; VI-NEXT: .LBB12_15: ; %frem.loop_exit55
-; VI-NEXT: v_add_u32_e32 v3, vcc, -11, v3
-; VI-NEXT: v_ldexp_f32 v3, v6, v3
-; VI-NEXT: v_mul_f32_e32 v4, v3, v4
-; VI-NEXT: v_rndne_f32_e32 v4, v4
-; VI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; VI-NEXT: v_ldexp_f32 v1, v2, v1
-; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; VI-NEXT: s_and_b32 s2, s5, 0x80000000
-; VI-NEXT: v_or_b32_e32 v1, s2, v1
+; VI-NEXT: s_add_i32 s12, s12, -11
+; VI-NEXT: v_mov_b32_e32 v2, s12
+; VI-NEXT: v_ldexp_f32 v2, s14, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s12, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s13, v0
+; VI-NEXT: s_cselect_b32 s12, s13, s12
+; VI-NEXT: v_mov_b32_e32 v0, s3
+; VI-NEXT: v_ldexp_f32 v0, s12, v0
+; VI-NEXT: v_readfirstlane_b32 s3, v0
+; VI-NEXT: s_bitset0_b32 s3, 31
+; VI-NEXT: s_and_b32 s12, s5, 0x80000000
+; VI-NEXT: s_or_b32 s3, s3, s12
; VI-NEXT: .LBB12_16: ; %Flow124
-; VI-NEXT: v_mov_b32_e32 v2, s10
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s6|, |v2|
-; VI-NEXT: s_mov_b32 s2, 1
-; VI-NEXT: ; implicit-def: $vgpr2
-; VI-NEXT: s_cbranch_vccz .LBB12_18
+; VI-NEXT: v_mov_b32_e32 v0, s10
+; VI-NEXT: v_cmp_ngt_f32_e64 s[12:13], |s6|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: s_mov_b32 s13, 1
+; VI-NEXT: ; implicit-def: $sgpr12
+; VI-NEXT: s_cbranch_scc0 .LBB12_18
; VI-NEXT: ; %bb.17: ; %frem.else16
-; VI-NEXT: s_and_b32 s2, s6, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v3, s10
-; VI-NEXT: v_mov_b32_e32 v2, s6
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s6|, |v3|
-; VI-NEXT: v_mov_b32_e32 v3, s2
-; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: v_mov_b32_e32 v0, s10
+; VI-NEXT: s_and_b32 s14, s6, 0x80000000
+; VI-NEXT: v_cmp_eq_f32_e64 s[12:13], |s6|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: s_cselect_b32 s12, s14, s6
+; VI-NEXT: s_mov_b32 s13, 0
; VI-NEXT: .LBB12_18: ; %Flow119
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s13, s13, 1
+; VI-NEXT: s_cmp_lg_u32 s13, 0
; VI-NEXT: s_cbranch_scc1 .LBB12_24
; VI-NEXT: ; %bb.19: ; %frem.compute15
-; VI-NEXT: v_frexp_mant_f32_e64 v3, |s10|
-; VI-NEXT: v_ldexp_f32 v3, v3, 1
-; VI-NEXT: v_div_scale_f32 v5, s[2:3], v3, v3, 1.0
-; VI-NEXT: v_frexp_mant_f32_e64 v2, |s6|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s6|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v8, |s10|
-; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v7
-; VI-NEXT: v_ldexp_f32 v6, v2, 12
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8
-; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v3, 1.0
-; VI-NEXT: v_rcp_f32_e32 v10, v5
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s6|
+; VI-NEXT: v_ldexp_f32 v0, v0, 12
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s6|
+; VI-NEXT: v_readfirstlane_b32 s14, v0
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s10|
+; VI-NEXT: v_readfirstlane_b32 s15, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s10|
+; VI-NEXT: v_ldexp_f32 v0, v0, 1
+; VI-NEXT: v_readfirstlane_b32 s16, v1
+; VI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s13, s15, -1
+; VI-NEXT: s_add_i32 s12, s16, -1
+; VI-NEXT: s_sub_i32 s13, s13, s12
+; VI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[18:19], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v11, -v5, v10, 1.0
-; VI-NEXT: v_fma_f32 v10, v11, v10, v10
-; VI-NEXT: v_mul_f32_e32 v11, v9, v10
-; VI-NEXT: v_fma_f32 v12, -v5, v11, v9
-; VI-NEXT: v_fma_f32 v11, v12, v10, v11
-; VI-NEXT: v_fma_f32 v5, -v5, v11, v9
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v4
-; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_22
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s13, 12
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB12_22
; VI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
-; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v7
-; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v8
+; VI-NEXT: s_add_i32 s15, s15, 12
+; VI-NEXT: s_sub_i32 s13, s15, s16
; VI-NEXT: .LBB12_21: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v6
-; VI-NEXT: v_mul_f32_e32 v6, v7, v5
-; VI-NEXT: v_rndne_f32_e32 v6, v6
-; VI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; VI-NEXT: v_add_f32_e32 v8, v6, v3
-; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; VI-NEXT: v_add_u32_e32 v4, vcc, -12, v4
-; VI-NEXT: v_ldexp_f32 v6, v6, 12
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; VI-NEXT: s_cbranch_vccnz .LBB12_21
+; VI-NEXT: v_mul_f32_e32 v2, s14, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s14
+; VI-NEXT: v_readfirstlane_b32 s15, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s16, v2
+; VI-NEXT: s_cselect_b32 s15, s16, s15
+; VI-NEXT: v_ldexp_f32 v2, s15, 12
+; VI-NEXT: v_readfirstlane_b32 s16, v2
+; VI-NEXT: s_add_i32 s13, s13, -12
+; VI-NEXT: s_cmp_gt_i32 s13, 12
+; VI-NEXT: s_mov_b32 s15, s14
+; VI-NEXT: s_mov_b32 s14, s16
+; VI-NEXT: s_cbranch_scc1 .LBB12_21
; VI-NEXT: s_branch .LBB12_23
; VI-NEXT: .LBB12_22:
-; VI-NEXT: v_mov_b32_e32 v7, v6
+; VI-NEXT: s_mov_b32 s15, s14
; VI-NEXT: .LBB12_23: ; %frem.loop_exit24
-; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
-; VI-NEXT: v_ldexp_f32 v4, v7, v4
-; VI-NEXT: v_mul_f32_e32 v5, v4, v5
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v4, -v5, v3, v4
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: v_ldexp_f32 v2, v3, v2
-; VI-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
-; VI-NEXT: s_and_b32 s2, s6, 0x80000000
-; VI-NEXT: v_or_b32_e32 v2, s2, v2
+; VI-NEXT: s_add_i32 s13, s13, -11
+; VI-NEXT: v_mov_b32_e32 v2, s13
+; VI-NEXT: v_ldexp_f32 v2, s15, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s13, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s14, v0
+; VI-NEXT: s_cselect_b32 s13, s14, s13
+; VI-NEXT: v_mov_b32_e32 v0, s12
+; VI-NEXT: v_ldexp_f32 v0, s13, v0
+; VI-NEXT: v_readfirstlane_b32 s12, v0
+; VI-NEXT: s_bitset0_b32 s12, 31
+; VI-NEXT: s_and_b32 s13, s6, 0x80000000
+; VI-NEXT: s_or_b32 s12, s12, s13
; VI-NEXT: .LBB12_24: ; %Flow120
-; VI-NEXT: v_mov_b32_e32 v3, s11
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s7|, |v3|
-; VI-NEXT: s_mov_b32 s2, 1
-; VI-NEXT: ; implicit-def: $vgpr3
-; VI-NEXT: s_cbranch_vccz .LBB12_26
+; VI-NEXT: v_mov_b32_e32 v0, s11
+; VI-NEXT: v_cmp_ngt_f32_e64 s[14:15], |s7|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: s_mov_b32 s14, 1
+; VI-NEXT: ; implicit-def: $sgpr13
+; VI-NEXT: s_cbranch_scc0 .LBB12_26
; VI-NEXT: ; %bb.25: ; %frem.else
-; VI-NEXT: s_and_b32 s2, s7, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v4, s11
-; VI-NEXT: v_mov_b32_e32 v3, s7
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s7|, |v4|
-; VI-NEXT: v_mov_b32_e32 v4, s2
-; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: v_mov_b32_e32 v0, s11
+; VI-NEXT: s_and_b32 s13, s7, 0x80000000
+; VI-NEXT: v_cmp_eq_f32_e64 s[14:15], |s7|, |v0|
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: s_cselect_b32 s13, s13, s7
+; VI-NEXT: s_mov_b32 s14, 0
; VI-NEXT: .LBB12_26: ; %Flow115
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s14, s14, 1
+; VI-NEXT: s_cmp_lg_u32 s14, 0
; VI-NEXT: s_cbranch_scc1 .LBB12_32
; VI-NEXT: ; %bb.27: ; %frem.compute
-; VI-NEXT: v_frexp_mant_f32_e64 v4, |s11|
-; VI-NEXT: v_ldexp_f32 v4, v4, 1
-; VI-NEXT: v_div_scale_f32 v6, s[2:3], v4, v4, 1.0
-; VI-NEXT: v_frexp_mant_f32_e64 v3, |s7|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v8, |s7|
-; VI-NEXT: v_frexp_exp_i32_f32_e64 v9, |s11|
-; VI-NEXT: v_add_u32_e32 v5, vcc, -1, v8
-; VI-NEXT: v_ldexp_f32 v7, v3, 12
-; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v9
-; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v3
-; VI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v4, 1.0
-; VI-NEXT: v_rcp_f32_e32 v11, v6
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s7|
+; VI-NEXT: v_ldexp_f32 v0, v0, 12
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s7|
+; VI-NEXT: v_readfirstlane_b32 s15, v0
+; VI-NEXT: v_frexp_mant_f32_e64 v0, |s11|
+; VI-NEXT: v_readfirstlane_b32 s16, v1
+; VI-NEXT: v_frexp_exp_i32_f32_e64 v1, |s11|
+; VI-NEXT: v_ldexp_f32 v0, v0, 1
+; VI-NEXT: v_readfirstlane_b32 s17, v1
+; VI-NEXT: v_div_scale_f32 v1, s[18:19], v0, v0, 1.0
+; VI-NEXT: s_add_i32 s14, s16, -1
+; VI-NEXT: s_add_i32 s13, s17, -1
+; VI-NEXT: s_sub_i32 s14, s14, s13
+; VI-NEXT: v_div_scale_f32 v2, s[18:19], 1.0, v0, 1.0
+; VI-NEXT: s_cmp_lg_u64 s[18:19], 0
+; VI-NEXT: v_rcp_f32_e32 v3, v1
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT: v_fma_f32 v12, -v6, v11, 1.0
-; VI-NEXT: v_fma_f32 v11, v12, v11, v11
-; VI-NEXT: v_mul_f32_e32 v12, v10, v11
-; VI-NEXT: v_fma_f32 v13, -v6, v12, v10
-; VI-NEXT: v_fma_f32 v12, v13, v11, v12
-; VI-NEXT: v_fma_f32 v6, -v6, v12, v10
+; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; VI-NEXT: v_fma_f32 v3, v4, v3, v3
+; VI-NEXT: v_mul_f32_e32 v4, v2, v3
+; VI-NEXT: v_fma_f32 v5, -v1, v4, v2
+; VI-NEXT: v_fma_f32 v4, v5, v3, v4
+; VI-NEXT: v_fma_f32 v1, -v1, v4, v2
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v6, v6, v11, v12
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v5
-; VI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_30
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; VI-NEXT: s_cmp_le_i32 s14, 12
+; VI-NEXT: v_div_fixup_f32 v1, v1, v0, 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB12_30
; VI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v5, vcc, 12, v8
-; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v9
+; VI-NEXT: s_add_i32 s16, s16, 12
+; VI-NEXT: s_sub_i32 s14, s16, s17
; VI-NEXT: .LBB12_29: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v8, v7
-; VI-NEXT: v_mul_f32_e32 v7, v8, v6
-; VI-NEXT: v_rndne_f32_e32 v7, v7
-; VI-NEXT: v_fma_f32 v7, -v7, v4, v8
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; VI-NEXT: v_add_f32_e32 v9, v7, v4
-; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; VI-NEXT: v_add_u32_e32 v5, vcc, -12, v5
-; VI-NEXT: v_ldexp_f32 v7, v7, 12
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v5
-; VI-NEXT: s_cbranch_vccnz .LBB12_29
+; VI-NEXT: v_mul_f32_e32 v2, s15, v1
+; VI-NEXT: v_rndne_f32_e32 v2, v2
+; VI-NEXT: v_fma_f32 v2, -v2, v0, s15
+; VI-NEXT: v_readfirstlane_b32 s16, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2
+; VI-NEXT: v_add_f32_e32 v2, v2, v0
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s17, v2
+; VI-NEXT: s_cselect_b32 s16, s17, s16
+; VI-NEXT: v_ldexp_f32 v2, s16, 12
+; VI-NEXT: v_readfirstlane_b32 s17, v2
+; VI-NEXT: s_add_i32 s14, s14, -12
+; VI-NEXT: s_cmp_gt_i32 s14, 12
+; VI-NEXT: s_mov_b32 s16, s15
+; VI-NEXT: s_mov_b32 s15, s17
+; VI-NEXT: s_cbranch_scc1 .LBB12_29
; VI-NEXT: s_branch .LBB12_31
; VI-NEXT: .LBB12_30:
-; VI-NEXT: v_mov_b32_e32 v8, v7
+; VI-NEXT: s_mov_b32 s16, s15
; VI-NEXT: .LBB12_31: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v5, vcc, -11, v5
-; VI-NEXT: v_ldexp_f32 v5, v8, v5
-; VI-NEXT: v_mul_f32_e32 v6, v5, v6
-; VI-NEXT: v_rndne_f32_e32 v6, v6
-; VI-NEXT: v_fma_f32 v5, -v6, v4, v5
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v4, v5, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; VI-NEXT: v_ldexp_f32 v3, v4, v3
-; VI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; VI-NEXT: s_and_b32 s2, s7, 0x80000000
-; VI-NEXT: v_or_b32_e32 v3, s2, v3
+; VI-NEXT: s_add_i32 s14, s14, -11
+; VI-NEXT: v_mov_b32_e32 v2, s14
+; VI-NEXT: v_ldexp_f32 v2, s16, v2
+; VI-NEXT: v_mul_f32_e32 v1, v2, v1
+; VI-NEXT: v_rndne_f32_e32 v1, v1
+; VI-NEXT: v_fma_f32 v1, -v1, v0, v2
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1
+; VI-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-NEXT: v_readfirstlane_b32 s14, v1
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s15, v0
+; VI-NEXT: s_cselect_b32 s14, s15, s14
+; VI-NEXT: v_mov_b32_e32 v0, s13
+; VI-NEXT: v_ldexp_f32 v0, s14, v0
+; VI-NEXT: v_readfirstlane_b32 s13, v0
+; VI-NEXT: s_bitset0_b32 s13, 31
+; VI-NEXT: s_and_b32 s14, s7, 0x80000000
+; VI-NEXT: s_or_b32 s13, s13, s14
; VI-NEXT: .LBB12_32: ; %Flow116
-; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s8, 0
-; VI-NEXT: v_mov_b32_e32 v4, 0x7fc00000
-; VI-NEXT: v_mov_b32_e32 v5, 0x7f800000
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s4|, v5
-; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s9, 0
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s5|, v5
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s10, 0
-; VI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s6|, v5
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s11, 0
-; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s7|, v5
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-NEXT: v_cmp_nlg_f32_e64 s[14:15], s8, 0
+; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: v_cmp_nge_f32_e64 s[14:15], |s4|, v0
+; VI-NEXT: s_cselect_b32 s2, 0x7fc00000, s2
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: v_cmp_nlg_f32_e64 s[8:9], s9, 0
+; VI-NEXT: s_cselect_b32 s4, s2, 0x7fc00000
+; VI-NEXT: s_cmp_lg_u64 s[8:9], 0
+; VI-NEXT: s_cselect_b32 s8, 0x7fc00000, s3
+; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s5|, v0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s10, 0
+; VI-NEXT: s_cselect_b32 s5, s8, 0x7fc00000
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s6|, v0
+; VI-NEXT: s_cselect_b32 s8, 0x7fc00000, s12
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s11, 0
+; VI-NEXT: s_cselect_b32 s6, s8, 0x7fc00000
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |s7|, v0
+; VI-NEXT: s_cselect_b32 s8, 0x7fc00000, s13
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b32 s7, s8, 0x7fc00000
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v5, s1
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -3141,201 +3771,236 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; CI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
+; CI-NEXT: s_mov_b32 s12, 1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; CI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10
-; CI-NEXT: s_mov_b32 s2, 1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s8
; CI-NEXT: v_mov_b32_e32 v1, s9
-; CI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[4:5]|, |v[0:1]|
-; CI-NEXT: ; implicit-def: $vgpr0_vgpr1
-; CI-NEXT: s_cbranch_vccz .LBB13_2
+; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |s[4:5]|, |v[0:1]|
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: ; implicit-def: $sgpr2_sgpr3
+; CI-NEXT: s_cbranch_scc0 .LBB13_2
; CI-NEXT: ; %bb.1: ; %frem.else16
; CI-NEXT: v_mov_b32_e32 v0, s8
; CI-NEXT: v_mov_b32_e32 v1, s9
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |s[4:5]|, |v[0:1]|
+; CI-NEXT: v_cmp_eq_f64_e64 s[12:13], |s[4:5]|, |v[0:1]|
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_brev_b32 s3, 1
; CI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
-; CI-NEXT: v_mov_b32_e32 v0, s2
-; CI-NEXT: v_mov_b32_e32 v1, s3
-; CI-NEXT: v_mov_b32_e32 v2, s4
-; CI-NEXT: v_mov_b32_e32 v3, s5
-; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; CI-NEXT: s_mov_b32 s12, 0
; CI-NEXT: .LBB13_2: ; %Flow53
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s12, s12, 1
+; CI-NEXT: s_cmp_lg_u32 s12, 0
; CI-NEXT: s_cbranch_scc1 .LBB13_8
; CI-NEXT: ; %bb.3: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]|
-; CI-NEXT: v_frexp_exp_i32_f64_e64 v6, |s[4:5]|
-; CI-NEXT: v_frexp_exp_i32_f64_e64 v7, |s[8:9]|
-; CI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
+; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[4:5]|
+; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26
+; CI-NEXT: v_readfirstlane_b32 s12, v2
+; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[8:9]|
+; CI-NEXT: s_add_i32 s15, s12, -1
+; CI-NEXT: v_readfirstlane_b32 s2, v0
+; CI-NEXT: v_readfirstlane_b32 s3, v1
; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[8:9]|
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v6
-; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v7
-; CI-NEXT: v_sub_i32_e32 v9, vcc, v2, v8
+; CI-NEXT: v_readfirstlane_b32 s13, v2
+; CI-NEXT: s_add_i32 s14, s13, -1
+; CI-NEXT: s_sub_i32 s15, s15, s14
; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
-; CI-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], 1.0
-; CI-NEXT: v_div_scale_f64 v[14:15], vcc, 1.0, v[0:1], 1.0
-; CI-NEXT: v_rcp_f64_e32 v[10:11], v[2:3]
-; CI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
-; CI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; CI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
-; CI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; CI-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
-; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15]
-; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[12:13]
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v9
+; CI-NEXT: v_div_scale_f64 v[2:3], s[16:17], v[0:1], v[0:1], 1.0
+; CI-NEXT: v_div_scale_f64 v[8:9], s[16:17], 1.0, v[0:1], 1.0
+; CI-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17]
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: s_cmp_le_i32 s15, 26
+; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
+; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
+; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
+; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB13_6
+; CI-NEXT: s_cbranch_scc1 .LBB13_6
; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
-; CI-NEXT: v_add_i32_e32 v6, vcc, 26, v6
-; CI-NEXT: v_sub_i32_e32 v9, vcc, v6, v7
+; CI-NEXT: s_add_i32 s12, s12, 26
+; CI-NEXT: s_sub_i32 s15, s12, s13
; CI-NEXT: .LBB13_5: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mov_b32_e32 v6, v4
-; CI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3]
+; CI-NEXT: v_mul_f64 v[4:5], s[2:3], v[2:3]
; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
-; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
+; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[2:3]
; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; CI-NEXT: v_add_f64 v[10:11], v[4:5], v[0:1]
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
-; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; CI-NEXT: v_add_i32_e32 v9, vcc, 0xffffffe6, v9
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v9
-; CI-NEXT: s_cbranch_vccnz .LBB13_5
+; CI-NEXT: v_readfirstlane_b32 s12, v4
+; CI-NEXT: v_readfirstlane_b32 s13, v5
+; CI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1]
+; CI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; CI-NEXT: v_readfirstlane_b32 s16, v4
+; CI-NEXT: v_readfirstlane_b32 s17, v5
+; CI-NEXT: s_cselect_b64 s[12:13], s[16:17], s[12:13]
+; CI-NEXT: v_ldexp_f64 v[4:5], s[12:13], 26
+; CI-NEXT: s_sub_i32 s15, s15, 26
+; CI-NEXT: s_cmp_gt_i32 s15, 26
+; CI-NEXT: s_mov_b64 s[12:13], s[2:3]
+; CI-NEXT: v_readfirstlane_b32 s16, v4
+; CI-NEXT: v_readfirstlane_b32 s17, v5
+; CI-NEXT: s_mov_b64 s[2:3], s[16:17]
+; CI-NEXT: s_cbranch_scc1 .LBB13_5
; CI-NEXT: s_branch .LBB13_7
; CI-NEXT: .LBB13_6:
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mov_b32_e32 v6, v4
+; CI-NEXT: s_mov_b64 s[12:13], s[2:3]
; CI-NEXT: .LBB13_7: ; %frem.loop_exit24
-; CI-NEXT: v_add_i32_e32 v4, vcc, 0xffffffe7, v9
-; CI-NEXT: v_ldexp_f64 v[4:5], v[6:7], v4
-; CI-NEXT: s_mov_b32 s2, 0
-; CI-NEXT: s_brev_b32 s3, 1
-; CI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
+; CI-NEXT: s_sub_i32 s2, s15, 25
+; CI-NEXT: v_mov_b32_e32 v4, s2
+; CI-NEXT: v_ldexp_f64 v[4:5], s[12:13], v4
; CI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
; CI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; CI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
-; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
-; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; CI-NEXT: v_or_b32_e32 v0, s2, v0
-; CI-NEXT: v_or_b32_e32 v1, s3, v1
+; CI-NEXT: v_readfirstlane_b32 s2, v2
+; CI-NEXT: v_readfirstlane_b32 s3, v3
+; CI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; CI-NEXT: v_readfirstlane_b32 s12, v0
+; CI-NEXT: v_readfirstlane_b32 s13, v1
+; CI-NEXT: s_cselect_b64 s[2:3], s[12:13], s[2:3]
+; CI-NEXT: v_mov_b32_e32 v0, s14
+; CI-NEXT: v_ldexp_f64 v[0:1], s[2:3], v0
+; CI-NEXT: s_mov_b32 s12, 0
+; CI-NEXT: s_brev_b32 s13, 1
+; CI-NEXT: s_and_b64 s[12:13], s[4:5], s[12:13]
+; CI-NEXT: v_readfirstlane_b32 s3, v1
+; CI-NEXT: v_readfirstlane_b32 s2, v0
+; CI-NEXT: s_bitset0_b32 s3, 31
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[12:13]
; CI-NEXT: .LBB13_8: ; %Flow54
-; CI-NEXT: v_mov_b32_e32 v2, s10
-; CI-NEXT: v_mov_b32_e32 v3, s11
-; CI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[6:7]|, |v[2:3]|
-; CI-NEXT: s_mov_b32 s2, 1
-; CI-NEXT: ; implicit-def: $vgpr2_vgpr3
-; CI-NEXT: s_cbranch_vccz .LBB13_10
+; CI-NEXT: v_mov_b32_e32 v0, s10
+; CI-NEXT: v_mov_b32_e32 v1, s11
+; CI-NEXT: v_cmp_ngt_f64_e64 s[12:13], |s[6:7]|, |v[0:1]|
+; CI-NEXT: s_mov_b32 s14, 1
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
+; CI-NEXT: ; implicit-def: $sgpr12_sgpr13
+; CI-NEXT: s_cbranch_scc0 .LBB13_10
; CI-NEXT: ; %bb.9: ; %frem.else
-; CI-NEXT: v_mov_b32_e32 v2, s10
-; CI-NEXT: v_mov_b32_e32 v3, s11
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |s[6:7]|, |v[2:3]|
-; CI-NEXT: s_mov_b32 s2, 0
-; CI-NEXT: s_brev_b32 s3, 1
-; CI-NEXT: s_and_b64 s[2:3], s[6:7], s[2:3]
-; CI-NEXT: v_mov_b32_e32 v2, s2
-; CI-NEXT: v_mov_b32_e32 v3, s3
-; CI-NEXT: v_mov_b32_e32 v4, s6
-; CI-NEXT: v_mov_b32_e32 v5, s7
-; CI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v0, s10
+; CI-NEXT: v_mov_b32_e32 v1, s11
+; CI-NEXT: v_cmp_eq_f64_e64 s[14:15], |s[6:7]|, |v[0:1]|
+; CI-NEXT: s_mov_b32 s12, 0
+; CI-NEXT: s_brev_b32 s13, 1
+; CI-NEXT: s_and_b64 s[12:13], s[6:7], s[12:13]
+; CI-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15]
+; CI-NEXT: s_cselect_b64 s[12:13], s[12:13], s[6:7]
+; CI-NEXT: s_mov_b32 s14, 0
; CI-NEXT: .LBB13_10: ; %Flow49
-; CI-NEXT: s_xor_b32 s2, s2, 1
-; CI-NEXT: s_cmp_lg_u32 s2, 0
+; CI-NEXT: s_xor_b32 s14, s14, 1
+; CI-NEXT: s_cmp_lg_u32 s14, 0
; CI-NEXT: s_cbranch_scc1 .LBB13_16
; CI-NEXT: ; %bb.11: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[6:7]|
-; CI-NEXT: v_frexp_exp_i32_f64_e64 v8, |s[6:7]|
-; CI-NEXT: v_frexp_exp_i32_f64_e64 v9, |s[10:11]|
-; CI-NEXT: v_ldexp_f64 v[6:7], v[2:3], 26
-; CI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[10:11]|
-; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v8
-; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v9
-; CI-NEXT: v_sub_i32_e32 v11, vcc, v4, v10
-; CI-NEXT: v_ldexp_f64 v[2:3], v[2:3], 1
-; CI-NEXT: v_div_scale_f64 v[4:5], s[2:3], v[2:3], v[2:3], 1.0
-; CI-NEXT: v_div_scale_f64 v[16:17], vcc, 1.0, v[2:3], 1.0
-; CI-NEXT: v_rcp_f64_e32 v[12:13], v[4:5]
-; CI-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
-; CI-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
-; CI-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
-; CI-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
-; CI-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13]
-; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[16:17]
-; CI-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[14:15]
-; CI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v11
-; CI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB13_14
+; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[6:7]|
+; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[6:7]|
+; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26
+; CI-NEXT: v_readfirstlane_b32 s14, v2
+; CI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[10:11]|
+; CI-NEXT: s_add_i32 s17, s14, -1
+; CI-NEXT: v_readfirstlane_b32 s12, v0
+; CI-NEXT: v_readfirstlane_b32 s13, v1
+; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[10:11]|
+; CI-NEXT: v_readfirstlane_b32 s15, v2
+; CI-NEXT: s_add_i32 s16, s15, -1
+; CI-NEXT: s_sub_i32 s17, s17, s16
+; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
+; CI-NEXT: v_div_scale_f64 v[2:3], s[18:19], v[0:1], v[0:1], 1.0
+; CI-NEXT: v_div_scale_f64 v[8:9], s[18:19], 1.0, v[0:1], 1.0
+; CI-NEXT: s_or_b64 s[18:19], s[18:19], s[18:19]
+; CI-NEXT: s_cselect_b64 vcc, exec, 0
+; CI-NEXT: s_cmp_le_i32 s17, 26
+; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
+; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
+; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
+; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
+; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
+; CI-NEXT: s_cbranch_scc1 .LBB13_14
; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v8, vcc, 26, v8
-; CI-NEXT: v_sub_i32_e32 v11, vcc, v8, v9
+; CI-NEXT: s_add_i32 s14, s14, 26
+; CI-NEXT: s_sub_i32 s17, s14, s15
; CI-NEXT: .LBB13_13: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v9, v7
-; CI-NEXT: v_mov_b32_e32 v8, v6
-; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
-; CI-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
-; CI-NEXT: v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
-; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; CI-NEXT: v_add_f64 v[12:13], v[6:7], v[2:3]
-; CI-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
-; CI-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc
-; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; CI-NEXT: v_add_i32_e32 v11, vcc, 0xffffffe6, v11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v11
-; CI-NEXT: s_cbranch_vccnz .LBB13_13
+; CI-NEXT: v_mul_f64 v[4:5], s[12:13], v[2:3]
+; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
+; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[12:13]
+; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; CI-NEXT: v_readfirstlane_b32 s14, v4
+; CI-NEXT: v_readfirstlane_b32 s15, v5
+; CI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1]
+; CI-NEXT: s_or_b64 s[18:19], vcc, vcc
+; CI-NEXT: v_readfirstlane_b32 s18, v4
+; CI-NEXT: v_readfirstlane_b32 s19, v5
+; CI-NEXT: s_cselect_b64 s[14:15], s[18:19], s[14:15]
+; CI-NEXT: v_ldexp_f64 v[4:5], s[14:15], 26
+; CI-NEXT: s_sub_i32 s17, s17, 26
+; CI-NEXT: s_cmp_gt_i32 s17, 26
+; CI-NEXT: s_mov_b64 s[14:15], s[12:13]
+; CI-NEXT: v_readfirstlane_b32 s18, v4
+; CI-NEXT: v_readfirstlane_b32 s19, v5
+; CI-NEXT: s_mov_b64 s[12:13], s[18:19]
+; CI-NEXT: s_cbranch_scc1 .LBB13_13
; CI-NEXT: s_branch .LBB13_15
; CI-NEXT: .LBB13_14:
-; CI-NEXT: v_mov_b32_e32 v9, v7
-; CI-NEXT: v_mov_b32_e32 v8, v6
+; CI-NEXT: s_mov_b64 s[14:15], s[12:13]
; CI-NEXT: .LBB13_15: ; %frem.loop_exit
-; CI-NEXT: v_add_i32_e32 v6, vcc, 0xffffffe7, v11
-; CI-NEXT: v_ldexp_f64 v[6:7], v[8:9], v6
-; CI-NEXT: s_mov_b32 s2, 0
-; CI-NEXT: s_brev_b32 s3, 1
-; CI-NEXT: s_and_b64 s[2:3], s[6:7], s[2:3]
-; CI-NEXT: v_mul_f64 v[4:5], v[6:7], v[4:5]
-; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
-; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
-; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; CI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
-; CI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; CI-NEXT: v_ldexp_f64 v[2:3], v[2:3], v10
-; CI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; CI-NEXT: v_or_b32_e32 v2, s2, v2
-; CI-NEXT: v_or_b32_e32 v3, s3, v3
+; CI-NEXT: s_sub_i32 s12, s17, 25
+; CI-NEXT: v_mov_b32_e32 v4, s12
+; CI-NEXT: v_ldexp_f64 v[4:5], s[14:15], v4
+; CI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
+; CI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
+; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3]
+; CI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; CI-NEXT: v_readfirstlane_b32 s12, v2
+; CI-NEXT: v_readfirstlane_b32 s13, v3
+; CI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; CI-NEXT: v_readfirstlane_b32 s14, v0
+; CI-NEXT: v_readfirstlane_b32 s15, v1
+; CI-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13]
+; CI-NEXT: v_mov_b32_e32 v0, s16
+; CI-NEXT: v_ldexp_f64 v[0:1], s[12:13], v0
+; CI-NEXT: s_mov_b32 s14, 0
+; CI-NEXT: s_brev_b32 s15, 1
+; CI-NEXT: s_and_b64 s[14:15], s[6:7], s[14:15]
+; CI-NEXT: v_readfirstlane_b32 s13, v1
+; CI-NEXT: v_readfirstlane_b32 s12, v0
+; CI-NEXT: s_bitset0_b32 s13, 31
+; CI-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
; CI-NEXT: .LBB13_16: ; %Flow50
-; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[8:9], 0
-; CI-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; CI-NEXT: v_mov_b32_e32 v4, 0
-; CI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
+; CI-NEXT: v_cmp_nlg_f64_e64 s[8:9], s[8:9], 0
+; CI-NEXT: v_mov_b32_e32 v0, 0
+; CI-NEXT: v_mov_b32_e32 v1, 0x7ff00000
+; CI-NEXT: v_cmp_nge_f64_e64 s[4:5], |s[4:5]|, v[0:1]
+; CI-NEXT: v_cmp_nge_f64_e64 s[6:7], |s[6:7]|, v[0:1]
+; CI-NEXT: s_or_b64 s[8:9], s[8:9], s[8:9]
+; CI-NEXT: s_mov_b32 s8, 0
+; CI-NEXT: s_mov_b32 s9, 0x7ff80000
+; CI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3]
+; CI-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; CI-NEXT: s_cselect_b64 s[4:5], s[2:3], s[8:9]
+; CI-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[10:11], 0
+; CI-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; CI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[12:13]
+; CI-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; CI-NEXT: s_cselect_b64 s[6:7], s[2:3], s[8:9]
+; CI-NEXT: v_mov_b32_e32 v0, s4
+; CI-NEXT: v_mov_b32_e32 v1, s5
+; CI-NEXT: v_mov_b32_e32 v2, s6
+; CI-NEXT: v_mov_b32_e32 v3, s7
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s3, 0xf000
-; CI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[4:5]|, v[4:5]
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[10:11], 0
-; CI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; CI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[6:7]|, v[4:5]
-; CI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: s_endpgm
;
@@ -3343,201 +4008,236 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34
+; VI-NEXT: s_mov_b32 s12, 1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x40
-; VI-NEXT: s_mov_b32 s2, 1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v1, s9
-; VI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[4:5]|, |v[0:1]|
-; VI-NEXT: ; implicit-def: $vgpr0_vgpr1
-; VI-NEXT: s_cbranch_vccz .LBB13_2
+; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |s[4:5]|, |v[0:1]|
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: ; implicit-def: $sgpr2_sgpr3
+; VI-NEXT: s_cbranch_scc0 .LBB13_2
; VI-NEXT: ; %bb.1: ; %frem.else16
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v1, s9
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |s[4:5]|, |v[0:1]|
+; VI-NEXT: v_cmp_eq_f64_e64 s[12:13], |s[4:5]|, |v[0:1]|
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_brev_b32 s3, 1
; VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
-; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_mov_b32_e32 v2, s4
-; VI-NEXT: v_mov_b32_e32 v3, s5
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; VI-NEXT: s_mov_b32 s12, 0
; VI-NEXT: .LBB13_2: ; %Flow53
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s12, s12, 1
+; VI-NEXT: s_cmp_lg_u32 s12, 0
; VI-NEXT: s_cbranch_scc1 .LBB13_8
; VI-NEXT: ; %bb.3: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]|
-; VI-NEXT: v_frexp_exp_i32_f64_e64 v6, |s[4:5]|
-; VI-NEXT: v_frexp_exp_i32_f64_e64 v7, |s[8:9]|
-; VI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
+; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[4:5]|
+; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26
+; VI-NEXT: v_readfirstlane_b32 s12, v2
+; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[8:9]|
+; VI-NEXT: s_add_i32 s15, s12, -1
+; VI-NEXT: v_readfirstlane_b32 s2, v0
+; VI-NEXT: v_readfirstlane_b32 s3, v1
; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[8:9]|
-; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v6
-; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v7
-; VI-NEXT: v_sub_u32_e32 v9, vcc, v2, v8
+; VI-NEXT: v_readfirstlane_b32 s13, v2
+; VI-NEXT: s_add_i32 s14, s13, -1
+; VI-NEXT: s_sub_i32 s15, s15, s14
; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
-; VI-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], 1.0
-; VI-NEXT: v_div_scale_f64 v[14:15], vcc, 1.0, v[0:1], 1.0
-; VI-NEXT: v_rcp_f64_e32 v[10:11], v[2:3]
-; VI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
-; VI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; VI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0
-; VI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; VI-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
-; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15]
-; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[12:13]
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v9
+; VI-NEXT: v_div_scale_f64 v[2:3], s[16:17], v[0:1], v[0:1], 1.0
+; VI-NEXT: v_div_scale_f64 v[8:9], s[16:17], 1.0, v[0:1], 1.0
+; VI-NEXT: s_cmp_lg_u64 s[16:17], 0
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: s_cmp_le_i32 s15, 26
+; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
+; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
+; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
+; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB13_6
+; VI-NEXT: s_cbranch_scc1 .LBB13_6
; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
-; VI-NEXT: v_add_u32_e32 v6, vcc, 26, v6
-; VI-NEXT: v_sub_u32_e32 v9, vcc, v6, v7
+; VI-NEXT: s_add_i32 s12, s12, 26
+; VI-NEXT: s_sub_i32 s15, s12, s13
; VI-NEXT: .LBB13_5: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: v_mov_b32_e32 v6, v4
-; VI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3]
+; VI-NEXT: v_mul_f64 v[4:5], s[2:3], v[2:3]
; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
-; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
+; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[2:3]
+; VI-NEXT: v_readfirstlane_b32 s12, v4
+; VI-NEXT: v_readfirstlane_b32 s13, v5
; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; VI-NEXT: v_add_f64 v[10:11], v[4:5], v[0:1]
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
-; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; VI-NEXT: v_add_u32_e32 v9, vcc, 0xffffffe6, v9
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v9
-; VI-NEXT: s_cbranch_vccnz .LBB13_5
+; VI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1]
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s16, v4
+; VI-NEXT: v_readfirstlane_b32 s17, v5
+; VI-NEXT: s_cselect_b64 s[12:13], s[16:17], s[12:13]
+; VI-NEXT: v_ldexp_f64 v[4:5], s[12:13], 26
+; VI-NEXT: s_sub_i32 s15, s15, 26
+; VI-NEXT: s_cmp_gt_i32 s15, 26
+; VI-NEXT: s_mov_b64 s[12:13], s[2:3]
+; VI-NEXT: v_readfirstlane_b32 s16, v4
+; VI-NEXT: v_readfirstlane_b32 s17, v5
+; VI-NEXT: s_mov_b64 s[2:3], s[16:17]
+; VI-NEXT: s_cbranch_scc1 .LBB13_5
; VI-NEXT: s_branch .LBB13_7
; VI-NEXT: .LBB13_6:
-; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: v_mov_b32_e32 v6, v4
+; VI-NEXT: s_mov_b64 s[12:13], s[2:3]
; VI-NEXT: .LBB13_7: ; %frem.loop_exit24
-; VI-NEXT: v_add_u32_e32 v4, vcc, 0xffffffe7, v9
-; VI-NEXT: v_ldexp_f64 v[4:5], v[6:7], v4
-; VI-NEXT: s_mov_b32 s2, 0
-; VI-NEXT: s_brev_b32 s3, 1
-; VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
+; VI-NEXT: s_sub_i32 s2, s15, 25
+; VI-NEXT: v_mov_b32_e32 v4, s2
+; VI-NEXT: v_ldexp_f64 v[4:5], s[12:13], v4
; VI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3]
; VI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
-; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; VI-NEXT: v_or_b32_e32 v0, s2, v0
-; VI-NEXT: v_or_b32_e32 v1, s3, v1
+; VI-NEXT: v_readfirstlane_b32 s2, v2
+; VI-NEXT: v_readfirstlane_b32 s3, v3
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s12, v0
+; VI-NEXT: v_readfirstlane_b32 s13, v1
+; VI-NEXT: s_cselect_b64 s[2:3], s[12:13], s[2:3]
+; VI-NEXT: v_mov_b32_e32 v0, s14
+; VI-NEXT: v_ldexp_f64 v[0:1], s[2:3], v0
+; VI-NEXT: s_mov_b32 s12, 0
+; VI-NEXT: s_brev_b32 s13, 1
+; VI-NEXT: s_and_b64 s[12:13], s[4:5], s[12:13]
+; VI-NEXT: v_readfirstlane_b32 s3, v1
+; VI-NEXT: v_readfirstlane_b32 s2, v0
+; VI-NEXT: s_bitset0_b32 s3, 31
+; VI-NEXT: s_or_b64 s[2:3], s[2:3], s[12:13]
; VI-NEXT: .LBB13_8: ; %Flow54
-; VI-NEXT: v_mov_b32_e32 v2, s10
-; VI-NEXT: v_mov_b32_e32 v3, s11
-; VI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[6:7]|, |v[2:3]|
-; VI-NEXT: s_mov_b32 s2, 1
-; VI-NEXT: ; implicit-def: $vgpr2_vgpr3
-; VI-NEXT: s_cbranch_vccz .LBB13_10
+; VI-NEXT: v_mov_b32_e32 v0, s10
+; VI-NEXT: v_mov_b32_e32 v1, s11
+; VI-NEXT: v_cmp_ngt_f64_e64 s[12:13], |s[6:7]|, |v[0:1]|
+; VI-NEXT: s_mov_b32 s14, 1
+; VI-NEXT: s_cmp_lg_u64 s[12:13], 0
+; VI-NEXT: ; implicit-def: $sgpr12_sgpr13
+; VI-NEXT: s_cbranch_scc0 .LBB13_10
; VI-NEXT: ; %bb.9: ; %frem.else
-; VI-NEXT: v_mov_b32_e32 v2, s10
-; VI-NEXT: v_mov_b32_e32 v3, s11
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |s[6:7]|, |v[2:3]|
-; VI-NEXT: s_mov_b32 s2, 0
-; VI-NEXT: s_brev_b32 s3, 1
-; VI-NEXT: s_and_b64 s[2:3], s[6:7], s[2:3]
-; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v3, s3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_mov_b32_e32 v5, s7
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; VI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; VI-NEXT: s_mov_b32 s2, 0
+; VI-NEXT: v_mov_b32_e32 v0, s10
+; VI-NEXT: v_mov_b32_e32 v1, s11
+; VI-NEXT: v_cmp_eq_f64_e64 s[14:15], |s[6:7]|, |v[0:1]|
+; VI-NEXT: s_mov_b32 s12, 0
+; VI-NEXT: s_brev_b32 s13, 1
+; VI-NEXT: s_and_b64 s[12:13], s[6:7], s[12:13]
+; VI-NEXT: s_cmp_lg_u64 s[14:15], 0
+; VI-NEXT: s_cselect_b64 s[12:13], s[12:13], s[6:7]
+; VI-NEXT: s_mov_b32 s14, 0
; VI-NEXT: .LBB13_10: ; %Flow49
-; VI-NEXT: s_xor_b32 s2, s2, 1
-; VI-NEXT: s_cmp_lg_u32 s2, 0
+; VI-NEXT: s_xor_b32 s14, s14, 1
+; VI-NEXT: s_cmp_lg_u32 s14, 0
; VI-NEXT: s_cbranch_scc1 .LBB13_16
; VI-NEXT: ; %bb.11: ; %frem.compute
-; VI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[6:7]|
-; VI-NEXT: v_frexp_exp_i32_f64_e64 v8, |s[6:7]|
-; VI-NEXT: v_frexp_exp_i32_f64_e64 v9, |s[10:11]|
-; VI-NEXT: v_ldexp_f64 v[6:7], v[2:3], 26
-; VI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[10:11]|
-; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v8
-; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v9
-; VI-NEXT: v_sub_u32_e32 v11, vcc, v4, v10
-; VI-NEXT: v_ldexp_f64 v[2:3], v[2:3], 1
-; VI-NEXT: v_div_scale_f64 v[4:5], s[2:3], v[2:3], v[2:3], 1.0
-; VI-NEXT: v_div_scale_f64 v[16:17], vcc, 1.0, v[2:3], 1.0
-; VI-NEXT: v_rcp_f64_e32 v[12:13], v[4:5]
-; VI-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
-; VI-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
-; VI-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0
-; VI-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
-; VI-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13]
-; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[16:17]
-; VI-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[14:15]
-; VI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v11
-; VI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB13_14
+; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[6:7]|
+; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[6:7]|
+; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 26
+; VI-NEXT: v_readfirstlane_b32 s14, v2
+; VI-NEXT: v_frexp_exp_i32_f64_e64 v2, |s[10:11]|
+; VI-NEXT: s_add_i32 s17, s14, -1
+; VI-NEXT: v_readfirstlane_b32 s12, v0
+; VI-NEXT: v_readfirstlane_b32 s13, v1
+; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[10:11]|
+; VI-NEXT: v_readfirstlane_b32 s15, v2
+; VI-NEXT: s_add_i32 s16, s15, -1
+; VI-NEXT: s_sub_i32 s17, s17, s16
+; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
+; VI-NEXT: v_div_scale_f64 v[2:3], s[18:19], v[0:1], v[0:1], 1.0
+; VI-NEXT: v_div_scale_f64 v[8:9], s[18:19], 1.0, v[0:1], 1.0
+; VI-NEXT: s_cmp_lg_u64 s[18:19], 0
+; VI-NEXT: s_cselect_b64 vcc, exec, 0
+; VI-NEXT: s_cmp_le_i32 s17, 26
+; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
+; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
+; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
+; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
+; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
+; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
+; VI-NEXT: s_cbranch_scc1 .LBB13_14
; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v8, vcc, 26, v8
-; VI-NEXT: v_sub_u32_e32 v11, vcc, v8, v9
+; VI-NEXT: s_add_i32 s14, s14, 26
+; VI-NEXT: s_sub_i32 s17, s14, s15
; VI-NEXT: .LBB13_13: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v9, v7
-; VI-NEXT: v_mov_b32_e32 v8, v6
-; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
-; VI-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
-; VI-NEXT: v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
-; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; VI-NEXT: v_add_f64 v[12:13], v[6:7], v[2:3]
-; VI-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
-; VI-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc
-; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; VI-NEXT: v_add_u32_e32 v11, vcc, 0xffffffe6, v11
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v11
-; VI-NEXT: s_cbranch_vccnz .LBB13_13
+; VI-NEXT: v_mul_f64 v[4:5], s[12:13], v[2:3]
+; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
+; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], s[12:13]
+; VI-NEXT: v_readfirstlane_b32 s14, v4
+; VI-NEXT: v_readfirstlane_b32 s15, v5
+; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; VI-NEXT: v_add_f64 v[4:5], v[4:5], v[0:1]
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s18, v4
+; VI-NEXT: v_readfirstlane_b32 s19, v5
+; VI-NEXT: s_cselect_b64 s[14:15], s[18:19], s[14:15]
+; VI-NEXT: v_ldexp_f64 v[4:5], s[14:15], 26
+; VI-NEXT: s_sub_i32 s17, s17, 26
+; VI-NEXT: s_cmp_gt_i32 s17, 26
+; VI-NEXT: s_mov_b64 s[14:15], s[12:13]
+; VI-NEXT: v_readfirstlane_b32 s18, v4
+; VI-NEXT: v_readfirstlane_b32 s19, v5
+; VI-NEXT: s_mov_b64 s[12:13], s[18:19]
+; VI-NEXT: s_cbranch_scc1 .LBB13_13
; VI-NEXT: s_branch .LBB13_15
; VI-NEXT: .LBB13_14:
-; VI-NEXT: v_mov_b32_e32 v9, v7
-; VI-NEXT: v_mov_b32_e32 v8, v6
+; VI-NEXT: s_mov_b64 s[14:15], s[12:13]
; VI-NEXT: .LBB13_15: ; %frem.loop_exit
-; VI-NEXT: v_add_u32_e32 v6, vcc, 0xffffffe7, v11
-; VI-NEXT: v_ldexp_f64 v[6:7], v[8:9], v6
-; VI-NEXT: s_mov_b32 s2, 0
-; VI-NEXT: s_brev_b32 s3, 1
-; VI-NEXT: s_and_b64 s[2:3], s[6:7], s[2:3]
-; VI-NEXT: v_mul_f64 v[4:5], v[6:7], v[4:5]
-; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
-; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7]
-; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; VI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; VI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; VI-NEXT: v_ldexp_f64 v[2:3], v[2:3], v10
-; VI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; VI-NEXT: v_or_b32_e32 v2, s2, v2
-; VI-NEXT: v_or_b32_e32 v3, s3, v3
+; VI-NEXT: s_sub_i32 s12, s17, 25
+; VI-NEXT: v_mov_b32_e32 v4, s12
+; VI-NEXT: v_ldexp_f64 v[4:5], s[14:15], v4
+; VI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
+; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5]
+; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3]
+; VI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; VI-NEXT: v_readfirstlane_b32 s12, v2
+; VI-NEXT: v_readfirstlane_b32 s13, v3
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-NEXT: v_readfirstlane_b32 s14, v0
+; VI-NEXT: v_readfirstlane_b32 s15, v1
+; VI-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13]
+; VI-NEXT: v_mov_b32_e32 v0, s16
+; VI-NEXT: v_ldexp_f64 v[0:1], s[12:13], v0
+; VI-NEXT: s_mov_b32 s14, 0
+; VI-NEXT: s_brev_b32 s15, 1
+; VI-NEXT: s_and_b64 s[14:15], s[6:7], s[14:15]
+; VI-NEXT: v_readfirstlane_b32 s13, v1
+; VI-NEXT: v_readfirstlane_b32 s12, v0
+; VI-NEXT: s_bitset0_b32 s13, 31
+; VI-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
; VI-NEXT: .LBB13_16: ; %Flow50
-; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[8:9], 0
-; VI-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; VI-NEXT: v_mov_b32_e32 v4, 0
-; VI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[4:5]|, v[4:5]
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[10:11], 0
-; VI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
-; VI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[6:7]|, v[4:5]
+; VI-NEXT: v_cmp_nlg_f64_e64 s[8:9], s[8:9], 0
+; VI-NEXT: v_mov_b32_e32 v0, 0
+; VI-NEXT: v_mov_b32_e32 v1, 0x7ff00000
+; VI-NEXT: v_cmp_nge_f64_e64 s[4:5], |s[4:5]|, v[0:1]
+; VI-NEXT: v_cmp_nge_f64_e64 s[6:7], |s[6:7]|, v[0:1]
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; VI-NEXT: s_cmp_lg_u64 s[8:9], 0
+; VI-NEXT: s_mov_b32 s8, 0
+; VI-NEXT: s_mov_b32 s9, 0x7ff80000
+; VI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3]
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-NEXT: s_cselect_b64 s[4:5], s[2:3], s[8:9]
+; VI-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[10:11], 0
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[12:13]
+; VI-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-NEXT: s_cselect_b64 s[6:7], s[2:3], s[8:9]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
%gep2 = getelementptr <2 x double>, ptr addrspace(1) %in2, i32 4
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll b/llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
index 28b5f3bed45e0..0886a646987c1 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
@@ -3,14 +3,14 @@
; between implementations.
; RUN: llc -global-isel=0 -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,CODEGEN-IEEE-SDAG %s
-; RUN: llc -global-isel=1 -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,CODEGEN-IEEE-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,CODEGEN-IEEE-GISEL %s
; RUN: llc -global-isel=0 -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,IR-IEEE,IR-IEEE-SDAG %s
-; RUN: llc -global-isel=1 -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,IR-IEEE,IR-IEEE-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,IR-IEEE,IR-IEEE-GISEL %s
; RUN: llc -global-isel=0 -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,CODEGEN-DAZ,CODEGEN-DAZ-SDAG %s
-; RUN: llc -global-isel=1 -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,CODEGEN-DAZ,CODEGEN-DAZ-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,CODEGEN-DAZ,CODEGEN-DAZ-GISEL %s
; RUN: llc -global-isel=0 -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,IR-DAZ,IR-DAZ-SDAG %s
-; RUN: llc -global-isel=1 -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,IR-DAZ,IR-DAZ-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,IR-DAZ,IR-DAZ-GISEL %s
define float @v_fdiv_f32(float %x, float %y) {
; IEEE-LABEL: v_fdiv_f32:
diff --git a/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll b/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
index 342359c68fa93..4fe58ab538a7e 100644
--- a/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SDAG,GCN-IEEE,SDAG-IEEE %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GISEL,GCN-IEEE,GISEL-IEEE %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GISEL,GCN-IEEE,GISEL-IEEE %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN,SDAG,GCN-DAZ,SDAG-DAZ %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN,GISEL,GCN-DAZ,GISEL-DAZ %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN,GISEL,GCN-DAZ,GISEL-DAZ %s
define float @v_sqrt_f32(float %x) {
; SDAG-IEEE-LABEL: v_sqrt_f32:
@@ -705,27 +705,37 @@ define amdgpu_ps i32 @s_sqrt_f32(float inreg %x) {
;
; GISEL-IEEE-LABEL: s_sqrt_f32:
; GISEL-IEEE: ; %bb.0:
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, s0, v2
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v2, s[0:1], -1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v3, -v2, v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v4, s[0:1], 1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v5, -v4, v1, v0
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v5
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GISEL-IEEE-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s0, v0
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s3, s1, s0
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v0, s3
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-IEEE-NEXT: s_add_i32 s5, s4, -1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s5
+; GISEL-IEEE-NEXT: s_add_i32 s6, s4, 1
+; GISEL-IEEE-NEXT: v_fma_f32 v1, -v1, v0, s3
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s6
+; GISEL-IEEE-NEXT: v_fma_f32 v0, -v2, v0, s3
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s0, s6, s4
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x37800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s0, v0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s2, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s3, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, s1, s0
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s0, s3, s2
; GISEL-IEEE-NEXT: ; return to shader part epilog
;
; SDAG-DAZ-LABEL: s_sqrt_f32:
@@ -754,26 +764,29 @@ define amdgpu_ps i32 @s_sqrt_f32(float inreg %x) {
;
; GISEL-DAZ-LABEL: s_sqrt_f32:
; GISEL-DAZ: ; %bb.0:
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, s0, v2
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v1, v0
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, v0, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v1, v2, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v3, v2
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v3, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v2, v2, v0
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v3, v1, v2
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0xf800000
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, s0, v0
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s2, s1, s0
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v0, s2
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s2, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v0, v1, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v2, v1
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v0, v2, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v1, v1, s2
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v2, v0, v1
; GISEL-DAZ-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0x37800000, v0
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s2, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s3, s1, s0
+; GISEL-DAZ-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-DAZ-NEXT: s_cselect_b32 s0, s2, s3
; GISEL-DAZ-NEXT: ; return to shader part epilog
%result = call float @llvm.sqrt.f32(float %x)
%cast = bitcast float %result to i32
@@ -809,27 +822,37 @@ define amdgpu_ps i32 @s_sqrt_f32_ninf(float inreg %x) {
;
; GISEL-IEEE-LABEL: s_sqrt_f32_ninf:
; GISEL-IEEE: ; %bb.0:
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, s0, v2
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v2, s[0:1], -1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v3, -v2, v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v4, s[0:1], 1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v5, -v4, v1, v0
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v5
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GISEL-IEEE-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s0, v0
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s3, s1, s0
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v0, s3
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-IEEE-NEXT: s_add_i32 s5, s4, -1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s5
+; GISEL-IEEE-NEXT: s_add_i32 s6, s4, 1
+; GISEL-IEEE-NEXT: v_fma_f32 v1, -v1, v0, s3
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s6
+; GISEL-IEEE-NEXT: v_fma_f32 v0, -v2, v0, s3
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s0, s6, s4
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x37800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s0, v0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s2, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s3, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, s1, s0
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s0, s3, s2
; GISEL-IEEE-NEXT: ; return to shader part epilog
;
; SDAG-DAZ-LABEL: s_sqrt_f32_ninf:
@@ -858,26 +881,29 @@ define amdgpu_ps i32 @s_sqrt_f32_ninf(float inreg %x) {
;
; GISEL-DAZ-LABEL: s_sqrt_f32_ninf:
; GISEL-DAZ: ; %bb.0:
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, s0, v2
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v1, v0
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, v0, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v1, v2, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v3, v2
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v3, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v2, v2, v0
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v3, v1, v2
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0xf800000
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, s0, v0
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s2, s1, s0
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v0, s2
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s2, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v0, v1, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v2, v1
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v0, v2, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v1, v1, s2
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v2, v0, v1
; GISEL-DAZ-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0x37800000, v0
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s1, v0
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s2, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s3, s1, s0
+; GISEL-DAZ-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-DAZ-NEXT: s_cselect_b32 s0, s2, s3
; GISEL-DAZ-NEXT: ; return to shader part epilog
%result = call ninf float @llvm.sqrt.f32(float %x)
%cast = bitcast float %result to i32
@@ -3972,36 +3998,49 @@ define amdgpu_kernel void @elim_redun_check_neg0(ptr addrspace(1) %out, float %i
;
; GISEL-IEEE-LABEL: elim_redun_check_neg0:
; GISEL-IEEE: ; %bb.0: ; %entry
-; GISEL-IEEE-NEXT: s_load_dword s2, s[4:5], 0xb
+; GISEL-IEEE-NEXT: s_load_dword s6, s[4:5], 0xb
; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GISEL-IEEE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; GISEL-IEEE-NEXT: s_mov_b32 s6, -1
; GISEL-IEEE-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v1, s2, v1
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v1, v0
-; GISEL-IEEE-NEXT: s_mov_b32 s7, 0xf000
-; GISEL-IEEE-NEXT: v_add_i32_e64 v2, s[0:1], -1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v3, -v2, v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v4, s[0:1], 1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v5, -v4, v1, v0
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v5
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GISEL-IEEE-NEXT: v_bfrev_b32_e32 v1, 1
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GISEL-IEEE-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s6, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s8, s0, s6
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v0, s8
+; GISEL-IEEE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-IEEE-NEXT: s_add_i32 s5, s4, -1
+; GISEL-IEEE-NEXT: s_add_i32 s9, s4, 1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s5
+; GISEL-IEEE-NEXT: v_fma_f32 v1, -v1, v0, s8
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s9
+; GISEL-IEEE-NEXT: v_fma_f32 v0, -v2, v0, s8
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, s9, s4
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x37800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s2, v0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s3, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s7, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s8, v0
+; GISEL-IEEE-NEXT: v_bfrev_b32_e32 v0, 1
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s3, s2
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s8, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, 0x7fc00000, s4
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-IEEE-NEXT: s_mov_b32 s2, -1
+; GISEL-IEEE-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-IEEE-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-IEEE-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GISEL-IEEE-NEXT: s_endpgm
;
; SDAG-DAZ-LABEL: elim_redun_check_neg0:
@@ -4036,34 +4075,40 @@ define amdgpu_kernel void @elim_redun_check_neg0(ptr addrspace(1) %out, float %i
;
; GISEL-DAZ-LABEL: elim_redun_check_neg0:
; GISEL-DAZ: ; %bb.0: ; %entry
-; GISEL-DAZ-NEXT: s_load_dword s2, s[4:5], 0xb
-; GISEL-DAZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-DAZ-NEXT: s_load_dword s6, s[4:5], 0xb
; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GISEL-DAZ-NEXT: s_mov_b32 s3, 0xf000
; GISEL-DAZ-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s2, v1
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v1, v0
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, v0, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v1, v2, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v3, v2
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v3, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v2, v2, v0
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v3, v1, v2
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GISEL-DAZ-NEXT: v_bfrev_b32_e32 v1, 1
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, s6, v1
+; GISEL-DAZ-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s0, s6
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v0, s7
+; GISEL-DAZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s7, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v0, v1, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v2, v1
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v0, v2, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v1, v1, s7
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v2, v0, v1
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s2, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0x37800000, v0
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s3, v0
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s7, v0
+; GISEL-DAZ-NEXT: v_bfrev_b32_e32 v0, 1
+; GISEL-DAZ-NEXT: s_cselect_b32 s4, s3, s2
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s4, s7, s4
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: s_cselect_b32 s2, 0x7fc00000, s4
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, s2
; GISEL-DAZ-NEXT: s_mov_b32 s2, -1
+; GISEL-DAZ-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-DAZ-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-DAZ-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GISEL-DAZ-NEXT: s_endpgm
entry:
@@ -4107,35 +4152,48 @@ define amdgpu_kernel void @elim_redun_check_pos0(ptr addrspace(1) %out, float %i
;
; GISEL-IEEE-LABEL: elim_redun_check_pos0:
; GISEL-IEEE: ; %bb.0: ; %entry
-; GISEL-IEEE-NEXT: s_load_dword s2, s[4:5], 0xb
+; GISEL-IEEE-NEXT: s_load_dword s6, s[4:5], 0xb
; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GISEL-IEEE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; GISEL-IEEE-NEXT: s_mov_b32 s6, -1
; GISEL-IEEE-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v1, s2, v1
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v1, v0
-; GISEL-IEEE-NEXT: s_mov_b32 s7, 0xf000
-; GISEL-IEEE-NEXT: v_add_i32_e64 v2, s[0:1], -1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v3, -v2, v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v4, s[0:1], 1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v5, -v4, v1, v0
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v5
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0x7fc00000
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, s2, 0
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GISEL-IEEE-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s6, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s8, s0, s6
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v0, s8
+; GISEL-IEEE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-IEEE-NEXT: s_add_i32 s5, s4, -1
+; GISEL-IEEE-NEXT: s_add_i32 s9, s4, 1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s5
+; GISEL-IEEE-NEXT: v_fma_f32 v1, -v1, v0, s8
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s9
+; GISEL-IEEE-NEXT: v_fma_f32 v0, -v2, v0, s8
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, s9, s4
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x37800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s2, v0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s3, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s7, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s8, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s3, s2
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[2:3], s6, 0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s8, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, 0x7fc00000, s4
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-IEEE-NEXT: s_mov_b32 s2, -1
+; GISEL-IEEE-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-IEEE-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-IEEE-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GISEL-IEEE-NEXT: s_endpgm
;
; SDAG-DAZ-LABEL: elim_redun_check_pos0:
@@ -4170,33 +4228,39 @@ define amdgpu_kernel void @elim_redun_check_pos0(ptr addrspace(1) %out, float %i
;
; GISEL-DAZ-LABEL: elim_redun_check_pos0:
; GISEL-DAZ: ; %bb.0: ; %entry
-; GISEL-DAZ-NEXT: s_load_dword s2, s[4:5], 0xb
-; GISEL-DAZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-DAZ-NEXT: s_load_dword s6, s[4:5], 0xb
; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GISEL-DAZ-NEXT: s_mov_b32 s3, 0xf000
; GISEL-DAZ-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s2, v1
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v1, v0
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, v0, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v1, v2, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v3, v2
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v3, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v2, v2, v0
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v3, v1, v2
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0x7fc00000
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e64 vcc, s2, 0
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, s6, v1
+; GISEL-DAZ-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s0, s6
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v0, s7
+; GISEL-DAZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s7, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v0, v1, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v2, v1
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v0, v2, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v1, v1, s7
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v2, v0, v1
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s2, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0x37800000, v0
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s3, v0
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s7, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s4, s3, s2
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e64 s[2:3], s6, 0
+; GISEL-DAZ-NEXT: s_cselect_b32 s4, s7, s4
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; GISEL-DAZ-NEXT: s_cselect_b32 s2, 0x7fc00000, s4
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, s2
; GISEL-DAZ-NEXT: s_mov_b32 s2, -1
+; GISEL-DAZ-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-DAZ-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-DAZ-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GISEL-DAZ-NEXT: s_endpgm
entry:
@@ -4240,36 +4304,49 @@ define amdgpu_kernel void @elim_redun_check_ult(ptr addrspace(1) %out, float %in
;
; GISEL-IEEE-LABEL: elim_redun_check_ult:
; GISEL-IEEE: ; %bb.0: ; %entry
-; GISEL-IEEE-NEXT: s_load_dword s2, s[4:5], 0xb
+; GISEL-IEEE-NEXT: s_load_dword s6, s[4:5], 0xb
; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GISEL-IEEE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; GISEL-IEEE-NEXT: s_mov_b32 s6, -1
; GISEL-IEEE-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v1, s2, v1
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v1, v0
-; GISEL-IEEE-NEXT: s_mov_b32 s7, 0xf000
-; GISEL-IEEE-NEXT: v_add_i32_e64 v2, s[0:1], -1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v3, -v2, v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v4, s[0:1], 1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v5, -v4, v1, v0
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v5
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GISEL-IEEE-NEXT: v_bfrev_b32_e32 v1, 1
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GISEL-IEEE-NEXT: v_cmp_nge_f32_e32 vcc, s2, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GISEL-IEEE-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s6, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s8, s0, s6
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v0, s8
+; GISEL-IEEE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-IEEE-NEXT: s_add_i32 s5, s4, -1
+; GISEL-IEEE-NEXT: s_add_i32 s9, s4, 1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s5
+; GISEL-IEEE-NEXT: v_fma_f32 v1, -v1, v0, s8
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s9
+; GISEL-IEEE-NEXT: v_fma_f32 v0, -v2, v0, s8
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, s9, s4
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x37800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s2, v0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s3, v0
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s7, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s8, v0
+; GISEL-IEEE-NEXT: v_bfrev_b32_e32 v0, 1
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s3, s2
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_nge_f32_e32 vcc, s6, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s8, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, 0x7fc00000, s4
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-IEEE-NEXT: s_mov_b32 s2, -1
+; GISEL-IEEE-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-IEEE-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-IEEE-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GISEL-IEEE-NEXT: s_endpgm
;
; SDAG-DAZ-LABEL: elim_redun_check_ult:
@@ -4304,34 +4381,40 @@ define amdgpu_kernel void @elim_redun_check_ult(ptr addrspace(1) %out, float %in
;
; GISEL-DAZ-LABEL: elim_redun_check_ult:
; GISEL-DAZ: ; %bb.0: ; %entry
-; GISEL-DAZ-NEXT: s_load_dword s2, s[4:5], 0xb
-; GISEL-DAZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-DAZ-NEXT: s_load_dword s6, s[4:5], 0xb
; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GISEL-DAZ-NEXT: s_mov_b32 s3, 0xf000
; GISEL-DAZ-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s2, v1
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v1, v0
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, v0, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v1, v2, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v3, v2
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v3, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v3, -v2, v2, v0
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v3, v1, v2
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x260
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GISEL-DAZ-NEXT: v_bfrev_b32_e32 v1, 1
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; GISEL-DAZ-NEXT: v_cmp_nge_f32_e32 vcc, s2, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, s6, v1
+; GISEL-DAZ-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s0, s6
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v0, s7
+; GISEL-DAZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s7, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v0, v1, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v2, v1
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v0, v2, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v2, -v1, v1, s7
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v2, v0, v1
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s2, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0x37800000, v0
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s3, v0
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0x260
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s7, v0
+; GISEL-DAZ-NEXT: v_bfrev_b32_e32 v0, 1
+; GISEL-DAZ-NEXT: s_cselect_b32 s4, s3, s2
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_nge_f32_e32 vcc, s6, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s4, s7, s4
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: s_cselect_b32 s2, 0x7fc00000, s4
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, s2
; GISEL-DAZ-NEXT: s_mov_b32 s2, -1
+; GISEL-DAZ-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-DAZ-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-DAZ-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GISEL-DAZ-NEXT: s_endpgm
entry:
@@ -4393,54 +4476,82 @@ define amdgpu_kernel void @elim_redun_check_v2(ptr addrspace(1) %out, <2 x float
;
; GISEL-IEEE-LABEL: elim_redun_check_v2:
; GISEL-IEEE: ; %bb.0: ; %entry
-; GISEL-IEEE-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
+; GISEL-IEEE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GISEL-IEEE-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s6
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v3, s6, v1
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v3, v2
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v1, s7, v1
-; GISEL-IEEE-NEXT: v_add_i32_e64 v4, s[0:1], -1, v3
-; GISEL-IEEE-NEXT: v_add_i32_e64 v5, s[0:1], 1, v3
-; GISEL-IEEE-NEXT: v_fma_f32 v6, -v4, v3, v2
-; GISEL-IEEE-NEXT: v_fma_f32 v7, -v5, v3, v2
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v6
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v7
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v4, 0x37800000, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v5, s7
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v1, v0
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, 0x260
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e64 s[0:1], v2, v4
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[0:1]
-; GISEL-IEEE-NEXT: v_add_i32_e64 v3, s[0:1], -1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v5, -v3, v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v6, s[0:1], 1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v7, -v6, v1, v0
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v5
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v7
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v3, 0x37800000, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v4
-; GISEL-IEEE-NEXT: v_bfrev_b32_e32 v3, 1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, 0x7fc00000
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s7, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GISEL-IEEE-NEXT: s_mov_b32 s6, -1
-; GISEL-IEEE-NEXT: s_mov_b32 s7, 0xf000
-; GISEL-IEEE-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, s2, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v2
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, s4, s2
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v2, s7
+; GISEL-IEEE-NEXT: s_cselect_b32 s6, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s8, v2
+; GISEL-IEEE-NEXT: s_add_i32 s9, s8, -1
+; GISEL-IEEE-NEXT: s_add_i32 s10, s8, 1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v3, s9
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, s10
+; GISEL-IEEE-NEXT: v_fma_f32 v3, -v3, v2, s7
+; GISEL-IEEE-NEXT: v_fma_f32 v2, -v4, v2, s7
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v3
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v2
+; GISEL-IEEE-NEXT: s_cselect_b32 s8, s9, s8
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s10, s8
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x37800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v3, s4, v2
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s5, v3
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v3, 0x260
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s6, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s7, v3
+; GISEL-IEEE-NEXT: s_cselect_b32 s6, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s6, s7, s6
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s3, v1
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s8, s4, s3
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v0, s8
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s9, v0
+; GISEL-IEEE-NEXT: s_add_i32 s10, s9, -1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s10
+; GISEL-IEEE-NEXT: s_add_i32 s11, s9, 1
+; GISEL-IEEE-NEXT: v_fma_f32 v1, -v1, v0, s8
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, s11
+; GISEL-IEEE-NEXT: v_fma_f32 v0, -v4, v0, s8
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s9, s10, s9
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s11, s9
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s4, v2
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s5, v0
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s7, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s8, v3
+; GISEL-IEEE-NEXT: v_bfrev_b32_e32 v0, 1
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, s8, s7
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, 1, 0
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s3, 1, 0
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s4, 0
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, 0x7fc00000, s6
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s3, 0
+; GISEL-IEEE-NEXT: s_cselect_b32 s3, 0x7fc00000, s7
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-IEEE-NEXT: s_mov_b32 s2, -1
+; GISEL-IEEE-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-IEEE-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GISEL-IEEE-NEXT: s_endpgm
;
; SDAG-DAZ-LABEL: elim_redun_check_v2:
@@ -4491,52 +4602,67 @@ define amdgpu_kernel void @elim_redun_check_v2(ptr addrspace(1) %out, <2 x float
;
; GISEL-DAZ-LABEL: elim_redun_check_v2:
; GISEL-DAZ: ; %bb.0: ; %entry
-; GISEL-DAZ-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
+; GISEL-DAZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GISEL-DAZ-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, s6
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, s6, v1
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v3, v2
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v4, s7
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s7, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v5, v2, v3
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, 0.5, v3
-; GISEL-DAZ-NEXT: v_fma_f32 v6, -v3, v5, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v5, v5, v6, v5
-; GISEL-DAZ-NEXT: v_fma_f32 v3, v3, v6, v3
-; GISEL-DAZ-NEXT: v_fma_f32 v6, -v5, v5, v2
-; GISEL-DAZ-NEXT: v_fma_f32 v3, v6, v3, v5
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v5, 0x37800000, v3
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v1, v0
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v4, 0x260
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e64 s[0:1], v2, v4
-; GISEL-DAZ-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[0:1]
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, v0, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v5, -v1, v3, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v3, v3, v5, v3
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v5, -v3, v3, v0
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v5, v1, v3
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, 0x37800000, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v4
-; GISEL-DAZ-NEXT: v_bfrev_b32_e32 v3, 1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v4, 0x7fc00000
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s6, v3
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s7, v3
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GISEL-DAZ-NEXT: s_mov_b32 s6, -1
-; GISEL-DAZ-NEXT: s_mov_b32 s7, 0xf000
-; GISEL-DAZ-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, s2, v1
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s4, v2
+; GISEL-DAZ-NEXT: s_cselect_b32 s6, s4, s2
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v2, s6
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, s6, v2
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0.5, v2
+; GISEL-DAZ-NEXT: v_fma_f32 v4, -v2, v3, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v3, v3, v4, v3
+; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v4, v2
+; GISEL-DAZ-NEXT: v_fma_f32 v4, -v3, v3, s6
+; GISEL-DAZ-NEXT: v_fma_f32 v2, v4, v2, v3
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s4, v2
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v2
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s5, v2
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x260
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s6, v2
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s5, s4
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s6, s6, s7
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, s3, v1
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s4, s3
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v0, s7
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s7, v2
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s7, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v3, -v0, v1, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v3, v1
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v0, v3, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v3, -v1, v1, s7
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v3, v0, v1
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0x37800000, v0
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s5, v0
+; GISEL-DAZ-NEXT: v_bfrev_b32_e32 v0, 1
+; GISEL-DAZ-NEXT: s_cselect_b32 s8, s5, s4
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s7, s8
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s4, 1, 0
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: s_cselect_b32 s3, 1, 0
+; GISEL-DAZ-NEXT: s_cmp_lg_u32 s4, 0
+; GISEL-DAZ-NEXT: s_cselect_b32 s2, 0x7fc00000, s6
+; GISEL-DAZ-NEXT: s_cmp_lg_u32 s3, 0
+; GISEL-DAZ-NEXT: s_cselect_b32 s3, 0x7fc00000, s7
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-DAZ-NEXT: s_mov_b32 s2, -1
+; GISEL-DAZ-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-DAZ-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GISEL-DAZ-NEXT: s_endpgm
entry:
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
@@ -4597,54 +4723,82 @@ define amdgpu_kernel void @elim_redun_check_v2_ult(ptr addrspace(1) %out, <2 x f
;
; GISEL-IEEE-LABEL: elim_redun_check_v2_ult:
; GISEL-IEEE: ; %bb.0: ; %entry
-; GISEL-IEEE-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
+; GISEL-IEEE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GISEL-IEEE-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, s6
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v3, s6, v1
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v3, v2
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v1, s7, v1
-; GISEL-IEEE-NEXT: v_add_i32_e64 v4, s[0:1], -1, v3
-; GISEL-IEEE-NEXT: v_add_i32_e64 v5, s[0:1], 1, v3
-; GISEL-IEEE-NEXT: v_fma_f32 v6, -v4, v3, v2
-; GISEL-IEEE-NEXT: v_fma_f32 v7, -v5, v3, v2
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v6
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v7
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v4, 0x37800000, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v5, s7
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v1, v0
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, 0x260
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e64 s[0:1], v2, v4
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[0:1]
-; GISEL-IEEE-NEXT: v_add_i32_e64 v3, s[0:1], -1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v5, -v3, v1, v0
-; GISEL-IEEE-NEXT: v_add_i32_e64 v6, s[0:1], 1, v1
-; GISEL-IEEE-NEXT: v_fma_f32 v7, -v6, v1, v0
-; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v5
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v7
-; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1]
-; GISEL-IEEE-NEXT: v_mul_f32_e32 v3, 0x37800000, v1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v4
-; GISEL-IEEE-NEXT: v_bfrev_b32_e32 v3, 1
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
-; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, 0x7fc00000
-; GISEL-IEEE-NEXT: v_cmp_nge_f32_e32 vcc, s6, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
-; GISEL-IEEE-NEXT: v_cmp_nge_f32_e32 vcc, s7, v3
-; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GISEL-IEEE-NEXT: s_mov_b32 s6, -1
-; GISEL-IEEE-NEXT: s_mov_b32 s7, 0xf000
-; GISEL-IEEE-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, s2, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v2
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, s4, s2
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v2, s7
+; GISEL-IEEE-NEXT: s_cselect_b32 s6, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s8, v2
+; GISEL-IEEE-NEXT: s_add_i32 s9, s8, -1
+; GISEL-IEEE-NEXT: s_add_i32 s10, s8, 1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v3, s9
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, s10
+; GISEL-IEEE-NEXT: v_fma_f32 v3, -v3, v2, s7
+; GISEL-IEEE-NEXT: v_fma_f32 v2, -v4, v2, s7
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v3
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v2
+; GISEL-IEEE-NEXT: s_cselect_b32 s8, s9, s8
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s10, s8
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x37800000
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v3, s4, v2
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s5, v3
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v3, 0x260
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s6, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s7, v3
+; GISEL-IEEE-NEXT: s_cselect_b32 s6, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s6, s7, s6
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s3, v1
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s8, s4, s3
+; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v0, s8
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, 1, 0
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s9, v0
+; GISEL-IEEE-NEXT: s_add_i32 s10, s9, -1
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s10
+; GISEL-IEEE-NEXT: s_add_i32 s11, s9, 1
+; GISEL-IEEE-NEXT: v_fma_f32 v1, -v1, v0, s8
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, s11
+; GISEL-IEEE-NEXT: v_fma_f32 v0, -v4, v0, s8
+; GISEL-IEEE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v1
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s9, s10, s9
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, s11, s9
+; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, s4, v2
+; GISEL-IEEE-NEXT: v_readfirstlane_b32 s5, v0
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s7, 0
+; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, s8, v3
+; GISEL-IEEE-NEXT: v_bfrev_b32_e32 v0, 1
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, s5, s4
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_nge_f32_e32 vcc, s2, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s7, s8, s7
+; GISEL-IEEE-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-IEEE-NEXT: v_cmp_nge_f32_e32 vcc, s3, v0
+; GISEL-IEEE-NEXT: s_cselect_b32 s4, 1, 0
+; GISEL-IEEE-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-IEEE-NEXT: s_cselect_b32 s3, 1, 0
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s4, 0
+; GISEL-IEEE-NEXT: s_cselect_b32 s2, 0x7fc00000, s6
+; GISEL-IEEE-NEXT: s_cmp_lg_u32 s3, 0
+; GISEL-IEEE-NEXT: s_cselect_b32 s3, 0x7fc00000, s7
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-IEEE-NEXT: s_mov_b32 s2, -1
+; GISEL-IEEE-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-IEEE-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GISEL-IEEE-NEXT: s_endpgm
;
; SDAG-DAZ-LABEL: elim_redun_check_v2_ult:
@@ -4695,52 +4849,67 @@ define amdgpu_kernel void @elim_redun_check_v2_ult(ptr addrspace(1) %out, <2 x f
;
; GISEL-DAZ-LABEL: elim_redun_check_v2_ult:
; GISEL-DAZ: ; %bb.0: ; %entry
-; GISEL-DAZ-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
+; GISEL-DAZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, 0xf800000
; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GISEL-DAZ-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, s6
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, s6, v1
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v3, v2
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v4, s7
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s7, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v5, v2, v3
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, 0.5, v3
-; GISEL-DAZ-NEXT: v_fma_f32 v6, -v3, v5, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v5, v5, v6, v5
-; GISEL-DAZ-NEXT: v_fma_f32 v3, v3, v6, v3
-; GISEL-DAZ-NEXT: v_fma_f32 v6, -v5, v5, v2
-; GISEL-DAZ-NEXT: v_fma_f32 v3, v6, v3, v5
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v5, 0x37800000, v3
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GISEL-DAZ-NEXT: v_rsq_f32_e32 v1, v0
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v4, 0x260
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e64 s[0:1], v2, v4
-; GISEL-DAZ-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[0:1]
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, v0, v1
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v5, -v1, v3, 0.5
-; GISEL-DAZ-NEXT: v_fma_f32 v3, v3, v5, v3
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v5, v1
-; GISEL-DAZ-NEXT: v_fma_f32 v5, -v3, v3, v0
-; GISEL-DAZ-NEXT: v_fma_f32 v1, v5, v1, v3
-; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, 0x37800000, v1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v4
-; GISEL-DAZ-NEXT: v_bfrev_b32_e32 v3, 1
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
-; GISEL-DAZ-NEXT: v_mov_b32_e32 v4, 0x7fc00000
-; GISEL-DAZ-NEXT: v_cmp_nge_f32_e32 vcc, s6, v3
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
-; GISEL-DAZ-NEXT: v_cmp_nge_f32_e32 vcc, s7, v3
-; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GISEL-DAZ-NEXT: s_mov_b32 s6, -1
-; GISEL-DAZ-NEXT: s_mov_b32 s7, 0xf000
-; GISEL-DAZ-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, s2, v1
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s4, v2
+; GISEL-DAZ-NEXT: s_cselect_b32 s6, s4, s2
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v2, s6
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, s6, v2
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0.5, v2
+; GISEL-DAZ-NEXT: v_fma_f32 v4, -v2, v3, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v3, v3, v4, v3
+; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v4, v2
+; GISEL-DAZ-NEXT: v_fma_f32 v4, -v3, v3, s6
+; GISEL-DAZ-NEXT: v_fma_f32 v2, v4, v2, v3
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s4, v2
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v2
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s5, v2
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v2, 0x260
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s6, v2
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s5, s4
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s6, s6, s7
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, s3, v1
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s4, s3
+; GISEL-DAZ-NEXT: v_rsq_f32_e32 v0, s7
+; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, s7, v2
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, s7, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0.5, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v3, -v0, v1, 0.5
+; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v3, v1
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v0, v3, v0
+; GISEL-DAZ-NEXT: v_fma_f32 v3, -v1, v1, s7
+; GISEL-DAZ-NEXT: v_fma_f32 v0, v3, v0, v1
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-DAZ-NEXT: v_mul_f32_e32 v0, 0x37800000, v0
+; GISEL-DAZ-NEXT: v_readfirstlane_b32 s5, v0
+; GISEL-DAZ-NEXT: v_bfrev_b32_e32 v0, 1
+; GISEL-DAZ-NEXT: s_cselect_b32 s8, s5, s4
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_nge_f32_e32 vcc, s2, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s7, s7, s8
+; GISEL-DAZ-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GISEL-DAZ-NEXT: v_cmp_nge_f32_e32 vcc, s3, v0
+; GISEL-DAZ-NEXT: s_cselect_b32 s4, 1, 0
+; GISEL-DAZ-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GISEL-DAZ-NEXT: s_cselect_b32 s3, 1, 0
+; GISEL-DAZ-NEXT: s_cmp_lg_u32 s4, 0
+; GISEL-DAZ-NEXT: s_cselect_b32 s2, 0x7fc00000, s6
+; GISEL-DAZ-NEXT: s_cmp_lg_u32 s3, 0
+; GISEL-DAZ-NEXT: s_cselect_b32 s3, 0x7fc00000, s7
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-DAZ-NEXT: s_mov_b32 s2, -1
+; GISEL-DAZ-NEXT: s_mov_b32 s3, 0xf000
+; GISEL-DAZ-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GISEL-DAZ-NEXT: s_endpgm
entry:
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
index 185e5bab702c4..cf193035c9d05 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
@@ -1,12 +1,43 @@
-; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-GISEL %s
declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a)
-; GCN-LABEL: {{^}}frexp_exp_f16
-; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
-; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
-; GCN: buffer_store_short v[[R_I16]]
define amdgpu_kernel void @frexp_exp_f16(
+; VI-SDAG-LABEL: frexp_exp_f16:
+; VI-SDAG: ; %bb.0: ; %entry
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; VI-SDAG-NEXT: s_mov_b32 s6, -1
+; VI-SDAG-NEXT: s_mov_b32 s10, s6
+; VI-SDAG-NEXT: s_mov_b32 s11, s7
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s8, s2
+; VI-SDAG-NEXT: s_mov_b32 s9, s3
+; VI-SDAG-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; VI-SDAG-NEXT: s_mov_b32 s4, s0
+; VI-SDAG-NEXT: s_mov_b32 s5, s1
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
+; VI-SDAG-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; VI-SDAG-NEXT: buffer_store_short v0, off, s[4:7], 0
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: frexp_exp_f16:
+; VI-GISEL: ; %bb.0: ; %entry
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: s_mov_b32 s6, -1
+; VI-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
+; VI-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: v_frexp_exp_i16_f16_e32 v0, s2
+; VI-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
+; VI-GISEL-NEXT: s_nop 2
+; VI-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; VI-GISEL-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
@@ -16,12 +47,44 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}frexp_exp_f16_sext
-; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
-; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
-; VI: v_bfe_i32 v[[R_I32:[0-9]+]], v[[R_I16]], 0, 16{{$}}
-; GCN: buffer_store_dword v[[R_I32]]
define amdgpu_kernel void @frexp_exp_f16_sext(
+; VI-SDAG-LABEL: frexp_exp_f16_sext:
+; VI-SDAG: ; %bb.0: ; %entry
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; VI-SDAG-NEXT: s_mov_b32 s6, -1
+; VI-SDAG-NEXT: s_mov_b32 s10, s6
+; VI-SDAG-NEXT: s_mov_b32 s11, s7
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s8, s2
+; VI-SDAG-NEXT: s_mov_b32 s9, s3
+; VI-SDAG-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; VI-SDAG-NEXT: s_mov_b32 s4, s0
+; VI-SDAG-NEXT: s_mov_b32 s5, s1
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
+; VI-SDAG-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; VI-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 16
+; VI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: frexp_exp_f16_sext:
+; VI-GISEL: ; %bb.0: ; %entry
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: s_mov_b32 s6, -1
+; VI-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
+; VI-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: v_frexp_exp_i16_f16_e32 v0, s2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: s_sext_i32_i16 s2, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
+; VI-GISEL-NEXT: s_nop 1
+; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-GISEL-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
@@ -32,11 +95,43 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}frexp_exp_f16_zext
-; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
-; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
-; GCN: buffer_store_dword v[[R_I16]]
define amdgpu_kernel void @frexp_exp_f16_zext(
+; VI-SDAG-LABEL: frexp_exp_f16_zext:
+; VI-SDAG: ; %bb.0: ; %entry
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; VI-SDAG-NEXT: s_mov_b32 s6, -1
+; VI-SDAG-NEXT: s_mov_b32 s10, s6
+; VI-SDAG-NEXT: s_mov_b32 s11, s7
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s8, s2
+; VI-SDAG-NEXT: s_mov_b32 s9, s3
+; VI-SDAG-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; VI-SDAG-NEXT: s_mov_b32 s4, s0
+; VI-SDAG-NEXT: s_mov_b32 s5, s1
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
+; VI-SDAG-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; VI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: frexp_exp_f16_zext:
+; VI-GISEL: ; %bb.0: ; %entry
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: s_mov_b32 s6, -1
+; VI-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
+; VI-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: v_frexp_exp_i16_f16_e32 v0, s2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: s_and_b32 s2, 0xffff, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
+; VI-GISEL-NEXT: s_nop 1
+; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-GISEL-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
@@ -46,3 +141,20 @@ entry:
store i32 %r.val.zext, ptr addrspace(1) %r
ret void
}
+
+define amdgpu_ps i32 @v_test_frexp_exp_f16(half %src) {
+; VI-SDAG-LABEL: v_test_frexp_exp_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; VI-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; VI-SDAG-NEXT: ; return to shader part epilog
+;
+; VI-GISEL-LABEL: v_test_frexp_exp_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; VI-GISEL-NEXT: ; return to shader part epilog
+ %frexp.exp = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %src)
+ %frexp.exp.zext = zext i16 %frexp.exp to i32
+ ret i32 %frexp.exp.zext
+}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
index 7356b7a42394a..daabf5c40ea4c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
@@ -1,5 +1,8 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX6-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX6-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX8-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX8-GISEL %s
declare float @llvm.fabs.f32(float) #0
declare float @llvm.copysign.f32(float, float) #0
@@ -7,26 +10,149 @@ declare double @llvm.fabs.f64(double) #0
declare i32 @llvm.amdgcn.frexp.exp.i32.f32(float) #0
declare i32 @llvm.amdgcn.frexp.exp.i32.f64(double) #0
-; GCN-LABEL: {{^}}s_test_frexp_exp_f32:
-; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
define amdgpu_kernel void @s_test_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
+; GFX6-SDAG-LABEL: s_test_frexp_exp_f32:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
+; GFX6-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX6-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX6-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-SDAG-NEXT: s_endpgm
+;
+; GFX6-GISEL-LABEL: s_test_frexp_exp_f32:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
+; GFX6-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, s3
+; GFX6-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-GISEL-NEXT: s_endpgm
+;
+; GFX8-SDAG-LABEL: s_test_frexp_exp_f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: s_test_frexp_exp_f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, s3
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %src)
store i32 %frexp.exp, ptr addrspace(1) %out
ret void
}
-; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f32:
-; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
define amdgpu_kernel void @s_test_fabs_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
+; GFX6-SDAG-LABEL: s_test_fabs_frexp_exp_f32:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
+; GFX6-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX6-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX6-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-SDAG-NEXT: s_endpgm
+;
+; GFX6-GISEL-LABEL: s_test_fabs_frexp_exp_f32:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
+; GFX6-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e64 v0, |s3|
+; GFX6-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-GISEL-NEXT: s_endpgm
+;
+; GFX8-SDAG-LABEL: s_test_fabs_frexp_exp_f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: s_test_fabs_frexp_exp_f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f32_e64 v0, |s3|
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
%fabs.src = call float @llvm.fabs.f32(float %src)
%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fabs.src)
store i32 %frexp.exp, ptr addrspace(1) %out
ret void
}
-; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f32:
-; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
+; GFX6-SDAG-LABEL: s_test_fneg_fabs_frexp_exp_f32:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
+; GFX6-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX6-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX6-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-SDAG-NEXT: s_endpgm
+;
+; GFX6-GISEL-LABEL: s_test_fneg_fabs_frexp_exp_f32:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
+; GFX6-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e64 v0, -|s3|
+; GFX6-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-GISEL-NEXT: s_endpgm
+;
+; GFX8-SDAG-LABEL: s_test_fneg_fabs_frexp_exp_f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX8-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: s_test_fneg_fabs_frexp_exp_f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX8-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f32_e64 v0, -|s3|
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
%fabs.src = call float @llvm.fabs.f32(float %src)
%fneg.fabs.src = fneg float %fabs.src
%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fneg.fabs.src)
@@ -34,35 +160,197 @@ define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f32(ptr addrspace(1) %out,
ret void
}
-; GCN-LABEL: {{^}}s_test_copysign_frexp_exp_f32:
-; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
define amdgpu_kernel void @s_test_copysign_frexp_exp_f32(ptr addrspace(1) %out, float %src, float %sign) #1 {
+; GFX6-SDAG-LABEL: s_test_copysign_frexp_exp_f32:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
+; GFX6-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, s4
+; GFX6-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-SDAG-NEXT: s_endpgm
+;
+; GFX6-GISEL-LABEL: s_test_copysign_frexp_exp_f32:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: s_and_b32 s4, s2, 0x7fffffff
+; GFX6-GISEL-NEXT: s_and_b32 s3, s3, 0x80000000
+; GFX6-GISEL-NEXT: s_or_b32 s4, s4, s3
+; GFX6-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, s4
+; GFX6-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-GISEL-NEXT: s_endpgm
+;
+; GFX8-SDAG-LABEL: s_test_copysign_frexp_exp_f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, s4
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: s_test_copysign_frexp_exp_f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: s_and_b32 s4, s2, 0x7fffffff
+; GFX8-GISEL-NEXT: s_and_b32 s3, s3, 0x80000000
+; GFX8-GISEL-NEXT: s_or_b32 s4, s4, s3
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, s4
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
%copysign = call float @llvm.copysign.f32(float %src, float %sign)
%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %copysign)
store i32 %frexp.exp, ptr addrspace(1) %out
ret void
}
-; GCN-LABEL: {{^}}s_test_frexp_exp_f64:
-; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @s_test_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
+; GFX6-SDAG-LABEL: s_test_frexp_exp_f64:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX6-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, s[2:3]
+; GFX6-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX6-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX6-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-SDAG-NEXT: s_endpgm
+;
+; GFX6-GISEL-LABEL: s_test_frexp_exp_f64:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f64_e32 v0, s[2:3]
+; GFX6-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX6-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-GISEL-NEXT: s_endpgm
+;
+; GFX8-SDAG-LABEL: s_test_frexp_exp_f64:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, s[2:3]
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: s_test_frexp_exp_f64:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f64_e32 v0, s[2:3]
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %src)
store i32 %frexp.exp, ptr addrspace(1) %out
ret void
}
-; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f64:
-; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @s_test_fabs_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
+; GFX6-SDAG-LABEL: s_test_fabs_frexp_exp_f64:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX6-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, s[2:3]
+; GFX6-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX6-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX6-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-SDAG-NEXT: s_endpgm
+;
+; GFX6-GISEL-LABEL: s_test_fabs_frexp_exp_f64:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f64_e64 v0, |s[2:3]|
+; GFX6-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX6-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-GISEL-NEXT: s_endpgm
+;
+; GFX8-SDAG-LABEL: s_test_fabs_frexp_exp_f64:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, s[2:3]
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: s_test_fabs_frexp_exp_f64:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f64_e64 v0, |s[2:3]|
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
%fabs.src = call double @llvm.fabs.f64(double %src)
%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fabs.src)
store i32 %frexp.exp, ptr addrspace(1) %out
ret void
}
-; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f64:
-; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
+; GFX6-SDAG-LABEL: s_test_fneg_fabs_frexp_exp_f64:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX6-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, s[2:3]
+; GFX6-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX6-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX6-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-SDAG-NEXT: s_endpgm
+;
+; GFX6-GISEL-LABEL: s_test_fneg_fabs_frexp_exp_f64:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f64_e64 v0, -|s[2:3]|
+; GFX6-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX6-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-GISEL-NEXT: s_endpgm
+;
+; GFX8-SDAG-LABEL: s_test_fneg_fabs_frexp_exp_f64:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, s[2:3]
+; GFX8-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-SDAG-NEXT: s_mov_b32 s2, -1
+; GFX8-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-SDAG-NEXT: s_endpgm
+;
+; GFX8-GISEL-LABEL: s_test_fneg_fabs_frexp_exp_f64:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f64_e64 v0, -|s[2:3]|
+; GFX8-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX8-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-GISEL-NEXT: s_endpgm
%fabs.src = call double @llvm.fabs.f64(double %src)
%fneg.fabs.src = fneg double %fabs.src
%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fneg.fabs.src)
@@ -70,5 +358,61 @@ define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f64(ptr addrspace(1) %out,
ret void
}
+define amdgpu_ps i32 @v_test_frexp_exp_f32(float %src) {
+; GFX6-SDAG-LABEL: v_test_frexp_exp_f32:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX6-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX6-GISEL-LABEL: v_test_frexp_exp_f32:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX6-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX8-SDAG-LABEL: v_test_frexp_exp_f32:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX8-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX8-GISEL-LABEL: v_test_frexp_exp_f32:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-GISEL-NEXT: ; return to shader part epilog
+ %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %src)
+ ret i32 %frexp.exp
+}
+
+define amdgpu_ps i32 @v_test_frexp_exp_f64(double %src) {
+; GFX6-SDAG-LABEL: v_test_frexp_exp_f64:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX6-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX6-GISEL-LABEL: v_test_frexp_exp_f64:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX6-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX8-SDAG-LABEL: v_test_frexp_exp_f64:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX8-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX8-GISEL-LABEL: v_test_frexp_exp_f64:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX8-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-GISEL-NEXT: ; return to shader part epilog
+ %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %src)
+ ret i32 %frexp.exp
+}
+
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
index e239f37a8c055..456b76a4dcec6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
@@ -7,13 +7,13 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define { half, i32 } @test_frexp_f16_i32(half %a) {
; GFX6-SDAG-LABEL: test_frexp_f16_i32:
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