[llvm] [AArch64][GlobalISel] Add handling for cls intrinsic (PR #200440)

[Joshua Rodriguez via llvm-commits]

https://github.com/JoshdRod updated https://github.com/llvm/llvm-project/pull/200440

>From 473c00533ac0102239c5c88f6c1c6da966277fed Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Fri, 29 May 2026 15:59:09 +0000
Subject: [PATCH 1/2] [AArch64][GlobalISel] Add handling for cls intrinsic

Neon intrinsic neon.cls wasn't linked to the generic node G_CTLS, which wasn't linked to AArch64 specific SDAG node ctls.
Add in these links to allow the intrinsic to properly lower.
---
 llvm/lib/Target/AArch64/AArch64InstrGISel.td           | 2 ++
 llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 ++
 llvm/test/CodeGen/AArch64/arm64-vcnt.ll                | 1 +
 3 files changed, 5 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index ec95448f61043..b4d04f428bcd2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -355,6 +355,8 @@ def : GINodeEquiv<G_AARCH64_RANGE_PREFETCH, AArch64RangePrefetch>;
 
 def : GINodeEquiv<G_FPTRUNC_ODD, AArch64fcvtxn_n>;
 
+def : GINodeEquiv<G_CTLS, ctls>;
+
 // These are patterns that we only use for GlobalISel via the importer.
 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
                      (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 6092f63fcde72..78c2268aac986 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -2106,6 +2106,8 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
     return LowerUnaryOp(TargetOpcode::G_FPTOUI_SAT);
   case Intrinsic::aarch64_neon_fcvtzs:
     return LowerUnaryOp(TargetOpcode::G_FPTOSI_SAT);
+  case Intrinsic::aarch64_neon_cls:
+    return LowerUnaryOp(TargetOpcode::G_CTLS);
 
   case Intrinsic::vector_reverse:
     // TODO: Add support for vector_reverse
diff --git a/llvm/test/CodeGen/AArch64/arm64-vcnt.ll b/llvm/test/CodeGen/AArch64/arm64-vcnt.ll
index f2113d45589b3..c5ef62293c25a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vcnt.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vcnt.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s
 
 define <8 x i8> @cls_8b(ptr %A) nounwind {
 ;CHECK-LABEL: cls_8b:

>From 9bec3bbd6d49a1f65a58d55d68f880306eb9db60 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 2 Jun 2026 13:11:50 +0000
Subject: [PATCH 2/2] [AArch64][GlobalISel] Remove duplicate GI node
 equivalence statement

The generic opcode G_CTLS is already defined as equivalent to the SDAG node ctls in a generic SelectionDAGCompat file.
Hence, we can remove this AArch64-specific duplicate definition.
---
 llvm/lib/Target/AArch64/AArch64InstrGISel.td | 1 -
 1 file changed, 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index b4d04f428bcd2..9c646c43cdcbf 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -355,7 +355,6 @@ def : GINodeEquiv<G_AARCH64_RANGE_PREFETCH, AArch64RangePrefetch>;
 
 def : GINodeEquiv<G_FPTRUNC_ODD, AArch64fcvtxn_n>;
 
-def : GINodeEquiv<G_CTLS, ctls>;
 
 // These are patterns that we only use for GlobalISel via the importer.
 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),