[llvm] 4b212e5 - [VPlan] Propagate interleave-group metadata to narrowed wide load/store. (#199356)

[via llvm-commits]

Author: Florian Hahn
Date: 2026-06-02T09:41:28Z
New Revision: 4b212e5418097e31b13ab51dd9574c8cc6a3fdab

URL: https://github.com/llvm/llvm-project/commit/4b212e5418097e31b13ab51dd9574c8cc6a3fdab
DIFF: https://github.com/llvm/llvm-project/commit/4b212e5418097e31b13ab51dd9574c8cc6a3fdab.diff

LOG: [VPlan] Propagate interleave-group metadata to narrowed wide load/store. (#199356)

VPInterleaveRecipe now carries the common metadata valid for all members
and as such hold for any member. Propagate it to narrowed load and
stores.

PR: https://github.com/llvm/llvm-project/pull/199356

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 60d1c70393dc3..3ed50e27c8534 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -5528,7 +5528,7 @@ narrowInterleaveGroupOp(VPValue *V, SmallPtrSetImpl<VPValue *> &NarrowedOps) {
     auto *LI = cast<LoadInst>(LoadGroup->getInterleaveGroup()->getInsertPos());
     auto *L = new VPWidenLoadRecipe(*LI, LoadGroup->getAddr(),
                                     LoadGroup->getMask(), /*Consecutive=*/true,
-                                    {}, LoadGroup->getDebugLoc());
+                                    *LoadGroup, LoadGroup->getDebugLoc());
     L->insertBefore(LoadGroup);
     NarrowedOps.insert(L);
     return L;
@@ -5690,7 +5690,7 @@ VPlanTransforms::narrowInterleaveGroups(VPlan &Plan,
     auto *SI =
         cast<StoreInst>(StoreGroup->getInterleaveGroup()->getInsertPos());
     auto *S = new VPWidenStoreRecipe(*SI, StoreGroup->getAddr(), Res, nullptr,
-                                     /*Consecutive=*/true, {},
+                                     /*Consecutive=*/true, *StoreGroup,
                                      StoreGroup->getDebugLoc());
     S->insertBefore(StoreGroup);
     StoreGroup->eraseFromParent();

diff  --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll
index 9b9da8c18fe2a..782665b9a1768 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll
@@ -47,8 +47,7 @@ exit:
   ret void
 }
 
-; All members share !tbaa !2.
-; FIXME: the narrowed wide load/store should preserve it.
+; All members share !tbaa !2. The narrowed wide load/store preserve it.
 define void @load_store_interleave_group_with_shared_metadata(ptr noalias %data) {
 ; VF2-LABEL: define void @load_store_interleave_group_with_shared_metadata(
 ; VF2-SAME: ptr noalias [[DATA:%.*]]) {
@@ -60,11 +59,11 @@ define void @load_store_interleave_group_with_shared_metadata(ptr noalias %data)
 ; VF2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
 ; VF2-NEXT:    [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1
 ; VF2-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP0]]
-; VF2-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP1]], align 8
-; VF2-NEXT:    store <2 x i64> [[WIDE_LOAD]], ptr [[TMP1]], align 8
+; VF2-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP1]], align 8, !tbaa [[TBAA3:![0-9]+]]
+; VF2-NEXT:    store <2 x i64> [[WIDE_LOAD]], ptr [[TMP1]], align 8, !tbaa [[TBAA3]]
 ; VF2-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
 ; VF2-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
-; VF2-NEXT:    br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF2-NEXT:    br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
 ; VF2:       [[MIDDLE_BLOCK]]:
 ; VF2-NEXT:    br label %[[EXIT:.*]]
 ; VF2:       [[EXIT]]:
@@ -102,5 +101,9 @@ exit:
 ; VF2: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
 ; VF2: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
 ; VF2: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; VF2: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}
+; VF2: [[TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0, i64 0}
+; VF2: [[META4]] = !{!"A", [[META5:![0-9]+]]}
+; VF2: [[META5]] = !{!"omnipotent char", [[META6:![0-9]+]], i64 0}
+; VF2: [[META6]] = !{!"Simple C/C++ TBAA"}
+; VF2: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}
 ;.