[llvm] [SelectionDAG] Look through ISD::FREEZE in SimplifyDemanded checks (PR #200931)

[Simon Pilgrim via llvm-commits]

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@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+f16c \
+; RUN:   -stop-after=x86-isel < %s | FileCheck %s --check-prefix=COMBINE
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+f16c \
+; RUN:   -combiner-disabled -stop-after=x86-isel < %s | FileCheck %s \
+; RUN:   --check-prefix=NOCOMBINE
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RKSimon wrote:

this isn't the typical way we test combines - why are you doing it this way? why not a regular ll or mir test?

https://github.com/llvm/llvm-project/pull/200931