[llvm] [AArch64][SME] Add multi-vector store/load opcodes to getMemOpInfo (PR #201073)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 2 02:18:28 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Benjamin Maxwell (MacDue)
<details>
<summary>Changes</summary>
Follow-up to #<!-- -->200238
---
Patch is 55.94 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/201073.diff
2 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+112)
- (modified) llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir (+667)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index ac7af4ed14119..63cdaa9c44850 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -3190,6 +3190,62 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) {
case AArch64::LD1H_4Z_IMM_PSEUDO:
case AArch64::LD1W_4Z_IMM_PSEUDO:
case AArch64::LD1D_4Z_IMM_PSEUDO:
+ case AArch64::ST1B_2Z_IMM:
+ case AArch64::ST1B_2Z_STRIDED_IMM:
+ case AArch64::ST1H_2Z_IMM:
+ case AArch64::ST1H_2Z_STRIDED_IMM:
+ case AArch64::ST1W_2Z_IMM:
+ case AArch64::ST1W_2Z_STRIDED_IMM:
+ case AArch64::ST1D_2Z_IMM:
+ case AArch64::ST1D_2Z_STRIDED_IMM:
+ case AArch64::LDNT1B_2Z_IMM_PSEUDO:
+ case AArch64::LDNT1B_2Z_IMM:
+ case AArch64::LDNT1B_2Z_STRIDED_IMM:
+ case AArch64::LDNT1H_2Z_IMM_PSEUDO:
+ case AArch64::LDNT1H_2Z_IMM:
+ case AArch64::LDNT1H_2Z_STRIDED_IMM:
+ case AArch64::LDNT1W_2Z_IMM_PSEUDO:
+ case AArch64::LDNT1W_2Z_IMM:
+ case AArch64::LDNT1W_2Z_STRIDED_IMM:
+ case AArch64::LDNT1D_2Z_IMM_PSEUDO:
+ case AArch64::LDNT1D_2Z_IMM:
+ case AArch64::LDNT1D_2Z_STRIDED_IMM:
+ case AArch64::STNT1B_2Z_IMM:
+ case AArch64::STNT1B_2Z_STRIDED_IMM:
+ case AArch64::STNT1H_2Z_IMM:
+ case AArch64::STNT1H_2Z_STRIDED_IMM:
+ case AArch64::STNT1W_2Z_IMM:
+ case AArch64::STNT1W_2Z_STRIDED_IMM:
+ case AArch64::STNT1D_2Z_IMM:
+ case AArch64::STNT1D_2Z_STRIDED_IMM:
+ case AArch64::ST1B_4Z_IMM:
+ case AArch64::ST1B_4Z_STRIDED_IMM:
+ case AArch64::ST1H_4Z_IMM:
+ case AArch64::ST1H_4Z_STRIDED_IMM:
+ case AArch64::ST1W_4Z_IMM:
+ case AArch64::ST1W_4Z_STRIDED_IMM:
+ case AArch64::ST1D_4Z_IMM:
+ case AArch64::ST1D_4Z_STRIDED_IMM:
+ case AArch64::LDNT1B_4Z_IMM_PSEUDO:
+ case AArch64::LDNT1B_4Z_IMM:
+ case AArch64::LDNT1B_4Z_STRIDED_IMM:
+ case AArch64::LDNT1H_4Z_IMM_PSEUDO:
+ case AArch64::LDNT1H_4Z_IMM:
+ case AArch64::LDNT1H_4Z_STRIDED_IMM:
+ case AArch64::LDNT1W_4Z_IMM_PSEUDO:
+ case AArch64::LDNT1W_4Z_IMM:
+ case AArch64::LDNT1W_4Z_STRIDED_IMM:
+ case AArch64::LDNT1D_4Z_IMM_PSEUDO:
+ case AArch64::LDNT1D_4Z_IMM:
+ case AArch64::LDNT1D_4Z_STRIDED_IMM:
+ case AArch64::STNT1B_4Z_IMM:
+ case AArch64::STNT1B_4Z_STRIDED_IMM:
+ case AArch64::STNT1H_4Z_IMM:
+ case AArch64::STNT1H_4Z_STRIDED_IMM:
+ case AArch64::STNT1W_4Z_IMM:
+ case AArch64::STNT1W_4Z_STRIDED_IMM:
+ case AArch64::STNT1D_4Z_IMM:
+ case AArch64::STNT1D_4Z_STRIDED_IMM:
return 3;
case AArch64::LDPDpost:
case AArch64::LDPDpre:
@@ -4892,6 +4948,34 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
case AArch64::LD1H_2Z_IMM_PSEUDO:
case AArch64::LD1W_2Z_IMM_PSEUDO:
case AArch64::LD1D_2Z_IMM_PSEUDO:
+ case AArch64::ST1B_2Z_IMM:
+ case AArch64::ST1B_2Z_STRIDED_IMM:
+ case AArch64::ST1H_2Z_IMM:
+ case AArch64::ST1H_2Z_STRIDED_IMM:
+ case AArch64::ST1W_2Z_IMM:
+ case AArch64::ST1W_2Z_STRIDED_IMM:
+ case AArch64::ST1D_2Z_IMM:
+ case AArch64::ST1D_2Z_STRIDED_IMM:
+ case AArch64::LDNT1B_2Z_IMM_PSEUDO:
+ case AArch64::LDNT1B_2Z_IMM:
+ case AArch64::LDNT1B_2Z_STRIDED_IMM:
+ case AArch64::LDNT1H_2Z_IMM_PSEUDO:
+ case AArch64::LDNT1H_2Z_IMM:
+ case AArch64::LDNT1H_2Z_STRIDED_IMM:
+ case AArch64::LDNT1W_2Z_IMM_PSEUDO:
+ case AArch64::LDNT1W_2Z_IMM:
+ case AArch64::LDNT1W_2Z_STRIDED_IMM:
+ case AArch64::LDNT1D_2Z_IMM_PSEUDO:
+ case AArch64::LDNT1D_2Z_IMM:
+ case AArch64::LDNT1D_2Z_STRIDED_IMM:
+ case AArch64::STNT1B_2Z_IMM:
+ case AArch64::STNT1B_2Z_STRIDED_IMM:
+ case AArch64::STNT1H_2Z_IMM:
+ case AArch64::STNT1H_2Z_STRIDED_IMM:
+ case AArch64::STNT1W_2Z_IMM:
+ case AArch64::STNT1W_2Z_STRIDED_IMM:
+ case AArch64::STNT1D_2Z_IMM:
+ case AArch64::STNT1D_2Z_STRIDED_IMM:
Scale = TypeSize::getScalable(32);
Width = TypeSize::getScalable(16 * 2);
MinOffset = -8;
@@ -4930,6 +5014,34 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
case AArch64::LD1H_4Z_IMM_PSEUDO:
case AArch64::LD1W_4Z_IMM_PSEUDO:
case AArch64::LD1D_4Z_IMM_PSEUDO:
+ case AArch64::ST1B_4Z_IMM:
+ case AArch64::ST1B_4Z_STRIDED_IMM:
+ case AArch64::ST1H_4Z_IMM:
+ case AArch64::ST1H_4Z_STRIDED_IMM:
+ case AArch64::ST1W_4Z_IMM:
+ case AArch64::ST1W_4Z_STRIDED_IMM:
+ case AArch64::ST1D_4Z_IMM:
+ case AArch64::ST1D_4Z_STRIDED_IMM:
+ case AArch64::LDNT1B_4Z_IMM_PSEUDO:
+ case AArch64::LDNT1B_4Z_IMM:
+ case AArch64::LDNT1B_4Z_STRIDED_IMM:
+ case AArch64::LDNT1H_4Z_IMM_PSEUDO:
+ case AArch64::LDNT1H_4Z_IMM:
+ case AArch64::LDNT1H_4Z_STRIDED_IMM:
+ case AArch64::LDNT1W_4Z_IMM_PSEUDO:
+ case AArch64::LDNT1W_4Z_IMM:
+ case AArch64::LDNT1W_4Z_STRIDED_IMM:
+ case AArch64::LDNT1D_4Z_IMM_PSEUDO:
+ case AArch64::LDNT1D_4Z_IMM:
+ case AArch64::LDNT1D_4Z_STRIDED_IMM:
+ case AArch64::STNT1B_4Z_IMM:
+ case AArch64::STNT1B_4Z_STRIDED_IMM:
+ case AArch64::STNT1H_4Z_IMM:
+ case AArch64::STNT1H_4Z_STRIDED_IMM:
+ case AArch64::STNT1W_4Z_IMM:
+ case AArch64::STNT1W_4Z_STRIDED_IMM:
+ case AArch64::STNT1D_4Z_IMM:
+ case AArch64::STNT1D_4Z_STRIDED_IMM:
Scale = TypeSize::getScalable(64);
Width = TypeSize::getScalable(16 * 4);
MinOffset = -8;
diff --git a/llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir b/llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
index a33dc8d2d1261..1213914f80baa 100644
--- a/llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
+++ b/llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
@@ -27,6 +27,46 @@ body: |
; CHECK-NEXT: $z16_z24 = LD1W_2Z_IMM_PSEUDO renamable $pn8, $sp, 7
; CHECK-NEXT: $z16_z24 = LD1D_2Z_IMM_PSEUDO renamable $pn8, $sp, -8
; CHECK-NEXT: $z16_z24 = LD1D_2Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1B_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1B_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1H_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1H_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1W_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1W_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1D_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1D_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1B_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1B_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1H_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1H_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1W_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1W_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1D_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1D_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: $z16_z24 = LDNT1B_2Z_IMM_PSEUDO renamable $pn8, $sp, -8
+ ; CHECK-NEXT: $z16_z24 = LDNT1B_2Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: $z16_z24 = LDNT1H_2Z_IMM_PSEUDO renamable $pn8, $sp, -8
+ ; CHECK-NEXT: $z16_z24 = LDNT1H_2Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: $z16_z24 = LDNT1W_2Z_IMM_PSEUDO renamable $pn8, $sp, -8
+ ; CHECK-NEXT: $z16_z24 = LDNT1W_2Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: $z16_z24 = LDNT1D_2Z_IMM_PSEUDO renamable $pn8, $sp, -8
+ ; CHECK-NEXT: $z16_z24 = LDNT1D_2Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1B_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1B_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1H_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1H_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1W_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1W_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1D_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1D_2Z_IMM renamable $z16_z17, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1B_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1B_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1H_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1H_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1W_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1W_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1D_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1D_2Z_STRIDED_IMM renamable $z16_z24, renamable $pn8, $sp, 7
; CHECK-NEXT: $z16_z20_z24_z28 = LD1B_4Z_IMM_PSEUDO renamable $pn8, $sp, -8
; CHECK-NEXT: $z16_z20_z24_z28 = LD1B_4Z_IMM_PSEUDO renamable $pn8, $sp, 7
; CHECK-NEXT: $z16_z20_z24_z28 = LD1H_4Z_IMM_PSEUDO renamable $pn8, $sp, -8
@@ -35,6 +75,46 @@ body: |
; CHECK-NEXT: $z16_z20_z24_z28 = LD1W_4Z_IMM_PSEUDO renamable $pn8, $sp, 7
; CHECK-NEXT: $z16_z20_z24_z28 = LD1D_4Z_IMM_PSEUDO renamable $pn8, $sp, -8
; CHECK-NEXT: $z16_z20_z24_z28 = LD1D_4Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1B_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1B_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1H_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1H_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1W_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1W_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1D_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1D_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1B_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1B_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1H_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1H_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1W_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1W_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: ST1D_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: ST1D_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: $z16_z20_z24_z28 = LDNT1B_4Z_IMM_PSEUDO renamable $pn8, $sp, -8
+ ; CHECK-NEXT: $z16_z20_z24_z28 = LDNT1B_4Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: $z16_z20_z24_z28 = LDNT1H_4Z_IMM_PSEUDO renamable $pn8, $sp, -8
+ ; CHECK-NEXT: $z16_z20_z24_z28 = LDNT1H_4Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: $z16_z20_z24_z28 = LDNT1W_4Z_IMM_PSEUDO renamable $pn8, $sp, -8
+ ; CHECK-NEXT: $z16_z20_z24_z28 = LDNT1W_4Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: $z16_z20_z24_z28 = LDNT1D_4Z_IMM_PSEUDO renamable $pn8, $sp, -8
+ ; CHECK-NEXT: $z16_z20_z24_z28 = LDNT1D_4Z_IMM_PSEUDO renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1B_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1B_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1H_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1H_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1W_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1W_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1D_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1D_4Z_IMM renamable $z16_z17_z18_z19, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1B_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1B_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1H_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1H_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1W_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1W_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, 7
+ ; CHECK-NEXT: STNT1D_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, -8
+ ; CHECK-NEXT: STNT1D_4Z_STRIDED_IMM renamable $z16_z20_z24_z28, renamable $pn8, $sp, 7
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 31, implicit $vg
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 1, implicit $vg
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.1)
@@ -51,6 +131,46 @@ body: |
; CHECK-OFFSET-NEXT: ld1w { z16.s, z24.s }, pn8/z, [sp, #14, mul vl]
; CHECK-OFFSET-NEXT: ld1d { z16.d, z24.d }, pn8/z, [sp, #-16, mul vl]
; CHECK-OFFSET-NEXT: ld1d { z16.d, z24.d }, pn8/z, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: st1b { z16.b, z17.b }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: st1b { z16.b, z17.b }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: st1h { z16.h, z17.h }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: st1h { z16.h, z17.h }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: st1w { z16.s, z17.s }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: st1w { z16.s, z17.s }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: st1d { z16.d, z17.d }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: st1d { z16.d, z17.d }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: st1b { z16.b, z24.b }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: st1b { z16.b, z24.b }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: st1h { z16.h, z24.h }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: st1h { z16.h, z24.h }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: st1w { z16.s, z24.s }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: st1w { z16.s, z24.s }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: st1d { z16.d, z24.d }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: st1d { z16.d, z24.d }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1b { z16.b, z24.b }, pn8/z, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1b { z16.b, z24.b }, pn8/z, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1h { z16.h, z24.h }, pn8/z, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1h { z16.h, z24.h }, pn8/z, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1w { z16.s, z24.s }, pn8/z, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1w { z16.s, z24.s }, pn8/z, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1d { z16.d, z24.d }, pn8/z, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1d { z16.d, z24.d }, pn8/z, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1b { z16.b, z17.b }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1b { z16.b, z17.b }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1h { z16.h, z17.h }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1h { z16.h, z17.h }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1w { z16.s, z17.s }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1w { z16.s, z17.s }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1d { z16.d, z17.d }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1d { z16.d, z17.d }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1b { z16.b, z24.b }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1b { z16.b, z24.b }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1h { z16.h, z24.h }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1h { z16.h, z24.h }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1w { z16.s, z24.s }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1w { z16.s, z24.s }, pn8, [sp, #14, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1d { z16.d, z24.d }, pn8, [sp, #-16, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1d { z16.d, z24.d }, pn8, [sp, #14, mul vl]
; CHECK-OFFSET-NEXT: ld1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [sp, #-32, mul vl]
; CHECK-OFFSET-NEXT: ld1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [sp, #28, mul vl]
; CHECK-OFFSET-NEXT: ld1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [sp, #-32, mul vl]
@@ -59,11 +179,52 @@ body: |
; CHECK-OFFSET-NEXT: ld1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [sp, #28, mul vl]
; CHECK-OFFSET-NEXT: ld1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [sp, #-32, mul vl]
; CHECK-OFFSET-NEXT: ld1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: st1b { z16.b - z19.b }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: st1b { z16.b - z19.b }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: st1h { z16.h - z19.h }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: st1h { z16.h - z19.h }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: st1w { z16.s - z19.s }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: st1w { z16.s - z19.s }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: st1d { z16.d - z19.d }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: st1d { z16.d - z19.d }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: st1b { z16.b, z20.b, z24.b, z28.b }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: st1b { z16.b, z20.b, z24.b, z28.b }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: st1h { z16.h, z20.h, z24.h, z28.h }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: st1h { z16.h, z20.h, z24.h, z28.h }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: st1w { z16.s, z20.s, z24.s, z28.s }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: st1w { z16.s, z20.s, z24.s, z28.s }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: st1d { z16.d, z20.d, z24.d, z28.d }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: st1d { z16.d, z20.d, z24.d, z28.d }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: ldnt1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1b { z16.b - z19.b }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1b { z16.b - z19.b }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1h { z16.h - z19.h }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1h { z16.h - z19.h }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1w { z16.s - z19.s }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1w { z16.s - z19.s }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1d { z16.d - z19.d }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1d { z16.d - z19.d }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1b { z16.b, z20.b, z24.b, z28.b }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1b { z16.b, z20.b, z24.b, z28.b }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1h { z16.h, z20.h, z24.h, z28.h }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1h { z16.h, z20.h, z24.h, z28.h }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1w { z16.s, z20.s, z24.s, z28.s }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1w { z16.s, z20.s, z24.s, z28.s }, pn8, [sp, #28, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1d { z16.d, z20.d, z24.d, z28.d }, pn8, [sp, #-32, mul vl]
+ ; CHECK-OFFSET-NEXT: stnt1d { z16.d, z20.d, z24.d, z28.d }, pn8, [sp, #28, mul vl]
; CHECK-OFFSET-NEXT: addvl sp, sp, #31
; CHECK-OFFSET-NEXT: addvl sp, sp, #1
; CHECK-OFFSET-NEXT: ldr x29, [sp], #16
; CHECK-OFFSET-NEXT: ret
+ ; 2x loads
$z16_z24 = LD1B_2Z_IMM_PSEUDO renamable $pn8, %stack.0, -8
$z16_z24 = LD1B_2Z_IMM_PSEUDO renamable $pn8, %stack.0, 7
$z16_z24 = LD1H_2...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/201073
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