[llvm] [PowerPC] Prefer VSX scalar compares over FPU compares for f64 (PR #201022)

[Aditi Medhane via llvm-commits]

https://github.com/AditiRM created https://github.com/llvm/llvm-project/pull/201022

This patch enables VSX scalar compare instructions (`xscmpudp`/`xscmpodp`) for double-precision comparisons on PowerPC targets with P8Vector support, replacing legacy FPU compare instructions (`fcmpu`/`fcmpo`).

## Motivation

**Problem:** Current codegen uses FPU compare instructions which only access 32 FP registers (f0-f31), leading to increased register pressure and spill/reload overhead.

**Solution:** VSX compare instructions access all 64 VSX registers (vs0-vs63), reducing register pressure in register-constrained code.

>From ca9e18f0e73553816517f7386cce68443616ca51 Mon Sep 17 00:00:00 2001
From: AditiRM <aditimedhane73 at gmail.com>
Date: Tue, 2 Jun 2026 06:33:57 +0000
Subject: [PATCH] [PowerPC] Prefer VSX scalar compares over FPU compares for
 f64

---
 llvm/lib/Target/PowerPC/PPCInstrInfo.td     | 13 ++++++++++++
 llvm/test/CodeGen/PowerPC/vsx-cmp-prefer.ll | 22 +++++++++++++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 llvm/test/CodeGen/PowerPC/vsx-cmp-prefer.ll

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index ad976cb317c2c..176868c411546 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4199,6 +4199,19 @@ defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>;
 defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>;
 }
 
+// Prefer VSX scalar compares over FPU compares when P8Vector is available.
+// Both have same cycle counts, but VSX instructions access all 64 VSX registers
+// vs only 32 FP registers, reducing register pressure and avoiding unnecessary copies.
+// Per Power ISA Programming Notes: xscmpudp and xscmpodp can operate on both
+// single-precision and double-precision source operands.
+let Predicates = [HasVSX, HasP8Vector], AddedComplexity = 400 in {
+  // Unordered compares: xscmpudp replaces fcmpu for f64
+  defm : FSetCCPat<any_fsetcc, f64, XSCMPUDP>;
+
+  // Ordered compares: xscmpodp replaces fcmpo for f64
+  defm : FSetCCPat<strict_fsetccs, f64, XSCMPODP>;
+}
+
 // This must be in this file because it relies on patterns defined in this file
 // after the inclusion of the instruction sets.
 let Predicates = [HasSPE] in {
diff --git a/llvm/test/CodeGen/PowerPC/vsx-cmp-prefer.ll b/llvm/test/CodeGen/PowerPC/vsx-cmp-prefer.ll
new file mode 100644
index 0000000000000..8b904e41ba8bf
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vsx-cmp-prefer.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+; Test that VSX scalar compare instructions are preferred over FPU compares
+; when register pressure forces use of VSX registers (VSR32-VSR63).
+
+define signext i32 @test_f64_lt(double %a, double %b) {
+; CHECK-LABEL: test_f64_lt:
+; CHECK:       # %bb.0:
+; CHECK:       #APP
+; CHECK:       #NO_APP
+; CHECK:       xscmpudp
+; CHECK-NOT:   fcmpu
+; CHECK:       blr
+entry:
+  ; Clobber all 32 FP registers to force use of VSX registers
+  call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
+  %cmp = fcmp olt double %a, %b
+  %cond = select i1 %cmp, i32 17, i32 97
+  ret i32 %cond
+}