[llvm] [AMDGPU] Reject named single register inline asm constraints for wider types (PR #200771)

[Arseniy Obolenskiy via llvm-commits]

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@@ -19287,8 +19287,11 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
         }
       }
 
-      // Check for lossy scalar/vector conversions.
-      if (VT.isVector() && VT.getSizeInBits() != 32)
+      // Reject types that do not fit a single 32-bit register: any scalar wider
+      // than 32 bits, or a vector that is not exactly 32 bits.
+      if (VT.SimpleTy != MVT::Other &&
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aobolensk wrote:

Hm, I don't really get it. There is a check `VT.getSizeInBits() != 32` before my changes, so sizes smaller than 32 wereaccepted before and are accepted now (scalar case). Vector case remains unchanged: vector and size == 32 only are rejected now and then

https://github.com/llvm/llvm-project/pull/200771