[llvm] [NVPTX] Respect FTZ flag when lowering atomicrmw fadd. (PR #200732)
Justin Lebar via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 1 20:56:50 PDT 2026
================
@@ -7467,22 +7467,52 @@ NVPTXTargetLowering::AtomicExpansionKind
NVPTXTargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const {
Type *Ty = AI->getValOperand()->getType();
- if (AI->isFloatingPointOperation()) {
- if (AI->getOperation() == AtomicRMWInst::BinOp::FAdd) {
- if (Ty->isHalfTy() && STI.getSmVersion() >= 70 &&
- STI.getPTXVersion() >= 63)
- return AtomicExpansionKind::None;
- if (Ty->isBFloatTy() && STI.getSmVersion() >= 90 &&
- STI.getPTXVersion() >= 78)
- return AtomicExpansionKind::None;
- if (Ty->isFloatTy())
- return AtomicExpansionKind::None;
- if (Ty->isDoubleTy() && STI.hasAtomAddF64())
- return AtomicExpansionKind::None;
+ // Try to lower LLVM atomicrmw fadd to PTX atomic.add. This is complicated
+ // by the weird FTZ behavior PTX atom.add has:
+ // - atom.add.f32 on global memory flushes denormals
+ // - atom.add.f32 on shared memory does not flush denormals
+ // - atom.add.f16 and atomic.add.bf16 never flush denormals
+ //
+ // We lower to atom.add only if the function's FTZ behavior matches that of
+ // atom.add; otherwise, we lower to a CAS loop. But we always allow
+ // atomic.add.bf16; even though it never flushes denormals, we never flush
+ // bf16 denormals when doing regular arithmetic, even when FTZ is enabled.
+ if (AI->isFloatingPointOperation() &&
+ AI->getOperation() == AtomicRMWInst::BinOp::FAdd) {
+ const bool FTZ =
+ AI->getFunction()->getDenormalMode(APFloat::IEEEsingle()).Output ==
+ DenormalMode::PreserveSign;
----------------
jlebar wrote:
I do not think "dynamic" means "anything goes". In any case I would say that a change here should be done as a separate PR.
https://github.com/llvm/llvm-project/pull/200732
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