[llvm] [DAGCombiner] Teach MatchLoadCombine to look through AND masks (PR #200247)

[Craig Topper via llvm-commits]

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@@ -9614,11 +9614,42 @@ calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth,
                        SDByteProvider::getConstantZero())
                  : std::nullopt;
     return calculateByteProvider(NarrowOp, Index, Depth + 1, VectorIndex,
-                                 StartingIndex);
+                                 StartingIndex, ByteMask);
   }
   case ISD::BSWAP:
     return calculateByteProvider(Op->getOperand(0), ByteWidth - Index - 1,
-                                 Depth + 1, VectorIndex, StartingIndex);
+                                 Depth + 1, VectorIndex, StartingIndex,
+                                 ByteMask);
+  case ISD::AND: {
+    unsigned MaskIdx = 1;
+    auto MaskOp = dyn_cast<ConstantSDNode>(Op->getOperand(MaskIdx));
+    if (!MaskOp) {
+      MaskIdx = 0;
+      MaskOp = dyn_cast<ConstantSDNode>(Op->getOperand(MaskIdx));
+      if (!MaskOp)
+        return std::nullopt;
+    }
+
+    uint64_t Mask = MaskOp->getZExtValue();
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topperc wrote:

Is MaskOp guarantee to fit in uint64_t? Do we restrict to i64 or small types somewhere?

https://github.com/llvm/llvm-project/pull/200247