[llvm] 734012d - [RISCV] Disable Zilsd CSR-pair generation when push/pop or save-restore is enabled (#200623)
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Mon Jun 1 19:04:29 PDT 2026
Author: Sudharsan Veeravalli
Date: 2026-06-02T07:34:24+05:30
New Revision: 734012d9897c5b6a9157b8e3a8f8c38dd8ac63f4
URL: https://github.com/llvm/llvm-project/commit/734012d9897c5b6a9157b8e3a8f8c38dd8ac63f4
DIFF: https://github.com/llvm/llvm-project/commit/734012d9897c5b6a9157b8e3a8f8c38dd8ac63f4.diff
LOG: [RISCV] Disable Zilsd CSR-pair generation when push/pop or save-restore is enabled (#200623)
We were generating duplicate/worse code due to the generation of the
`Zilsd` load/store doubles for handling `CSR's` when `Zcmp/Xqccmp` or
`Save/Restore Libcalls` were enabled.
Added:
llvm/test/CodeGen/RISCV/cmp-zilsd-csr.ll
llvm/test/CodeGen/RISCV/saverestore-zilsd-fixed-location.ll
Modified:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 42c0ce94210c8..00c24820e9058 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1690,9 +1690,11 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
// For Zilsd on RV32, append GPRPair registers to the CSR list. This prevents
// the need to create register sets for each abi which is a lot more complex.
// Don't use Zilsd for callee-saved coalescing if the required alignment
- // exceeds the stack alignment.
+ // exceeds the stack alignment or when Zcmp/Xqccmp or save/restore libcalls
+ // are enabled.
bool UseZilsd = !STI.is64Bit() && STI.hasStdExtZilsd() &&
- STI.getZilsdAlign() <= getStackAlign();
+ STI.getZilsdAlign() <= getStackAlign() &&
+ !RVFI->isPushable(MF) && !RVFI->useSaveRestoreLibCalls(MF);
if (UseZilsd) {
SmallVector<MCPhysReg, 32> NewCSRs;
SmallSet<MCPhysReg, 16> CSRSet;
diff --git a/llvm/test/CodeGen/RISCV/cmp-zilsd-csr.ll b/llvm/test/CodeGen/RISCV/cmp-zilsd-csr.ll
new file mode 100644
index 0000000000000..69b801fddbf3b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/cmp-zilsd-csr.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv32 -mattr=+zcmp -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefix=ZCMP
+; RUN: llc -mtriple=riscv32 -mattr=+zcmp,+zilsd -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefix=ZCMP-ZILSD
+; RUN: llc -mtriple=riscv32 -mattr=+xqccmp -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefix=XQCCMP
+; RUN: llc -mtriple=riscv32 -mattr=+xqccmp,+zilsd -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefix=XQCCMP-ZILSD
+
+
+declare i32 @foo()
+declare void @bar()
+
+define void @c_expand_asm_operands(ptr %p, i32 %a) optsize nounwind{
+; ZCMP-LABEL: c_expand_asm_operands:
+; ZCMP: # %bb.0: # %entry
+; ZCMP-NEXT: cm.push {ra, s0-s2}, -16
+; ZCMP-NEXT: addi s0, sp, 16
+; ZCMP-NEXT: cm.mvsa01 s2, s1
+; ZCMP-NEXT: call foo
+; ZCMP-NEXT: addi s1, s1, 15
+; ZCMP-NEXT: andi s1, s1, -16
+; ZCMP-NEXT: sub a0, sp, s1
+; ZCMP-NEXT: mv sp, a0
+; ZCMP-NEXT: sw a0, 0(s2)
+; ZCMP-NEXT: addi sp, s0, -16
+; ZCMP-NEXT: cm.pop {ra, s0-s2}, 16
+; ZCMP-NEXT: tail bar
+;
+; ZCMP-ZILSD-LABEL: c_expand_asm_operands:
+; ZCMP-ZILSD: # %bb.0: # %entry
+; ZCMP-ZILSD-NEXT: cm.push {ra, s0-s2}, -16
+; ZCMP-ZILSD-NEXT: addi s0, sp, 16
+; ZCMP-ZILSD-NEXT: cm.mvsa01 s2, s1
+; ZCMP-ZILSD-NEXT: call foo
+; ZCMP-ZILSD-NEXT: addi s1, s1, 15
+; ZCMP-ZILSD-NEXT: andi s1, s1, -16
+; ZCMP-ZILSD-NEXT: sub a0, sp, s1
+; ZCMP-ZILSD-NEXT: mv sp, a0
+; ZCMP-ZILSD-NEXT: sw a0, 0(s2)
+; ZCMP-ZILSD-NEXT: addi sp, s0, -16
+; ZCMP-ZILSD-NEXT: cm.pop {ra, s0-s2}, 16
+; ZCMP-ZILSD-NEXT: tail bar
+;
+; XQCCMP-LABEL: c_expand_asm_operands:
+; XQCCMP: # %bb.0: # %entry
+; XQCCMP-NEXT: qc.cm.pushfp {ra, s0-s2}, -16
+; XQCCMP-NEXT: qc.cm.mvsa01 s2, s1
+; XQCCMP-NEXT: call foo
+; XQCCMP-NEXT: addi s1, s1, 15
+; XQCCMP-NEXT: andi s1, s1, -16
+; XQCCMP-NEXT: sub a0, sp, s1
+; XQCCMP-NEXT: mv sp, a0
+; XQCCMP-NEXT: sw a0, 0(s2)
+; XQCCMP-NEXT: addi sp, s0, -16
+; XQCCMP-NEXT: qc.cm.pop {ra, s0-s2}, 16
+; XQCCMP-NEXT: tail bar
+;
+; XQCCMP-ZILSD-LABEL: c_expand_asm_operands:
+; XQCCMP-ZILSD: # %bb.0: # %entry
+; XQCCMP-ZILSD-NEXT: qc.cm.pushfp {ra, s0-s2}, -16
+; XQCCMP-ZILSD-NEXT: qc.cm.mvsa01 s2, s1
+; XQCCMP-ZILSD-NEXT: call foo
+; XQCCMP-ZILSD-NEXT: addi s1, s1, 15
+; XQCCMP-ZILSD-NEXT: andi s1, s1, -16
+; XQCCMP-ZILSD-NEXT: sub a0, sp, s1
+; XQCCMP-ZILSD-NEXT: mv sp, a0
+; XQCCMP-ZILSD-NEXT: sw a0, 0(s2)
+; XQCCMP-ZILSD-NEXT: addi sp, s0, -16
+; XQCCMP-ZILSD-NEXT: qc.cm.pop {ra, s0-s2}, 16
+; XQCCMP-ZILSD-NEXT: tail bar
+entry:
+ %call1 = call i32 @foo()
+ %0 = alloca i8, i32 %a, align 8
+ store ptr %0, ptr %p, align 8
+ tail call void @bar()
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/RISCV/saverestore-zilsd-fixed-location.ll b/llvm/test/CodeGen/RISCV/saverestore-zilsd-fixed-location.ll
new file mode 100644
index 0000000000000..ec46ccf478d58
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/saverestore-zilsd-fixed-location.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefix=SR
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore,+zilsd -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefix=SR-ZILSD
+
+define void @fixed_location_sr() nounwind {
+; SR-LABEL: fixed_location_sr:
+; SR: # %bb.0: # %entry
+; SR-NEXT: call t0, __riscv_save_5
+; SR-NEXT: #APP
+; SR-NEXT: #NO_APP
+; SR-NEXT: tail __riscv_restore_5
+;
+; SR-ZILSD-LABEL: fixed_location_sr:
+; SR-ZILSD: # %bb.0: # %entry
+; SR-ZILSD-NEXT: call t0, __riscv_save_5
+; SR-ZILSD-NEXT: #APP
+; SR-ZILSD-NEXT: #NO_APP
+; SR-ZILSD-NEXT: tail __riscv_restore_5
+entry:
+ call void asm sideeffect "", "~{x9},~{x18},~{x19},~{x20}"()
+ ret void
+}
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