[llvm] [AMDGPU] Allow null operands in VImage tensor instructions (PR #200911)
Ryan Mitchell via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 1 15:57:46 PDT 2026
https://github.com/RyanRio updated https://github.com/llvm/llvm-project/pull/200911
>From ffb0affa26b1480a1b6ceda59479bf9c35f485c2 Mon Sep 17 00:00:00 2001
From: Ryan Mitchell <Ryan.Mitchell at amd.com>
Date: Mon, 1 Jun 2026 12:19:59 -0700
Subject: [PATCH 1/2] Allow null operands in VIMage tensor instructions
---
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 6 ++--
llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s | 36 --------------------
2 files changed, 3 insertions(+), 39 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 0f31697f15688..a425e06a7554c 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -2182,9 +2182,9 @@ class VIMAGE_TENSOR_Pseudo<string opName, bit _UpTo2D = 0> :
let hasSideEffects = 0;
bit UpTo2D = _UpTo2D;
- let InOperandList = !if(UpTo2D, (ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, R128A16:$r128, CPol:$cpol),
- (ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, SReg_128_XNULL:$vaddr2,
- SReg_128_XNULL:$vaddr3, R128A16:$r128, CPol:$cpol));
+ let InOperandList = !if(UpTo2D, (ins SReg_128:$vaddr0, SReg_256:$vaddr1, R128A16:$r128, CPol:$cpol),
+ (ins SReg_128:$vaddr0, SReg_256:$vaddr1, SReg_128:$vaddr2,
+ SReg_128:$vaddr3, R128A16:$r128, CPol:$cpol));
string AsmOperands = " $vaddr0, $vaddr1"#!if(UpTo2D, "", ", $vaddr2, $vaddr3")#"$r128$cpol";
}
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
index 2f911ae79c00f..3f8a913b2c458 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
@@ -25,42 +25,6 @@ tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] r128
tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_LOAD_NT_HT scope:SCOPE_DEV
// GFX1250-ERR: :[[@LINE-1]]:59: error: invalid th value for store instructions
-tensor_load_to_lds null, s[4:11]
-// GFX1250-ERR: :[[@LINE-1]]:20: error: invalid operand for instruction
-
-tensor_load_to_lds s[0:3], null
-// GFX1250-ERR: :[[@LINE-1]]:28: error: invalid operand for instruction
-
-tensor_load_to_lds null, s[4:11], s[12:15], s[16:19]
-// GFX1250-ERR: :[[@LINE-1]]:20: error: invalid operand for instruction
-
-tensor_load_to_lds s[0:3], null, s[12:15], s[16:19]
-// GFX1250-ERR: :[[@LINE-1]]:28: error: invalid operand for instruction
-
-tensor_load_to_lds s[0:3], s[4:11], null, s[16:19]
-// GFX1250-ERR: :[[@LINE-1]]:37: error: invalid operand for instruction
-
-tensor_load_to_lds s[0:3], s[4:11], s[12:15], null
-// GFX1250-ERR: :[[@LINE-1]]:47: error: invalid operand for instruction
-
-tensor_store_from_lds null, s[4:11]
-// GFX1250-ERR: :[[@LINE-1]]:23: error: invalid operand for instruction
-
-tensor_store_from_lds s[0:3], null
-// GFX1250-ERR: :[[@LINE-1]]:31: error: invalid operand for instruction
-
-tensor_store_from_lds null, s[4:11], s[12:15], s[16:19]
-// GFX1250-ERR: :[[@LINE-1]]:23: error: invalid operand for instruction
-
-tensor_store_from_lds s[0:3], null, s[12:15], s[16:19]
-// GFX1250-ERR: :[[@LINE-1]]:31: error: invalid operand for instruction
-
-tensor_store_from_lds s[0:3], s[4:11], null, s[16:19]
-// GFX1250-ERR: :[[@LINE-1]]:40: error: invalid operand for instruction
-
-tensor_store_from_lds s[0:3], s[4:11], s[12:15], null
-// GFX1250-ERR: :[[@LINE-1]]:50: error: invalid operand for instruction
-
tensor_load_to_lds s[14:17], s[4:11]
// GFX1250-ERR: :[[@LINE-1]]:20: error: invalid register alignment
>From 3ff2e426990bc2d8035abbde16481a8d2360c549 Mon Sep 17 00:00:00 2001
From: Ryan Mitchell <Ryan.Mitchell at amd.com>
Date: Mon, 1 Jun 2026 15:57:24 -0700
Subject: [PATCH 2/2] only v2-v3 can be null
---
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 4 ++--
llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s | 24 ++++++++++++++++++++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index a425e06a7554c..90764c1a7850b 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -2182,8 +2182,8 @@ class VIMAGE_TENSOR_Pseudo<string opName, bit _UpTo2D = 0> :
let hasSideEffects = 0;
bit UpTo2D = _UpTo2D;
- let InOperandList = !if(UpTo2D, (ins SReg_128:$vaddr0, SReg_256:$vaddr1, R128A16:$r128, CPol:$cpol),
- (ins SReg_128:$vaddr0, SReg_256:$vaddr1, SReg_128:$vaddr2,
+ let InOperandList = !if(UpTo2D, (ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, R128A16:$r128, CPol:$cpol),
+ (ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, SReg_128:$vaddr2,
SReg_128:$vaddr3, R128A16:$r128, CPol:$cpol));
string AsmOperands = " $vaddr0, $vaddr1"#!if(UpTo2D, "", ", $vaddr2, $vaddr3")#"$r128$cpol";
}
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
index 3f8a913b2c458..d9f5b8047e701 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
@@ -25,6 +25,30 @@ tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] r128
tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_LOAD_NT_HT scope:SCOPE_DEV
// GFX1250-ERR: :[[@LINE-1]]:59: error: invalid th value for store instructions
+tensor_load_to_lds null, s[4:11]
+// GFX1250-ERR: :[[@LINE-1]]:20: error: invalid operand for instruction
+
+tensor_load_to_lds s[0:3], null
+// GFX1250-ERR: :[[@LINE-1]]:28: error: invalid operand for instruction
+
+tensor_load_to_lds null, s[4:11], s[12:15], s[16:19]
+// GFX1250-ERR: :[[@LINE-1]]:20: error: invalid operand for instruction
+
+tensor_load_to_lds s[0:3], null, s[12:15], s[16:19]
+// GFX1250-ERR: :[[@LINE-1]]:28: error: invalid operand for instruction
+
+tensor_store_from_lds null, s[4:11]
+// GFX1250-ERR: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+tensor_store_from_lds s[0:3], null
+// GFX1250-ERR: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+tensor_store_from_lds null, s[4:11], s[12:15], s[16:19]
+// GFX1250-ERR: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+tensor_store_from_lds s[0:3], null, s[12:15], s[16:19]
+// GFX1250-ERR: :[[@LINE-1]]:31: error: invalid operand for instruction
+
tensor_load_to_lds s[14:17], s[4:11]
// GFX1250-ERR: :[[@LINE-1]]:20: error: invalid register alignment
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