[llvm] [X86][SSE] Improve ISD::FP_TO_*INT_SAT vector lowering (PR #199416)

[via llvm-commits]

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@@ -22828,8 +22822,89 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
     SDValue Res = DAG.getNode(IsSigned ? X86ISD::CVTTP2IBS : X86ISD::CVTTP2IUBS,
                               dl, VecI16VT, Src);
     return DAG.getNode(ISD::TRUNCATE, dl, DstVT, Res);
-  }
+  } else if (DstVT == MVT::v4i32 && Subtarget.hasSSE2()) {
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Panadulek wrote:

how i understand v8i32 and v16i32 are 256 and 512 bits vectors. And in  SSE2 we have only 128 bits vector. So when we make specialization for SSE2 (AVX is one condition before) when avx isnt avaiable should we care about v8i32 and v16i32? 

https://github.com/llvm/llvm-project/pull/199416