[llvm] [LV] Add test for printing cast flags. (PR #200806)

[Florian Hahn via llvm-commits]

https://github.com/fhahn created https://github.com/llvm/llvm-project/pull/200806

Add test showing missing flags when printing VPInstructionWithType casts.

>From 80b7093881660f894453cf68a5f86103cc4a22a6 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Mon, 1 Jun 2026 11:59:40 +0100
Subject: [PATCH] Add flag printing test

---
 .../VPlan/vplan-printing-flags.ll             | 104 ++++++++++++++++++
 1 file changed, 104 insertions(+)
 create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll

diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
new file mode 100644
index 0000000000000..94b4293965ec1
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
@@ -0,0 +1,104 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "middle.block:" --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 \
+; RUN:     -vplan-print-after=printAfterInitialConstruction -disable-output %s 2>&1 \
+; RUN:   | FileCheck --strict-whitespace %s
+
+define void @cast_flags_mixed(ptr noalias %A, ptr noalias %B) {
+; CHECK-LABEL: VPlan for loop in 'cast_flags_mixed'
+; CHECK:  VPlan ' for UF>=1' {
+; CHECK-NEXT:  Live-in ir<4> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<entry>:
+; CHECK-NEXT:  Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT:  vector.ph:
+; CHECK-NEXT:  Successor(s): loop
+; CHECK-EMPTY:
+; CHECK-NEXT:  loop:
+; CHECK-NEXT:    EMIT-SCALAR ir<%iv> = phi [ ir<0>, vector.ph ], [ ir<%iv.next>, loop ]
+; CHECK-NEXT:    EMIT-SCALAR ir<%zext.nneg> = zext ir<3> to i64
+; CHECK-NEXT:    EMIT ir<%gep.zext> = getelementptr ir<%A>, ir<%zext.nneg>
+; CHECK-NEXT:    EMIT-SCALAR ir<%sext.plain> = sext ir<%iv> to i64
+; CHECK-NEXT:    EMIT ir<%gep.sext> = getelementptr ir<%A>, ir<%sext.plain>
+; CHECK-NEXT:    EMIT-SCALAR ir<%trunc.flags> = trunc ir<3> to i8
+; CHECK-NEXT:    EMIT ir<%gep.trunc> = getelementptr ir<%B>, ir<%trunc.flags>
+; CHECK-NEXT:    EMIT store ir<%gep.sext>, ir<%gep.zext>
+; CHECK-NEXT:    EMIT store ir<0>, ir<%gep.trunc>
+; CHECK-NEXT:    EMIT ir<%iv.next> = add nsw ir<%iv>, ir<1>
+; CHECK-NEXT:    EMIT ir<%ec> = icmp slt ir<%iv.next>, ir<4>
+; CHECK-NEXT:    EMIT vp<[[VP1:%[0-9]+]]> = not ir<%ec>
+; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP1]]>
+; CHECK-NEXT:  Successor(s): middle.block, loop
+; CHECK-EMPTY:
+; CHECK-NEXT:  middle.block:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i16 [ 0, %entry ], [ %iv.next, %loop ]
+  %zext.nneg = zext nneg i16 3 to i64
+  %gep.zext = getelementptr  ptr, ptr %A, i64 %zext.nneg
+  %sext.plain = sext i16 %iv to i64
+  %gep.sext = getelementptr [4 x ptr], ptr %A, i64 %sext.plain
+  %trunc.flags = trunc nuw nsw i16 3 to i8
+  %gep.trunc = getelementptr [4 x i8], ptr %B, i8 %trunc.flags
+  store ptr %gep.sext, ptr %gep.zext
+  store i8 0, ptr %gep.trunc
+  %iv.next = add nsw i16 %iv, 1
+  %ec = icmp slt i16 %iv.next, 4
+  br i1 %ec, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+define void @cast_flags_single(ptr noalias %A, ptr noalias %B) {
+; CHECK-LABEL: VPlan for loop in 'cast_flags_single'
+; CHECK:  VPlan ' for UF>=1' {
+; CHECK-NEXT:  Live-in ir<4> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<entry>:
+; CHECK-NEXT:  Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT:  vector.ph:
+; CHECK-NEXT:  Successor(s): loop
+; CHECK-EMPTY:
+; CHECK-NEXT:  loop:
+; CHECK-NEXT:    EMIT-SCALAR ir<%iv> = phi [ ir<0>, vector.ph ], [ ir<%iv.next>, loop ]
+; CHECK-NEXT:    EMIT-SCALAR ir<%trunc.nuw.only> = trunc ir<3> to i8
+; CHECK-NEXT:    EMIT-SCALAR ir<%trunc.nsw.only> = trunc ir<3> to i8
+; CHECK-NEXT:    EMIT-SCALAR ir<%zext.plain> = zext ir<3> to i64
+; CHECK-NEXT:    EMIT ir<%gep.a> = getelementptr ir<%A>, ir<%iv>
+; CHECK-NEXT:    EMIT ir<%gep.b> = getelementptr ir<%B>, ir<%iv>
+; CHECK-NEXT:    EMIT store ir<%trunc.nuw.only>, ir<%gep.a>
+; CHECK-NEXT:    EMIT store ir<%trunc.nsw.only>, ir<%gep.a>
+; CHECK-NEXT:    EMIT store ir<%zext.plain>, ir<%gep.b>
+; CHECK-NEXT:    EMIT ir<%iv.next> = add nsw ir<%iv>, ir<1>
+; CHECK-NEXT:    EMIT ir<%ec> = icmp slt ir<%iv.next>, ir<4>
+; CHECK-NEXT:    EMIT vp<[[VP1:%[0-9]+]]> = not ir<%ec>
+; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP1]]>
+; CHECK-NEXT:  Successor(s): middle.block, loop
+; CHECK-EMPTY:
+; CHECK-NEXT:  middle.block:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i16 [ 0, %entry ], [ %iv.next, %loop ]
+  %trunc.nuw.only = trunc nuw i16 3 to i8
+  %trunc.nsw.only = trunc nsw i16 3 to i8
+  %zext.plain = zext i16 3 to i64
+  %gep.a = getelementptr i8, ptr %A, i16 %iv
+  %gep.b = getelementptr i64, ptr %B, i16 %iv
+  store i8 %trunc.nuw.only, ptr %gep.a
+  store i8 %trunc.nsw.only, ptr %gep.a
+  store i64 %zext.plain, ptr %gep.b
+  %iv.next = add nsw i16 %iv, 1
+  %ec = icmp slt i16 %iv.next, 4
+  br i1 %ec, label %loop, label %exit
+
+exit:
+  ret void
+}