[llvm] Aarch64 add gisel runlines for zcz tests (PR #200797)
Tomer Shafir via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 1 05:35:20 PDT 2026
https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/200797
Depends on https://github.com/llvm/llvm-project/pull/200645. The first 2 commits are from the base PR.
>From 459c81c6f944304edf16d0067ce73dfe4e19422d Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Thu, 28 May 2026 17:20:17 +0300
Subject: [PATCH 1/3] [AArch64] Fix arm64-zero-cycle-zeroing-fpr.ll check
lines(NFC)
Fix `mov`->`fmov` + add `--match-full-lines` to avoid such a pitfall again.
---
.../AArch64/arm64-zero-cycle-zeroing-fpr.ll | 134 +++++++++---------
1 file changed, 67 insertions(+), 67 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
index ccdaa8779e38f..293faf2405fdd 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
@@ -1,148 +1,148 @@
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-NOZCZ-FPR128
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+fullfp16 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16
-; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+fullfp16 | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+zcz-fpr128 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR128
-; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,FP-WORKAROUND
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR128
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-NOZCZ-FPR128
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+fullfp16 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+fullfp16 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+zcz-fpr128 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR128
+; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s --match-full-lines -check-prefixes=ALL,FP-WORKAROUND
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR128
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
define half @tf16() {
entry:
-; ALL-LABEL: tf16:
-; FP-WORKAROUND: mov s0, wzr
-; NOZCZ-FPR64-NOZCZ-FPR128: mov s0, wzr
-; NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16: mov h0, wzr
-; ZCZ-FPR64: movi d0, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; ALL-LABEL: {{_?}}tf16:{{ *}}{{(;|//)}}{{ *}}@tf16
+; FP-WORKAROUND: fmov s0, wzr
+; NOZCZ-FPR64-NOZCZ-FPR128: fmov s0, wzr
+; NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16: fmov h0, wzr
+; ZCZ-FPR64: movi d0, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret half 0.0
}
define float @tf32() {
entry:
-; ALL-LABEL: tf32:
-; FP-WORKAROUND: mov s0, wzr
-; NOZCZ-FPR64-NOZCZ-FPR128: mov s0, wzr
-; ZCZ-FPR64: movi d0, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; ALL-LABEL: {{_?}}tf32:{{ *}}{{(;|//)}}{{ *}}@tf32
+; FP-WORKAROUND: fmov s0, wzr
+; NOZCZ-FPR64-NOZCZ-FPR128: fmov s0, wzr
+; ZCZ-FPR64: movi d0, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret float 0.0
}
define double @td64() {
entry:
-; ALL-LABEL: td64:
-; FP-WORKAROUND: mov d0, xzr
-; NOZCZ-FPR64-NOZCZ-FPR128: mov d0, xzr
-; ZCZ-FPR64: movi d0, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; ALL-LABEL: {{_?}}td64:{{ *}}{{(;|//)}}{{ *}}@td64
+; FP-WORKAROUND: fmov d0, xzr
+; NOZCZ-FPR64-NOZCZ-FPR128: fmov d0, xzr
+; ZCZ-FPR64: movi d0, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret double 0.0
}
define <8 x i8> @tv8i8() {
entry:
-; ALL-LABEL: tv8i8:
+; ALL-LABEL: {{_?}}tv8i8:{{ *}}{{(;|//)}}{{ *}}@tv8i8
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
}
define <4 x i16> @tv4i16() {
entry:
-; ALL-LABEL: tv4i16:
+; ALL-LABEL: {{_?}}tv4i16:{{ *}}{{(;|//)}}{{ *}}@tv4i16
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <4 x i16> <i16 0, i16 0, i16 0, i16 0>
}
define <2 x i32> @tv2i32() {
entry:
-; ALL-LABEL: tv2i32:
+; ALL-LABEL: {{_?}}tv2i32:{{ *}}{{(;|//)}}{{ *}}@tv2i32
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <2 x i32> <i32 0, i32 0>
}
define <2 x float> @tv2f32() {
entry:
-; ALL-LABEL: tv2f32:
+; ALL-LABEL: {{_?}}tv2f32:{{ *}}{{(;|//)}}{{ *}}@tv2f32
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <2 x float> <float 0.0, float 0.0>
}
define <16 x i8> @tv16i8() {
entry:
-; ALL-LABEL: tv16i8:
+; ALL-LABEL: {{_?}}tv16i8:{{ *}}{{(;|//)}}{{ *}}@tv16i8
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
}
define <8 x i16> @tv8i16() {
entry:
-; ALL-LABEL: tv8i16:
+; ALL-LABEL: {{_?}}tv8i16:{{ *}}{{(;|//)}}{{ *}}@tv8i16
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
}
define <4 x i32> @tv4i32() {
entry:
-; ALL-LABEL: tv4i32:
+; ALL-LABEL: {{_?}}tv4i32:{{ *}}{{(;|//)}}{{ *}}@tv4i32
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <4 x i32> <i32 0, i32 0, i32 0, i32 0>
}
define <2 x i64> @tv2i64() {
entry:
-; ALL-LABEL: tv2i64:
+; ALL-LABEL: {{_?}}tv2i64:{{ *}}{{(;|//)}}{{ *}}@tv2i64
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <2 x i64> <i64 0, i64 0>
}
define <4 x float> @tv4f32() {
entry:
-; ALL-LABEL: tv4f32:
+; ALL-LABEL: {{_?}}tv4f32:{{ *}}{{(;|//)}}{{ *}}@tv4f32
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
}
define <2 x double> @tv2d64() {
entry:
-; ALL-LABEL: tv2d64:
+; ALL-LABEL: {{_?}}tv2d64:{{ *}}{{(;|//)}}{{ *}}@tv2d64
; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
-; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0
-; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0
+; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
+; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
ret <2 x double> <double 0.0, double 0.0>
}
; We used to produce spills+reloads for a Q register with zero cycle zeroing
; enabled.
-; ALL-LABEL: foo:
+; ALL-LABEL: {{_?}}foo:{{ *}}{{(;|//)}}{{ *}}@foo
; ALL-NOT: str q{{[0-9]+}}
; ALL-NOT: ldr q{{[0-9]+}}
define double @foo(i32 %n) {
>From 5191cd72c60b9c8a9619713f2ec227d72ba5ea79 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Sun, 31 May 2026 11:39:05 +0300
Subject: [PATCH 2/3] [AArch64] Align ZCM/ZCZ test strictness(NFC)
---
.../AArch64/arm64-zero-cycle-regmove-fpr.ll | 10 ++---
.../AArch64/arm64-zero-cycle-regmove-fpr8.mir | 10 ++---
.../AArch64/arm64-zero-cycle-regmove-gpr.ll | 10 ++---
.../AArch64/arm64-zero-cycle-zeroing-gpr.ll | 42 +++++++++----------
4 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
index 8980457b8c9e7..ef5ad5029c1b6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-CPU --match-full-lines
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-CPU --match-full-lines
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=CHECK,ZCM-FPR128-CPU --match-full-lines
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 | FileCheck %s -check-prefixes=CHECK,NOZCM-FPR128-ATTR --match-full-lines
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 | FileCheck %s -check-prefixes=CHECK,ZCM-FPR128-ATTR --match-full-lines
+; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-CPU
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-CPU
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=CHECK,ZCM-FPR128-CPU
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 | FileCheck %s --match-full-lines -check-prefixes=CHECK,NOZCM-FPR128-ATTR
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 | FileCheck %s --match-full-lines -check-prefixes=CHECK,ZCM-FPR128-ATTR
define void @zero_cycle_regmove_FPR64(double %a, double %b, double %c, double %d) {
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir
index f8ebc26f5e0ae..22917a89d928a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-fpr8.mir
@@ -1,8 +1,8 @@
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-linux-gnu %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-CPU --match-full-lines
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=generic %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-CPU --match-full-lines
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 %s | FileCheck %s -check-prefixes=ALL,ZCM-FPR128-CPU --match-full-lines
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 %s | FileCheck %s -check-prefixes=ALL,NOZCM-FPR128-ATTR --match-full-lines
-# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 %s | FileCheck %s -check-prefixes=ALL,ZCM-FPR128-ATTR --match-full-lines
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-linux-gnu %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-CPU
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=generic %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-CPU
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCM-FPR128-CPU
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-fpr128 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCM-FPR128-ATTR
+# RUN: llc -o - -run-pass=postrapseudos -mtriple=arm64-apple-macosx -mattr=+zcm-fpr128 %s | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCM-FPR128-ATTR
---
name: zero_cycle_regmove_FPR8
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
index f3a99cb7e83b3..354a89c16b124 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmove-gpr.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOTCPU-LINUX
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOTCPU-APPLE
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,CPU
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-gpr64 | FileCheck %s -check-prefixes=ALL,NOTATTR
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-gpr64 | FileCheck %s -check-prefixes=ALL,ATTR
+; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTCPU-LINUX
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTCPU-APPLE
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=ALL,CPU
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 -mattr=-zcm-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOTATTR
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mattr=+zcm-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,ATTR
define void @zero_cycle_regmove_GPR32(i32 %a, i32 %b, i32 %c, i32 %d) {
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
index 0f284aa9ad282..abfd79e092395 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
@@ -1,44 +1,44 @@
-; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr32 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-ZCZ-GPR64
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
-; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
-; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
-; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr32 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-ZCZ-GPR64
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
+; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
define i8 @ti8() {
entry:
-; ALL-LABEL: ti8:
+; ALL-LABEL: {{_?}}ti8:{{ *}}{{(;|//)}}{{ *}}@ti8
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
+; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
ret i8 0
}
define i16 @ti16() {
entry:
-; ALL-LABEL: ti16:
+; ALL-LABEL: {{_?}}ti16:{{ *}}{{(;|//)}}{{ *}}@ti16
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
+; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
ret i16 0
}
define i32 @ti32() {
entry:
-; ALL-LABEL: ti32:
+; ALL-LABEL: {{_?}}ti32:{{ *}}{{(;|//)}}{{ *}}@ti32
; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr
-; ZCZ-GPR32: mov w0, #0
-; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0
+; ZCZ-GPR32: mov w0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
+; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
ret i32 0
}
define i64 @ti64() {
entry:
-; ALL-LABEL: ti64:
-; NOZCZ-GPR32-NOZCZ-GPR64 mov x0, xzr
-; ZCZ-GPR64: mov x0, #0
+; ALL-LABEL: {{_?}}ti64:{{ *}}{{(;|//)}}{{ *}}@ti64
+; NOZCZ-GPR32-NOZCZ-GPR64: mov x0, xzr
+; ZCZ-GPR64: mov x0, #0{{ *}}{{(;|//)}}{{ *}}=0x0
ret i64 0
}
>From 27789b0e7bdbd63171b2793432c7a3c410f7ddc1 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Mon, 1 Jun 2026 15:31:50 +0300
Subject: [PATCH 3/3] [AArch64] Add -global-isel runlines to ZCZ tests(NFC)
ZCZ lowering relies on ISel (for FPR - pseudo instruction pattern matching, for GPR - canonical form pattern matching). This patch adds -global-isel runlines to catch possible regressions, though these are not very likely because both selectors should share the patterns.
---
llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll | 3 +++
llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll | 3 +++
2 files changed, 6 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
index 293faf2405fdd..34396a76b970f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
@@ -9,6 +9,9 @@
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
+;; Test Global ISel
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -global-isel | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR128
+
define half @tf16() {
entry:
; ALL-LABEL: {{_?}}tf16:{{ *}}{{(;|//)}}{{ *}}@tf16
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
index abfd79e092395..8d69f22d3187a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll
@@ -8,6 +8,9 @@
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+;; Test Global ISel
+; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -global-isel | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64
+
define i8 @ti8() {
entry:
; ALL-LABEL: {{_?}}ti8:{{ *}}{{(;|//)}}{{ *}}@ti8
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