[llvm] [AArch64][SVE] Handle multi-vector load/store opcodes in frame-index elimination (PR #200695)

[Benjamin Maxwell via llvm-commits]

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@@ -4887,6 +4968,99 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
     MinOffset = -8;
     MaxOffset = 7;
     break;
+  // SME2/SVE2p1 multi-vector contiguous, non-temporal and strided loads/stores
+  // operating on 2 consecutive vectors (2Z).
+  case AArch64::LD1B_2Z_IMM:
+  case AArch64::LD1H_2Z_IMM:
+  case AArch64::LD1W_2Z_IMM:
+  case AArch64::LD1D_2Z_IMM:
+  case AArch64::LD1B_2Z_IMM_PSEUDO:
+  case AArch64::LD1H_2Z_IMM_PSEUDO:
+  case AArch64::LD1W_2Z_IMM_PSEUDO:
+  case AArch64::LD1D_2Z_IMM_PSEUDO:
+  case AArch64::LD1B_2Z_STRIDED_IMM:
+  case AArch64::LD1H_2Z_STRIDED_IMM:
+  case AArch64::LD1W_2Z_STRIDED_IMM:
+  case AArch64::LD1D_2Z_STRIDED_IMM:
+  case AArch64::LDNT1B_2Z_IMM:
+  case AArch64::LDNT1H_2Z_IMM:
+  case AArch64::LDNT1W_2Z_IMM:
+  case AArch64::LDNT1D_2Z_IMM:
+  case AArch64::LDNT1B_2Z_IMM_PSEUDO:
+  case AArch64::LDNT1H_2Z_IMM_PSEUDO:
+  case AArch64::LDNT1W_2Z_IMM_PSEUDO:
+  case AArch64::LDNT1D_2Z_IMM_PSEUDO:
----------------
MacDue wrote:

Most of these are not really tested. (I was working on a follow-up to https://github.com/llvm/llvm-project/pull/200238, which included a MIR test for these)

https://github.com/llvm/llvm-project/pull/200695